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Use new DMA subsystem

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This commit is contained in:
Alex Forencich 2019-10-17 16:02:14 -07:00
parent 16c5eee499
commit 8fa7e40507
31 changed files with 3732 additions and 5473 deletions
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397
fpga/common/rtl/cpl_write.v
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@ -44,20 +44,24 @@ module cpl_write #
parameter PORTS = 2,
// Select field width
parameter SELECT_WIDTH = $clog2(PORTS),
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = 256,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 16,
// Width of AXI wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// PCIe address width
parameter PCIE_ADDR_WIDTH = 64,
// PCIe DMA length field width
parameter PCIE_DMA_LEN_WIDTH = 20,
// PCIe DMA tag field width
parameter PCIE_DMA_TAG_WIDTH = 8,
// RAM segment count
parameter SEG_COUNT = 2,
// RAM segment data width
parameter SEG_DATA_WIDTH = 64,
// RAM segment address width
parameter SEG_ADDR_WIDTH = 8,
// RAM segment byte enable width
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
// RAM address width
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
// DMA RAM pipeline stages
parameter RAM_PIPELINE = 2,
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// DMA length field width
parameter DMA_LEN_WIDTH = 20,
// DMA tag field width
parameter DMA_TAG_WIDTH = 8,
// Transmit request tag field width
parameter REQ_TAG_WIDTH = 8,
// Queue request tag field width
@ -69,9 +73,7 @@ module cpl_write #
// Completion size (in bytes)
parameter CPL_SIZE = 32,
// Descriptor table size (number of in-flight operations)
parameter DESC_TABLE_SIZE = 8,
// AXI base address of this module (as seen by PCIe DMA)
parameter AXI_BASE_ADDR = 16'h0000
parameter DESC_TABLE_SIZE = 8
)
(
input wire clk,
@ -106,7 +108,7 @@ module cpl_write #
/*
* Completion enqueue response input
*/
input wire [PORTS*PCIE_ADDR_WIDTH-1:0] s_axis_cpl_enqueue_resp_addr,
input wire [PORTS*DMA_ADDR_WIDTH-1:0] s_axis_cpl_enqueue_resp_addr,
input wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0] s_axis_cpl_enqueue_resp_tag,
input wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0] s_axis_cpl_enqueue_resp_op_tag,
input wire [PORTS-1:0] s_axis_cpl_enqueue_resp_full,
@ -122,40 +124,30 @@ module cpl_write #
input wire [PORTS-1:0] m_axis_cpl_enqueue_commit_ready,
/*
* PCIe AXI DMA write descriptor output
* DMA write descriptor output
*/
output wire [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_pcie_addr,
output wire [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_axi_addr,
output wire [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_len,
output wire [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_tag,
output wire m_axis_pcie_axi_dma_write_desc_valid,
input wire m_axis_pcie_axi_dma_write_desc_ready,
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag,
output wire m_axis_dma_write_desc_valid,
input wire m_axis_dma_write_desc_ready,
/*
* PCIe AXI DMA write descriptor status input
* DMA write descriptor status input
*/
input wire [PCIE_DMA_TAG_WIDTH-1:0] s_axis_pcie_axi_dma_write_desc_status_tag,
input wire s_axis_pcie_axi_dma_write_desc_status_valid,
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
input wire s_axis_dma_write_desc_status_valid,
/*
* AXI slave interface (read)
* RAM interface
*/
input wire [AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [7:0] s_axi_arlen,
input wire [2:0] s_axi_arsize,
input wire [1:0] s_axi_arburst,
input wire s_axi_arlock,
input wire [3:0] s_axi_arcache,
input wire [2:0] s_axi_arprot,
input wire s_axi_arvalid,
output wire s_axi_arready,
output wire [AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr,
input wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid,
output wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data,
output wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid,
input wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready,
/*
* Configuration
@ -163,10 +155,6 @@ module cpl_write #
input wire enable
);
parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
parameter CL_DESC_TABLE_SIZE = $clog2(DESC_TABLE_SIZE);
parameter DESC_PTR_MASK = {CL_DESC_TABLE_SIZE{1'b1}};
@ -174,8 +162,8 @@ parameter CL_PORTS = $clog2(PORTS);
// bus width assertions
initial begin
if (PCIE_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE+1) begin
$error("Error: PCIe tag width insufficient for descriptor table size (instance %m)");
if (DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE+1) begin
$error("Error: DMA tag width insufficient for descriptor table size (instance %m)");
$finish;
end
@ -183,21 +171,6 @@ initial begin
$error("Error: Queue request tag width insufficient for descriptor table size (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH < CPL_SIZE) begin
$error("Error: AXI interface width must be at least as large as one descriptor (instance %m)");
$finish;
end
if (AXI_BASE_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
$error("Error: AXI base address must be aligned to interface width (instance %m)");
$finish;
end
end
reg s_axis_req_ready_reg = 1'b0, s_axis_req_ready_next;
@ -216,11 +189,11 @@ reg [PORTS-1:0] s_axis_cpl_enqueue_resp_ready_reg = {PORTS{1'b0}}, s_axis_cpl_en
reg [QUEUE_OP_TAG_WIDTH-1:0] m_axis_cpl_enqueue_commit_op_tag_reg = {QUEUE_OP_TAG_WIDTH{1'b0}}, m_axis_cpl_enqueue_commit_op_tag_next;
reg [PORTS-1:0] m_axis_cpl_enqueue_commit_valid_reg = {PORTS{1'b0}}, m_axis_cpl_enqueue_commit_valid_next;
reg [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_pcie_addr_next;
reg [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_axi_addr_next;
reg [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_len_next;
reg [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_tag_next;
reg m_axis_pcie_axi_dma_write_desc_valid_reg = 1'b0, m_axis_pcie_axi_dma_write_desc_valid_next;
reg [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr_reg = {DMA_ADDR_WIDTH{1'b0}}, m_axis_dma_write_desc_dma_addr_next;
reg [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, m_axis_dma_write_desc_ram_addr_next;
reg [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len_reg = {DMA_LEN_WIDTH{1'b0}}, m_axis_dma_write_desc_len_next;
reg [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag_reg = {DMA_TAG_WIDTH{1'b0}}, m_axis_dma_write_desc_tag_next;
reg m_axis_dma_write_desc_valid_reg = 1'b0, m_axis_dma_write_desc_valid_next;
reg [DESC_TABLE_SIZE-1:0] desc_table_active = 0;
reg [DESC_TABLE_SIZE-1:0] desc_table_invalid = 0;
@ -228,12 +201,10 @@ reg [DESC_TABLE_SIZE-1:0] desc_table_cpl_write_done = 0;
reg [CL_PORTS-1:0] desc_table_sel[DESC_TABLE_SIZE-1:0];
reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0];
reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_queue_op_tag[DESC_TABLE_SIZE-1:0];
reg [CPL_SIZE*8-1:0] desc_table_data[DESC_TABLE_SIZE-1:0];
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0;
reg [CL_PORTS-1:0] desc_table_start_sel;
reg [REQ_TAG_WIDTH-1:0] desc_table_start_tag;
reg [CPL_SIZE*8-1:0] desc_table_start_data;
reg [QUEUE_INDEX_WIDTH-1:0] desc_table_start_cpl_queue;
reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_start_queue_op_tag;
reg desc_table_start_en;
@ -246,6 +217,20 @@ reg desc_table_cpl_write_done_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_finish_ptr_reg = 0;
reg desc_table_finish_en;
reg [RAM_ADDR_WIDTH-1:0] dma_write_desc_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, dma_write_desc_ram_addr_next;
reg [7:0] dma_write_desc_len_reg = 8'd0, dma_write_desc_len_next;
reg [CL_DESC_TABLE_SIZE-1:0] dma_write_desc_tag_reg = {CL_DESC_TABLE_SIZE{1'b0}}, dma_write_desc_tag_next;
reg dma_write_desc_user_reg = 1'b0, dma_write_desc_user_next;
reg dma_write_desc_valid_reg = 1'b0, dma_write_desc_valid_next;
wire dma_write_desc_ready;
wire [CL_DESC_TABLE_SIZE-1:0] dma_write_desc_status_tag;
wire dma_write_desc_status_valid;
reg [CPL_SIZE*8-1:0] cpl_data_reg = 0, cpl_data_next;
reg cpl_data_valid_reg = 1'b0, cpl_data_valid_next;
wire cpl_data_ready;
assign s_axis_req_ready = s_axis_req_ready_reg;
assign m_axis_req_status_tag = m_axis_req_status_tag_reg;
@ -262,11 +247,11 @@ assign s_axis_cpl_enqueue_resp_ready = s_axis_cpl_enqueue_resp_ready_reg;
assign m_axis_cpl_enqueue_commit_op_tag = {PORTS{m_axis_cpl_enqueue_commit_op_tag_reg}};
assign m_axis_cpl_enqueue_commit_valid = m_axis_cpl_enqueue_commit_valid_reg;
assign m_axis_pcie_axi_dma_write_desc_pcie_addr = m_axis_pcie_axi_dma_write_desc_pcie_addr_reg;
assign m_axis_pcie_axi_dma_write_desc_axi_addr = m_axis_pcie_axi_dma_write_desc_axi_addr_reg;
assign m_axis_pcie_axi_dma_write_desc_len = m_axis_pcie_axi_dma_write_desc_len_reg;
assign m_axis_pcie_axi_dma_write_desc_tag = m_axis_pcie_axi_dma_write_desc_tag_reg;
assign m_axis_pcie_axi_dma_write_desc_valid = m_axis_pcie_axi_dma_write_desc_valid_reg;
assign m_axis_dma_write_desc_dma_addr = m_axis_dma_write_desc_dma_addr_reg;
assign m_axis_dma_write_desc_ram_addr = m_axis_dma_write_desc_ram_addr_reg;
assign m_axis_dma_write_desc_len = m_axis_dma_write_desc_len_reg;
assign m_axis_dma_write_desc_tag = m_axis_dma_write_desc_tag_reg;
assign m_axis_dma_write_desc_valid = m_axis_dma_write_desc_valid_reg;
wire [CL_PORTS-1:0] enqueue_resp_enc;
wire enqueue_resp_enc_valid;
@ -282,88 +267,112 @@ op_table_start_enc_inst (
.output_unencoded()
);
wire [AXI_ID_WIDTH-1:0] ram_rd_cmd_id;
wire [AXI_ADDR_WIDTH-1:0] ram_rd_cmd_addr;
wire ram_rd_cmd_en;
wire ram_rd_cmd_last;
reg ram_rd_cmd_ready_reg = 1'b0;
reg [AXI_ID_WIDTH-1:0] ram_rd_resp_id_reg = {AXI_ID_WIDTH{1'b0}};
reg [AXI_DATA_WIDTH-1:0] ram_rd_resp_data_reg = {AXI_DATA_WIDTH{1'b0}};
reg ram_rd_resp_last_reg = 1'b0;
reg ram_rd_resp_valid_reg = 1'b0;
wire ram_rd_resp_ready;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be_int;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr_int;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data_int;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid_int;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready_int;
axi_ram_rd_if #(
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH),
.STRB_WIDTH(AXI_STRB_WIDTH),
.ID_WIDTH(AXI_ID_WIDTH),
.ARUSER_ENABLE(0),
.RUSER_ENABLE(0),
.PIPELINE_OUTPUT(0)
dma_psdpram #(
.SIZE(DESC_TABLE_SIZE*SEG_COUNT*SEG_BE_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.PIPELINE(RAM_PIPELINE)
)
axi_ram_rd_if_inst (
.clk(clk),
.rst(rst),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(0),
.s_axi_arregion(0),
.s_axi_aruser(0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.ram_rd_cmd_id(ram_rd_cmd_id),
.ram_rd_cmd_addr(ram_rd_cmd_addr),
.ram_rd_cmd_lock(),
.ram_rd_cmd_cache(),
.ram_rd_cmd_prot(),
.ram_rd_cmd_qos(),
.ram_rd_cmd_region(),
.ram_rd_cmd_auser(),
.ram_rd_cmd_en(ram_rd_cmd_en),
.ram_rd_cmd_last(ram_rd_cmd_last),
.ram_rd_cmd_ready(ram_rd_cmd_ready_reg),
.ram_rd_resp_id(ram_rd_resp_id_reg),
.ram_rd_resp_data(ram_rd_resp_data_reg),
.ram_rd_resp_last(ram_rd_resp_last_reg),
.ram_rd_resp_user(0),
.ram_rd_resp_valid(ram_rd_resp_valid_reg),
.ram_rd_resp_ready(ram_rd_resp_ready)
dma_psdpram_inst (
/*
* Write port
*/
.clk_wr(clk),
.rst_wr(rst),
.wr_cmd_be(dma_ram_wr_cmd_be_int),
.wr_cmd_addr(dma_ram_wr_cmd_addr_int),
.wr_cmd_data(dma_ram_wr_cmd_data_int),
.wr_cmd_valid(dma_ram_wr_cmd_valid_int),
.wr_cmd_ready(dma_ram_wr_cmd_ready_int),
/*
* Read port
*/
.clk_rd(clk),
.rst_rd(rst),
.rd_cmd_addr(dma_ram_rd_cmd_addr),
.rd_cmd_valid(dma_ram_rd_cmd_valid),
.rd_cmd_ready(dma_ram_rd_cmd_ready),
.rd_resp_data(dma_ram_rd_resp_data),
.rd_resp_valid(dma_ram_rd_resp_valid),
.rd_resp_ready(dma_ram_rd_resp_ready)
);
always @(posedge clk) begin
ram_rd_resp_valid_reg <= ram_rd_resp_valid_reg && !ram_rd_resp_ready;
ram_rd_cmd_ready_reg <= !ram_rd_resp_valid_reg || ram_rd_resp_ready;
dma_client_axis_sink #(
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.AXIS_DATA_WIDTH(CPL_SIZE*8),
.AXIS_KEEP_ENABLE(CPL_SIZE > 1),
.AXIS_KEEP_WIDTH(CPL_SIZE),
.AXIS_LAST_ENABLE(1),
.AXIS_ID_ENABLE(0),
.AXIS_DEST_ENABLE(0),
.AXIS_USER_ENABLE(1),
.AXIS_USER_WIDTH(1),
.LEN_WIDTH(8),
.TAG_WIDTH(CL_DESC_TABLE_SIZE)
)
dma_client_axis_sink_inst (
.clk(clk),
.rst(rst),
if (ram_rd_cmd_en && ram_rd_cmd_ready_reg) begin
// AXI read
ram_rd_resp_id_reg <= ram_rd_cmd_id;
ram_rd_resp_data_reg <= 0;
ram_rd_resp_last_reg <= ram_rd_cmd_last;
ram_rd_resp_valid_reg <= 1'b1;
ram_rd_cmd_ready_reg <= ram_rd_resp_ready;
/*
* DMA write descriptor input
*/
.s_axis_write_desc_ram_addr(dma_write_desc_ram_addr_reg),
.s_axis_write_desc_len(dma_write_desc_len_reg),
.s_axis_write_desc_tag(dma_write_desc_tag_reg),
.s_axis_write_desc_valid(dma_write_desc_valid_reg),
.s_axis_write_desc_ready(dma_write_desc_ready),
ram_rd_resp_data_reg <= desc_table_data[ram_rd_cmd_addr[CL_DESC_TABLE_SIZE+5-1:5]];
end
/*
* DMA write descriptor status output
*/
.m_axis_write_desc_status_len(),
.m_axis_write_desc_status_tag(dma_write_desc_status_tag),
.m_axis_write_desc_status_id(),
.m_axis_write_desc_status_dest(),
.m_axis_write_desc_status_user(),
.m_axis_write_desc_status_valid(dma_write_desc_status_valid),
if (rst) begin
ram_rd_cmd_ready_reg <= 1'b1;
ram_rd_resp_valid_reg <= 1'b0;
end
end
/*
* AXI stream write data input
*/
.s_axis_write_data_tdata(cpl_data_reg),
.s_axis_write_data_tkeep({CPL_SIZE{1'b1}}),
.s_axis_write_data_tvalid(cpl_data_valid_reg),
.s_axis_write_data_tready(cpl_data_ready),
.s_axis_write_data_tlast(1'b1),
.s_axis_write_data_tid(0),
.s_axis_write_data_tdest(0),
.s_axis_write_data_tuser(1'b0),
/*
* RAM interface
*/
.ram_wr_cmd_be(dma_ram_wr_cmd_be_int),
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr_int),
.ram_wr_cmd_data(dma_ram_wr_cmd_data_int),
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid_int),
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready_int),
/*
* Configuration
*/
.enable(1'b1),
.abort(1'b0)
);
always @* begin
s_axis_req_ready_next = 1'b0;
@ -382,45 +391,68 @@ always @* begin
m_axis_cpl_enqueue_commit_op_tag_next = m_axis_cpl_enqueue_commit_op_tag_reg;
m_axis_cpl_enqueue_commit_valid_next = m_axis_cpl_enqueue_commit_valid_reg & ~m_axis_cpl_enqueue_commit_ready;
m_axis_pcie_axi_dma_write_desc_pcie_addr_next = m_axis_pcie_axi_dma_write_desc_pcie_addr_reg;
m_axis_pcie_axi_dma_write_desc_axi_addr_next = m_axis_pcie_axi_dma_write_desc_axi_addr_reg;
m_axis_pcie_axi_dma_write_desc_len_next = m_axis_pcie_axi_dma_write_desc_len_reg;
m_axis_pcie_axi_dma_write_desc_tag_next = m_axis_pcie_axi_dma_write_desc_tag_reg;
m_axis_pcie_axi_dma_write_desc_valid_next = m_axis_pcie_axi_dma_write_desc_valid_reg && !m_axis_pcie_axi_dma_write_desc_ready;
m_axis_dma_write_desc_dma_addr_next = m_axis_dma_write_desc_dma_addr_reg;
m_axis_dma_write_desc_ram_addr_next = m_axis_dma_write_desc_ram_addr_reg;
m_axis_dma_write_desc_len_next = m_axis_dma_write_desc_len_reg;
m_axis_dma_write_desc_tag_next = m_axis_dma_write_desc_tag_reg;
m_axis_dma_write_desc_valid_next = m_axis_dma_write_desc_valid_reg && !m_axis_dma_write_desc_ready;
dma_write_desc_ram_addr_next = dma_write_desc_ram_addr_reg;
dma_write_desc_len_next = dma_write_desc_len_reg;
dma_write_desc_tag_next = dma_write_desc_tag_reg;
dma_write_desc_user_next = dma_write_desc_user_reg;
dma_write_desc_valid_next = dma_write_desc_valid_reg && !dma_write_desc_ready;
cpl_data_next = cpl_data_reg;
cpl_data_valid_next = cpl_data_valid_reg && !cpl_data_ready;
desc_table_start_sel = s_axis_req_sel;
desc_table_start_tag = s_axis_req_tag;
desc_table_start_data = s_axis_req_data;
desc_table_start_en = 1'b0;
desc_table_enqueue_ptr = s_axis_cpl_enqueue_resp_tag[enqueue_resp_enc*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH] & DESC_PTR_MASK;
desc_table_enqueue_queue_op_tag = s_axis_cpl_enqueue_resp_op_tag[enqueue_resp_enc*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH];
desc_table_enqueue_invalid = 1'b0;
desc_table_enqueue_en = 1'b0;
desc_table_cpl_write_done_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
desc_table_cpl_write_done_ptr = s_axis_dma_write_desc_status_tag & DESC_PTR_MASK;
desc_table_cpl_write_done_en = 1'b0;
desc_table_finish_en = 1'b0;
// queue query
// wait for descriptor request
s_axis_req_ready_next = enable && !desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] && ($unsigned(desc_table_start_ptr_reg - desc_table_finish_ptr_reg) < DESC_TABLE_SIZE) && (!m_axis_cpl_enqueue_req_valid || (m_axis_cpl_enqueue_req_valid & m_axis_cpl_enqueue_req_ready));
s_axis_req_ready_next = enable && !desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] && ($unsigned(desc_table_start_ptr_reg - desc_table_finish_ptr_reg) < DESC_TABLE_SIZE) && (!m_axis_cpl_enqueue_req_valid || (m_axis_cpl_enqueue_req_valid & m_axis_cpl_enqueue_req_ready)) && (!dma_write_desc_valid_reg) && (!cpl_data_valid_reg);
if (s_axis_req_ready && s_axis_req_valid) begin
s_axis_req_ready_next = 1'b0;
// store in descriptor table
desc_table_start_sel = s_axis_req_sel;
desc_table_start_tag = s_axis_req_tag;
desc_table_start_data = s_axis_req_data;
desc_table_start_en = 1'b1;
// initiate queue query
m_axis_cpl_enqueue_req_queue_next = s_axis_req_queue;
m_axis_cpl_enqueue_req_tag_next = desc_table_start_ptr_reg & DESC_PTR_MASK;
m_axis_cpl_enqueue_req_valid_next = 1 << s_axis_req_sel;
// initiate completion write to DMA RAM
cpl_data_next = s_axis_req_data;
cpl_data_valid_next = 1'b1;
dma_write_desc_ram_addr_next = (desc_table_start_ptr_reg & DESC_PTR_MASK) << 5;
dma_write_desc_len_next = CPL_SIZE;
dma_write_desc_tag_next = (desc_table_start_ptr_reg & DESC_PTR_MASK);
dma_write_desc_valid_next = 1'b1;
end
// finish completion write to DMA RAM
if (dma_write_desc_status_valid) begin
// update entry in descriptor table
// desc_table_cpl_write_done_ptr = s_axis_dma_write_desc_status_tag & DESC_PTR_MASK;
// desc_table_cpl_write_done_en = 1'b1;
end
// start completion write
// wait for queue query response
if (enqueue_resp_enc_valid && !m_axis_pcie_axi_dma_write_desc_valid_reg) begin
if (enqueue_resp_enc_valid && !m_axis_dma_write_desc_valid_reg) begin
s_axis_cpl_enqueue_resp_ready_next = 1 << enqueue_resp_enc;
// update entry in descriptor table
@ -436,10 +468,10 @@ always @* begin
m_axis_req_status_valid_next = 1'b1;
// initiate completion write
m_axis_pcie_axi_dma_write_desc_pcie_addr_next = s_axis_cpl_enqueue_resp_addr[enqueue_resp_enc*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH];
m_axis_pcie_axi_dma_write_desc_axi_addr_next = AXI_BASE_ADDR + ((s_axis_cpl_enqueue_resp_tag[enqueue_resp_enc*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH] & DESC_PTR_MASK) << 5);
m_axis_pcie_axi_dma_write_desc_len_next = CPL_SIZE;
m_axis_pcie_axi_dma_write_desc_tag_next = (s_axis_cpl_enqueue_resp_tag[enqueue_resp_enc*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH] & DESC_PTR_MASK);
m_axis_dma_write_desc_dma_addr_next = s_axis_cpl_enqueue_resp_addr[enqueue_resp_enc*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH];
m_axis_dma_write_desc_ram_addr_next = (s_axis_cpl_enqueue_resp_tag[enqueue_resp_enc*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH] & DESC_PTR_MASK) << 5;
m_axis_dma_write_desc_len_next = CPL_SIZE;
m_axis_dma_write_desc_tag_next = (s_axis_cpl_enqueue_resp_tag[enqueue_resp_enc*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH] & DESC_PTR_MASK);
if (s_axis_cpl_enqueue_resp_error[enqueue_resp_enc*1 +: 1] || s_axis_cpl_enqueue_resp_full[enqueue_resp_enc*1 +: 1]) begin
// queue empty or not active
@ -450,14 +482,14 @@ always @* begin
// descriptor available to enqueue
// initiate completion write
m_axis_pcie_axi_dma_write_desc_valid_next = 1'b1;
m_axis_dma_write_desc_valid_next = 1'b1;
end
end
// finish completion write
if (s_axis_pcie_axi_dma_write_desc_status_valid) begin
if (s_axis_dma_write_desc_status_valid) begin
// update entry in descriptor table
desc_table_cpl_write_done_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
desc_table_cpl_write_done_ptr = s_axis_dma_write_desc_status_tag & DESC_PTR_MASK;
desc_table_cpl_write_done_en = 1'b1;
end
@ -495,11 +527,20 @@ always @(posedge clk) begin
m_axis_cpl_enqueue_commit_op_tag_reg <= m_axis_cpl_enqueue_commit_op_tag_next;
m_axis_cpl_enqueue_commit_valid_reg <= m_axis_cpl_enqueue_commit_valid_next;
m_axis_pcie_axi_dma_write_desc_pcie_addr_reg <= m_axis_pcie_axi_dma_write_desc_pcie_addr_next;
m_axis_pcie_axi_dma_write_desc_axi_addr_reg <= m_axis_pcie_axi_dma_write_desc_axi_addr_next;
m_axis_pcie_axi_dma_write_desc_len_reg <= m_axis_pcie_axi_dma_write_desc_len_next;
m_axis_pcie_axi_dma_write_desc_tag_reg <= m_axis_pcie_axi_dma_write_desc_tag_next;
m_axis_pcie_axi_dma_write_desc_valid_reg <= m_axis_pcie_axi_dma_write_desc_valid_next;
m_axis_dma_write_desc_dma_addr_reg <= m_axis_dma_write_desc_dma_addr_next;
m_axis_dma_write_desc_ram_addr_reg <= m_axis_dma_write_desc_ram_addr_next;
m_axis_dma_write_desc_len_reg <= m_axis_dma_write_desc_len_next;
m_axis_dma_write_desc_tag_reg <= m_axis_dma_write_desc_tag_next;
m_axis_dma_write_desc_valid_reg <= m_axis_dma_write_desc_valid_next;
dma_write_desc_ram_addr_reg <= dma_write_desc_ram_addr_next;
dma_write_desc_len_reg <= dma_write_desc_len_next;
dma_write_desc_tag_reg <= dma_write_desc_tag_next;
dma_write_desc_user_reg <= dma_write_desc_user_next;
dma_write_desc_valid_reg <= dma_write_desc_valid_next;
cpl_data_reg <= cpl_data_next;
cpl_data_valid_reg <= cpl_data_valid_next;
if (desc_table_start_en) begin
desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b1;
@ -507,7 +548,6 @@ always @(posedge clk) begin
desc_table_cpl_write_done[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
desc_table_sel[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_sel;
desc_table_tag[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_tag;
desc_table_data[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_data;
desc_table_start_ptr_reg <= desc_table_start_ptr_reg + 1;
end
@ -531,7 +571,10 @@ always @(posedge clk) begin
m_axis_cpl_enqueue_req_valid_reg <= 1'b0;
s_axis_cpl_enqueue_resp_ready_reg <= 1'b0;
m_axis_cpl_enqueue_commit_valid_reg <= 1'b0;
m_axis_pcie_axi_dma_write_desc_valid_reg <= 1'b0;
m_axis_dma_write_desc_valid_reg <= 1'b0;
dma_write_desc_valid_reg <= 1'b0;
cpl_data_valid_reg <= 1'b0;
desc_table_active <= 0;
desc_table_invalid <= 0;

462
fpga/common/rtl/desc_fetch.v
View File

@ -44,24 +44,24 @@ module desc_fetch #
parameter PORTS = 2,
// Select field width
parameter SELECT_WIDTH = $clog2(PORTS),
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = 256,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 16,
// Width of AXI wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// Width of AXI stream interface in bits
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH,
// PCIe address width
parameter PCIE_ADDR_WIDTH = 64,
// PCIe DMA length field width
parameter PCIE_DMA_LEN_WIDTH = 20,
// PCIe DMA tag field width
parameter PCIE_DMA_TAG_WIDTH = 8,
// RAM segment count
parameter SEG_COUNT = 2,
// RAM segment data width
parameter SEG_DATA_WIDTH = 64,
// RAM segment address width
parameter SEG_ADDR_WIDTH = 8,
// RAM segment byte enable width
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
// RAM address width
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
// DMA RAM pipeline stages
parameter RAM_PIPELINE = 2,
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// DMA length field width
parameter DMA_LEN_WIDTH = 20,
// DMA tag field width
parameter DMA_TAG_WIDTH = 8,
// Transmit request tag field width
parameter REQ_TAG_WIDTH = 8,
// Queue request tag field width
@ -78,8 +78,10 @@ module desc_fetch #
parameter DESC_SIZE = 16,
// Descriptor table size (number of in-flight operations)
parameter DESC_TABLE_SIZE = 8,
// AXI base address of this module (as seen by PCIe DMA)
parameter AXI_BASE_ADDR = 16'h0000
// Width of AXI stream interface in bits
parameter AXIS_DATA_WIDTH = DESC_SIZE*8,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8
)
(
input wire clk,
@ -129,7 +131,7 @@ module desc_fetch #
*/
input wire [PORTS*QUEUE_INDEX_WIDTH-1:0] s_axis_desc_dequeue_resp_queue,
input wire [PORTS*QUEUE_PTR_WIDTH-1:0] s_axis_desc_dequeue_resp_ptr,
input wire [PORTS*PCIE_ADDR_WIDTH-1:0] s_axis_desc_dequeue_resp_addr,
input wire [PORTS*DMA_ADDR_WIDTH-1:0] s_axis_desc_dequeue_resp_addr,
input wire [PORTS*CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_dequeue_resp_cpl,
input wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0] s_axis_desc_dequeue_resp_tag,
input wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0] s_axis_desc_dequeue_resp_op_tag,
@ -146,43 +148,29 @@ module desc_fetch #
input wire [PORTS-1:0] m_axis_desc_dequeue_commit_ready,
/*
* PCIe AXI DMA read descriptor output
* DMA read descriptor output
*/
output wire [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_pcie_addr,
output wire [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_axi_addr,
output wire [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_len,
output wire [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_tag,
output wire m_axis_pcie_axi_dma_read_desc_valid,
input wire m_axis_pcie_axi_dma_read_desc_ready,
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag,
output wire m_axis_dma_read_desc_valid,
input wire m_axis_dma_read_desc_ready,
/*
* PCIe AXI DMA read descriptor status input
* DMA read descriptor status input
*/
input wire [PCIE_DMA_TAG_WIDTH-1:0] s_axis_pcie_axi_dma_read_desc_status_tag,
input wire s_axis_pcie_axi_dma_read_desc_status_valid,
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag,
input wire s_axis_dma_read_desc_status_valid,
/*
* AXI slave interface (write)
* RAM interface
*/
input wire [AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [7:0] s_axi_awlen,
input wire [2:0] s_axi_awsize,
input wire [1:0] s_axi_awburst,
input wire s_axi_awlock,
input wire [3:0] s_axi_awcache,
input wire [2:0] s_axi_awprot,
input wire s_axi_awvalid,
output wire s_axi_awready,
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [AXI_STRB_WIDTH-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
output wire [AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
input wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be,
input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr,
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data,
input wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid,
output wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready,
/*
* Configuration
@ -190,10 +178,6 @@ module desc_fetch #
input wire enable
);
parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
parameter CL_DESC_TABLE_SIZE = $clog2(DESC_TABLE_SIZE);
parameter DESC_PTR_MASK = {CL_DESC_TABLE_SIZE{1'b1}};
@ -201,8 +185,8 @@ parameter CL_PORTS = $clog2(PORTS);
// bus width assertions
initial begin
if (PCIE_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
$error("Error: PCIe tag width insufficient for descriptor table size (instance %m)");
if (DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
$error("Error: DMA tag width insufficient for descriptor table size (instance %m)");
$finish;
end
@ -216,26 +200,6 @@ initial begin
$finish;
end
if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH < DESC_SIZE) begin
$error("Error: AXI interface width must be at least as large as one descriptor (instance %m)");
$finish;
end
if (AXI_BASE_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
$error("Error: AXI base address must be aligned to interface width (instance %m)");
$finish;
end
if (AXIS_DATA_WIDTH != AXI_DATA_WIDTH) begin
$error("Error: AXI stream interface width must match AXI interface width (instance %m)");
$finish;
end
if (AXIS_KEEP_WIDTH * 8 != AXIS_DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
@ -252,13 +216,6 @@ reg m_axis_req_status_empty_reg = 1'b0, m_axis_req_status_empty_next;
reg m_axis_req_status_error_reg = 1'b0, m_axis_req_status_error_next;
reg m_axis_req_status_valid_reg = 1'b0, m_axis_req_status_valid_next;
reg [AXIS_DATA_WIDTH-1:0] m_axis_desc_tdata_reg = {AXIS_DATA_WIDTH{1'b0}}, m_axis_desc_tdata_next;
reg [AXIS_KEEP_WIDTH-1:0] m_axis_desc_tkeep_reg = {AXIS_KEEP_WIDTH{1'b0}}, m_axis_desc_tkeep_next;
reg m_axis_desc_tvalid_reg = 1'b0, m_axis_desc_tvalid_next;
reg m_axis_desc_tlast_reg = 1'b0, m_axis_desc_tlast_next;
reg [REQ_TAG_WIDTH-1:0] m_axis_desc_tid_reg = {REQ_TAG_WIDTH{1'b0}}, m_axis_desc_tid_next;
reg m_axis_desc_tuser_reg = 1'b0, m_axis_desc_tuser_next;
reg [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_dequeue_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}, m_axis_desc_dequeue_req_queue_next;
reg [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_desc_dequeue_req_tag_reg = {QUEUE_REQ_TAG_WIDTH{1'b0}}, m_axis_desc_dequeue_req_tag_next;
reg [PORTS-1:0] m_axis_desc_dequeue_req_valid_reg = {PORTS{1'b0}}, m_axis_desc_dequeue_req_valid_next;
@ -268,11 +225,11 @@ reg [PORTS-1:0] s_axis_desc_dequeue_resp_ready_reg = {PORTS{1'b0}}, s_axis_desc_
reg [QUEUE_OP_TAG_WIDTH-1:0] m_axis_desc_dequeue_commit_op_tag_reg = {QUEUE_OP_TAG_WIDTH{1'b0}}, m_axis_desc_dequeue_commit_op_tag_next;
reg [PORTS-1:0] m_axis_desc_dequeue_commit_valid_reg = {PORTS{1'b0}}, m_axis_desc_dequeue_commit_valid_next;
reg [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_pcie_addr_next;
reg [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_axi_addr_next;
reg [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_len_next;
reg [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_tag_next;
reg m_axis_pcie_axi_dma_read_desc_valid_reg = 1'b0, m_axis_pcie_axi_dma_read_desc_valid_next;
reg [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr_reg = {DMA_ADDR_WIDTH{1'b0}}, m_axis_dma_read_desc_dma_addr_next;
reg [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, m_axis_dma_read_desc_ram_addr_next;
reg [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len_reg = {DMA_LEN_WIDTH{1'b0}}, m_axis_dma_read_desc_len_next;
reg [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag_reg = {DMA_TAG_WIDTH{1'b0}}, m_axis_dma_read_desc_tag_next;
reg m_axis_dma_read_desc_valid_reg = 1'b0, m_axis_dma_read_desc_valid_next;
reg [CL_DESC_TABLE_SIZE+1-1:0] active_count_reg = 0;
reg inc_active;
@ -281,10 +238,10 @@ reg dec_active_2;
reg [DESC_TABLE_SIZE-1:0] desc_table_active = 0;
reg [DESC_TABLE_SIZE-1:0] desc_table_desc_fetched = 0;
reg [DESC_TABLE_SIZE-1:0] desc_table_desc_read_done = 0;
reg [CL_PORTS-1:0] desc_table_sel[DESC_TABLE_SIZE-1:0];
reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0];
reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_queue_op_tag[DESC_TABLE_SIZE-1:0];
reg [DESC_SIZE*8-1:0] desc_table_data[DESC_TABLE_SIZE-1:0];
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0;
reg [CL_PORTS-1:0] desc_table_start_sel;
@ -293,9 +250,24 @@ reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_start_queue_op_tag;
reg desc_table_start_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_desc_fetched_ptr;
reg desc_table_desc_fetched_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_desc_read_ptr_reg = 0;
reg desc_table_desc_read_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_desc_read_done_ptr;
reg desc_table_desc_read_done_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_finish_ptr_reg = 0;
reg desc_table_finish_en;
reg [RAM_ADDR_WIDTH-1:0] dma_read_desc_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, dma_read_desc_ram_addr_next;
reg [7:0] dma_read_desc_len_reg = 8'd0, dma_read_desc_len_next;
reg [CL_DESC_TABLE_SIZE-1:0] dma_read_desc_tag_reg = {CL_DESC_TABLE_SIZE{1'b0}}, dma_read_desc_tag_next;
reg [REQ_TAG_WIDTH-1:0] dma_read_desc_id_reg = {REQ_TAG_WIDTH{1'b0}}, dma_read_desc_id_next;
reg dma_read_desc_user_reg = 1'b0, dma_read_desc_user_next;
reg dma_read_desc_valid_reg = 1'b0, dma_read_desc_valid_next;
wire dma_read_desc_ready;
wire [CL_DESC_TABLE_SIZE-1:0] dma_read_desc_status_tag;
wire dma_read_desc_status_valid;
assign s_axis_req_ready = s_axis_req_ready_reg;
assign m_axis_req_status_queue = m_axis_req_status_queue_reg;
@ -306,13 +278,6 @@ assign m_axis_req_status_empty = m_axis_req_status_empty_reg;
assign m_axis_req_status_error = m_axis_req_status_error_reg;
assign m_axis_req_status_valid = m_axis_req_status_valid_reg;
assign m_axis_desc_tdata = m_axis_desc_tdata_reg;
assign m_axis_desc_tkeep = m_axis_desc_tkeep_reg;
assign m_axis_desc_tvalid = m_axis_desc_tvalid_reg;
assign m_axis_desc_tlast = m_axis_desc_tlast_reg;
assign m_axis_desc_tid = m_axis_desc_tid_reg;
assign m_axis_desc_tuser = m_axis_desc_tuser_reg;
assign m_axis_desc_dequeue_req_queue = {PORTS{m_axis_desc_dequeue_req_queue_reg}};
assign m_axis_desc_dequeue_req_tag = {PORTS{m_axis_desc_dequeue_req_tag_reg}};
assign m_axis_desc_dequeue_req_valid = m_axis_desc_dequeue_req_valid_reg;
@ -322,11 +287,11 @@ assign s_axis_desc_dequeue_resp_ready = s_axis_desc_dequeue_resp_ready_reg;
assign m_axis_desc_dequeue_commit_op_tag = {PORTS{m_axis_desc_dequeue_commit_op_tag_reg}};
assign m_axis_desc_dequeue_commit_valid = m_axis_desc_dequeue_commit_valid_reg;
assign m_axis_pcie_axi_dma_read_desc_pcie_addr = m_axis_pcie_axi_dma_read_desc_pcie_addr_reg;
assign m_axis_pcie_axi_dma_read_desc_axi_addr = m_axis_pcie_axi_dma_read_desc_axi_addr_reg;
assign m_axis_pcie_axi_dma_read_desc_len = m_axis_pcie_axi_dma_read_desc_len_reg;
assign m_axis_pcie_axi_dma_read_desc_tag = m_axis_pcie_axi_dma_read_desc_tag_reg;
assign m_axis_pcie_axi_dma_read_desc_valid = m_axis_pcie_axi_dma_read_desc_valid_reg;
assign m_axis_dma_read_desc_dma_addr = m_axis_dma_read_desc_dma_addr_reg;
assign m_axis_dma_read_desc_ram_addr = m_axis_dma_read_desc_ram_addr_reg;
assign m_axis_dma_read_desc_len = m_axis_dma_read_desc_len_reg;
assign m_axis_dma_read_desc_tag = m_axis_dma_read_desc_tag_reg;
assign m_axis_dma_read_desc_valid = m_axis_dma_read_desc_valid_reg;
wire [CL_PORTS-1:0] dequeue_resp_enc;
wire dequeue_resp_enc_valid;
@ -342,71 +307,113 @@ op_table_start_enc_inst (
.output_unencoded()
);
wire [AXI_ID_WIDTH-1:0] ram_wr_cmd_id;
wire [AXI_ADDR_WIDTH-1:0] ram_wr_cmd_addr;
wire [AXI_DATA_WIDTH-1:0] ram_wr_cmd_data;
wire [AXI_STRB_WIDTH-1:0] ram_wr_cmd_strb;
wire ram_wr_cmd_en;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr_int;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid_int;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready_int;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data_int;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid_int;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready_int;
axi_ram_wr_if #(
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH),
.STRB_WIDTH(AXI_STRB_WIDTH),
.ID_WIDTH(AXI_ID_WIDTH),
.AWUSER_ENABLE(0),
.WUSER_ENABLE(0),
.BUSER_ENABLE(0)
dma_psdpram #(
.SIZE(DESC_TABLE_SIZE*SEG_COUNT*SEG_BE_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.PIPELINE(RAM_PIPELINE)
)
axi_ram_wr_if_inst (
.clk(clk),
.rst(rst),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(0),
.s_axi_awregion(0),
.s_axi_awuser(0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.ram_wr_cmd_id(ram_wr_cmd_id),
.ram_wr_cmd_addr(ram_wr_cmd_addr),
.ram_wr_cmd_lock(),
.ram_wr_cmd_cache(),
.ram_wr_cmd_prot(),
.ram_wr_cmd_qos(),
.ram_wr_cmd_region(),
.ram_wr_cmd_auser(),
.ram_wr_cmd_data(ram_wr_cmd_data),
.ram_wr_cmd_strb(ram_wr_cmd_strb),
.ram_wr_cmd_user(),
.ram_wr_cmd_en(ram_wr_cmd_en),
.ram_wr_cmd_last(),
.ram_wr_cmd_ready(1'b1)
dma_psdpram_inst (
/*
* Write port
*/
.clk_wr(clk),
.rst_wr(rst),
.wr_cmd_be(dma_ram_wr_cmd_be),
.wr_cmd_addr(dma_ram_wr_cmd_addr),
.wr_cmd_data(dma_ram_wr_cmd_data),
.wr_cmd_valid(dma_ram_wr_cmd_valid),
.wr_cmd_ready(dma_ram_wr_cmd_ready),
/*
* Read port
*/
.clk_rd(clk),
.rst_rd(rst),
.rd_cmd_addr(dma_ram_rd_cmd_addr_int),
.rd_cmd_valid(dma_ram_rd_cmd_valid_int),
.rd_cmd_ready(dma_ram_rd_cmd_ready_int),
.rd_resp_data(dma_ram_rd_resp_data_int),
.rd_resp_valid(dma_ram_rd_resp_valid_int),
.rd_resp_ready(dma_ram_rd_resp_ready_int)
);
always @(posedge clk) begin
if (ram_wr_cmd_en) begin
// AXI write
// TODO byte enables
desc_table_data[ram_wr_cmd_addr[CL_DESC_TABLE_SIZE+5-1:5]] <= ram_wr_cmd_data;
end
end
dma_client_axis_source #(
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_LAST_ENABLE(1),
.AXIS_ID_ENABLE(1),
.AXIS_ID_WIDTH(REQ_TAG_WIDTH),
.AXIS_DEST_ENABLE(0),
.AXIS_USER_ENABLE(1),
.AXIS_USER_WIDTH(1),
.LEN_WIDTH(8),
.TAG_WIDTH(CL_DESC_TABLE_SIZE)
)
dma_client_axis_source_inst (
.clk(clk),
.rst(rst),
/*
* DMA read descriptor input
*/
.s_axis_read_desc_ram_addr(dma_read_desc_ram_addr_reg),
.s_axis_read_desc_len(dma_read_desc_len_reg),
.s_axis_read_desc_tag(dma_read_desc_tag_reg),
.s_axis_read_desc_id(dma_read_desc_id_reg),
.s_axis_read_desc_dest(0),
.s_axis_read_desc_user(dma_read_desc_user_reg),
.s_axis_read_desc_valid(dma_read_desc_valid_reg),
.s_axis_read_desc_ready(dma_read_desc_ready),
/*
* DMA read descriptor status output
*/
.m_axis_read_desc_status_tag(dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(dma_read_desc_status_valid),
/*
* AXI stream read data output
*/
.m_axis_read_data_tdata(m_axis_desc_tdata),
.m_axis_read_data_tkeep(m_axis_desc_tkeep),
.m_axis_read_data_tvalid(m_axis_desc_tvalid),
.m_axis_read_data_tready(m_axis_desc_tready),
.m_axis_read_data_tlast(m_axis_desc_tlast),
.m_axis_read_data_tid(m_axis_desc_tid),
.m_axis_read_data_tdest(),
.m_axis_read_data_tuser(m_axis_desc_tuser),
/*
* RAM interface
*/
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr_int),
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid_int),
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready_int),
.ram_rd_resp_data(dma_ram_rd_resp_data_int),
.ram_rd_resp_valid(dma_ram_rd_resp_valid_int),
.ram_rd_resp_ready(dma_ram_rd_resp_ready_int),
/*
* Configuration
*/
.enable(1'b1)
);
always @* begin
s_axis_req_ready_next = 1'b0;
@ -419,13 +426,6 @@ always @* begin
m_axis_req_status_error_next = m_axis_req_status_error_reg;
m_axis_req_status_valid_next = 1'b0;
m_axis_desc_tdata_next = m_axis_desc_tdata_reg;
m_axis_desc_tkeep_next = m_axis_desc_tkeep_reg;
m_axis_desc_tvalid_next = m_axis_desc_tvalid_reg && !m_axis_desc_tready;
m_axis_desc_tlast_next = m_axis_desc_tlast_reg;
m_axis_desc_tid_next = m_axis_desc_tid_reg;
m_axis_desc_tuser_next = m_axis_desc_tuser_reg;
m_axis_desc_dequeue_req_queue_next = m_axis_desc_dequeue_req_queue_reg;
m_axis_desc_dequeue_req_tag_next = m_axis_desc_dequeue_req_tag_reg;
m_axis_desc_dequeue_req_valid_next = m_axis_desc_dequeue_req_valid_reg & ~m_axis_desc_dequeue_req_ready;
@ -435,11 +435,18 @@ always @* begin
m_axis_desc_dequeue_commit_op_tag_next = m_axis_desc_dequeue_commit_op_tag_reg;
m_axis_desc_dequeue_commit_valid_next = m_axis_desc_dequeue_commit_valid_reg & ~m_axis_desc_dequeue_commit_ready;
m_axis_pcie_axi_dma_read_desc_pcie_addr_next = m_axis_pcie_axi_dma_read_desc_pcie_addr_reg;
m_axis_pcie_axi_dma_read_desc_axi_addr_next = m_axis_pcie_axi_dma_read_desc_axi_addr_reg;
m_axis_pcie_axi_dma_read_desc_len_next = m_axis_pcie_axi_dma_read_desc_len_reg;
m_axis_pcie_axi_dma_read_desc_tag_next = m_axis_pcie_axi_dma_read_desc_tag_reg;
m_axis_pcie_axi_dma_read_desc_valid_next = m_axis_pcie_axi_dma_read_desc_valid_reg && !m_axis_pcie_axi_dma_read_desc_ready;
m_axis_dma_read_desc_dma_addr_next = m_axis_dma_read_desc_dma_addr_reg;
m_axis_dma_read_desc_ram_addr_next = m_axis_dma_read_desc_ram_addr_reg;
m_axis_dma_read_desc_len_next = m_axis_dma_read_desc_len_reg;
m_axis_dma_read_desc_tag_next = m_axis_dma_read_desc_tag_reg;
m_axis_dma_read_desc_valid_next = m_axis_dma_read_desc_valid_reg && !m_axis_dma_read_desc_ready;
dma_read_desc_ram_addr_next = dma_read_desc_ram_addr_reg;
dma_read_desc_len_next = dma_read_desc_len_reg;
dma_read_desc_tag_next = dma_read_desc_tag_reg;
dma_read_desc_id_next = dma_read_desc_id_reg;
dma_read_desc_user_next = dma_read_desc_user_reg;
dma_read_desc_valid_next = dma_read_desc_valid_reg && !dma_read_desc_ready;
inc_active = 1'b0;
dec_active_1 = 1'b0;
@ -449,8 +456,11 @@ always @* begin
desc_table_start_tag = s_axis_desc_dequeue_resp_tag[dequeue_resp_enc*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH];
desc_table_start_queue_op_tag = s_axis_desc_dequeue_resp_op_tag[dequeue_resp_enc*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH];
desc_table_start_en = 1'b0;
desc_table_desc_fetched_ptr = s_axis_pcie_axi_dma_read_desc_status_tag & DESC_PTR_MASK;
desc_table_desc_fetched_ptr = s_axis_dma_read_desc_status_tag & DESC_PTR_MASK;
desc_table_desc_fetched_en = 1'b0;
desc_table_desc_read_en = 1'b0;
desc_table_desc_read_done_ptr = dma_read_desc_status_tag & DESC_PTR_MASK;
desc_table_desc_read_done_en = 1'b0;
desc_table_finish_en = 1'b0;
// queue query
@ -469,7 +479,7 @@ always @* begin
// descriptor fetch
// wait for queue query response
if (dequeue_resp_enc_valid && !m_axis_pcie_axi_dma_read_desc_valid_reg && !desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] && ($unsigned(desc_table_start_ptr_reg - desc_table_finish_ptr_reg) < DESC_TABLE_SIZE)) begin
if (dequeue_resp_enc_valid && !m_axis_dma_read_desc_valid_reg && !desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] && ($unsigned(desc_table_start_ptr_reg - desc_table_finish_ptr_reg) < DESC_TABLE_SIZE)) begin
s_axis_desc_dequeue_resp_ready_next = 1 << dequeue_resp_enc;
// store in descriptor table
@ -487,10 +497,10 @@ always @* begin
m_axis_req_status_valid_next = 1'b1;
// initiate descriptor fetch
m_axis_pcie_axi_dma_read_desc_pcie_addr_next = s_axis_desc_dequeue_resp_addr[dequeue_resp_enc*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH];
m_axis_pcie_axi_dma_read_desc_axi_addr_next = AXI_BASE_ADDR + ((desc_table_start_ptr_reg & DESC_PTR_MASK) << 5);
m_axis_pcie_axi_dma_read_desc_len_next = DESC_SIZE;
m_axis_pcie_axi_dma_read_desc_tag_next = (desc_table_start_ptr_reg & DESC_PTR_MASK);
m_axis_dma_read_desc_dma_addr_next = s_axis_desc_dequeue_resp_addr[dequeue_resp_enc*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH];
m_axis_dma_read_desc_ram_addr_next = (desc_table_start_ptr_reg & DESC_PTR_MASK) << 5;
m_axis_dma_read_desc_len_next = DESC_SIZE;
m_axis_dma_read_desc_tag_next = (desc_table_start_ptr_reg & DESC_PTR_MASK);
if (s_axis_desc_dequeue_resp_error[dequeue_resp_enc*1 +: 1] || s_axis_desc_dequeue_resp_empty[dequeue_resp_enc*1 +: 1]) begin
// queue empty or not active
@ -503,37 +513,54 @@ always @* begin
desc_table_start_en = 1'b1;
// initiate descriptor fetch
m_axis_pcie_axi_dma_read_desc_valid_next = 1'b1;
m_axis_dma_read_desc_valid_next = 1'b1;
end
end
// descriptor fetch completion
// wait for descriptor fetch completion
if (s_axis_pcie_axi_dma_read_desc_status_valid) begin
if (s_axis_dma_read_desc_status_valid) begin
// update entry in descriptor table
desc_table_desc_fetched_ptr = s_axis_pcie_axi_dma_read_desc_status_tag & DESC_PTR_MASK;
desc_table_desc_fetched_ptr = s_axis_dma_read_desc_status_tag & DESC_PTR_MASK;
desc_table_desc_fetched_en = 1'b1;
end
// return descriptor and finish operation
// return descriptor
// wait for descriptor fetch completion
// TODO descriptor validation?
if (desc_table_active[desc_table_finish_ptr_reg & DESC_PTR_MASK] && desc_table_finish_ptr_reg != desc_table_start_ptr_reg && !m_axis_desc_tvalid) begin
if (desc_table_desc_fetched[desc_table_finish_ptr_reg & DESC_PTR_MASK] && !(m_axis_desc_dequeue_commit_valid & 1 << desc_table_sel[desc_table_finish_ptr_reg & DESC_PTR_MASK]) && !m_axis_desc_tvalid) begin
// invalidate entry in descriptor table
desc_table_finish_en = 1'b1;
if (desc_table_active[desc_table_desc_read_ptr_reg & DESC_PTR_MASK] && desc_table_desc_read_ptr_reg != desc_table_start_ptr_reg) begin
if (desc_table_desc_fetched[desc_table_desc_read_ptr_reg & DESC_PTR_MASK] && !(m_axis_desc_dequeue_commit_valid & 1 << desc_table_sel[desc_table_desc_read_ptr_reg & DESC_PTR_MASK]) && !dma_read_desc_valid_reg) begin
// update entry in descriptor table
desc_table_desc_read_en = 1'b1;
// commit dequeue operation
m_axis_desc_dequeue_commit_op_tag_next = desc_table_queue_op_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK];
m_axis_desc_dequeue_commit_valid_next = 1 << desc_table_sel[desc_table_finish_ptr_reg & DESC_PTR_MASK];
m_axis_desc_dequeue_commit_op_tag_next = desc_table_queue_op_tag[desc_table_desc_read_ptr_reg & DESC_PTR_MASK];
m_axis_desc_dequeue_commit_valid_next = 1 << desc_table_sel[desc_table_desc_read_ptr_reg & DESC_PTR_MASK];
// return descriptor
m_axis_desc_tdata_next = desc_table_data[desc_table_finish_ptr_reg & DESC_PTR_MASK];
m_axis_desc_tkeep_next = {AXIS_KEEP_WIDTH{1'b1}};
m_axis_desc_tlast_next = 1'b1;
m_axis_desc_tid_next = desc_table_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK];
m_axis_desc_tuser_next = 1'b0;
m_axis_desc_tvalid_next = 1'b1;
// initiate descriptor read from DMA RAM
dma_read_desc_ram_addr_next = (desc_table_desc_read_ptr_reg & DESC_PTR_MASK) << 5;
dma_read_desc_len_next = DESC_SIZE;
dma_read_desc_tag_next = (desc_table_desc_read_ptr_reg & DESC_PTR_MASK);
dma_read_desc_id_next = desc_table_tag[desc_table_desc_read_ptr_reg & DESC_PTR_MASK];
dma_read_desc_user_next = 1'b0;
dma_read_desc_valid_next = 1'b1;
end
end
// descriptor read completion
// wait for descriptor read completion
if (dma_read_desc_status_valid) begin
// update entry in descriptor table
desc_table_desc_read_done_ptr = dma_read_desc_status_tag & DESC_PTR_MASK;
desc_table_desc_read_done_en = 1'b1;
end
// finish operation
// wait for descriptor read completion
if (desc_table_active[desc_table_finish_ptr_reg & DESC_PTR_MASK] && desc_table_finish_ptr_reg != desc_table_start_ptr_reg) begin
if (desc_table_desc_read_done[desc_table_finish_ptr_reg & DESC_PTR_MASK]) begin
// invalidate entry in descriptor table
desc_table_finish_en = 1'b1;
dec_active_2 = 1'b1;
end
@ -551,13 +578,6 @@ always @(posedge clk) begin
m_axis_req_status_error_reg <= m_axis_req_status_error_next;
m_axis_req_status_valid_reg <= m_axis_req_status_valid_next;
m_axis_desc_tdata_reg <= m_axis_desc_tdata_next;
m_axis_desc_tkeep_reg <= m_axis_desc_tkeep_next;
m_axis_desc_tvalid_reg <= m_axis_desc_tvalid_next;
m_axis_desc_tlast_reg <= m_axis_desc_tlast_next;
m_axis_desc_tid_reg <= m_axis_desc_tid_next;
m_axis_desc_tuser_reg <= m_axis_desc_tuser_next;
m_axis_desc_dequeue_req_queue_reg <= m_axis_desc_dequeue_req_queue_next;
m_axis_desc_dequeue_req_tag_reg <= m_axis_desc_dequeue_req_tag_next;
m_axis_desc_dequeue_req_valid_reg <= m_axis_desc_dequeue_req_valid_next;
@ -567,17 +587,25 @@ always @(posedge clk) begin
m_axis_desc_dequeue_commit_op_tag_reg <= m_axis_desc_dequeue_commit_op_tag_next;
m_axis_desc_dequeue_commit_valid_reg <= m_axis_desc_dequeue_commit_valid_next;
m_axis_pcie_axi_dma_read_desc_pcie_addr_reg <= m_axis_pcie_axi_dma_read_desc_pcie_addr_next;
m_axis_pcie_axi_dma_read_desc_axi_addr_reg <= m_axis_pcie_axi_dma_read_desc_axi_addr_next;
m_axis_pcie_axi_dma_read_desc_len_reg <= m_axis_pcie_axi_dma_read_desc_len_next;
m_axis_pcie_axi_dma_read_desc_tag_reg <= m_axis_pcie_axi_dma_read_desc_tag_next;
m_axis_pcie_axi_dma_read_desc_valid_reg <= m_axis_pcie_axi_dma_read_desc_valid_next;
m_axis_dma_read_desc_dma_addr_reg <= m_axis_dma_read_desc_dma_addr_next;
m_axis_dma_read_desc_ram_addr_reg <= m_axis_dma_read_desc_ram_addr_next;
m_axis_dma_read_desc_len_reg <= m_axis_dma_read_desc_len_next;
m_axis_dma_read_desc_tag_reg <= m_axis_dma_read_desc_tag_next;
m_axis_dma_read_desc_valid_reg <= m_axis_dma_read_desc_valid_next;
dma_read_desc_ram_addr_reg <= dma_read_desc_ram_addr_next;
dma_read_desc_len_reg <= dma_read_desc_len_next;
dma_read_desc_tag_reg <= dma_read_desc_tag_next;
dma_read_desc_id_reg <= dma_read_desc_id_next;
dma_read_desc_user_reg <= dma_read_desc_user_next;
dma_read_desc_valid_reg <= dma_read_desc_valid_next;
active_count_reg <= active_count_reg + inc_active - dec_active_1 - dec_active_2;
if (desc_table_start_en) begin
desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b1;
desc_table_desc_fetched[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
desc_table_desc_read_done[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
desc_table_sel[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_sel;
desc_table_tag[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_tag;
desc_table_queue_op_tag[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_queue_op_tag;
@ -588,6 +616,14 @@ always @(posedge clk) begin
desc_table_desc_fetched[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= 1'b1;
end
if (desc_table_desc_read_en) begin
desc_table_desc_read_ptr_reg <= desc_table_desc_read_ptr_reg + 1;
end
if (desc_table_desc_read_done_en) begin
desc_table_desc_read_done[desc_table_desc_read_done_ptr & DESC_PTR_MASK] <= 1'b1;
end
if (desc_table_finish_en) begin
desc_table_active[desc_table_finish_ptr_reg & DESC_PTR_MASK] <= 1'b0;
desc_table_finish_ptr_reg <= desc_table_finish_ptr_reg + 1;
@ -596,11 +632,12 @@ always @(posedge clk) begin
if (rst) begin
s_axis_req_ready_reg <= 1'b0;
m_axis_req_status_valid_reg <= 1'b0;
m_axis_desc_tvalid_reg <= 1'b0;
m_axis_desc_dequeue_req_valid_reg <= {PORTS{1'b0}};
s_axis_desc_dequeue_resp_ready_reg <= {PORTS{1'b0}};
m_axis_desc_dequeue_commit_valid_reg <= {PORTS{1'b0}};
m_axis_pcie_axi_dma_read_desc_valid_reg <= 1'b0;
m_axis_dma_read_desc_valid_reg <= 1'b0;
dma_read_desc_valid_reg <= 1'b0;
active_count_reg <= 0;
@ -608,6 +645,7 @@ always @(posedge clk) begin
desc_table_desc_fetched <= 0;
desc_table_start_ptr_reg <= 0;
desc_table_desc_read_ptr_reg <= 0;
desc_table_finish_ptr_reg <= 0;
end
end

1221
fpga/common/rtl/interface.v
View File

File diff suppressed because it is too large Load Diff

501
fpga/common/rtl/port.v
View File

@ -40,12 +40,12 @@ either expressed or implied, of The Regents of the University of California.
*/
module port #
(
// PCIe address width
parameter PCIE_ADDR_WIDTH = 64,
// PCIe DMA length field width
parameter PCIE_DMA_LEN_WIDTH = 16,
// PCIe DMA tag field width
parameter PCIE_DMA_TAG_WIDTH = 8,
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// DMA length field width
parameter DMA_LEN_WIDTH = 16,
// DMA tag field width
parameter DMA_TAG_WIDTH = 8,
// Request tag field width
parameter REQ_TAG_WIDTH = 8,
// Descriptor request tag field width
@ -96,30 +96,38 @@ module port #
parameter AXIL_ADDR_WIDTH = 16,
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = 256,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 16,
// Width of AXI wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// Maximum AXI burst length to generate
parameter AXI_MAX_BURST_LEN = 16,
// AXI base address of this module (as seen by PCIe DMA)
parameter AXI_BASE_ADDR = 0,
// AXI base address of TX packet RAM (as seen by PCIe DMA and AXI DMA in this module)
parameter TX_RAM_AXI_BASE_ADDR = 0,
// AXI base address of RX packet RAM (as seen by PCIe DMA and AXI DMA in this module)
parameter RX_RAM_AXI_BASE_ADDR = 0,
// DMA RAM segment count
parameter SEG_COUNT = 2,
// DMA RAM segment data width
parameter SEG_DATA_WIDTH = 64,
// DMA RAM segment address width
parameter SEG_ADDR_WIDTH = 8,
// DMA RAM segment byte enable width
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
// DMA RAM address width
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
// DMA RAM pipeline stages
parameter RAM_PIPELINE = 2,
// Width of AXI stream interfaces in bits
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
parameter AXIS_DATA_WIDTH = 256,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH,
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
// Max transmit packet size
parameter MAX_TX_SIZE = 2048,
// Max receive packet size
parameter MAX_RX_SIZE = 2048,
// Descriptor size (in bytes)
parameter DESC_SIZE = 16,
// Descriptor size (in bytes)
parameter CPL_SIZE = 32
parameter CPL_SIZE = 32,
// Width of AXI stream descriptor interfaces in bits
parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8,
// AXI stream descriptor tkeep signal width (words per cycle)
parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
// DMA TX RAM size
parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE,
// DMA RX RAM size
parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE
)
(
input wire clk,
@ -148,8 +156,8 @@ module port #
/*
* Descriptor data input
*/
input wire [AXIS_DATA_WIDTH-1:0] s_axis_desc_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata,
input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
input wire s_axis_desc_tvalid,
output wire s_axis_desc_tready,
input wire s_axis_desc_tlast,
@ -181,36 +189,36 @@ module port #
input wire s_axis_tx_doorbell_valid,
/*
* PCIe read descriptor output
* DMA read descriptor output
*/
output wire [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_pcie_addr,
output wire [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_axi_addr,
output wire [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_len,
output wire [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_tag,
output wire m_axis_pcie_axi_dma_read_desc_valid,
input wire m_axis_pcie_axi_dma_read_desc_ready,
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag,
output wire m_axis_dma_read_desc_valid,
input wire m_axis_dma_read_desc_ready,
/*
* PCIe read descriptor status input
* DMA read descriptor status input
*/
input wire [PCIE_DMA_TAG_WIDTH-1:0] s_axis_pcie_axi_dma_read_desc_status_tag,
input wire s_axis_pcie_axi_dma_read_desc_status_valid,
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag,
input wire s_axis_dma_read_desc_status_valid,
/*
* PCIe write descriptor output
* DMA write descriptor output
*/
output wire [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_pcie_addr,
output wire [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_axi_addr,
output wire [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_len,
output wire [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_tag,
output wire m_axis_pcie_axi_dma_write_desc_valid,
input wire m_axis_pcie_axi_dma_write_desc_ready,
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag,
output wire m_axis_dma_write_desc_valid,
input wire m_axis_dma_write_desc_ready,
/*
* PCIe write descriptor status input
* DMA write descriptor status input
*/
input wire [PCIE_DMA_TAG_WIDTH-1:0] s_axis_pcie_axi_dma_write_desc_status_tag,
input wire s_axis_pcie_axi_dma_write_desc_status_valid,
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
input wire s_axis_dma_write_desc_status_valid,
/*
* AXI-Lite slave interface
@ -236,43 +244,19 @@ module port #
input wire s_axil_rready,
/*
* AXI master interface
* RAM interface
*/
output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst,
output wire m_axi_awlock,
output wire [3:0] m_axi_awcache,
output wire [2:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst,
output wire m_axi_arlock,
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready,
input wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be,
input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr,
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data,
input wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid,
output wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready,
input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr,
input wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid,
output wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data,
output wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid,
input wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready,
/*
* Transmit data output
@ -315,8 +299,8 @@ module port #
input wire ptp_ts_step
);
parameter AXI_DMA_TAG_WIDTH = 8;
parameter AXI_DMA_LEN_WIDTH = 16;
parameter DMA_CLIENT_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE > RX_DESC_TABLE_SIZE ? TX_DESC_TABLE_SIZE : RX_DESC_TABLE_SIZE);
parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH;
parameter DESC_REQ_TAG_WIDTH_INT = DESC_REQ_TAG_WIDTH - $clog2(2);
@ -384,8 +368,8 @@ wire rx_desc_req_status_empty;
wire rx_desc_req_status_error;
wire rx_desc_req_status_valid;
wire [AXIS_DATA_WIDTH-1:0] rx_desc_tdata;
wire [AXIS_KEEP_WIDTH-1:0] rx_desc_tkeep;
wire [AXIS_DESC_DATA_WIDTH-1:0] rx_desc_tdata;
wire [AXIS_DESC_KEEP_WIDTH-1:0] rx_desc_tkeep;
wire rx_desc_tvalid;
wire rx_desc_tready;
wire rx_desc_tlast;
@ -406,8 +390,8 @@ wire tx_desc_req_status_empty;
wire tx_desc_req_status_error;
wire tx_desc_req_status_valid;
wire [AXIS_DATA_WIDTH-1:0] tx_desc_tdata;
wire [AXIS_KEEP_WIDTH-1:0] tx_desc_tkeep;
wire [AXIS_DESC_DATA_WIDTH-1:0] tx_desc_tdata;
wire [AXIS_DESC_KEEP_WIDTH-1:0] tx_desc_tkeep;
wire tx_desc_tvalid;
wire tx_desc_tready;
wire tx_desc_tlast;
@ -444,7 +428,7 @@ wire [REQ_TAG_WIDTH-1:0] tx_req_tag;
wire tx_req_valid;
wire tx_req_ready;
wire [AXI_DMA_LEN_WIDTH-1:0] tx_req_status_len;
wire [DMA_CLIENT_LEN_WIDTH-1:0] tx_req_status_len;
wire [REQ_TAG_WIDTH-1:0] tx_req_status_tag;
wire tx_req_status_valid;
@ -499,28 +483,28 @@ wire tx_fifo_csum_cmd_valid;
wire tx_fifo_csum_cmd_ready;
// Interface DMA control
wire [AXI_ADDR_WIDTH-1:0] dma_tx_desc_addr;
wire [AXI_DMA_LEN_WIDTH-1:0] dma_tx_desc_len;
wire [AXI_DMA_TAG_WIDTH-1:0] dma_tx_desc_tag;
wire dma_tx_desc_user;
wire dma_tx_desc_valid;
wire dma_tx_desc_ready;
wire [RAM_ADDR_WIDTH-1:0] dma_tx_desc_addr;
wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_tx_desc_len;
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_tag;
wire dma_tx_desc_user;
wire dma_tx_desc_valid;
wire dma_tx_desc_ready;
wire [AXI_DMA_TAG_WIDTH-1:0] dma_tx_desc_status_tag;
wire dma_tx_desc_status_valid;
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_status_tag;
wire dma_tx_desc_status_valid;
wire [AXI_ADDR_WIDTH-1:0] dma_rx_desc_addr;
wire [AXI_DMA_LEN_WIDTH-1:0] dma_rx_desc_len;
wire [AXI_DMA_TAG_WIDTH-1:0] dma_rx_desc_tag;
wire dma_rx_desc_valid;
wire dma_rx_desc_ready;
wire [RAM_ADDR_WIDTH-1:0] dma_rx_desc_addr;
wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_len;
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_tag;
wire dma_rx_desc_valid;
wire dma_rx_desc_ready;
wire [AXI_DMA_LEN_WIDTH-1:0] dma_rx_desc_status_len;
wire [AXI_DMA_TAG_WIDTH-1:0] dma_rx_desc_status_tag;
wire dma_rx_desc_status_user;
wire dma_rx_desc_status_valid;
wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_status_len;
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_status_tag;
wire dma_rx_desc_status_user;
wire dma_rx_desc_status_valid;
wire dma_enable = 1;
wire dma_enable = 1;
// Port control registers
reg axil_ctrl_awready_reg = 1'b0;
@ -746,8 +730,8 @@ desc_op_mux #(
.CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH),
.S_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
.M_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
@ -877,7 +861,7 @@ if (TX_SCHEDULER == "RR") begin
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(20),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.AXI_DMA_LEN_WIDTH(AXI_DMA_LEN_WIDTH),
.DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
@ -944,7 +928,7 @@ end else if (TX_SCHEDULER == "TDMA_RR") begin
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(20),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.AXI_DMA_LEN_WIDTH(AXI_DMA_LEN_WIDTH),
.DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.TDMA_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
@ -1017,16 +1001,14 @@ end
endgenerate
tx_engine #(
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.AXI_DMA_LEN_WIDTH(AXI_DMA_LEN_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
.PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.AXI_DMA_TAG_WIDTH(AXI_DMA_TAG_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH),
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
@ -1034,7 +1016,11 @@ tx_engine #(
.CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE),
.SCRATCH_PKT_AXI_ADDR(TX_RAM_AXI_BASE_ADDR),
.MAX_TX_SIZE(MAX_TX_SIZE),
.DESC_SIZE(DESC_SIZE),
.CPL_SIZE(CPL_SIZE),
.AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
.AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE)
)
@ -1105,20 +1091,20 @@ tx_engine_inst (
.s_axis_cpl_req_status_valid(tx_cpl_req_status_valid),
/*
* PCIe DMA read descriptor output
* DMA read descriptor output
*/
.m_axis_pcie_axi_dma_read_desc_pcie_addr(m_axis_pcie_axi_dma_read_desc_pcie_addr),
.m_axis_pcie_axi_dma_read_desc_axi_addr(m_axis_pcie_axi_dma_read_desc_axi_addr),
.m_axis_pcie_axi_dma_read_desc_len(m_axis_pcie_axi_dma_read_desc_len),
.m_axis_pcie_axi_dma_read_desc_tag(m_axis_pcie_axi_dma_read_desc_tag),
.m_axis_pcie_axi_dma_read_desc_valid(m_axis_pcie_axi_dma_read_desc_valid),
.m_axis_pcie_axi_dma_read_desc_ready(m_axis_pcie_axi_dma_read_desc_ready),
.m_axis_dma_read_desc_dma_addr(m_axis_dma_read_desc_dma_addr),
.m_axis_dma_read_desc_ram_addr(m_axis_dma_read_desc_ram_addr),
.m_axis_dma_read_desc_len(m_axis_dma_read_desc_len),
.m_axis_dma_read_desc_tag(m_axis_dma_read_desc_tag),
.m_axis_dma_read_desc_valid(m_axis_dma_read_desc_valid),
.m_axis_dma_read_desc_ready(m_axis_dma_read_desc_ready),
/*
* PCIe DMA read descriptor status input
* DMA read descriptor status input
*/
.s_axis_pcie_axi_dma_read_desc_status_tag(s_axis_pcie_axi_dma_read_desc_status_tag),
.s_axis_pcie_axi_dma_read_desc_status_valid(s_axis_pcie_axi_dma_read_desc_status_valid),
.s_axis_dma_read_desc_status_tag(s_axis_dma_read_desc_status_tag),
.s_axis_dma_read_desc_status_valid(s_axis_dma_read_desc_status_valid),
/*
* Transmit descriptor output
@ -1159,24 +1145,26 @@ tx_engine_inst (
);
rx_engine #(
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.AXI_DMA_LEN_WIDTH(AXI_DMA_LEN_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
.PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.AXI_DMA_TAG_WIDTH(AXI_DMA_TAG_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH),
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.DESC_SIZE(DESC_SIZE),
.CPL_SIZE(CPL_SIZE),
.AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
.AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
.PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
.SCRATCH_PKT_AXI_ADDR(RX_RAM_AXI_BASE_ADDR),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE)
)
@ -1246,20 +1234,20 @@ rx_engine_inst (
.s_axis_cpl_req_status_valid(rx_cpl_req_status_valid),
/*
* PCIe DMA write descriptor output
* DMA write descriptor output
*/
.m_axis_pcie_axi_dma_write_desc_pcie_addr(m_axis_pcie_axi_dma_write_desc_pcie_addr),
.m_axis_pcie_axi_dma_write_desc_axi_addr(m_axis_pcie_axi_dma_write_desc_axi_addr),
.m_axis_pcie_axi_dma_write_desc_len(m_axis_pcie_axi_dma_write_desc_len),
.m_axis_pcie_axi_dma_write_desc_tag(m_axis_pcie_axi_dma_write_desc_tag),
.m_axis_pcie_axi_dma_write_desc_valid(m_axis_pcie_axi_dma_write_desc_valid),
.m_axis_pcie_axi_dma_write_desc_ready(m_axis_pcie_axi_dma_write_desc_ready),
.m_axis_dma_write_desc_dma_addr(m_axis_dma_write_desc_dma_addr),
.m_axis_dma_write_desc_ram_addr(m_axis_dma_write_desc_ram_addr),
.m_axis_dma_write_desc_len(m_axis_dma_write_desc_len),
.m_axis_dma_write_desc_tag(m_axis_dma_write_desc_tag),
.m_axis_dma_write_desc_valid(m_axis_dma_write_desc_valid),
.m_axis_dma_write_desc_ready(m_axis_dma_write_desc_ready),
/*
* PCIe DMA write descriptor status input
* DMA write descriptor status input
*/
.s_axis_pcie_axi_dma_write_desc_status_tag(s_axis_pcie_axi_dma_write_desc_status_tag),
.s_axis_pcie_axi_dma_write_desc_status_valid(s_axis_pcie_axi_dma_write_desc_status_valid),
.s_axis_dma_write_desc_status_tag(s_axis_dma_write_desc_status_tag),
.s_axis_dma_write_desc_status_valid(s_axis_dma_write_desc_status_valid),
/*
* Receive descriptor output
@ -1303,7 +1291,7 @@ generate
if (RX_CHECKSUM_ENABLE) begin
rx_checksum #(
.DATA_WIDTH(AXI_DATA_WIDTH)
.DATA_WIDTH(AXIS_DATA_WIDTH)
)
rx_checksum_inst (
.clk(clk),
@ -1406,7 +1394,7 @@ if (TX_CHECKSUM_ENABLE) begin
);
tx_checksum #(
.DATA_WIDTH(AXI_DATA_WIDTH),
.DATA_WIDTH(AXIS_DATA_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
@ -1469,12 +1457,52 @@ end
endgenerate
axi_dma #(
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr_int;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid_int;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready_int;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data_int;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid_int;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready_int;
dma_psdpram #(
.SIZE(TX_RAM_SIZE),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.PIPELINE(RAM_PIPELINE)
)
dma_psdpram_tx_inst (
/*
* Write port
*/
.clk_wr(clk),
.rst_wr(rst),
.wr_cmd_be(dma_ram_wr_cmd_be),
.wr_cmd_addr(dma_ram_wr_cmd_addr),
.wr_cmd_data(dma_ram_wr_cmd_data),
.wr_cmd_valid(dma_ram_wr_cmd_valid),
.wr_cmd_ready(dma_ram_wr_cmd_ready),
/*
* Read port
*/
.clk_rd(clk),
.rst_rd(rst),
.rd_cmd_addr(dma_ram_rd_cmd_addr_int),
.rd_cmd_valid(dma_ram_rd_cmd_valid_int),
.rd_cmd_ready(dma_ram_rd_cmd_ready_int),
.rd_resp_data(dma_ram_rd_resp_data_int),
.rd_resp_valid(dma_ram_rd_resp_valid_int),
.rd_resp_ready(dma_ram_rd_resp_ready_int)
);
dma_client_axis_source #(
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
@ -1483,16 +1511,17 @@ axi_dma #(
.AXIS_DEST_ENABLE(0),
.AXIS_USER_ENABLE(1),
.AXIS_USER_WIDTH(1),
.LEN_WIDTH(AXI_DMA_LEN_WIDTH),
.TAG_WIDTH(AXI_DMA_TAG_WIDTH),
.ENABLE_SG(0),
.ENABLE_UNALIGNED(0)
.LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
.TAG_WIDTH(DMA_CLIENT_TAG_WIDTH)
)
axi_dma_inst (
dma_client_axis_source_inst (
.clk(clk),
.rst(rst),
.s_axis_read_desc_addr(dma_tx_desc_addr),
/*
* DMA read descriptor input
*/
.s_axis_read_desc_ram_addr(dma_tx_desc_addr),
.s_axis_read_desc_len(dma_tx_desc_len),
.s_axis_read_desc_tag(dma_tx_desc_tag),
.s_axis_read_desc_id(0),
@ -1501,9 +1530,15 @@ axi_dma_inst (
.s_axis_read_desc_valid(dma_tx_desc_valid),
.s_axis_read_desc_ready(dma_tx_desc_ready),
/*
* DMA read descriptor status output
*/
.m_axis_read_desc_status_tag(dma_tx_desc_status_tag),
.m_axis_read_desc_status_valid(dma_tx_desc_status_valid),
/*
* AXI stream read data output
*/
.m_axis_read_data_tdata(tx_axis_tdata_int),
.m_axis_read_data_tkeep(tx_axis_tkeep_int),
.m_axis_read_data_tvalid(tx_axis_tvalid_int),
@ -1513,12 +1548,94 @@ axi_dma_inst (
.m_axis_read_data_tdest(),
.m_axis_read_data_tuser(tx_axis_tuser_int),
.s_axis_write_desc_addr(dma_rx_desc_addr),
/*
* RAM interface
*/
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr_int),
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid_int),
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready_int),
.ram_rd_resp_data(dma_ram_rd_resp_data_int),
.ram_rd_resp_valid(dma_ram_rd_resp_valid_int),
.ram_rd_resp_ready(dma_ram_rd_resp_ready_int),
/*
* Configuration
*/
.enable(dma_enable)
);
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be_int;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr_int;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data_int;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid_int;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready_int;
dma_psdpram #(
.SIZE(RX_RAM_SIZE),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.PIPELINE(RAM_PIPELINE)
)
dma_psdpram_rx_inst (
/*
* Write port
*/
.clk_wr(clk),
.rst_wr(rst),
.wr_cmd_be(dma_ram_wr_cmd_be_int),
.wr_cmd_addr(dma_ram_wr_cmd_addr_int),
.wr_cmd_data(dma_ram_wr_cmd_data_int),
.wr_cmd_valid(dma_ram_wr_cmd_valid_int),
.wr_cmd_ready(dma_ram_wr_cmd_ready_int),
/*
* Read port
*/
.clk_rd(clk),
.rst_rd(rst),
.rd_cmd_addr(dma_ram_rd_cmd_addr),
.rd_cmd_valid(dma_ram_rd_cmd_valid),
.rd_cmd_ready(dma_ram_rd_cmd_ready),
.rd_resp_data(dma_ram_rd_resp_data),
.rd_resp_valid(dma_ram_rd_resp_valid),
.rd_resp_ready(dma_ram_rd_resp_ready)
);
dma_client_axis_sink #(
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_LAST_ENABLE(1),
.AXIS_ID_ENABLE(0),
.AXIS_DEST_ENABLE(0),
.AXIS_USER_ENABLE(1),
.AXIS_USER_WIDTH(1),
.LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
.TAG_WIDTH(DMA_CLIENT_TAG_WIDTH)
)
dma_client_axis_sink_inst (
.clk(clk),
.rst(rst),
/*
* DMA write descriptor input
*/
.s_axis_write_desc_ram_addr(dma_rx_desc_addr),
.s_axis_write_desc_len(dma_rx_desc_len),
.s_axis_write_desc_tag(dma_rx_desc_tag),
.s_axis_write_desc_valid(dma_rx_desc_valid),
.s_axis_write_desc_ready(dma_rx_desc_ready),
/*
* DMA write descriptor status output
*/
.m_axis_write_desc_status_len(dma_rx_desc_status_len),
.m_axis_write_desc_status_tag(dma_rx_desc_status_tag),
.m_axis_write_desc_status_id(),
@ -1526,6 +1643,9 @@ axi_dma_inst (
.m_axis_write_desc_status_user(dma_rx_desc_status_user),
.m_axis_write_desc_status_valid(dma_rx_desc_status_valid),
/*
* AXI stream write data input
*/
.s_axis_write_data_tdata(rx_axis_tdata),
.s_axis_write_data_tkeep(rx_axis_tkeep),
.s_axis_write_data_tvalid(rx_axis_tvalid),
@ -1535,45 +1655,20 @@ axi_dma_inst (
.s_axis_write_data_tdest(0),
.s_axis_write_data_tuser(rx_axis_tuser),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready),
/*
* RAM interface
*/
.ram_wr_cmd_be(dma_ram_wr_cmd_be_int),
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr_int),
.ram_wr_cmd_data(dma_ram_wr_cmd_data_int),
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid_int),
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready_int),
.read_enable(dma_enable),
.write_enable(dma_enable),
.write_abort(1'b0)
/*
* Configuration
*/
.enable(dma_enable),
.abort(1'b0)
);
endmodule

232
fpga/common/rtl/rx_engine.v
View File

@ -40,32 +40,22 @@ either expressed or implied, of The Regents of the University of California.
*/
module rx_engine #
(
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = 256,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 16,
// Width of AXI wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// Width of AXI stream interface in bits
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH,
// PCIe address width
parameter PCIE_ADDR_WIDTH = 64,
// PCIe DMA length field width
parameter PCIE_DMA_LEN_WIDTH = 20,
// AXI DMA length field width
parameter AXI_DMA_LEN_WIDTH = 20,
// DMA RAM address width
parameter RAM_ADDR_WIDTH = 16,
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// DMA length field width
parameter DMA_LEN_WIDTH = 20,
// DMA client length field width
parameter DMA_CLIENT_LEN_WIDTH = 20,
// Receive request tag field width
parameter REQ_TAG_WIDTH = 8,
// Descriptor request tag field width
parameter DESC_REQ_TAG_WIDTH = 8,
// PCIe DMA tag field width
parameter PCIE_DMA_TAG_WIDTH = 8,
// AXI DMA tag field width
parameter AXI_DMA_TAG_WIDTH = 8,
// DMA tag field width
parameter DMA_TAG_WIDTH = 8,
// DMA client tag field width
parameter DMA_CLIENT_TAG_WIDTH = 8,
// Queue request tag field width
parameter QUEUE_REQ_TAG_WIDTH = 8,
// Queue operation tag field width
@ -86,10 +76,10 @@ module rx_engine #
parameter DESC_SIZE = 16,
// Descriptor size (in bytes)
parameter CPL_SIZE = 32,
// AXI address of packet scratchpad RAM (as seen by PCIe DMA and port AXI DMA)
parameter SCRATCH_PKT_AXI_ADDR = 16'h1000,
// Packet scratchpad RAM log segment size
parameter SCRATCH_PKT_AXI_ADDR_SHIFT = 12,
// Width of AXI stream descriptor interfaces in bits
parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8,
// AXI stream descriptor tkeep signal width (words per cycle)
parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// Enable RX checksum offload
@ -110,7 +100,7 @@ module rx_engine #
/*
* Receive request status output
*/
output wire [AXI_DMA_LEN_WIDTH-1:0] m_axis_rx_req_status_len,
output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_rx_req_status_len,
output wire [REQ_TAG_WIDTH-1:0] m_axis_rx_req_status_tag,
output wire m_axis_rx_req_status_valid,
@ -136,8 +126,8 @@ module rx_engine #
/*
* Descriptor data input
*/
input wire [AXIS_DATA_WIDTH-1:0] s_axis_desc_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata,
input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
input wire s_axis_desc_tvalid,
output wire s_axis_desc_tready,
input wire s_axis_desc_tlast,
@ -162,35 +152,35 @@ module rx_engine #
input wire s_axis_cpl_req_status_valid,
/*
* PCIe AXI DMA write descriptor output
* DMA write descriptor output
*/
output wire [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_pcie_addr,
output wire [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_axi_addr,
output wire [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_len,
output wire [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_tag,
output wire m_axis_pcie_axi_dma_write_desc_valid,
input wire m_axis_pcie_axi_dma_write_desc_ready,
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag,
output wire m_axis_dma_write_desc_valid,
input wire m_axis_dma_write_desc_ready,
/*
* PCIe AXI DMA write descriptor status input
* DMA write descriptor status input
*/
input wire [PCIE_DMA_TAG_WIDTH-1:0] s_axis_pcie_axi_dma_write_desc_status_tag,
input wire s_axis_pcie_axi_dma_write_desc_status_valid,
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
input wire s_axis_dma_write_desc_status_valid,
/*
* Receive descriptor output
*/
output wire [AXI_ADDR_WIDTH-1:0] m_axis_rx_desc_addr,
output wire [AXI_DMA_LEN_WIDTH-1:0] m_axis_rx_desc_len,
output wire [AXI_DMA_TAG_WIDTH-1:0] m_axis_rx_desc_tag,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_rx_desc_addr,
output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_rx_desc_len,
output wire [DMA_CLIENT_TAG_WIDTH-1:0] m_axis_rx_desc_tag,
output wire m_axis_rx_desc_valid,
input wire m_axis_rx_desc_ready,
/*
* Receive descriptor status input
*/
input wire [AXI_DMA_LEN_WIDTH-1:0] s_axis_rx_desc_status_len,
input wire [AXI_DMA_TAG_WIDTH-1:0] s_axis_rx_desc_status_tag,
input wire [DMA_CLIENT_LEN_WIDTH-1:0] s_axis_rx_desc_status_len,
input wire [DMA_CLIENT_TAG_WIDTH-1:0] s_axis_rx_desc_status_tag,
input wire s_axis_rx_desc_status_user,
input wire s_axis_rx_desc_status_valid,
@ -204,8 +194,8 @@ module rx_engine #
/*
* Receive checksum input
*/
input wire [15:0] s_axis_rx_csum,
input wire s_axis_rx_csum_valid,
input wire [15:0] s_axis_rx_csum,
input wire s_axis_rx_csum_valid,
output wire s_axis_rx_csum_ready,
/*
@ -214,44 +204,21 @@ module rx_engine #
input wire enable
);
parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
parameter CL_DESC_TABLE_SIZE = $clog2(DESC_TABLE_SIZE);
parameter DESC_PTR_MASK = {CL_DESC_TABLE_SIZE{1'b1}};
parameter CL_PKT_TABLE_SIZE = $clog2(PKT_TABLE_SIZE);
parameter PKT_TAG_MASK = {CL_PKT_TABLE_SIZE{1'b1}};
parameter CL_MAX_RX_SIZE = $clog2(MAX_RX_SIZE);
// bus width assertions
initial begin
if (PCIE_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
$error("Error: PCIe tag width insufficient for descriptor table size (instance %m)");
if (DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
$error("Error: DMA tag width insufficient for descriptor table size (instance %m)");
$finish;
end
if (AXI_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
$error("Error: AXI tag width insufficient for descriptor table size (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (SCRATCH_PKT_AXI_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
$error("Error: AXI base address must be aligned to interface width (instance %m)");
$finish;
end
if (SCRATCH_PKT_AXI_ADDR_SHIFT < $clog2(AXI_STRB_WIDTH)) begin
$error("Error: Packet scratch address increment must be aligned to interface width (instance %m)");
$finish;
end
if (SCRATCH_PKT_AXI_ADDR_SHIFT < $clog2(MAX_RX_SIZE)) begin
$error("Error: Packet scratch address increment must be at least as large as one packet (instance %m)");
if (DMA_CLIENT_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
$error("Error: DMA client tag width insufficient for descriptor table size (instance %m)");
$finish;
end
@ -268,7 +235,7 @@ end
reg s_axis_rx_req_ready_reg = 1'b0, s_axis_rx_req_ready_next;
reg [AXI_DMA_LEN_WIDTH-1:0] m_axis_rx_req_status_len_reg = {AXI_DMA_LEN_WIDTH{1'b0}}, m_axis_rx_req_status_len_next;
reg [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_rx_req_status_len_reg = {DMA_CLIENT_LEN_WIDTH{1'b0}}, m_axis_rx_req_status_len_next;
reg [REQ_TAG_WIDTH-1:0] m_axis_rx_req_status_tag_reg = {REQ_TAG_WIDTH{1'b0}}, m_axis_rx_req_status_tag_next;
reg m_axis_rx_req_status_valid_reg = 1'b0, m_axis_rx_req_status_valid_next;
@ -283,15 +250,15 @@ reg [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {DESC_REQ_TAG_WIDTH{1'b0}}
reg [CPL_SIZE*8-1:0] m_axis_cpl_req_data_reg = {CPL_SIZE*8{1'b0}}, m_axis_cpl_req_data_next;
reg m_axis_cpl_req_valid_reg = 1'b0, m_axis_cpl_req_valid_next;
reg [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_pcie_addr_next;
reg [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_axi_addr_next;
reg [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_len_next;
reg [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_tag_next;
reg m_axis_pcie_axi_dma_write_desc_valid_reg = 1'b0, m_axis_pcie_axi_dma_write_desc_valid_next;
reg [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr_reg = {DMA_ADDR_WIDTH{1'b0}}, m_axis_dma_write_desc_dma_addr_next;
reg [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, m_axis_dma_write_desc_ram_addr_next;
reg [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len_reg = {DMA_LEN_WIDTH{1'b0}}, m_axis_dma_write_desc_len_next;
reg [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag_reg = {DMA_TAG_WIDTH{1'b0}}, m_axis_dma_write_desc_tag_next;
reg m_axis_dma_write_desc_valid_reg = 1'b0, m_axis_dma_write_desc_valid_next;
reg [AXI_ADDR_WIDTH-1:0] m_axis_rx_desc_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_rx_desc_addr_next;
reg [AXI_DMA_LEN_WIDTH-1:0] m_axis_rx_desc_len_reg = {AXI_DMA_LEN_WIDTH{1'b0}}, m_axis_rx_desc_len_next;
reg [AXI_DMA_TAG_WIDTH-1:0] m_axis_rx_desc_tag_reg = {AXI_DMA_TAG_WIDTH{1'b0}}, m_axis_rx_desc_tag_next;
reg [RAM_ADDR_WIDTH-1:0] m_axis_rx_desc_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, m_axis_rx_desc_addr_next;
reg [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_rx_desc_len_reg = {DMA_CLIENT_LEN_WIDTH{1'b0}}, m_axis_rx_desc_len_next;
reg [DMA_CLIENT_TAG_WIDTH-1:0] m_axis_rx_desc_tag_reg = {DMA_CLIENT_TAG_WIDTH{1'b0}}, m_axis_rx_desc_tag_next;
reg m_axis_rx_desc_valid_reg = 1'b0, m_axis_rx_desc_valid_next;
reg s_axis_rx_ptp_ts_ready_reg = 1'b0, s_axis_rx_ptp_ts_ready_next;
@ -308,9 +275,9 @@ reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0];
reg [QUEUE_INDEX_WIDTH-1:0] desc_table_queue[DESC_TABLE_SIZE-1:0];
reg [QUEUE_PTR_WIDTH-1:0] desc_table_queue_ptr[DESC_TABLE_SIZE-1:0];
reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0];
reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_dma_len[DESC_TABLE_SIZE-1:0];
reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_desc_len[DESC_TABLE_SIZE-1:0];
reg [PCIE_ADDR_WIDTH-1:0] desc_table_pcie_addr[DESC_TABLE_SIZE-1:0];
reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_dma_len[DESC_TABLE_SIZE-1:0];
reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_desc_len[DESC_TABLE_SIZE-1:0];
reg [DMA_ADDR_WIDTH-1:0] desc_table_dma_addr[DESC_TABLE_SIZE-1:0];
reg [CL_PKT_TABLE_SIZE-1:0] desc_table_pkt[DESC_TABLE_SIZE-1:0];
reg [95:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0];
reg [15:0] desc_table_csum[DESC_TABLE_SIZE-1:0];
@ -321,7 +288,7 @@ reg [REQ_TAG_WIDTH-1:0] desc_table_start_tag;
reg [CL_PKT_TABLE_SIZE-1:0] desc_table_start_pkt;
reg desc_table_start_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_rx_finish_ptr;
reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_rx_finish_len;
reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_rx_finish_len;
reg desc_table_rx_finish_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_dequeue_start_ptr_reg = 0;
reg desc_table_dequeue_start_en;
@ -331,8 +298,8 @@ reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_dequeue_cpl_queue;
reg desc_table_dequeue_invalid;
reg desc_table_dequeue_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_desc_fetched_ptr;
reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_desc_fetched_len;
reg [PCIE_ADDR_WIDTH-1:0] desc_table_desc_fetched_pcie_addr;
reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_desc_fetched_len;
reg [DMA_ADDR_WIDTH-1:0] desc_table_desc_fetched_dma_addr;
reg desc_table_desc_fetched_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_data_write_start_ptr_reg = 0;
reg desc_table_data_write_start_en;
@ -374,11 +341,11 @@ assign m_axis_cpl_req_tag = m_axis_cpl_req_tag_reg;
assign m_axis_cpl_req_data = m_axis_cpl_req_data_reg;
assign m_axis_cpl_req_valid = m_axis_cpl_req_valid_reg;
assign m_axis_pcie_axi_dma_write_desc_pcie_addr = m_axis_pcie_axi_dma_write_desc_pcie_addr_reg;
assign m_axis_pcie_axi_dma_write_desc_axi_addr = m_axis_pcie_axi_dma_write_desc_axi_addr_reg;
assign m_axis_pcie_axi_dma_write_desc_len = m_axis_pcie_axi_dma_write_desc_len_reg;
assign m_axis_pcie_axi_dma_write_desc_tag = m_axis_pcie_axi_dma_write_desc_tag_reg;
assign m_axis_pcie_axi_dma_write_desc_valid = m_axis_pcie_axi_dma_write_desc_valid_reg;
assign m_axis_dma_write_desc_dma_addr = m_axis_dma_write_desc_dma_addr_reg;
assign m_axis_dma_write_desc_ram_addr = m_axis_dma_write_desc_ram_addr_reg;
assign m_axis_dma_write_desc_len = m_axis_dma_write_desc_len_reg;
assign m_axis_dma_write_desc_tag = m_axis_dma_write_desc_tag_reg;
assign m_axis_dma_write_desc_valid = m_axis_dma_write_desc_valid_reg;
assign m_axis_rx_desc_addr = m_axis_rx_desc_addr_reg;
assign m_axis_rx_desc_len = m_axis_rx_desc_len_reg;
@ -427,10 +394,10 @@ pkt_table_free_enc_inst (
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({desc_table_active, desc_table_rx_done, desc_table_invalid, desc_table_desc_fetched, desc_table_data_written, desc_table_cpl_write_done, pkt_table_active,
// m_axis_pcie_axi_dma_read_desc_len, m_axis_pcie_axi_dma_read_desc_tag, m_axis_pcie_axi_dma_read_desc_valid, m_axis_pcie_axi_dma_read_desc_ready,
// s_axis_pcie_axi_dma_read_desc_status_tag, s_axis_pcie_axi_dma_read_desc_status_valid,
// m_axis_pcie_axi_dma_write_desc_len, m_axis_pcie_axi_dma_write_desc_tag, m_axis_pcie_axi_dma_write_desc_valid, m_axis_pcie_axi_dma_write_desc_ready,
// s_axis_pcie_axi_dma_write_desc_status_tag, s_axis_pcie_axi_dma_write_desc_status_valid}),
// m_axis_dma_read_desc_len, m_axis_dma_read_desc_tag, m_axis_dma_read_desc_valid, m_axis_dma_read_desc_ready,
// s_axis_dma_read_desc_status_tag, s_axis_dma_read_desc_status_valid,
// m_axis_dma_write_desc_len, m_axis_dma_write_desc_tag, m_axis_dma_write_desc_valid, m_axis_dma_write_desc_ready,
// s_axis_dma_write_desc_status_tag, s_axis_dma_write_desc_status_valid}),
// .probe1(0),
// .probe2(0),
// .probe3(s_axis_rx_req_ready),
@ -456,11 +423,11 @@ always @* begin
m_axis_cpl_req_data_next = m_axis_cpl_req_data_reg;
m_axis_cpl_req_valid_next = m_axis_cpl_req_valid_reg && !m_axis_cpl_req_ready;
m_axis_pcie_axi_dma_write_desc_pcie_addr_next = m_axis_pcie_axi_dma_write_desc_pcie_addr_reg;
m_axis_pcie_axi_dma_write_desc_axi_addr_next = m_axis_pcie_axi_dma_write_desc_axi_addr_reg;
m_axis_pcie_axi_dma_write_desc_len_next = m_axis_pcie_axi_dma_write_desc_len_reg;
m_axis_pcie_axi_dma_write_desc_tag_next = m_axis_pcie_axi_dma_write_desc_tag_reg;
m_axis_pcie_axi_dma_write_desc_valid_next = m_axis_pcie_axi_dma_write_desc_valid_reg && !m_axis_pcie_axi_dma_write_desc_ready;
m_axis_dma_write_desc_dma_addr_next = m_axis_dma_write_desc_dma_addr_reg;
m_axis_dma_write_desc_ram_addr_next = m_axis_dma_write_desc_ram_addr_reg;
m_axis_dma_write_desc_len_next = m_axis_dma_write_desc_len_reg;
m_axis_dma_write_desc_tag_next = m_axis_dma_write_desc_tag_reg;
m_axis_dma_write_desc_valid_next = m_axis_dma_write_desc_valid_reg && !m_axis_dma_write_desc_ready;
m_axis_rx_desc_addr_next = m_axis_rx_desc_addr_reg;
m_axis_rx_desc_len_next = m_axis_rx_desc_len_reg;
@ -486,10 +453,10 @@ always @* begin
desc_table_dequeue_en = 1'b0;
desc_table_desc_fetched_ptr = s_axis_desc_tid & DESC_PTR_MASK;
desc_table_desc_fetched_len = s_axis_desc_tdata[64:32];
desc_table_desc_fetched_pcie_addr = s_axis_desc_tdata[127:64];
desc_table_desc_fetched_dma_addr = s_axis_desc_tdata[127:64];
desc_table_desc_fetched_en = 1'b0;
desc_table_data_write_start_en = 1'b0;
desc_table_data_written_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
desc_table_data_written_ptr = s_axis_dma_write_desc_status_tag & DESC_PTR_MASK;
desc_table_data_written_en = 1'b0;
desc_table_store_ptp_ts = s_axis_rx_ptp_ts_96;
desc_table_store_ptp_ts_en = 1'b0;
@ -522,7 +489,7 @@ always @* begin
pkt_table_start_en = 1'b1;
// initiate receive operation
m_axis_rx_desc_addr_next = SCRATCH_PKT_AXI_ADDR + (pkt_table_free_ptr << SCRATCH_PKT_AXI_ADDR_SHIFT);
m_axis_rx_desc_addr_next = pkt_table_free_ptr << CL_MAX_RX_SIZE;
m_axis_rx_desc_len_next = MAX_RX_SIZE;
m_axis_rx_desc_tag_next = desc_table_start_ptr_reg & DESC_PTR_MASK;
m_axis_rx_desc_valid_next = 1'b1;
@ -539,7 +506,6 @@ always @* begin
// descriptor fetch
if (desc_table_active[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && desc_table_dequeue_start_ptr_reg != desc_table_start_ptr_reg) begin
//if (desc_table_rx_done[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_dequeue_req_valid) begin
if (desc_table_rx_done[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_req_valid) begin
// update entry in descriptor table
desc_table_dequeue_start_en = 1'b1;
@ -581,41 +547,41 @@ always @* begin
// update entry in descriptor table
desc_table_desc_fetched_ptr = s_axis_desc_tid & DESC_PTR_MASK;
desc_table_desc_fetched_len = s_axis_desc_tdata[64:32];
desc_table_desc_fetched_pcie_addr = s_axis_desc_tdata[127:64];
desc_table_desc_fetched_dma_addr = s_axis_desc_tdata[127:64];
desc_table_desc_fetched_en = 1'b1;
end
// data write
// wait for descriptor fetch completion
// TODO descriptor validation?
if (desc_table_active[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] && desc_table_data_write_start_ptr_reg != desc_table_start_ptr_reg && desc_table_data_write_start_ptr_reg != desc_table_dequeue_start_ptr_reg && desc_table_data_write_start_ptr_reg == desc_table_cpl_enqueue_start_ptr_reg) begin
if (desc_table_active[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] && desc_table_data_write_start_ptr_reg != desc_table_start_ptr_reg && desc_table_data_write_start_ptr_reg != desc_table_dequeue_start_ptr_reg) begin
if (desc_table_invalid[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK]) begin
// invalid entry; skip
desc_table_data_write_start_en = 1'b1;
end else if (desc_table_desc_fetched[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] && !m_axis_pcie_axi_dma_write_desc_valid_reg) begin
end else if (desc_table_desc_fetched[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] && !m_axis_dma_write_desc_valid_reg) begin
// update entry in descriptor table
desc_table_data_write_start_en = 1'b1;
// initiate data write
m_axis_pcie_axi_dma_write_desc_pcie_addr_next = desc_table_pcie_addr[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
m_axis_pcie_axi_dma_write_desc_axi_addr_next = SCRATCH_PKT_AXI_ADDR + ((desc_table_pkt[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] & DESC_PTR_MASK) << SCRATCH_PKT_AXI_ADDR_SHIFT);
m_axis_dma_write_desc_dma_addr_next = desc_table_dma_addr[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
m_axis_dma_write_desc_ram_addr_next = (desc_table_pkt[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] & DESC_PTR_MASK) << CL_MAX_RX_SIZE;
if (desc_table_desc_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] < desc_table_dma_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK]) begin
// limit write to length provided in descriptor
m_axis_pcie_axi_dma_write_desc_len_next = desc_table_desc_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
m_axis_dma_write_desc_len_next = desc_table_desc_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
end else begin
// write actual packet length
m_axis_pcie_axi_dma_write_desc_len_next = desc_table_dma_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
m_axis_dma_write_desc_len_next = desc_table_dma_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
end
m_axis_pcie_axi_dma_write_desc_tag_next = desc_table_data_write_start_ptr_reg & DESC_PTR_MASK;
m_axis_pcie_axi_dma_write_desc_valid_next = 1'b1;
m_axis_dma_write_desc_tag_next = desc_table_data_write_start_ptr_reg & DESC_PTR_MASK;
m_axis_dma_write_desc_valid_next = 1'b1;
end
end
// data write completion
// wait for data write completion
if (s_axis_pcie_axi_dma_write_desc_status_valid) begin
if (s_axis_dma_write_desc_status_valid) begin
// update entry in descriptor table
desc_table_data_written_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
desc_table_data_written_ptr = s_axis_dma_write_desc_status_tag & DESC_PTR_MASK;
desc_table_data_written_en = 1'b1;
end
@ -675,14 +641,16 @@ always @* begin
m_axis_cpl_req_queue_next = desc_table_cpl_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_tag_next = desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK;
m_axis_cpl_req_data_next = 0;
m_axis_cpl_req_data_next[15:0] <= desc_table_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_data_next[31:16] <= desc_table_queue_ptr[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_data_next[47:32] <= desc_table_dma_len[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_data_next[15:0] = desc_table_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_data_next[31:16] = desc_table_queue_ptr[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_data_next[47:32] = desc_table_dma_len[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
if (PTP_TS_ENABLE) begin
//m_axis_cpl_req_data_next[127:64] <= desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
m_axis_cpl_req_data_next[111:64] <= desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
//m_axis_cpl_req_data_next[127:64] = desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
m_axis_cpl_req_data_next[111:64] = desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
end
if (RX_CHECKSUM_ENABLE) begin
m_axis_cpl_req_data_next[127:112] = desc_table_csum[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
end
m_axis_cpl_req_data_next[127:112] <= desc_table_csum[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_valid_next = 1'b1;
end
end
@ -724,7 +692,7 @@ always @(posedge clk) begin
m_axis_desc_req_valid_reg <= 1'b0;
s_axis_desc_tready_reg <= 1'b0;
m_axis_cpl_req_valid_reg <= 1'b0;
m_axis_pcie_axi_dma_write_desc_valid_reg <= 1'b0;
m_axis_dma_write_desc_valid_reg <= 1'b0;
m_axis_rx_desc_valid_reg <= 1'b0;
s_axis_rx_ptp_ts_ready_reg <= 1'b0;
s_axis_rx_csum_ready_reg <= 1'b0;
@ -750,7 +718,7 @@ always @(posedge clk) begin
m_axis_desc_req_valid_reg <= m_axis_desc_req_valid_next;
s_axis_desc_tready_reg <= s_axis_desc_tready_next;
m_axis_cpl_req_valid_reg <= m_axis_cpl_req_valid_next;
m_axis_pcie_axi_dma_write_desc_valid_reg <= m_axis_pcie_axi_dma_write_desc_valid_next;
m_axis_dma_write_desc_valid_reg <= m_axis_dma_write_desc_valid_next;
m_axis_rx_desc_valid_reg <= m_axis_rx_desc_valid_next;
s_axis_rx_ptp_ts_ready_reg <= s_axis_rx_ptp_ts_ready_next;
s_axis_rx_csum_ready_reg <= s_axis_rx_csum_ready_next;
@ -819,10 +787,10 @@ always @(posedge clk) begin
m_axis_cpl_req_tag_reg <= m_axis_cpl_req_tag_next;
m_axis_cpl_req_data_reg <= m_axis_cpl_req_data_next;
m_axis_pcie_axi_dma_write_desc_pcie_addr_reg <= m_axis_pcie_axi_dma_write_desc_pcie_addr_next;
m_axis_pcie_axi_dma_write_desc_axi_addr_reg <= m_axis_pcie_axi_dma_write_desc_axi_addr_next;
m_axis_pcie_axi_dma_write_desc_len_reg <= m_axis_pcie_axi_dma_write_desc_len_next;
m_axis_pcie_axi_dma_write_desc_tag_reg <= m_axis_pcie_axi_dma_write_desc_tag_next;
m_axis_dma_write_desc_dma_addr_reg <= m_axis_dma_write_desc_dma_addr_next;
m_axis_dma_write_desc_ram_addr_reg <= m_axis_dma_write_desc_ram_addr_next;
m_axis_dma_write_desc_len_reg <= m_axis_dma_write_desc_len_next;
m_axis_dma_write_desc_tag_reg <= m_axis_dma_write_desc_tag_next;
m_axis_rx_desc_addr_reg <= m_axis_rx_desc_addr_next;
m_axis_rx_desc_len_reg <= m_axis_rx_desc_len_next;
@ -842,7 +810,7 @@ always @(posedge clk) begin
end
if (desc_table_desc_fetched_en) begin
desc_table_desc_len[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_len;
desc_table_pcie_addr[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_pcie_addr;
desc_table_dma_addr[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_dma_addr;
end
if (desc_table_store_ptp_ts_en) begin
desc_table_ptp_ts[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] <= desc_table_store_ptp_ts;

216
fpga/common/rtl/tx_engine.v
View File

@ -40,32 +40,22 @@ either expressed or implied, of The Regents of the University of California.
*/
module tx_engine #
(
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = 256,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 16,
// Width of AXI wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// Width of AXI stream interface in bits
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH,
// PCIe address width
parameter PCIE_ADDR_WIDTH = 64,
// PCIe DMA length field width
parameter PCIE_DMA_LEN_WIDTH = 20,
// AXI DMA length field width
parameter AXI_DMA_LEN_WIDTH = 20,
// DMA RAM address width
parameter RAM_ADDR_WIDTH = 16,
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// DMA length field width
parameter DMA_LEN_WIDTH = 20,
// DMA client length field width
parameter DMA_CLIENT_LEN_WIDTH = 20,
// Transmit request tag field width
parameter REQ_TAG_WIDTH = 8,
// Descriptor request tag field width
parameter DESC_REQ_TAG_WIDTH = 8,
// PCIe DMA tag field width
parameter PCIE_DMA_TAG_WIDTH = 8,
// AXI DMA tag field width
parameter AXI_DMA_TAG_WIDTH = 8,
// DMA tag field width
parameter DMA_TAG_WIDTH = 8,
// DMA client tag field width
parameter DMA_CLIENT_TAG_WIDTH = 8,
// Queue request tag field width
parameter QUEUE_REQ_TAG_WIDTH = 8,
// Queue operation tag field width
@ -80,14 +70,16 @@ module tx_engine #
parameter DESC_TABLE_SIZE = 8,
// Packet table size (number of in-progress packets)
parameter PKT_TABLE_SIZE = 8,
// Max transmit packet size
parameter MAX_TX_SIZE = 2048,
// Descriptor size (in bytes)
parameter DESC_SIZE = 16,
// Descriptor size (in bytes)
parameter CPL_SIZE = 32,
// AXI address of packet scratchpad RAM (as seen by PCIe DMA and port AXI DMA)
parameter SCRATCH_PKT_AXI_ADDR = 16'h1000,
// Packet scratchpad RAM log segment size
parameter SCRATCH_PKT_AXI_ADDR_SHIFT = 12,
// Width of AXI stream descriptor interfaces in bits
parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8,
// AXI stream descriptor tkeep signal width (words per cycle)
parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// Enable TX checksum offload
@ -108,7 +100,7 @@ module tx_engine #
/*
* Transmit request status output
*/
output wire [AXI_DMA_LEN_WIDTH-1:0] m_axis_tx_req_status_len,
output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_req_status_len,
output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_status_tag,
output wire m_axis_tx_req_status_valid,
@ -134,8 +126,8 @@ module tx_engine #
/*
* Descriptor data input
*/
input wire [AXIS_DATA_WIDTH-1:0] s_axis_desc_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata,
input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
input wire s_axis_desc_tvalid,
output wire s_axis_desc_tready,
input wire s_axis_desc_tlast,
@ -160,27 +152,27 @@ module tx_engine #
input wire s_axis_cpl_req_status_valid,
/*
* PCIe AXI DMA read descriptor output
* DMA read descriptor output
*/
output wire [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_pcie_addr,
output wire [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_axi_addr,
output wire [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_len,
output wire [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_tag,
output wire m_axis_pcie_axi_dma_read_desc_valid,
input wire m_axis_pcie_axi_dma_read_desc_ready,
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag,
output wire m_axis_dma_read_desc_valid,
input wire m_axis_dma_read_desc_ready,
/*
* PCIe AXI DMA read descriptor status input
* DMA read descriptor status input
*/
input wire [PCIE_DMA_TAG_WIDTH-1:0] s_axis_pcie_axi_dma_read_desc_status_tag,
input wire s_axis_pcie_axi_dma_read_desc_status_valid,
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag,
input wire s_axis_dma_read_desc_status_valid,
/*
* Transmit descriptor output
*/
output wire [AXI_ADDR_WIDTH-1:0] m_axis_tx_desc_addr,
output wire [AXI_DMA_LEN_WIDTH-1:0] m_axis_tx_desc_len,
output wire [AXI_DMA_TAG_WIDTH-1:0] m_axis_tx_desc_tag,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_tx_desc_addr,
output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_desc_len,
output wire [DMA_CLIENT_TAG_WIDTH-1:0] m_axis_tx_desc_tag,
output wire m_axis_tx_desc_user,
output wire m_axis_tx_desc_valid,
input wire m_axis_tx_desc_ready,
@ -188,7 +180,7 @@ module tx_engine #
/*
* Transmit descriptor status input
*/
input wire [AXI_DMA_TAG_WIDTH-1:0] s_axis_tx_desc_status_tag,
input wire [DMA_CLIENT_TAG_WIDTH-1:0] s_axis_tx_desc_status_tag,
input wire s_axis_tx_desc_status_valid,
/*
@ -213,39 +205,21 @@ module tx_engine #
input wire enable
);
parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
parameter CL_DESC_TABLE_SIZE = $clog2(DESC_TABLE_SIZE);
parameter DESC_PTR_MASK = {CL_DESC_TABLE_SIZE{1'b1}};
parameter CL_PKT_TABLE_SIZE = $clog2(PKT_TABLE_SIZE);
parameter PKT_TAG_MASK = {CL_PKT_TABLE_SIZE{1'b1}};
parameter CL_MAX_TX_SIZE = $clog2(MAX_TX_SIZE);
// bus width assertions
initial begin
if (PCIE_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
$error("Error: PCIe tag width insufficient for descriptor table size (instance %m)");
if (DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
$error("Error: DMA tag width insufficient for descriptor table size (instance %m)");
$finish;
end
if (AXI_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
$error("Error: AXI tag width insufficient for descriptor table size (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (SCRATCH_PKT_AXI_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
$error("Error: AXI base address must be aligned to interface width (instance %m)");
$finish;
end
if (SCRATCH_PKT_AXI_ADDR_SHIFT < $clog2(AXI_STRB_WIDTH)) begin
$error("Error: Packet scratch address increment must be aligned to interface width (instance %m)");
if (DMA_CLIENT_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
$error("Error: DMA client tag width insufficient for descriptor table size (instance %m)");
$finish;
end
@ -267,7 +241,7 @@ end
reg s_axis_tx_req_ready_reg = 1'b0, s_axis_tx_req_ready_next;
reg [AXI_DMA_LEN_WIDTH-1:0] m_axis_tx_req_status_len_reg = {AXI_DMA_LEN_WIDTH{1'b0}}, m_axis_tx_req_status_len_next;
reg [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_req_status_len_reg = {DMA_CLIENT_LEN_WIDTH{1'b0}}, m_axis_tx_req_status_len_next;
reg [REQ_TAG_WIDTH-1:0] m_axis_tx_req_status_tag_reg = {REQ_TAG_WIDTH{1'b0}}, m_axis_tx_req_status_tag_next;
reg m_axis_tx_req_status_valid_reg = 1'b0, m_axis_tx_req_status_valid_next;
@ -282,15 +256,15 @@ reg [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {DESC_REQ_TAG_WIDTH{1'b0}}
reg [CPL_SIZE*8-1:0] m_axis_cpl_req_data_reg = {CPL_SIZE*8{1'b0}}, m_axis_cpl_req_data_next;
reg m_axis_cpl_req_valid_reg = 1'b0, m_axis_cpl_req_valid_next;
reg [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_pcie_addr_next;
reg [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_axi_addr_next;
reg [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_len_next;
reg [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_tag_next;
reg m_axis_pcie_axi_dma_read_desc_valid_reg = 1'b0, m_axis_pcie_axi_dma_read_desc_valid_next;
reg [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr_reg = {DMA_ADDR_WIDTH{1'b0}}, m_axis_dma_read_desc_dma_addr_next;
reg [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, m_axis_dma_read_desc_ram_addr_next;
reg [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len_reg = {DMA_LEN_WIDTH{1'b0}}, m_axis_dma_read_desc_len_next;
reg [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag_reg = {DMA_TAG_WIDTH{1'b0}}, m_axis_dma_read_desc_tag_next;
reg m_axis_dma_read_desc_valid_reg = 1'b0, m_axis_dma_read_desc_valid_next;
reg [AXI_ADDR_WIDTH-1:0] m_axis_tx_desc_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_tx_desc_addr_next;
reg [AXI_DMA_LEN_WIDTH-1:0] m_axis_tx_desc_len_reg = {AXI_DMA_LEN_WIDTH{1'b0}}, m_axis_tx_desc_len_next;
reg [AXI_DMA_TAG_WIDTH-1:0] m_axis_tx_desc_tag_reg = {AXI_DMA_TAG_WIDTH{1'b0}}, m_axis_tx_desc_tag_next;
reg [RAM_ADDR_WIDTH-1:0] m_axis_tx_desc_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, m_axis_tx_desc_addr_next;
reg [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_desc_len_reg = {DMA_CLIENT_LEN_WIDTH{1'b0}}, m_axis_tx_desc_len_next;
reg [DMA_CLIENT_TAG_WIDTH-1:0] m_axis_tx_desc_tag_reg = {DMA_CLIENT_TAG_WIDTH{1'b0}}, m_axis_tx_desc_tag_next;
reg m_axis_tx_desc_user_reg = 1'b0, m_axis_tx_desc_user_next;
reg m_axis_tx_desc_valid_reg = 1'b0, m_axis_tx_desc_valid_next;
@ -301,11 +275,11 @@ reg m_axis_tx_csum_cmd_valid_reg = 1'b0, m_axis_tx_csum_cmd_valid_next;
reg s_axis_tx_ptp_ts_ready_reg = 1'b0, s_axis_tx_ptp_ts_ready_next;
reg [AXI_DMA_LEN_WIDTH-1:0] early_tx_req_status_len_reg = {AXI_DMA_LEN_WIDTH{1'b0}}, early_tx_req_status_len_next;
reg [DMA_CLIENT_LEN_WIDTH-1:0] early_tx_req_status_len_reg = {DMA_CLIENT_LEN_WIDTH{1'b0}}, early_tx_req_status_len_next;
reg [REQ_TAG_WIDTH-1:0] early_tx_req_status_tag_reg = {REQ_TAG_WIDTH{1'b0}}, early_tx_req_status_tag_next;
reg early_tx_req_status_valid_reg = 1'b0, early_tx_req_status_valid_next;
reg [AXI_DMA_LEN_WIDTH-1:0] finish_tx_req_status_len_reg = {AXI_DMA_LEN_WIDTH{1'b0}}, finish_tx_req_status_len_next;
reg [DMA_CLIENT_LEN_WIDTH-1:0] finish_tx_req_status_len_reg = {DMA_CLIENT_LEN_WIDTH{1'b0}}, finish_tx_req_status_len_next;
reg [REQ_TAG_WIDTH-1:0] finish_tx_req_status_tag_reg = {REQ_TAG_WIDTH{1'b0}}, finish_tx_req_status_tag_next;
reg finish_tx_req_status_valid_reg = 1'b0, finish_tx_req_status_valid_next;
@ -322,8 +296,8 @@ reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0];
reg [6:0] desc_table_csum_start[DESC_TABLE_SIZE-1:0];
reg [7:0] desc_table_csum_offset[DESC_TABLE_SIZE-1:0];
reg desc_table_csum_enable[DESC_TABLE_SIZE-1:0];
reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_len[DESC_TABLE_SIZE-1:0];
reg [PCIE_ADDR_WIDTH-1:0] desc_table_pcie_addr[DESC_TABLE_SIZE-1:0];
reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_len[DESC_TABLE_SIZE-1:0];
reg [DMA_ADDR_WIDTH-1:0] desc_table_dma_addr[DESC_TABLE_SIZE-1:0];
reg [CL_PKT_TABLE_SIZE-1:0] desc_table_pkt[DESC_TABLE_SIZE-1:0];
reg [95:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0];
@ -345,8 +319,8 @@ reg [CL_DESC_TABLE_SIZE-1:0] desc_table_data_fetched_ptr;
reg [6:0] desc_table_desc_fetched_csum_start;
reg [7:0] desc_table_desc_fetched_csum_offset;
reg desc_table_desc_fetched_csum_enable;
reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_desc_fetched_len;
reg [PCIE_ADDR_WIDTH-1:0] desc_table_desc_fetched_pcie_addr;
reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_desc_fetched_len;
reg [DMA_ADDR_WIDTH-1:0] desc_table_desc_fetched_dma_addr;
reg desc_table_data_fetched_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_tx_start_ptr_reg = 0;
reg desc_table_tx_start_en;
@ -385,11 +359,11 @@ assign m_axis_cpl_req_tag = m_axis_cpl_req_tag_reg;
assign m_axis_cpl_req_data = m_axis_cpl_req_data_reg;
assign m_axis_cpl_req_valid = m_axis_cpl_req_valid_reg;
assign m_axis_pcie_axi_dma_read_desc_pcie_addr = m_axis_pcie_axi_dma_read_desc_pcie_addr_reg;
assign m_axis_pcie_axi_dma_read_desc_axi_addr = m_axis_pcie_axi_dma_read_desc_axi_addr_reg;
assign m_axis_pcie_axi_dma_read_desc_len = m_axis_pcie_axi_dma_read_desc_len_reg;
assign m_axis_pcie_axi_dma_read_desc_tag = m_axis_pcie_axi_dma_read_desc_tag_reg;
assign m_axis_pcie_axi_dma_read_desc_valid = m_axis_pcie_axi_dma_read_desc_valid_reg;
assign m_axis_dma_read_desc_dma_addr = m_axis_dma_read_desc_dma_addr_reg;
assign m_axis_dma_read_desc_ram_addr = m_axis_dma_read_desc_ram_addr_reg;
assign m_axis_dma_read_desc_len = m_axis_dma_read_desc_len_reg;
assign m_axis_dma_read_desc_tag = m_axis_dma_read_desc_tag_reg;
assign m_axis_dma_read_desc_valid = m_axis_dma_read_desc_valid_reg;
assign m_axis_tx_desc_addr = m_axis_tx_desc_addr_reg;
assign m_axis_tx_desc_len = m_axis_tx_desc_len_reg;
@ -442,10 +416,10 @@ pkt_table_free_enc_inst (
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({desc_table_active, desc_table_invalid, desc_table_desc_fetched, desc_table_data_fetched, desc_table_tx_done, desc_table_cpl_write_done, pkt_table_active,
// m_axis_pcie_axi_dma_read_desc_len, m_axis_pcie_axi_dma_read_desc_tag, m_axis_pcie_axi_dma_read_desc_valid, m_axis_pcie_axi_dma_read_desc_ready,
// s_axis_pcie_axi_dma_read_desc_status_tag, s_axis_pcie_axi_dma_read_desc_status_valid,
// m_axis_pcie_axi_dma_write_desc_len, m_axis_pcie_axi_dma_write_desc_tag, m_axis_pcie_axi_dma_write_desc_valid, m_axis_pcie_axi_dma_write_desc_ready,
// s_axis_pcie_axi_dma_write_desc_status_tag, s_axis_pcie_axi_dma_write_desc_status_valid}),
// m_axis_dma_read_desc_len, m_axis_dma_read_desc_tag, m_axis_dma_read_desc_valid, m_axis_dma_read_desc_ready,
// s_axis_dma_read_desc_status_tag, s_axis_dma_read_desc_status_valid,
// m_axis_dma_write_desc_len, m_axis_dma_write_desc_tag, m_axis_dma_write_desc_valid, m_axis_dma_write_desc_ready,
// s_axis_dma_write_desc_status_tag, s_axis_dma_write_desc_status_valid}),
// .probe1(0),
// .probe2(0),
// .probe3(s_axis_tx_req_ready),
@ -471,11 +445,11 @@ always @* begin
m_axis_cpl_req_data_next = m_axis_cpl_req_data_reg;
m_axis_cpl_req_valid_next = m_axis_cpl_req_valid_reg && !m_axis_cpl_req_ready;
m_axis_pcie_axi_dma_read_desc_pcie_addr_next = m_axis_pcie_axi_dma_read_desc_pcie_addr_reg;
m_axis_pcie_axi_dma_read_desc_axi_addr_next = m_axis_pcie_axi_dma_read_desc_axi_addr_reg;
m_axis_pcie_axi_dma_read_desc_len_next = m_axis_pcie_axi_dma_read_desc_len_reg;
m_axis_pcie_axi_dma_read_desc_tag_next = m_axis_pcie_axi_dma_read_desc_tag_reg;
m_axis_pcie_axi_dma_read_desc_valid_next = m_axis_pcie_axi_dma_read_desc_valid_reg && !m_axis_pcie_axi_dma_read_desc_ready;
m_axis_dma_read_desc_dma_addr_next = m_axis_dma_read_desc_dma_addr_reg;
m_axis_dma_read_desc_ram_addr_next = m_axis_dma_read_desc_ram_addr_reg;
m_axis_dma_read_desc_len_next = m_axis_dma_read_desc_len_reg;
m_axis_dma_read_desc_tag_next = m_axis_dma_read_desc_tag_reg;
m_axis_dma_read_desc_valid_next = m_axis_dma_read_desc_valid_reg && !m_axis_dma_read_desc_ready;
m_axis_tx_desc_addr_next = m_axis_tx_desc_addr_reg;
m_axis_tx_desc_len_next = m_axis_tx_desc_len_reg;
@ -517,11 +491,11 @@ always @* begin
desc_table_desc_fetched_csum_enable = 0;
end
desc_table_desc_fetched_len = s_axis_desc_tdata[64:32];
desc_table_desc_fetched_pcie_addr = s_axis_desc_tdata[127:64];
desc_table_desc_fetched_dma_addr = s_axis_desc_tdata[127:64];
desc_table_desc_fetched_en = 1'b0;
desc_table_data_fetch_start_pkt = 0;
desc_table_data_fetch_start_en = 1'b0;
desc_table_data_fetched_ptr = s_axis_pcie_axi_dma_read_desc_status_tag & DESC_PTR_MASK;
desc_table_data_fetched_ptr = s_axis_dma_read_desc_status_tag & DESC_PTR_MASK;
desc_table_data_fetched_en = 1'b0;
desc_table_tx_start_en = 1'b0;
desc_table_tx_finish_ptr = s_axis_tx_desc_status_tag;
@ -594,18 +568,18 @@ always @* begin
desc_table_desc_fetched_csum_enable = s_axis_desc_tdata[31];
end
desc_table_desc_fetched_len = s_axis_desc_tdata[64:32];
desc_table_desc_fetched_pcie_addr = s_axis_desc_tdata[127:64];
desc_table_desc_fetched_dma_addr = s_axis_desc_tdata[127:64];
desc_table_desc_fetched_en = 1'b1;
end
// data fetch
// wait for descriptor fetch completion
// TODO descriptor validation?
if (desc_table_active[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK] && desc_table_data_fetch_start_ptr_reg != desc_table_start_ptr_reg && desc_table_data_fetch_start_ptr_reg == desc_table_tx_start_ptr_reg) begin
if (desc_table_active[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK] && desc_table_data_fetch_start_ptr_reg != desc_table_start_ptr_reg) begin
if (desc_table_invalid[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK]) begin
// invalid entry; skip
desc_table_data_fetch_start_en = 1'b1;
end else if (desc_table_desc_fetched[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK] && pkt_table_free_ptr_valid && !m_axis_pcie_axi_dma_read_desc_valid_reg) begin
end else if (desc_table_desc_fetched[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK] && pkt_table_free_ptr_valid && !m_axis_dma_read_desc_valid_reg) begin
// update entry in descriptor table
desc_table_data_fetch_start_pkt = pkt_table_free_ptr;
desc_table_data_fetch_start_en = 1'b1;
@ -615,19 +589,19 @@ always @* begin
pkt_table_start_en = 1'b1;
// initiate data fetch to onboard RAM
m_axis_pcie_axi_dma_read_desc_pcie_addr_next = desc_table_pcie_addr[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK];
m_axis_pcie_axi_dma_read_desc_axi_addr_next = SCRATCH_PKT_AXI_ADDR + (pkt_table_free_ptr << SCRATCH_PKT_AXI_ADDR_SHIFT);
m_axis_pcie_axi_dma_read_desc_len_next = desc_table_len[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK];
m_axis_pcie_axi_dma_read_desc_tag_next = desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK;
m_axis_pcie_axi_dma_read_desc_valid_next = 1'b1;
m_axis_dma_read_desc_dma_addr_next = desc_table_dma_addr[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK];
m_axis_dma_read_desc_ram_addr_next = pkt_table_free_ptr << CL_MAX_TX_SIZE;
m_axis_dma_read_desc_len_next = desc_table_len[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK];
m_axis_dma_read_desc_tag_next = desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK;
m_axis_dma_read_desc_valid_next = 1'b1;
end
end
// data fetch completion
// wait for data fetch completion
if (s_axis_pcie_axi_dma_read_desc_status_valid) begin
if (s_axis_dma_read_desc_status_valid) begin
// update entry in descriptor table
desc_table_data_fetched_ptr = s_axis_pcie_axi_dma_read_desc_status_tag & DESC_PTR_MASK;
desc_table_data_fetched_ptr = s_axis_dma_read_desc_status_tag & DESC_PTR_MASK;
desc_table_data_fetched_en = 1'b1;
end
@ -642,7 +616,7 @@ always @* begin
desc_table_tx_start_en = 1'b1;
// initiate transmit operation
m_axis_tx_desc_addr_next = SCRATCH_PKT_AXI_ADDR + (desc_table_pkt[desc_table_tx_start_ptr_reg & DESC_PTR_MASK] << SCRATCH_PKT_AXI_ADDR_SHIFT);
m_axis_tx_desc_addr_next = desc_table_pkt[desc_table_tx_start_ptr_reg & DESC_PTR_MASK] << CL_MAX_TX_SIZE;
m_axis_tx_desc_len_next = desc_table_len[desc_table_tx_start_ptr_reg & DESC_PTR_MASK];
m_axis_tx_desc_tag_next = desc_table_tx_start_ptr_reg & DESC_PTR_MASK;
m_axis_tx_desc_user_next = 1'b0;
@ -700,12 +674,12 @@ always @* begin
m_axis_cpl_req_queue_next = desc_table_cpl_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_tag_next = desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK;
m_axis_cpl_req_data_next = 0;
m_axis_cpl_req_data_next[15:0] <= desc_table_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_data_next[31:16] <= desc_table_queue_ptr[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_data_next[47:32] <= desc_table_len[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_data_next[15:0] = desc_table_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_data_next[31:16] = desc_table_queue_ptr[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_data_next[47:32] = desc_table_len[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
if (PTP_TS_ENABLE) begin
//m_axis_cpl_req_data_next[127:64] <= desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
m_axis_cpl_req_data_next[111:64] <= desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
//m_axis_cpl_req_data_next[127:64] = desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
m_axis_cpl_req_data_next[111:64] = desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
end
m_axis_cpl_req_valid_next = 1'b1;
end
@ -756,7 +730,7 @@ always @(posedge clk) begin
m_axis_desc_req_valid_reg <= 1'b0;
s_axis_desc_tready_reg <= 1'b0;
m_axis_cpl_req_valid_reg <= 1'b0;
m_axis_pcie_axi_dma_read_desc_valid_reg <= 1'b0;
m_axis_dma_read_desc_valid_reg <= 1'b0;
m_axis_tx_desc_valid_reg <= 1'b0;
s_axis_tx_ptp_ts_ready_reg <= 1'b0;
m_axis_tx_csum_cmd_valid_reg <= 1'b0;
@ -784,7 +758,7 @@ always @(posedge clk) begin
m_axis_desc_req_valid_reg <= m_axis_desc_req_valid_next;
s_axis_desc_tready_reg <= s_axis_desc_tready_next;
m_axis_cpl_req_valid_reg <= m_axis_cpl_req_valid_next;
m_axis_pcie_axi_dma_read_desc_valid_reg <= m_axis_pcie_axi_dma_read_desc_valid_next;
m_axis_dma_read_desc_valid_reg <= m_axis_dma_read_desc_valid_next;
m_axis_tx_desc_valid_reg <= m_axis_tx_desc_valid_next;
s_axis_tx_ptp_ts_ready_reg <= s_axis_tx_ptp_ts_ready_next;
m_axis_tx_csum_cmd_valid_reg <= m_axis_tx_csum_cmd_valid_next;
@ -854,10 +828,10 @@ always @(posedge clk) begin
m_axis_cpl_req_tag_reg <= m_axis_cpl_req_tag_next;
m_axis_cpl_req_data_reg <= m_axis_cpl_req_data_next;
m_axis_pcie_axi_dma_read_desc_pcie_addr_reg <= m_axis_pcie_axi_dma_read_desc_pcie_addr_next;
m_axis_pcie_axi_dma_read_desc_axi_addr_reg <= m_axis_pcie_axi_dma_read_desc_axi_addr_next;
m_axis_pcie_axi_dma_read_desc_len_reg <= m_axis_pcie_axi_dma_read_desc_len_next;
m_axis_pcie_axi_dma_read_desc_tag_reg <= m_axis_pcie_axi_dma_read_desc_tag_next;
m_axis_dma_read_desc_dma_addr_reg <= m_axis_dma_read_desc_dma_addr_next;
m_axis_dma_read_desc_ram_addr_reg <= m_axis_dma_read_desc_ram_addr_next;
m_axis_dma_read_desc_len_reg <= m_axis_dma_read_desc_len_next;
m_axis_dma_read_desc_tag_reg <= m_axis_dma_read_desc_tag_next;
m_axis_tx_desc_addr_reg <= m_axis_tx_desc_addr_next;
m_axis_tx_desc_len_reg <= m_axis_tx_desc_len_next;
@ -887,7 +861,7 @@ always @(posedge clk) begin
desc_table_csum_offset[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_csum_offset;
desc_table_csum_enable[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_csum_enable;
desc_table_len[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_len;
desc_table_pcie_addr[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_pcie_addr;
desc_table_dma_addr[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_dma_addr;
end
if (desc_table_data_fetch_start_en) begin
desc_table_pkt[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK] <= desc_table_data_fetch_start_pkt;

68
fpga/common/rtl/tx_scheduler_rr.v
View File

@ -46,8 +46,8 @@ module tx_scheduler_rr #
parameter AXIL_ADDR_WIDTH = 16,
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// AXI DMA length field width
parameter AXI_DMA_LEN_WIDTH = 16,
// DMA client length field width
parameter DMA_CLIENT_LEN_WIDTH = 16,
// Transmit request tag field width
parameter REQ_TAG_WIDTH = 8,
// Number of outstanding operations
@ -58,58 +58,58 @@ module tx_scheduler_rr #
parameter PIPELINE = 2
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* Transmit request output (queue index)
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_req_queue,
output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_tag,
output wire m_axis_tx_req_valid,
input wire m_axis_tx_req_ready,
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_req_queue,
output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_tag,
output wire m_axis_tx_req_valid,
input wire m_axis_tx_req_ready,
/*
* Transmit request status input
*/
input wire [AXI_DMA_LEN_WIDTH-1:0] s_axis_tx_req_status_len,
input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_req_status_tag,
input wire s_axis_tx_req_status_valid,
input wire [DMA_CLIENT_LEN_WIDTH-1:0] s_axis_tx_req_status_len,
input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_req_status_tag,
input wire s_axis_tx_req_status_valid,
/*
* Doorbell input
*/
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_doorbell_queue,
input wire s_axis_doorbell_valid,
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_doorbell_queue,
input wire s_axis_doorbell_valid,
/*
* AXI-Lite slave interface
*/
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
output wire s_axil_awready,
input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
input wire s_axil_wvalid,
output wire s_axil_wready,
output wire [1:0] s_axil_bresp,
output wire s_axil_bvalid,
input wire s_axil_bready,
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
output wire [1:0] s_axil_rresp,
output wire s_axil_rvalid,
input wire s_axil_rready,
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
output wire s_axil_awready,
input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
input wire s_axil_wvalid,
output wire s_axil_wready,
output wire [1:0] s_axil_bresp,
output wire s_axil_bvalid,
input wire s_axil_bready,
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
output wire [1:0] s_axil_rresp,
output wire s_axil_rvalid,
input wire s_axil_rready,
/*
* Control
*/
input wire enable,
output wire active
input wire enable,
output wire active
);
parameter QUEUE_COUNT = 2**QUEUE_INDEX_WIDTH;

25
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
View File

@ -45,18 +45,6 @@ SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
SYN_FILES += lib/axi/rtl/axi_crossbar.v
SYN_FILES += lib/axi/rtl/axi_crossbar_addr.v
SYN_FILES += lib/axi/rtl/axi_crossbar_rd.v
SYN_FILES += lib/axi/rtl/axi_crossbar_wr.v
SYN_FILES += lib/axi/rtl/axi_dma.v
SYN_FILES += lib/axi/rtl/axi_dma_rd.v
SYN_FILES += lib/axi/rtl/axi_dma_wr.v
SYN_FILES += lib/axi/rtl/axi_ram.v
SYN_FILES += lib/axi/rtl/axi_ram_rd_if.v
SYN_FILES += lib/axi/rtl/axi_ram_wr_if.v
SYN_FILES += lib/axi/rtl/axi_register_rd.v
SYN_FILES += lib/axi/rtl/axi_register_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/arbiter.v
SYN_FILES += lib/axi/rtl/priority_encoder.v
@ -67,13 +55,18 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
SYN_FILES += lib/pcie/rtl/pcie_axi_dma_desc_mux.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files

736
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -257,15 +257,9 @@ parameter AXIL_DATA_WIDTH = 32;
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
parameter AXIL_ADDR_WIDTH = 24;
// AXI interface parameters
parameter AXI_ID_WIDTH = 8;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = 24;
// AXI stream interface parameters
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH;
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH;
parameter AXIS_DATA_WIDTH = 256;
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8;
// PCIe DMA parameters
parameter PCIE_DMA_LEN_WIDTH = 16;
@ -330,6 +324,20 @@ parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 32768;
parameter RX_FIFO_DEPTH = 32768;
parameter MAX_TX_SIZE = 2048;
parameter MAX_RX_SIZE = 2048;
// PCIe DMA parameters
parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2;
parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT;
parameter SEG_ADDR_WIDTH = 12;
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8;
parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+$clog2(PORTS_PER_IF+1);
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH);
parameter RAM_PIPELINE = 2;
parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE;
parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE;
// AXI lite connections
wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
@ -392,42 +400,20 @@ wire [1:0] axil_ber_rresp;
wire axil_ber_rvalid;
wire axil_ber_rready;
// AXI connections
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_awid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_awaddr;
wire [7:0] axi_pcie_dma_awlen;
wire [2:0] axi_pcie_dma_awsize;
wire [1:0] axi_pcie_dma_awburst;
wire axi_pcie_dma_awlock;
wire [3:0] axi_pcie_dma_awcache;
wire [2:0] axi_pcie_dma_awprot;
wire axi_pcie_dma_awvalid;
wire axi_pcie_dma_awready;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_wdata;
wire [AXI_STRB_WIDTH-1:0] axi_pcie_dma_wstrb;
wire axi_pcie_dma_wlast;
wire axi_pcie_dma_wvalid;
wire axi_pcie_dma_wready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_bid;
wire [1:0] axi_pcie_dma_bresp;
wire axi_pcie_dma_bvalid;
wire axi_pcie_dma_bready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_arid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_araddr;
wire [7:0] axi_pcie_dma_arlen;
wire [2:0] axi_pcie_dma_arsize;
wire [1:0] axi_pcie_dma_arburst;
wire axi_pcie_dma_arlock;
wire [3:0] axi_pcie_dma_arcache;
wire [2:0] axi_pcie_dma_arprot;
wire axi_pcie_dma_arvalid;
wire axi_pcie_dma_arready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_rid;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_rdata;
wire [1:0] axi_pcie_dma_rresp;
wire axi_pcie_dma_rlast;
wire axi_pcie_dma_rvalid;
wire axi_pcie_dma_rready;
// DMA connections
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready;
// Error handling
wire [1:0] status_error_uncor_int;
@ -438,25 +424,27 @@ wire [31:0] msi_irq;
wire ext_tag_enable;
// PCIe DMA control
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_tag;
wire pcie_axi_dma_read_desc_valid;
wire pcie_axi_dma_read_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_read_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_read_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_tag;
wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_status_tag;
wire pcie_axi_dma_read_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_tag;
wire pcie_axi_dma_write_desc_valid;
wire pcie_axi_dma_write_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_write_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_write_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_tag;
wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_status_tag;
wire pcie_axi_dma_write_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1;
@ -836,11 +824,11 @@ rc_reg (
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({pcie_axi_dma_read_desc_pcie_addr, pcie_axi_dma_read_desc_axi_addr, pcie_axi_dma_read_desc_tag, pcie_axi_dma_read_desc_status_tag, pcie_axi_dma_write_desc_pcie_addr, pcie_axi_dma_write_desc_axi_addr, pcie_axi_dma_write_desc_tag, pcie_axi_dma_write_desc_status_tag}),
// .probe0({pcie_dma_read_desc_pcie_addr, pcie_dma_read_desc_ram_sel, pcie_dma_read_desc_ram_addr, pcie_dma_read_desc_tag, pcie_dma_read_desc_status_tag, pcie_dma_write_desc_pcie_addr, pcie_dma_write_desc_ram_sel, pcie_dma_write_desc_ram_addr, pcie_dma_write_desc_tag, pcie_dma_write_desc_status_tag}),
// .probe1(0),
// .probe2(0),
// .probe3(0),
// .probe4({pcie_axi_dma_read_desc_valid, pcie_axi_dma_read_desc_ready, pcie_axi_dma_read_desc_len, pcie_axi_dma_read_desc_status_valid, pcie_axi_dma_write_desc_valid, pcie_axi_dma_write_desc_ready, pcie_axi_dma_write_desc_len, pcie_axi_dma_write_desc_status_valid, dbg, status_error_cor_int, status_error_uncor_int}),
// .probe4({pcie_dma_read_desc_valid, pcie_dma_read_desc_ready, pcie_dma_read_desc_len, pcie_dma_read_desc_status_valid, pcie_dma_write_desc_valid, pcie_dma_write_desc_ready, pcie_dma_write_desc_len, pcie_dma_write_desc_status_valid, status_error_cor_int, status_error_uncor_int}),
// .probe5(0)
// );
@ -854,7 +842,7 @@ rc_reg (
// .probe1(m_axis_rq_tkeep),
// .probe2(m_axis_rq_tvalid),
// .probe3(m_axis_rq_tready),
// .probe4({m_axis_rq_tuser, dbg}),
// .probe4(m_axis_rq_tuser),
// .probe5(m_axis_rq_tlast)
// );
@ -864,12 +852,26 @@ rc_reg (
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(s_axis_rc_tdata),
// .probe1(s_axis_rc_tkeep),
// .probe2(s_axis_rc_tvalid),
// .probe3(s_axis_rc_tready),
// .probe4({s_axis_rc_tuser, dbg}),
// .probe5(s_axis_rc_tlast)
// .probe0(axis_rc_tdata_r),
// .probe1(axis_rc_tkeep_r),
// .probe2(axis_rc_tvalid_r),
// .probe3(axis_rc_tready_r),
// .probe4({axis_rc_tuser_r, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.req_state_reg, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.tlp_state_reg, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.ram_mask_reg}),
// .probe5(axis_rc_tlast_r)
// );
// ila_0 ila_mem (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({dma_ram_wr_cmd_valid, dma_ram_wr_cmd_ready, dma_ram_wr_cmd_sel, if_dma_ram_wr_cmd_valid, if_dma_ram_wr_cmd_ready, if_dma_ram_wr_cmd_sel, iface[0].interface_inst.desc_dma_ram_wr_cmd_valid, iface[0].interface_inst.desc_dma_ram_wr_cmd_ready, iface[0].interface_inst.port_dma_ram_wr_cmd_valid, iface[0].interface_inst.port_dma_ram_wr_cmd_ready}),
// .probe1(0),
// .probe2(0),
// .probe3(0),
// .probe4(0),
// .probe5(0)
// );
// ila_0 ila_w (
@ -886,23 +888,25 @@ rc_reg (
// .probe5(axi_pcie_dma_wlast)
// );
pcie_us_axi_dma #(
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(256),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_CLIENT_TAG(1),
.PCIE_TAG_COUNT(64),
.PCIE_EXT_TAG_ENABLE(1),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.TAG_WIDTH(PCIE_DMA_TAG_WIDTH)
)
pcie_us_axi_dma_inst (
dma_if_pcie_us_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
@ -926,82 +930,56 @@ pcie_us_axi_dma_inst (
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* Tag input
*/
.s_axis_pcie_rq_tag(0),
.s_axis_pcie_rq_tag_valid(0),
/*
* AXI read descriptor input
*/
.s_axis_read_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.s_axis_read_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.s_axis_read_desc_len(pcie_axi_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_axi_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_axi_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_pcie_addr(pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(pcie_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* AXI read descriptor status output
*/
.m_axis_read_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* AXI write descriptor input
*/
.s_axis_write_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.s_axis_write_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.s_axis_write_desc_len(pcie_axi_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_axi_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_axi_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_pcie_addr(pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(pcie_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* AXI write descriptor status output
*/
.m_axis_write_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* AXI Master output
* RAM interface
*/
.m_axi_awid(axi_pcie_dma_awid),
.m_axi_awaddr(axi_pcie_dma_awaddr),
.m_axi_awlen(axi_pcie_dma_awlen),
.m_axi_awsize(axi_pcie_dma_awsize),
.m_axi_awburst(axi_pcie_dma_awburst),
.m_axi_awlock(axi_pcie_dma_awlock),
.m_axi_awcache(axi_pcie_dma_awcache),
.m_axi_awprot(axi_pcie_dma_awprot),
.m_axi_awvalid(axi_pcie_dma_awvalid),
.m_axi_awready(axi_pcie_dma_awready),
.m_axi_wdata(axi_pcie_dma_wdata),
.m_axi_wstrb(axi_pcie_dma_wstrb),
.m_axi_wlast(axi_pcie_dma_wlast),
.m_axi_wvalid(axi_pcie_dma_wvalid),
.m_axi_wready(axi_pcie_dma_wready),
.m_axi_bid(axi_pcie_dma_bid),
.m_axi_bresp(axi_pcie_dma_bresp),
.m_axi_bvalid(axi_pcie_dma_bvalid),
.m_axi_bready(axi_pcie_dma_bready),
.m_axi_arid(axi_pcie_dma_arid),
.m_axi_araddr(axi_pcie_dma_araddr),
.m_axi_arlen(axi_pcie_dma_arlen),
.m_axi_arsize(axi_pcie_dma_arsize),
.m_axi_arburst(axi_pcie_dma_arburst),
.m_axi_arlock(axi_pcie_dma_arlock),
.m_axi_arcache(axi_pcie_dma_arcache),
.m_axi_arprot(axi_pcie_dma_arprot),
.m_axi_arvalid(axi_pcie_dma_arvalid),
.m_axi_arready(axi_pcie_dma_arready),
.m_axi_rid(axi_pcie_dma_rid),
.m_axi_rdata(axi_pcie_dma_rdata),
.m_axi_rresp(axi_pcie_dma_rresp),
.m_axi_rlast(axi_pcie_dma_rlast),
.m_axi_rvalid(axi_pcie_dma_rvalid),
.m_axi_rready(axi_pcie_dma_rready),
.ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.ram_rd_resp_data(dma_ram_rd_resp_data),
.ram_rd_resp_valid(dma_ram_rd_resp_valid),
.ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* Configuration
@ -1089,22 +1067,6 @@ function [IF_AXIL_BASE_ADDR_WIDTH-1:0] calcIFAxiLiteBaseAddrs(input [31:0] if_ad
end
endfunction
parameter IF_AXI_ADDR_WIDTH = 32'd23;
parameter IF_AXI_BASE_ADDR_WIDTH = IF_COUNT*AXI_ADDR_WIDTH;
parameter IF_AXI_BASE_ADDR = calcIFAxiBaseAddrs(IF_AXI_ADDR_WIDTH);
function [IF_AXI_BASE_ADDR_WIDTH-1:0] calcIFAxiBaseAddrs(input [31:0] if_addr_width);
integer i;
begin
calcIFAxiBaseAddrs = {IF_AXI_BASE_ADDR_WIDTH{1'b0}};
for (i = 0; i < IF_COUNT; i = i + 1) begin
calcIFAxiBaseAddrs[i * AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = i * (2**if_addr_width);
end
end
endfunction
parameter IF_AXI_ID_WIDTH = AXI_ID_WIDTH+$clog2(2);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;
@ -1145,42 +1107,6 @@ wire [IF_COUNT*2-1:0] axil_if_csr_rresp;
wire [IF_COUNT-1:0] axil_if_csr_rvalid;
wire [IF_COUNT-1:0] axil_if_csr_rready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_awid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_awaddr;
wire [IF_COUNT*8-1:0] axi_if_awlen;
wire [IF_COUNT*3-1:0] axi_if_awsize;
wire [IF_COUNT*2-1:0] axi_if_awburst;
wire [IF_COUNT-1:0] axi_if_awlock;
wire [IF_COUNT*4-1:0] axi_if_awcache;
wire [IF_COUNT*3-1:0] axi_if_awprot;
wire [IF_COUNT-1:0] axi_if_awvalid;
wire [IF_COUNT-1:0] axi_if_awready;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_wdata;
wire [IF_COUNT*AXI_STRB_WIDTH-1:0] axi_if_wstrb;
wire [IF_COUNT-1:0] axi_if_wlast;
wire [IF_COUNT-1:0] axi_if_wvalid;
wire [IF_COUNT-1:0] axi_if_wready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_bid;
wire [IF_COUNT*2-1:0] axi_if_bresp;
wire [IF_COUNT-1:0] axi_if_bvalid;
wire [IF_COUNT-1:0] axi_if_bready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_arid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_araddr;
wire [IF_COUNT*8-1:0] axi_if_arlen;
wire [IF_COUNT*3-1:0] axi_if_arsize;
wire [IF_COUNT*2-1:0] axi_if_arburst;
wire [IF_COUNT-1:0] axi_if_arlock;
wire [IF_COUNT*4-1:0] axi_if_arcache;
wire [IF_COUNT*3-1:0] axi_if_arprot;
wire [IF_COUNT-1:0] axi_if_arvalid;
wire [IF_COUNT-1:0] axi_if_arready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_rid;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_rdata;
wire [IF_COUNT*2-1:0] axi_if_rresp;
wire [IF_COUNT-1:0] axi_if_rlast;
wire [IF_COUNT-1:0] axi_if_rvalid;
wire [IF_COUNT-1:0] axi_if_rready;
axil_interconnect #(
.DATA_WIDTH(AXIL_DATA_WIDTH),
.ADDR_WIDTH(AXIL_ADDR_WIDTH),
@ -1291,238 +1217,167 @@ axil_csr_interconnect_inst (
.m_axil_rready( {axil_ber_rready, axil_csr_rready})
);
axi_crossbar #(
.S_COUNT(1),
.M_COUNT(IF_COUNT),
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH),
.STRB_WIDTH(AXI_STRB_WIDTH),
.S_ID_WIDTH(AXI_ID_WIDTH),
.M_ID_WIDTH(IF_AXI_ID_WIDTH),
.AWUSER_ENABLE(0),
.WUSER_ENABLE(0),
.BUSER_ENABLE(0),
.ARUSER_ENABLE(0),
.RUSER_ENABLE(0),
.S_THREADS({2{32'd4}}),
.S_ACCEPT({2{32'd16}}),
.M_REGIONS(1),
.M_BASE_ADDR(IF_AXI_BASE_ADDR),
.M_ADDR_WIDTH({IF_COUNT{w_32(IF_AXI_ADDR_WIDTH)}}),
.M_CONNECT_READ({IF_COUNT{{2{1'b1}}}}),
.M_CONNECT_WRITE({IF_COUNT{{2{1'b1}}}}),
.M_ISSUE({IF_COUNT{32'd4}}),
.M_SECURE({IF_COUNT{1'b0}})
)
axi_crossbar_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.s_axi_awid( {axi_pcie_dma_awid}),
.s_axi_awaddr( {axi_pcie_dma_awaddr}),
.s_axi_awlen( {axi_pcie_dma_awlen}),
.s_axi_awsize( {axi_pcie_dma_awsize}),
.s_axi_awburst( {axi_pcie_dma_awburst}),
.s_axi_awlock( {axi_pcie_dma_awlock}),
.s_axi_awcache( {axi_pcie_dma_awcache}),
.s_axi_awprot( {axi_pcie_dma_awprot}),
.s_axi_awqos(0),
.s_axi_awuser(0),
.s_axi_awvalid( {axi_pcie_dma_awvalid}),
.s_axi_awready( {axi_pcie_dma_awready}),
.s_axi_wdata( {axi_pcie_dma_wdata}),
.s_axi_wstrb( {axi_pcie_dma_wstrb}),
.s_axi_wlast( {axi_pcie_dma_wlast}),
.s_axi_wuser(0),
.s_axi_wvalid( {axi_pcie_dma_wvalid}),
.s_axi_wready( {axi_pcie_dma_wready}),
.s_axi_bid( {axi_pcie_dma_bid}),
.s_axi_bresp( {axi_pcie_dma_bresp}),
.s_axi_buser(),
.s_axi_bvalid( {axi_pcie_dma_bvalid}),
.s_axi_bready( {axi_pcie_dma_bready}),
.s_axi_arid( {axi_pcie_dma_arid}),
.s_axi_araddr( {axi_pcie_dma_araddr}),
.s_axi_arlen( {axi_pcie_dma_arlen}),
.s_axi_arsize( {axi_pcie_dma_arsize}),
.s_axi_arburst( {axi_pcie_dma_arburst}),
.s_axi_arlock( {axi_pcie_dma_arlock}),
.s_axi_arcache( {axi_pcie_dma_arcache}),
.s_axi_arprot( {axi_pcie_dma_arprot}),
.s_axi_arqos(0),
.s_axi_aruser(0),
.s_axi_arvalid( {axi_pcie_dma_arvalid}),
.s_axi_arready( {axi_pcie_dma_arready}),
.s_axi_rid( {axi_pcie_dma_rid}),
.s_axi_rdata( {axi_pcie_dma_rdata}),
.s_axi_rresp( {axi_pcie_dma_rresp}),
.s_axi_rlast( {axi_pcie_dma_rlast}),
.s_axi_ruser(),
.s_axi_rvalid( {axi_pcie_dma_rvalid}),
.s_axi_rready( {axi_pcie_dma_rready}),
.m_axi_awid( {axi_if_awid}),
.m_axi_awaddr( {axi_if_awaddr}),
.m_axi_awlen( {axi_if_awlen}),
.m_axi_awsize( {axi_if_awsize}),
.m_axi_awburst( {axi_if_awburst}),
.m_axi_awlock( {axi_if_awlock}),
.m_axi_awcache( {axi_if_awcache}),
.m_axi_awprot( {axi_if_awprot}),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid( {axi_if_awvalid}),
.m_axi_awready( {axi_if_awready}),
.m_axi_wdata( {axi_if_wdata}),
.m_axi_wstrb( {axi_if_wstrb}),
.m_axi_wlast( {axi_if_wlast}),
.m_axi_wuser(),
.m_axi_wvalid( {axi_if_wvalid}),
.m_axi_wready( {axi_if_wready}),
.m_axi_bid( {axi_if_bid}),
.m_axi_bresp( {axi_if_bresp}),
.m_axi_buser(0),
.m_axi_bvalid( {axi_if_bvalid}),
.m_axi_bready( {axi_if_bready}),
.m_axi_arid( {axi_if_arid}),
.m_axi_araddr( {axi_if_araddr}),
.m_axi_arlen( {axi_if_arlen}),
.m_axi_arsize( {axi_if_arsize}),
.m_axi_arburst( {axi_if_arburst}),
.m_axi_arlock( {axi_if_arlock}),
.m_axi_arcache( {axi_if_arcache}),
.m_axi_arprot( {axi_if_arprot}),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid( {axi_if_arvalid}),
.m_axi_arready( {axi_if_arready}),
.m_axi_rid( {axi_if_rid}),
.m_axi_rdata( {axi_if_rdata}),
.m_axi_rresp( {axi_if_rresp}),
.m_axi_rlast( {axi_if_rlast}),
.m_axi_ruser(0),
.m_axi_rvalid( {axi_if_rvalid}),
.m_axi_rready( {axi_if_rready})
);
parameter IF_RAM_SEL_WIDTH = $clog2(PORTS_PER_IF+1);
parameter IF_PCIE_DMA_TAG_WIDTH = PCIE_DMA_TAG_WIDTH-$clog2(IF_COUNT);
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_pcie_addr;
wire [IF_COUNT*IF_RAM_SEL_WIDTH-1:0] if_pcie_dma_read_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_pcie_addr;
wire [IF_COUNT*IF_RAM_SEL_WIDTH-1:0] if_pcie_dma_write_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_status_valid;
pcie_axi_dma_desc_mux #
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_wr_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_BE_WIDTH-1:0] if_dma_ram_wr_cmd_be;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_wr_cmd_addr;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_wr_cmd_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_ready;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_rd_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_rd_cmd_addr;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_ready;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_rd_resp_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_ready;
dma_if_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.S_RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.M_RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_read_desc_mux_inst (
dma_if_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* Descriptor output
* Read descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_read_desc_len),
.m_axis_desc_tag(pcie_axi_dma_read_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_read_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_read_desc_ready),
.m_axis_read_desc_dma_addr(pcie_dma_read_desc_pcie_addr),
.m_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.m_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.m_axis_read_desc_len(pcie_dma_read_desc_len),
.m_axis_read_desc_tag(pcie_dma_read_desc_tag),
.m_axis_read_desc_valid(pcie_dma_read_desc_valid),
.m_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* Descriptor status input
* Read descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* Descriptor input
* Read descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_read_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_read_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_read_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(if_pcie_dma_read_desc_len),
.s_axis_read_desc_tag(if_pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(if_pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(if_pcie_dma_read_desc_ready),
/*
* Descriptor status output
* Read descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid)
);
pcie_axi_dma_desc_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_write_desc_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.m_axis_read_desc_status_tag(if_pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(if_pcie_dma_read_desc_status_valid),
/*
* Descriptor output
* Write descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_write_desc_len),
.m_axis_desc_tag(pcie_axi_dma_write_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_write_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_write_desc_ready),
.m_axis_write_desc_dma_addr(pcie_dma_write_desc_pcie_addr),
.m_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.m_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.m_axis_write_desc_len(pcie_dma_write_desc_len),
.m_axis_write_desc_tag(pcie_dma_write_desc_tag),
.m_axis_write_desc_valid(pcie_dma_write_desc_valid),
.m_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* Descriptor status input
* Write descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* Descriptor input
* Write descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_write_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_write_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_write_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(if_pcie_dma_write_desc_len),
.s_axis_write_desc_tag(if_pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(if_pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(if_pcie_dma_write_desc_ready),
/*
* Descriptor status output
* Write descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid)
.m_axis_write_desc_status_tag(if_pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(if_pcie_dma_write_desc_status_valid),
/*
* RAM interface (from DMA interface)
*/
.if_ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.if_ram_wr_cmd_be(dma_ram_wr_cmd_be),
.if_ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.if_ram_wr_cmd_data(dma_ram_wr_cmd_data),
.if_ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.if_ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.if_ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.if_ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.if_ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.if_ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.if_ram_rd_resp_data(dma_ram_rd_resp_data),
.if_ram_rd_resp_valid(dma_ram_rd_resp_valid),
.if_ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* RAM interface
*/
.ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(if_dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(if_dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready),
.ram_rd_resp_data(if_dma_ram_rd_resp_data),
.ram_rd_resp_valid(if_dma_ram_rd_resp_valid),
.ram_rd_resp_ready(if_dma_ram_rd_resp_ready)
);
// PTP clock
@ -1829,11 +1684,6 @@ generate
for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr_int;
assign if_pcie_axi_dma_read_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_read_desc_axi_addr_int | n*24'h800000;
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int;
assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
@ -1858,9 +1708,9 @@ generate
interface #(
.PORTS(PORTS_PER_IF),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1880,8 +1730,6 @@ generate
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),
.QUEUE_LOG_SIZE_WIDTH(4),
.RAM_ADDR_WIDTH(16),
.RAM_SIZE(2**15),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
@ -1889,49 +1737,57 @@ generate
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(IF_AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(IF_AXI_ID_WIDTH),
.AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE)
)
interface_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* PCIe DMA read descriptor output
* DMA read descriptor output
*/
.m_axis_pcie_axi_dma_read_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr_int),
.m_axis_pcie_axi_dma_read_desc_len(if_pcie_axi_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_tag(if_pcie_axi_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_valid(if_pcie_axi_dma_read_desc_valid[n]),
.m_axis_pcie_axi_dma_read_desc_ready(if_pcie_axi_dma_read_desc_ready[n]),
.m_axis_dma_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_read_desc_len(if_pcie_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_read_desc_tag(if_pcie_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_read_desc_valid(if_pcie_dma_read_desc_valid[n]),
.m_axis_dma_read_desc_ready(if_pcie_dma_read_desc_ready[n]),
/*
* PCIe DMA read descriptor status input
* DMA read descriptor status input
*/
.s_axis_pcie_axi_dma_read_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_read_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid[n]),
.s_axis_dma_read_desc_status_tag(if_pcie_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_read_desc_status_valid(if_pcie_dma_read_desc_status_valid[n]),
/*
* PCIe DMA write descriptor output
* DMA write descriptor output
*/
.m_axis_pcie_axi_dma_write_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr_int),
.m_axis_pcie_axi_dma_write_desc_len(if_pcie_axi_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_tag(if_pcie_axi_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_valid(if_pcie_axi_dma_write_desc_valid[n]),
.m_axis_pcie_axi_dma_write_desc_ready(if_pcie_axi_dma_write_desc_ready[n]),
.m_axis_dma_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_write_desc_len(if_pcie_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_write_desc_tag(if_pcie_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_write_desc_valid(if_pcie_dma_write_desc_valid[n]),
.m_axis_dma_write_desc_ready(if_pcie_dma_write_desc_ready[n]),
/*
* PCIe DMA write descriptor status input
* DMA write descriptor status input
*/
.s_axis_pcie_axi_dma_write_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_write_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid[n]),
.s_axis_dma_write_desc_status_tag(if_pcie_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_write_desc_status_valid(if_pcie_dma_write_desc_status_valid[n]),
/*
* AXI-Lite slave interface
@ -1980,43 +1836,21 @@ generate
.m_axil_csr_rready(axil_if_csr_rready[n]),
/*
* AXI slave inteface
* RAM interface
*/
.s_axi_awid(axi_if_awid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_awaddr(axi_if_awaddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_awlen(axi_if_awlen[n*8 +: 8]),
.s_axi_awsize(axi_if_awsize[n*3 +: 3]),
.s_axi_awburst(axi_if_awburst[n*2 +: 2]),
.s_axi_awlock(axi_if_awlock[n]),
.s_axi_awcache(axi_if_awcache[n*4 +: 4]),
.s_axi_awprot(axi_if_awprot[n*3 +: 3]),
.s_axi_awvalid(axi_if_awvalid[n]),
.s_axi_awready(axi_if_awready[n]),
.s_axi_wdata(axi_if_wdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_wstrb(axi_if_wstrb[n*AXI_STRB_WIDTH +: AXI_STRB_WIDTH]),
.s_axi_wlast(axi_if_wlast[n]),
.s_axi_wvalid(axi_if_wvalid[n]),
.s_axi_wready(axi_if_wready[n]),
.s_axi_bid(axi_if_bid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_bresp(axi_if_bresp[n*2 +: 2]),
.s_axi_bvalid(axi_if_bvalid[n]),
.s_axi_bready(axi_if_bready[n]),
.s_axi_arid(axi_if_arid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_araddr(axi_if_araddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_arlen(axi_if_arlen[n*8 +: 8]),
.s_axi_arsize(axi_if_arsize[n*3 +: 3]),
.s_axi_arburst(axi_if_arburst[n*2 +: 2]),
.s_axi_arlock(axi_if_arlock[n]),
.s_axi_arcache(axi_if_arcache[n*4 +: 4]),
.s_axi_arprot(axi_if_arprot[n*3 +: 3]),
.s_axi_arvalid(axi_if_arvalid[n]),
.s_axi_arready(axi_if_arready[n]),
.s_axi_rid(axi_if_rid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_rdata(axi_if_rdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_rresp(axi_if_rresp[n*2 +: 2]),
.s_axi_rlast(axi_if_rlast[n]),
.s_axi_rvalid(axi_if_rvalid[n]),
.s_axi_rready(axi_if_rready[n]),
.dma_ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_wr_cmd_be(if_dma_ram_wr_cmd_be[SEG_COUNT*SEG_BE_WIDTH*n +: SEG_COUNT*SEG_BE_WIDTH]),
.dma_ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_wr_cmd_data(if_dma_ram_wr_cmd_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_data(if_dma_ram_rd_resp_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_rd_resp_valid(if_dma_ram_rd_resp_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_ready(if_dma_ram_rd_resp_ready[SEG_COUNT*n +: SEG_COUNT]),
/*
* Transmit data output

25
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -78,18 +78,6 @@ srcs.append("../lib/eth/rtl/ptp_clock.v")
srcs.append("../lib/eth/rtl/ptp_clock_cdc.v")
srcs.append("../lib/eth/rtl/ptp_perout.v")
srcs.append("../lib/eth/rtl/ptp_ts_extract.v")
srcs.append("../lib/axi/rtl/axi_crossbar.v")
srcs.append("../lib/axi/rtl/axi_crossbar_addr.v")
srcs.append("../lib/axi/rtl/axi_crossbar_rd.v")
srcs.append("../lib/axi/rtl/axi_crossbar_wr.v")
srcs.append("../lib/axi/rtl/axi_dma.v")
srcs.append("../lib/axi/rtl/axi_dma_rd.v")
srcs.append("../lib/axi/rtl/axi_dma_wr.v")
srcs.append("../lib/axi/rtl/axi_ram.v")
srcs.append("../lib/axi/rtl/axi_ram_rd_if.v")
srcs.append("../lib/axi/rtl/axi_ram_wr_if.v")
srcs.append("../lib/axi/rtl/axi_register_rd.v")
srcs.append("../lib/axi/rtl/axi_register_wr.v")
srcs.append("../lib/axi/rtl/axil_interconnect.v")
srcs.append("../lib/axi/rtl/arbiter.v")
srcs.append("../lib/axi/rtl/priority_encoder.v")
@ -99,11 +87,16 @@ srcs.append("../lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/axis/rtl/axis_register.v")
srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v")
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_rd.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_mux.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_wr.v")
srcs.append("../lib/pcie/rtl/dma_psdpram.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_sink.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_source.v")
srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")

25
fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
View File

@ -43,18 +43,6 @@ SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
SYN_FILES += lib/axi/rtl/axi_crossbar.v
SYN_FILES += lib/axi/rtl/axi_crossbar_addr.v
SYN_FILES += lib/axi/rtl/axi_crossbar_rd.v
SYN_FILES += lib/axi/rtl/axi_crossbar_wr.v
SYN_FILES += lib/axi/rtl/axi_dma.v
SYN_FILES += lib/axi/rtl/axi_dma_rd.v
SYN_FILES += lib/axi/rtl/axi_dma_wr.v
SYN_FILES += lib/axi/rtl/axi_ram.v
SYN_FILES += lib/axi/rtl/axi_ram_rd_if.v
SYN_FILES += lib/axi/rtl/axi_ram_wr_if.v
SYN_FILES += lib/axi/rtl/axi_register_rd.v
SYN_FILES += lib/axi/rtl/axi_register_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/arbiter.v
SYN_FILES += lib/axi/rtl/priority_encoder.v
@ -65,13 +53,18 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
SYN_FILES += lib/pcie/rtl/pcie_axi_dma_desc_mux.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files

707
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -195,15 +195,9 @@ parameter AXIL_DATA_WIDTH = 32;
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
parameter AXIL_ADDR_WIDTH = 24;
// AXI interface parameters
parameter AXI_ID_WIDTH = 8;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = 24;
// AXI stream interface parameters
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH;
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH;
parameter AXIS_DATA_WIDTH = 256;
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8;
// PCIe DMA parameters
parameter PCIE_DMA_LEN_WIDTH = 16;
@ -268,6 +262,20 @@ parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 16384;
parameter RX_FIFO_DEPTH = 16384;
parameter MAX_TX_SIZE = 2048;
parameter MAX_RX_SIZE = 2048;
// PCIe DMA parameters
parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2;
parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT;
parameter SEG_ADDR_WIDTH = 12;
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8;
parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+$clog2(PORTS_PER_IF+1);
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH);
parameter RAM_PIPELINE = 4;
parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE;
parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE;
// AXI lite connections
wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
@ -310,42 +318,20 @@ wire [1:0] axil_csr_rresp;
wire axil_csr_rvalid;
wire axil_csr_rready;
// AXI connections
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_awid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_awaddr;
wire [7:0] axi_pcie_dma_awlen;
wire [2:0] axi_pcie_dma_awsize;
wire [1:0] axi_pcie_dma_awburst;
wire axi_pcie_dma_awlock;
wire [3:0] axi_pcie_dma_awcache;
wire [2:0] axi_pcie_dma_awprot;
wire axi_pcie_dma_awvalid;
wire axi_pcie_dma_awready;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_wdata;
wire [AXI_STRB_WIDTH-1:0] axi_pcie_dma_wstrb;
wire axi_pcie_dma_wlast;
wire axi_pcie_dma_wvalid;
wire axi_pcie_dma_wready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_bid;
wire [1:0] axi_pcie_dma_bresp;
wire axi_pcie_dma_bvalid;
wire axi_pcie_dma_bready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_arid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_araddr;
wire [7:0] axi_pcie_dma_arlen;
wire [2:0] axi_pcie_dma_arsize;
wire [1:0] axi_pcie_dma_arburst;
wire axi_pcie_dma_arlock;
wire [3:0] axi_pcie_dma_arcache;
wire [2:0] axi_pcie_dma_arprot;
wire axi_pcie_dma_arvalid;
wire axi_pcie_dma_arready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_rid;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_rdata;
wire [1:0] axi_pcie_dma_rresp;
wire axi_pcie_dma_rlast;
wire axi_pcie_dma_rvalid;
wire axi_pcie_dma_rready;
// DMA connections
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready;
// Error handling
wire [1:0] status_error_uncor_int;
@ -356,25 +342,27 @@ wire [31:0] msi_irq;
wire ext_tag_enable;
// PCIe DMA control
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_tag;
wire pcie_axi_dma_read_desc_valid;
wire pcie_axi_dma_read_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_read_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_read_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_tag;
wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_status_tag;
wire pcie_axi_dma_read_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_tag;
wire pcie_axi_dma_write_desc_valid;
wire pcie_axi_dma_write_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_write_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_write_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_tag;
wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_status_tag;
wire pcie_axi_dma_write_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1;
@ -887,23 +875,25 @@ rc_reg (
.m_axis_tuser(axis_rc_tuser_r)
);
pcie_us_axi_dma #(
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(256),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_CLIENT_TAG(1),
.PCIE_TAG_COUNT(64),
.PCIE_EXT_TAG_ENABLE(1),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.TAG_WIDTH(PCIE_DMA_TAG_WIDTH)
)
pcie_us_axi_dma_inst (
dma_if_pcie_us_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
@ -927,82 +917,56 @@ pcie_us_axi_dma_inst (
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* Tag input
*/
.s_axis_pcie_rq_tag(0),
.s_axis_pcie_rq_tag_valid(0),
/*
* AXI read descriptor input
*/
.s_axis_read_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.s_axis_read_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.s_axis_read_desc_len(pcie_axi_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_axi_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_axi_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_pcie_addr(pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(pcie_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* AXI read descriptor status output
*/
.m_axis_read_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* AXI write descriptor input
*/
.s_axis_write_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.s_axis_write_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.s_axis_write_desc_len(pcie_axi_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_axi_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_axi_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_pcie_addr(pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(pcie_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* AXI write descriptor status output
*/
.m_axis_write_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* AXI Master output
* RAM interface
*/
.m_axi_awid(axi_pcie_dma_awid),
.m_axi_awaddr(axi_pcie_dma_awaddr),
.m_axi_awlen(axi_pcie_dma_awlen),
.m_axi_awsize(axi_pcie_dma_awsize),
.m_axi_awburst(axi_pcie_dma_awburst),
.m_axi_awlock(axi_pcie_dma_awlock),
.m_axi_awcache(axi_pcie_dma_awcache),
.m_axi_awprot(axi_pcie_dma_awprot),
.m_axi_awvalid(axi_pcie_dma_awvalid),
.m_axi_awready(axi_pcie_dma_awready),
.m_axi_wdata(axi_pcie_dma_wdata),
.m_axi_wstrb(axi_pcie_dma_wstrb),
.m_axi_wlast(axi_pcie_dma_wlast),
.m_axi_wvalid(axi_pcie_dma_wvalid),
.m_axi_wready(axi_pcie_dma_wready),
.m_axi_bid(axi_pcie_dma_bid),
.m_axi_bresp(axi_pcie_dma_bresp),
.m_axi_bvalid(axi_pcie_dma_bvalid),
.m_axi_bready(axi_pcie_dma_bready),
.m_axi_arid(axi_pcie_dma_arid),
.m_axi_araddr(axi_pcie_dma_araddr),
.m_axi_arlen(axi_pcie_dma_arlen),
.m_axi_arsize(axi_pcie_dma_arsize),
.m_axi_arburst(axi_pcie_dma_arburst),
.m_axi_arlock(axi_pcie_dma_arlock),
.m_axi_arcache(axi_pcie_dma_arcache),
.m_axi_arprot(axi_pcie_dma_arprot),
.m_axi_arvalid(axi_pcie_dma_arvalid),
.m_axi_arready(axi_pcie_dma_arready),
.m_axi_rid(axi_pcie_dma_rid),
.m_axi_rdata(axi_pcie_dma_rdata),
.m_axi_rresp(axi_pcie_dma_rresp),
.m_axi_rlast(axi_pcie_dma_rlast),
.m_axi_rvalid(axi_pcie_dma_rvalid),
.m_axi_rready(axi_pcie_dma_rready),
.ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.ram_rd_resp_data(dma_ram_rd_resp_data),
.ram_rd_resp_valid(dma_ram_rd_resp_valid),
.ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* Configuration
@ -1090,22 +1054,6 @@ function [IF_AXIL_BASE_ADDR_WIDTH-1:0] calcIFAxiLiteBaseAddrs(input [31:0] if_ad
end
endfunction
parameter IF_AXI_ADDR_WIDTH = 32'd23;
parameter IF_AXI_BASE_ADDR_WIDTH = IF_COUNT*AXI_ADDR_WIDTH;
parameter IF_AXI_BASE_ADDR = calcIFAxiBaseAddrs(IF_AXI_ADDR_WIDTH);
function [IF_AXI_BASE_ADDR_WIDTH-1:0] calcIFAxiBaseAddrs(input [31:0] if_addr_width);
integer i;
begin
calcIFAxiBaseAddrs = {IF_AXI_BASE_ADDR_WIDTH{1'b0}};
for (i = 0; i < IF_COUNT; i = i + 1) begin
calcIFAxiBaseAddrs[i * AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = i * (2**if_addr_width);
end
end
endfunction
parameter IF_AXI_ID_WIDTH = AXI_ID_WIDTH+$clog2(2);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;
@ -1146,42 +1094,6 @@ wire [IF_COUNT*2-1:0] axil_if_csr_rresp;
wire [IF_COUNT-1:0] axil_if_csr_rvalid;
wire [IF_COUNT-1:0] axil_if_csr_rready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_awid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_awaddr;
wire [IF_COUNT*8-1:0] axi_if_awlen;
wire [IF_COUNT*3-1:0] axi_if_awsize;
wire [IF_COUNT*2-1:0] axi_if_awburst;
wire [IF_COUNT-1:0] axi_if_awlock;
wire [IF_COUNT*4-1:0] axi_if_awcache;
wire [IF_COUNT*3-1:0] axi_if_awprot;
wire [IF_COUNT-1:0] axi_if_awvalid;
wire [IF_COUNT-1:0] axi_if_awready;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_wdata;
wire [IF_COUNT*AXI_STRB_WIDTH-1:0] axi_if_wstrb;
wire [IF_COUNT-1:0] axi_if_wlast;
wire [IF_COUNT-1:0] axi_if_wvalid;
wire [IF_COUNT-1:0] axi_if_wready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_bid;
wire [IF_COUNT*2-1:0] axi_if_bresp;
wire [IF_COUNT-1:0] axi_if_bvalid;
wire [IF_COUNT-1:0] axi_if_bready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_arid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_araddr;
wire [IF_COUNT*8-1:0] axi_if_arlen;
wire [IF_COUNT*3-1:0] axi_if_arsize;
wire [IF_COUNT*2-1:0] axi_if_arburst;
wire [IF_COUNT-1:0] axi_if_arlock;
wire [IF_COUNT*4-1:0] axi_if_arcache;
wire [IF_COUNT*3-1:0] axi_if_arprot;
wire [IF_COUNT-1:0] axi_if_arvalid;
wire [IF_COUNT-1:0] axi_if_arready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_rid;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_rdata;
wire [IF_COUNT*2-1:0] axi_if_rresp;
wire [IF_COUNT-1:0] axi_if_rlast;
wire [IF_COUNT-1:0] axi_if_rvalid;
wire [IF_COUNT-1:0] axi_if_rready;
axil_interconnect #(
.DATA_WIDTH(AXIL_DATA_WIDTH),
.ADDR_WIDTH(AXIL_ADDR_WIDTH),
@ -1288,238 +1200,167 @@ axil_csr_interconnect_inst (
.m_axil_rready(axil_csr_rready)
);
axi_crossbar #(
.S_COUNT(1),
.M_COUNT(IF_COUNT),
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH),
.STRB_WIDTH(AXI_STRB_WIDTH),
.S_ID_WIDTH(AXI_ID_WIDTH),
.M_ID_WIDTH(IF_AXI_ID_WIDTH),
.AWUSER_ENABLE(0),
.WUSER_ENABLE(0),
.BUSER_ENABLE(0),
.ARUSER_ENABLE(0),
.RUSER_ENABLE(0),
.S_THREADS({2{32'd4}}),
.S_ACCEPT({2{32'd16}}),
.M_REGIONS(1),
.M_BASE_ADDR(IF_AXI_BASE_ADDR),
.M_ADDR_WIDTH({IF_COUNT{IF_AXI_ADDR_WIDTH}}),
.M_CONNECT_READ({IF_COUNT{{2{1'b1}}}}),
.M_CONNECT_WRITE({IF_COUNT{{2{1'b1}}}}),
.M_ISSUE({IF_COUNT{32'd4}}),
.M_SECURE({IF_COUNT{1'b0}})
)
axi_crossbar_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.s_axi_awid( {axi_pcie_dma_awid}),
.s_axi_awaddr( {axi_pcie_dma_awaddr}),
.s_axi_awlen( {axi_pcie_dma_awlen}),
.s_axi_awsize( {axi_pcie_dma_awsize}),
.s_axi_awburst( {axi_pcie_dma_awburst}),
.s_axi_awlock( {axi_pcie_dma_awlock}),
.s_axi_awcache( {axi_pcie_dma_awcache}),
.s_axi_awprot( {axi_pcie_dma_awprot}),
.s_axi_awqos(0),
.s_axi_awuser(0),
.s_axi_awvalid( {axi_pcie_dma_awvalid}),
.s_axi_awready( {axi_pcie_dma_awready}),
.s_axi_wdata( {axi_pcie_dma_wdata}),
.s_axi_wstrb( {axi_pcie_dma_wstrb}),
.s_axi_wlast( {axi_pcie_dma_wlast}),
.s_axi_wuser(0),
.s_axi_wvalid( {axi_pcie_dma_wvalid}),
.s_axi_wready( {axi_pcie_dma_wready}),
.s_axi_bid( {axi_pcie_dma_bid}),
.s_axi_bresp( {axi_pcie_dma_bresp}),
.s_axi_buser(),
.s_axi_bvalid( {axi_pcie_dma_bvalid}),
.s_axi_bready( {axi_pcie_dma_bready}),
.s_axi_arid( {axi_pcie_dma_arid}),
.s_axi_araddr( {axi_pcie_dma_araddr}),
.s_axi_arlen( {axi_pcie_dma_arlen}),
.s_axi_arsize( {axi_pcie_dma_arsize}),
.s_axi_arburst( {axi_pcie_dma_arburst}),
.s_axi_arlock( {axi_pcie_dma_arlock}),
.s_axi_arcache( {axi_pcie_dma_arcache}),
.s_axi_arprot( {axi_pcie_dma_arprot}),
.s_axi_arqos(0),
.s_axi_aruser(0),
.s_axi_arvalid( {axi_pcie_dma_arvalid}),
.s_axi_arready( {axi_pcie_dma_arready}),
.s_axi_rid( {axi_pcie_dma_rid}),
.s_axi_rdata( {axi_pcie_dma_rdata}),
.s_axi_rresp( {axi_pcie_dma_rresp}),
.s_axi_rlast( {axi_pcie_dma_rlast}),
.s_axi_ruser(),
.s_axi_rvalid( {axi_pcie_dma_rvalid}),
.s_axi_rready( {axi_pcie_dma_rready}),
.m_axi_awid( {axi_if_awid}),
.m_axi_awaddr( {axi_if_awaddr}),
.m_axi_awlen( {axi_if_awlen}),
.m_axi_awsize( {axi_if_awsize}),
.m_axi_awburst( {axi_if_awburst}),
.m_axi_awlock( {axi_if_awlock}),
.m_axi_awcache( {axi_if_awcache}),
.m_axi_awprot( {axi_if_awprot}),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid( {axi_if_awvalid}),
.m_axi_awready( {axi_if_awready}),
.m_axi_wdata( {axi_if_wdata}),
.m_axi_wstrb( {axi_if_wstrb}),
.m_axi_wlast( {axi_if_wlast}),
.m_axi_wuser(),
.m_axi_wvalid( {axi_if_wvalid}),
.m_axi_wready( {axi_if_wready}),
.m_axi_bid( {axi_if_bid}),
.m_axi_bresp( {axi_if_bresp}),
.m_axi_buser(0),
.m_axi_bvalid( {axi_if_bvalid}),
.m_axi_bready( {axi_if_bready}),
.m_axi_arid( {axi_if_arid}),
.m_axi_araddr( {axi_if_araddr}),
.m_axi_arlen( {axi_if_arlen}),
.m_axi_arsize( {axi_if_arsize}),
.m_axi_arburst( {axi_if_arburst}),
.m_axi_arlock( {axi_if_arlock}),
.m_axi_arcache( {axi_if_arcache}),
.m_axi_arprot( {axi_if_arprot}),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid( {axi_if_arvalid}),
.m_axi_arready( {axi_if_arready}),
.m_axi_rid( {axi_if_rid}),
.m_axi_rdata( {axi_if_rdata}),
.m_axi_rresp( {axi_if_rresp}),
.m_axi_rlast( {axi_if_rlast}),
.m_axi_ruser(0),
.m_axi_rvalid( {axi_if_rvalid}),
.m_axi_rready( {axi_if_rready})
);
parameter IF_RAM_SEL_WIDTH = $clog2(PORTS_PER_IF+1);
parameter IF_PCIE_DMA_TAG_WIDTH = PCIE_DMA_TAG_WIDTH-$clog2(IF_COUNT);
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_pcie_addr;
wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_read_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_pcie_addr;
wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_write_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_status_valid;
pcie_axi_dma_desc_mux #
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_wr_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_BE_WIDTH-1:0] if_dma_ram_wr_cmd_be;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_wr_cmd_addr;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_wr_cmd_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_ready;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_rd_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_rd_cmd_addr;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_ready;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_rd_resp_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_ready;
dma_if_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.S_RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.M_RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_read_desc_mux_inst (
dma_if_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* Descriptor output
* Read descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_read_desc_len),
.m_axis_desc_tag(pcie_axi_dma_read_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_read_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_read_desc_ready),
.m_axis_read_desc_dma_addr(pcie_dma_read_desc_pcie_addr),
.m_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.m_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.m_axis_read_desc_len(pcie_dma_read_desc_len),
.m_axis_read_desc_tag(pcie_dma_read_desc_tag),
.m_axis_read_desc_valid(pcie_dma_read_desc_valid),
.m_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* Descriptor status input
* Read descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* Descriptor input
* Read descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_read_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_read_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_read_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(if_pcie_dma_read_desc_len),
.s_axis_read_desc_tag(if_pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(if_pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(if_pcie_dma_read_desc_ready),
/*
* Descriptor status output
* Read descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid)
);
pcie_axi_dma_desc_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_write_desc_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.m_axis_read_desc_status_tag(if_pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(if_pcie_dma_read_desc_status_valid),
/*
* Descriptor output
* Write descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_write_desc_len),
.m_axis_desc_tag(pcie_axi_dma_write_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_write_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_write_desc_ready),
.m_axis_write_desc_dma_addr(pcie_dma_write_desc_pcie_addr),
.m_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.m_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.m_axis_write_desc_len(pcie_dma_write_desc_len),
.m_axis_write_desc_tag(pcie_dma_write_desc_tag),
.m_axis_write_desc_valid(pcie_dma_write_desc_valid),
.m_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* Descriptor status input
* Write descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* Descriptor input
* Write descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_write_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_write_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_write_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(if_pcie_dma_write_desc_len),
.s_axis_write_desc_tag(if_pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(if_pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(if_pcie_dma_write_desc_ready),
/*
* Descriptor status output
* Write descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid)
.m_axis_write_desc_status_tag(if_pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(if_pcie_dma_write_desc_status_valid),
/*
* RAM interface (from DMA interface)
*/
.if_ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.if_ram_wr_cmd_be(dma_ram_wr_cmd_be),
.if_ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.if_ram_wr_cmd_data(dma_ram_wr_cmd_data),
.if_ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.if_ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.if_ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.if_ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.if_ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.if_ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.if_ram_rd_resp_data(dma_ram_rd_resp_data),
.if_ram_rd_resp_valid(dma_ram_rd_resp_valid),
.if_ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* RAM interface
*/
.ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(if_dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(if_dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready),
.ram_rd_resp_data(if_dma_ram_rd_resp_data),
.ram_rd_resp_valid(if_dma_ram_rd_resp_valid),
.ram_rd_resp_ready(if_dma_ram_rd_resp_ready)
);
// PTP clock
@ -1652,11 +1493,6 @@ generate
for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr_int;
assign if_pcie_axi_dma_read_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_read_desc_axi_addr_int | n*24'h800000;
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int;
assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
@ -1679,12 +1515,11 @@ generate
wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
interface #
(
interface #(
.PORTS(PORTS_PER_IF),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1704,8 +1539,6 @@ generate
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),
.QUEUE_LOG_SIZE_WIDTH(4),
.RAM_ADDR_WIDTH(16),
.RAM_SIZE(2**15),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
@ -1713,49 +1546,57 @@ generate
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(IF_AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(IF_AXI_ID_WIDTH),
.AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE)
)
interface_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* PCIe DMA read descriptor output
* DMA read descriptor output
*/
.m_axis_pcie_axi_dma_read_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr_int),
.m_axis_pcie_axi_dma_read_desc_len(if_pcie_axi_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_tag(if_pcie_axi_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_valid(if_pcie_axi_dma_read_desc_valid[n]),
.m_axis_pcie_axi_dma_read_desc_ready(if_pcie_axi_dma_read_desc_ready[n]),
.m_axis_dma_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_read_desc_len(if_pcie_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_read_desc_tag(if_pcie_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_read_desc_valid(if_pcie_dma_read_desc_valid[n]),
.m_axis_dma_read_desc_ready(if_pcie_dma_read_desc_ready[n]),
/*
* PCIe DMA read descriptor status input
* DMA read descriptor status input
*/
.s_axis_pcie_axi_dma_read_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_read_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid[n]),
.s_axis_dma_read_desc_status_tag(if_pcie_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_read_desc_status_valid(if_pcie_dma_read_desc_status_valid[n]),
/*
* PCIe DMA write descriptor output
* DMA write descriptor output
*/
.m_axis_pcie_axi_dma_write_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr_int),
.m_axis_pcie_axi_dma_write_desc_len(if_pcie_axi_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_tag(if_pcie_axi_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_valid(if_pcie_axi_dma_write_desc_valid[n]),
.m_axis_pcie_axi_dma_write_desc_ready(if_pcie_axi_dma_write_desc_ready[n]),
.m_axis_dma_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_write_desc_len(if_pcie_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_write_desc_tag(if_pcie_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_write_desc_valid(if_pcie_dma_write_desc_valid[n]),
.m_axis_dma_write_desc_ready(if_pcie_dma_write_desc_ready[n]),
/*
* PCIe DMA write descriptor status input
* DMA write descriptor status input
*/
.s_axis_pcie_axi_dma_write_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_write_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid[n]),
.s_axis_dma_write_desc_status_tag(if_pcie_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_write_desc_status_valid(if_pcie_dma_write_desc_status_valid[n]),
/*
* AXI-Lite slave interface
@ -1804,43 +1645,21 @@ generate
.m_axil_csr_rready(axil_if_csr_rready[n]),
/*
* AXI slave inteface
* RAM interface
*/
.s_axi_awid(axi_if_awid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_awaddr(axi_if_awaddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_awlen(axi_if_awlen[n*8 +: 8]),
.s_axi_awsize(axi_if_awsize[n*3 +: 3]),
.s_axi_awburst(axi_if_awburst[n*2 +: 2]),
.s_axi_awlock(axi_if_awlock[n]),
.s_axi_awcache(axi_if_awcache[n*4 +: 4]),
.s_axi_awprot(axi_if_awprot[n*3 +: 3]),
.s_axi_awvalid(axi_if_awvalid[n]),
.s_axi_awready(axi_if_awready[n]),
.s_axi_wdata(axi_if_wdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_wstrb(axi_if_wstrb[n*AXI_STRB_WIDTH +: AXI_STRB_WIDTH]),
.s_axi_wlast(axi_if_wlast[n]),
.s_axi_wvalid(axi_if_wvalid[n]),
.s_axi_wready(axi_if_wready[n]),
.s_axi_bid(axi_if_bid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_bresp(axi_if_bresp[n*2 +: 2]),
.s_axi_bvalid(axi_if_bvalid[n]),
.s_axi_bready(axi_if_bready[n]),
.s_axi_arid(axi_if_arid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_araddr(axi_if_araddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_arlen(axi_if_arlen[n*8 +: 8]),
.s_axi_arsize(axi_if_arsize[n*3 +: 3]),
.s_axi_arburst(axi_if_arburst[n*2 +: 2]),
.s_axi_arlock(axi_if_arlock[n]),
.s_axi_arcache(axi_if_arcache[n*4 +: 4]),
.s_axi_arprot(axi_if_arprot[n*3 +: 3]),
.s_axi_arvalid(axi_if_arvalid[n]),
.s_axi_arready(axi_if_arready[n]),
.s_axi_rid(axi_if_rid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_rdata(axi_if_rdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_rresp(axi_if_rresp[n*2 +: 2]),
.s_axi_rlast(axi_if_rlast[n]),
.s_axi_rvalid(axi_if_rvalid[n]),
.s_axi_rready(axi_if_rready[n]),
.dma_ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_wr_cmd_be(if_dma_ram_wr_cmd_be[SEG_COUNT*SEG_BE_WIDTH*n +: SEG_COUNT*SEG_BE_WIDTH]),
.dma_ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_wr_cmd_data(if_dma_ram_wr_cmd_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_data(if_dma_ram_rd_resp_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_rd_resp_valid(if_dma_ram_rd_resp_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_ready(if_dma_ram_rd_resp_ready[SEG_COUNT*n +: SEG_COUNT]),
/*
* Transmit data output

25
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -76,18 +76,6 @@ srcs.append("../lib/eth/rtl/ptp_clock.v")
srcs.append("../lib/eth/rtl/ptp_clock_cdc.v")
srcs.append("../lib/eth/rtl/ptp_perout.v")
srcs.append("../lib/eth/rtl/ptp_ts_extract.v")
srcs.append("../lib/axi/rtl/axi_crossbar.v")
srcs.append("../lib/axi/rtl/axi_crossbar_addr.v")
srcs.append("../lib/axi/rtl/axi_crossbar_rd.v")
srcs.append("../lib/axi/rtl/axi_crossbar_wr.v")
srcs.append("../lib/axi/rtl/axi_dma.v")
srcs.append("../lib/axi/rtl/axi_dma_rd.v")
srcs.append("../lib/axi/rtl/axi_dma_wr.v")
srcs.append("../lib/axi/rtl/axi_ram.v")
srcs.append("../lib/axi/rtl/axi_ram_rd_if.v")
srcs.append("../lib/axi/rtl/axi_ram_wr_if.v")
srcs.append("../lib/axi/rtl/axi_register_rd.v")
srcs.append("../lib/axi/rtl/axi_register_wr.v")
srcs.append("../lib/axi/rtl/axil_interconnect.v")
srcs.append("../lib/axi/rtl/arbiter.v")
srcs.append("../lib/axi/rtl/priority_encoder.v")
@ -97,11 +85,16 @@ srcs.append("../lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/axis/rtl/axis_register.v")
srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v")
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_rd.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_mux.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_wr.v")
srcs.append("../lib/pcie/rtl/dma_psdpram.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_sink.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_source.v")
srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")

25
fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
View File

@ -45,18 +45,6 @@ SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
SYN_FILES += lib/axi/rtl/axi_crossbar.v
SYN_FILES += lib/axi/rtl/axi_crossbar_addr.v
SYN_FILES += lib/axi/rtl/axi_crossbar_rd.v
SYN_FILES += lib/axi/rtl/axi_crossbar_wr.v
SYN_FILES += lib/axi/rtl/axi_dma.v
SYN_FILES += lib/axi/rtl/axi_dma_rd.v
SYN_FILES += lib/axi/rtl/axi_dma_wr.v
SYN_FILES += lib/axi/rtl/axi_ram.v
SYN_FILES += lib/axi/rtl/axi_ram_rd_if.v
SYN_FILES += lib/axi/rtl/axi_ram_wr_if.v
SYN_FILES += lib/axi/rtl/axi_register_rd.v
SYN_FILES += lib/axi/rtl/axi_register_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/arbiter.v
SYN_FILES += lib/axi/rtl/priority_encoder.v
@ -67,13 +55,18 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
SYN_FILES += lib/pcie/rtl/pcie_axi_dma_desc_mux.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files

707
fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -223,15 +223,9 @@ parameter AXIL_DATA_WIDTH = 32;
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
parameter AXIL_ADDR_WIDTH = 24;
// AXI interface parameters
parameter AXI_ID_WIDTH = 8;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = 24;
// AXI stream interface parameters
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH;
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH;
parameter AXIS_DATA_WIDTH = 256;
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8;
// PCIe DMA parameters
parameter PCIE_DMA_LEN_WIDTH = 16;
@ -296,6 +290,20 @@ parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 32768;
parameter RX_FIFO_DEPTH = 32768;
parameter MAX_TX_SIZE = 2048;
parameter MAX_RX_SIZE = 2048;
// PCIe DMA parameters
parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2;
parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT;
parameter SEG_ADDR_WIDTH = 12;
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8;
parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+$clog2(PORTS_PER_IF+1);
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH);
parameter RAM_PIPELINE = 2;
parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE;
parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE;
// AXI lite connections
wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
@ -358,42 +366,20 @@ wire [1:0] axil_ber_rresp;
wire axil_ber_rvalid;
wire axil_ber_rready;
// AXI connections
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_awid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_awaddr;
wire [7:0] axi_pcie_dma_awlen;
wire [2:0] axi_pcie_dma_awsize;
wire [1:0] axi_pcie_dma_awburst;
wire axi_pcie_dma_awlock;
wire [3:0] axi_pcie_dma_awcache;
wire [2:0] axi_pcie_dma_awprot;
wire axi_pcie_dma_awvalid;
wire axi_pcie_dma_awready;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_wdata;
wire [AXI_STRB_WIDTH-1:0] axi_pcie_dma_wstrb;
wire axi_pcie_dma_wlast;
wire axi_pcie_dma_wvalid;
wire axi_pcie_dma_wready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_bid;
wire [1:0] axi_pcie_dma_bresp;
wire axi_pcie_dma_bvalid;
wire axi_pcie_dma_bready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_arid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_araddr;
wire [7:0] axi_pcie_dma_arlen;
wire [2:0] axi_pcie_dma_arsize;
wire [1:0] axi_pcie_dma_arburst;
wire axi_pcie_dma_arlock;
wire [3:0] axi_pcie_dma_arcache;
wire [2:0] axi_pcie_dma_arprot;
wire axi_pcie_dma_arvalid;
wire axi_pcie_dma_arready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_rid;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_rdata;
wire [1:0] axi_pcie_dma_rresp;
wire axi_pcie_dma_rlast;
wire axi_pcie_dma_rvalid;
wire axi_pcie_dma_rready;
// DMA connections
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready;
// Error handling
wire [1:0] status_error_uncor_int;
@ -404,25 +390,27 @@ wire [31:0] msi_irq;
wire ext_tag_enable;
// PCIe DMA control
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_tag;
wire pcie_axi_dma_read_desc_valid;
wire pcie_axi_dma_read_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_read_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_read_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_tag;
wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_status_tag;
wire pcie_axi_dma_read_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_tag;
wire pcie_axi_dma_write_desc_valid;
wire pcie_axi_dma_write_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_write_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_write_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_tag;
wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_status_tag;
wire pcie_axi_dma_write_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1;
@ -908,23 +896,25 @@ rc_reg (
.m_axis_tuser(axis_rc_tuser_r)
);
pcie_us_axi_dma #(
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(256),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_CLIENT_TAG(1),
.PCIE_TAG_COUNT(64),
.PCIE_EXT_TAG_ENABLE(1),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.TAG_WIDTH(PCIE_DMA_TAG_WIDTH)
)
pcie_us_axi_dma_inst (
dma_if_pcie_us_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
@ -948,82 +938,56 @@ pcie_us_axi_dma_inst (
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* Tag input
*/
.s_axis_pcie_rq_tag(0),
.s_axis_pcie_rq_tag_valid(0),
/*
* AXI read descriptor input
*/
.s_axis_read_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.s_axis_read_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.s_axis_read_desc_len(pcie_axi_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_axi_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_axi_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_pcie_addr(pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(pcie_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* AXI read descriptor status output
*/
.m_axis_read_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* AXI write descriptor input
*/
.s_axis_write_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.s_axis_write_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.s_axis_write_desc_len(pcie_axi_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_axi_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_axi_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_pcie_addr(pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(pcie_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* AXI write descriptor status output
*/
.m_axis_write_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* AXI Master output
* RAM interface
*/
.m_axi_awid(axi_pcie_dma_awid),
.m_axi_awaddr(axi_pcie_dma_awaddr),
.m_axi_awlen(axi_pcie_dma_awlen),
.m_axi_awsize(axi_pcie_dma_awsize),
.m_axi_awburst(axi_pcie_dma_awburst),
.m_axi_awlock(axi_pcie_dma_awlock),
.m_axi_awcache(axi_pcie_dma_awcache),
.m_axi_awprot(axi_pcie_dma_awprot),
.m_axi_awvalid(axi_pcie_dma_awvalid),
.m_axi_awready(axi_pcie_dma_awready),
.m_axi_wdata(axi_pcie_dma_wdata),
.m_axi_wstrb(axi_pcie_dma_wstrb),
.m_axi_wlast(axi_pcie_dma_wlast),
.m_axi_wvalid(axi_pcie_dma_wvalid),
.m_axi_wready(axi_pcie_dma_wready),
.m_axi_bid(axi_pcie_dma_bid),
.m_axi_bresp(axi_pcie_dma_bresp),
.m_axi_bvalid(axi_pcie_dma_bvalid),
.m_axi_bready(axi_pcie_dma_bready),
.m_axi_arid(axi_pcie_dma_arid),
.m_axi_araddr(axi_pcie_dma_araddr),
.m_axi_arlen(axi_pcie_dma_arlen),
.m_axi_arsize(axi_pcie_dma_arsize),
.m_axi_arburst(axi_pcie_dma_arburst),
.m_axi_arlock(axi_pcie_dma_arlock),
.m_axi_arcache(axi_pcie_dma_arcache),
.m_axi_arprot(axi_pcie_dma_arprot),
.m_axi_arvalid(axi_pcie_dma_arvalid),
.m_axi_arready(axi_pcie_dma_arready),
.m_axi_rid(axi_pcie_dma_rid),
.m_axi_rdata(axi_pcie_dma_rdata),
.m_axi_rresp(axi_pcie_dma_rresp),
.m_axi_rlast(axi_pcie_dma_rlast),
.m_axi_rvalid(axi_pcie_dma_rvalid),
.m_axi_rready(axi_pcie_dma_rready),
.ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.ram_rd_resp_data(dma_ram_rd_resp_data),
.ram_rd_resp_valid(dma_ram_rd_resp_valid),
.ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* Configuration
@ -1111,22 +1075,6 @@ function [IF_AXIL_BASE_ADDR_WIDTH-1:0] calcIFAxiLiteBaseAddrs(input [31:0] if_ad
end
endfunction
parameter IF_AXI_ADDR_WIDTH = 32'd23;
parameter IF_AXI_BASE_ADDR_WIDTH = IF_COUNT*AXI_ADDR_WIDTH;
parameter IF_AXI_BASE_ADDR = calcIFAxiBaseAddrs(IF_AXI_ADDR_WIDTH);
function [IF_AXI_BASE_ADDR_WIDTH-1:0] calcIFAxiBaseAddrs(input [31:0] if_addr_width);
integer i;
begin
calcIFAxiBaseAddrs = {IF_AXI_BASE_ADDR_WIDTH{1'b0}};
for (i = 0; i < IF_COUNT; i = i + 1) begin
calcIFAxiBaseAddrs[i * AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = i * (2**if_addr_width);
end
end
endfunction
parameter IF_AXI_ID_WIDTH = AXI_ID_WIDTH+$clog2(2);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;
@ -1167,42 +1115,6 @@ wire [IF_COUNT*2-1:0] axil_if_csr_rresp;
wire [IF_COUNT-1:0] axil_if_csr_rvalid;
wire [IF_COUNT-1:0] axil_if_csr_rready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_awid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_awaddr;
wire [IF_COUNT*8-1:0] axi_if_awlen;
wire [IF_COUNT*3-1:0] axi_if_awsize;
wire [IF_COUNT*2-1:0] axi_if_awburst;
wire [IF_COUNT-1:0] axi_if_awlock;
wire [IF_COUNT*4-1:0] axi_if_awcache;
wire [IF_COUNT*3-1:0] axi_if_awprot;
wire [IF_COUNT-1:0] axi_if_awvalid;
wire [IF_COUNT-1:0] axi_if_awready;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_wdata;
wire [IF_COUNT*AXI_STRB_WIDTH-1:0] axi_if_wstrb;
wire [IF_COUNT-1:0] axi_if_wlast;
wire [IF_COUNT-1:0] axi_if_wvalid;
wire [IF_COUNT-1:0] axi_if_wready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_bid;
wire [IF_COUNT*2-1:0] axi_if_bresp;
wire [IF_COUNT-1:0] axi_if_bvalid;
wire [IF_COUNT-1:0] axi_if_bready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_arid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_araddr;
wire [IF_COUNT*8-1:0] axi_if_arlen;
wire [IF_COUNT*3-1:0] axi_if_arsize;
wire [IF_COUNT*2-1:0] axi_if_arburst;
wire [IF_COUNT-1:0] axi_if_arlock;
wire [IF_COUNT*4-1:0] axi_if_arcache;
wire [IF_COUNT*3-1:0] axi_if_arprot;
wire [IF_COUNT-1:0] axi_if_arvalid;
wire [IF_COUNT-1:0] axi_if_arready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_rid;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_rdata;
wire [IF_COUNT*2-1:0] axi_if_rresp;
wire [IF_COUNT-1:0] axi_if_rlast;
wire [IF_COUNT-1:0] axi_if_rvalid;
wire [IF_COUNT-1:0] axi_if_rready;
axil_interconnect #(
.DATA_WIDTH(AXIL_DATA_WIDTH),
.ADDR_WIDTH(AXIL_ADDR_WIDTH),
@ -1313,238 +1225,167 @@ axil_csr_interconnect_inst (
.m_axil_rready( {axil_ber_rready, axil_csr_rready})
);
axi_crossbar #(
.S_COUNT(1),
.M_COUNT(IF_COUNT),
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH),
.STRB_WIDTH(AXI_STRB_WIDTH),
.S_ID_WIDTH(AXI_ID_WIDTH),
.M_ID_WIDTH(IF_AXI_ID_WIDTH),
.AWUSER_ENABLE(0),
.WUSER_ENABLE(0),
.BUSER_ENABLE(0),
.ARUSER_ENABLE(0),
.RUSER_ENABLE(0),
.S_THREADS({2{32'd4}}),
.S_ACCEPT({2{32'd16}}),
.M_REGIONS(1),
.M_BASE_ADDR(IF_AXI_BASE_ADDR),
.M_ADDR_WIDTH({IF_COUNT{IF_AXI_ADDR_WIDTH}}),
.M_CONNECT_READ({IF_COUNT{{2{1'b1}}}}),
.M_CONNECT_WRITE({IF_COUNT{{2{1'b1}}}}),
.M_ISSUE({IF_COUNT{32'd4}}),
.M_SECURE({IF_COUNT{1'b0}})
)
axi_crossbar_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.s_axi_awid( {axi_pcie_dma_awid}),
.s_axi_awaddr( {axi_pcie_dma_awaddr}),
.s_axi_awlen( {axi_pcie_dma_awlen}),
.s_axi_awsize( {axi_pcie_dma_awsize}),
.s_axi_awburst( {axi_pcie_dma_awburst}),
.s_axi_awlock( {axi_pcie_dma_awlock}),
.s_axi_awcache( {axi_pcie_dma_awcache}),
.s_axi_awprot( {axi_pcie_dma_awprot}),
.s_axi_awqos(0),
.s_axi_awuser(0),
.s_axi_awvalid( {axi_pcie_dma_awvalid}),
.s_axi_awready( {axi_pcie_dma_awready}),
.s_axi_wdata( {axi_pcie_dma_wdata}),
.s_axi_wstrb( {axi_pcie_dma_wstrb}),
.s_axi_wlast( {axi_pcie_dma_wlast}),
.s_axi_wuser(0),
.s_axi_wvalid( {axi_pcie_dma_wvalid}),
.s_axi_wready( {axi_pcie_dma_wready}),
.s_axi_bid( {axi_pcie_dma_bid}),
.s_axi_bresp( {axi_pcie_dma_bresp}),
.s_axi_buser(),
.s_axi_bvalid( {axi_pcie_dma_bvalid}),
.s_axi_bready( {axi_pcie_dma_bready}),
.s_axi_arid( {axi_pcie_dma_arid}),
.s_axi_araddr( {axi_pcie_dma_araddr}),
.s_axi_arlen( {axi_pcie_dma_arlen}),
.s_axi_arsize( {axi_pcie_dma_arsize}),
.s_axi_arburst( {axi_pcie_dma_arburst}),
.s_axi_arlock( {axi_pcie_dma_arlock}),
.s_axi_arcache( {axi_pcie_dma_arcache}),
.s_axi_arprot( {axi_pcie_dma_arprot}),
.s_axi_arqos(0),
.s_axi_aruser(0),
.s_axi_arvalid( {axi_pcie_dma_arvalid}),
.s_axi_arready( {axi_pcie_dma_arready}),
.s_axi_rid( {axi_pcie_dma_rid}),
.s_axi_rdata( {axi_pcie_dma_rdata}),
.s_axi_rresp( {axi_pcie_dma_rresp}),
.s_axi_rlast( {axi_pcie_dma_rlast}),
.s_axi_ruser(),
.s_axi_rvalid( {axi_pcie_dma_rvalid}),
.s_axi_rready( {axi_pcie_dma_rready}),
.m_axi_awid( {axi_if_awid}),
.m_axi_awaddr( {axi_if_awaddr}),
.m_axi_awlen( {axi_if_awlen}),
.m_axi_awsize( {axi_if_awsize}),
.m_axi_awburst( {axi_if_awburst}),
.m_axi_awlock( {axi_if_awlock}),
.m_axi_awcache( {axi_if_awcache}),
.m_axi_awprot( {axi_if_awprot}),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid( {axi_if_awvalid}),
.m_axi_awready( {axi_if_awready}),
.m_axi_wdata( {axi_if_wdata}),
.m_axi_wstrb( {axi_if_wstrb}),
.m_axi_wlast( {axi_if_wlast}),
.m_axi_wuser(),
.m_axi_wvalid( {axi_if_wvalid}),
.m_axi_wready( {axi_if_wready}),
.m_axi_bid( {axi_if_bid}),
.m_axi_bresp( {axi_if_bresp}),
.m_axi_buser(0),
.m_axi_bvalid( {axi_if_bvalid}),
.m_axi_bready( {axi_if_bready}),
.m_axi_arid( {axi_if_arid}),
.m_axi_araddr( {axi_if_araddr}),
.m_axi_arlen( {axi_if_arlen}),
.m_axi_arsize( {axi_if_arsize}),
.m_axi_arburst( {axi_if_arburst}),
.m_axi_arlock( {axi_if_arlock}),
.m_axi_arcache( {axi_if_arcache}),
.m_axi_arprot( {axi_if_arprot}),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid( {axi_if_arvalid}),
.m_axi_arready( {axi_if_arready}),
.m_axi_rid( {axi_if_rid}),
.m_axi_rdata( {axi_if_rdata}),
.m_axi_rresp( {axi_if_rresp}),
.m_axi_rlast( {axi_if_rlast}),
.m_axi_ruser(0),
.m_axi_rvalid( {axi_if_rvalid}),
.m_axi_rready( {axi_if_rready})
);
parameter IF_RAM_SEL_WIDTH = $clog2(PORTS_PER_IF+1);
parameter IF_PCIE_DMA_TAG_WIDTH = PCIE_DMA_TAG_WIDTH-$clog2(IF_COUNT);
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_pcie_addr;
wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_read_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_pcie_addr;
wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_write_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_status_valid;
pcie_axi_dma_desc_mux #
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_wr_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_BE_WIDTH-1:0] if_dma_ram_wr_cmd_be;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_wr_cmd_addr;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_wr_cmd_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_ready;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_rd_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_rd_cmd_addr;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_ready;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_rd_resp_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_ready;
dma_if_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.S_RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.M_RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_read_desc_mux_inst (
dma_if_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* Descriptor output
* Read descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_read_desc_len),
.m_axis_desc_tag(pcie_axi_dma_read_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_read_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_read_desc_ready),
.m_axis_read_desc_dma_addr(pcie_dma_read_desc_pcie_addr),
.m_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.m_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.m_axis_read_desc_len(pcie_dma_read_desc_len),
.m_axis_read_desc_tag(pcie_dma_read_desc_tag),
.m_axis_read_desc_valid(pcie_dma_read_desc_valid),
.m_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* Descriptor status input
* Read descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* Descriptor input
* Read descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_read_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_read_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_read_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(if_pcie_dma_read_desc_len),
.s_axis_read_desc_tag(if_pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(if_pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(if_pcie_dma_read_desc_ready),
/*
* Descriptor status output
* Read descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid)
);
pcie_axi_dma_desc_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_write_desc_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.m_axis_read_desc_status_tag(if_pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(if_pcie_dma_read_desc_status_valid),
/*
* Descriptor output
* Write descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_write_desc_len),
.m_axis_desc_tag(pcie_axi_dma_write_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_write_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_write_desc_ready),
.m_axis_write_desc_dma_addr(pcie_dma_write_desc_pcie_addr),
.m_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.m_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.m_axis_write_desc_len(pcie_dma_write_desc_len),
.m_axis_write_desc_tag(pcie_dma_write_desc_tag),
.m_axis_write_desc_valid(pcie_dma_write_desc_valid),
.m_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* Descriptor status input
* Write descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* Descriptor input
* Write descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_write_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_write_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_write_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(if_pcie_dma_write_desc_len),
.s_axis_write_desc_tag(if_pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(if_pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(if_pcie_dma_write_desc_ready),
/*
* Descriptor status output
* Write descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid)
.m_axis_write_desc_status_tag(if_pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(if_pcie_dma_write_desc_status_valid),
/*
* RAM interface (from DMA interface)
*/
.if_ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.if_ram_wr_cmd_be(dma_ram_wr_cmd_be),
.if_ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.if_ram_wr_cmd_data(dma_ram_wr_cmd_data),
.if_ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.if_ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.if_ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.if_ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.if_ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.if_ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.if_ram_rd_resp_data(dma_ram_rd_resp_data),
.if_ram_rd_resp_valid(dma_ram_rd_resp_valid),
.if_ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* RAM interface
*/
.ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(if_dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(if_dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready),
.ram_rd_resp_data(if_dma_ram_rd_resp_data),
.ram_rd_resp_valid(if_dma_ram_rd_resp_valid),
.ram_rd_resp_ready(if_dma_ram_rd_resp_ready)
);
// PTP clock
@ -1802,11 +1643,6 @@ generate
for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr_int;
assign if_pcie_axi_dma_read_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_read_desc_axi_addr_int | n*24'h800000;
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int;
assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
@ -1829,12 +1665,11 @@ generate
wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
interface #
(
interface #(
.PORTS(PORTS_PER_IF),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1854,8 +1689,6 @@ generate
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),
.QUEUE_LOG_SIZE_WIDTH(4),
.RAM_ADDR_WIDTH(16),
.RAM_SIZE(2**15),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
@ -1863,49 +1696,57 @@ generate
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(IF_AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(IF_AXI_ID_WIDTH),
.AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE)
)
interface_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* PCIe DMA read descriptor output
* DMA read descriptor output
*/
.m_axis_pcie_axi_dma_read_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr_int),
.m_axis_pcie_axi_dma_read_desc_len(if_pcie_axi_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_tag(if_pcie_axi_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_valid(if_pcie_axi_dma_read_desc_valid[n]),
.m_axis_pcie_axi_dma_read_desc_ready(if_pcie_axi_dma_read_desc_ready[n]),
.m_axis_dma_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_read_desc_len(if_pcie_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_read_desc_tag(if_pcie_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_read_desc_valid(if_pcie_dma_read_desc_valid[n]),
.m_axis_dma_read_desc_ready(if_pcie_dma_read_desc_ready[n]),
/*
* PCIe DMA read descriptor status input
* DMA read descriptor status input
*/
.s_axis_pcie_axi_dma_read_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_read_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid[n]),
.s_axis_dma_read_desc_status_tag(if_pcie_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_read_desc_status_valid(if_pcie_dma_read_desc_status_valid[n]),
/*
* PCIe DMA write descriptor output
* DMA write descriptor output
*/
.m_axis_pcie_axi_dma_write_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr_int),
.m_axis_pcie_axi_dma_write_desc_len(if_pcie_axi_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_tag(if_pcie_axi_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_valid(if_pcie_axi_dma_write_desc_valid[n]),
.m_axis_pcie_axi_dma_write_desc_ready(if_pcie_axi_dma_write_desc_ready[n]),
.m_axis_dma_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_write_desc_len(if_pcie_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_write_desc_tag(if_pcie_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_write_desc_valid(if_pcie_dma_write_desc_valid[n]),
.m_axis_dma_write_desc_ready(if_pcie_dma_write_desc_ready[n]),
/*
* PCIe DMA write descriptor status input
* DMA write descriptor status input
*/
.s_axis_pcie_axi_dma_write_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_write_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid[n]),
.s_axis_dma_write_desc_status_tag(if_pcie_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_write_desc_status_valid(if_pcie_dma_write_desc_status_valid[n]),
/*
* AXI-Lite slave interface
@ -1954,43 +1795,21 @@ generate
.m_axil_csr_rready(axil_if_csr_rready[n]),
/*
* AXI slave inteface
* RAM interface
*/
.s_axi_awid(axi_if_awid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_awaddr(axi_if_awaddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_awlen(axi_if_awlen[n*8 +: 8]),
.s_axi_awsize(axi_if_awsize[n*3 +: 3]),
.s_axi_awburst(axi_if_awburst[n*2 +: 2]),
.s_axi_awlock(axi_if_awlock[n]),
.s_axi_awcache(axi_if_awcache[n*4 +: 4]),
.s_axi_awprot(axi_if_awprot[n*3 +: 3]),
.s_axi_awvalid(axi_if_awvalid[n]),
.s_axi_awready(axi_if_awready[n]),
.s_axi_wdata(axi_if_wdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_wstrb(axi_if_wstrb[n*AXI_STRB_WIDTH +: AXI_STRB_WIDTH]),
.s_axi_wlast(axi_if_wlast[n]),
.s_axi_wvalid(axi_if_wvalid[n]),
.s_axi_wready(axi_if_wready[n]),
.s_axi_bid(axi_if_bid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_bresp(axi_if_bresp[n*2 +: 2]),
.s_axi_bvalid(axi_if_bvalid[n]),
.s_axi_bready(axi_if_bready[n]),
.s_axi_arid(axi_if_arid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_araddr(axi_if_araddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_arlen(axi_if_arlen[n*8 +: 8]),
.s_axi_arsize(axi_if_arsize[n*3 +: 3]),
.s_axi_arburst(axi_if_arburst[n*2 +: 2]),
.s_axi_arlock(axi_if_arlock[n]),
.s_axi_arcache(axi_if_arcache[n*4 +: 4]),
.s_axi_arprot(axi_if_arprot[n*3 +: 3]),
.s_axi_arvalid(axi_if_arvalid[n]),
.s_axi_arready(axi_if_arready[n]),
.s_axi_rid(axi_if_rid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_rdata(axi_if_rdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_rresp(axi_if_rresp[n*2 +: 2]),
.s_axi_rlast(axi_if_rlast[n]),
.s_axi_rvalid(axi_if_rvalid[n]),
.s_axi_rready(axi_if_rready[n]),
.dma_ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_wr_cmd_be(if_dma_ram_wr_cmd_be[SEG_COUNT*SEG_BE_WIDTH*n +: SEG_COUNT*SEG_BE_WIDTH]),
.dma_ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_wr_cmd_data(if_dma_ram_wr_cmd_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_data(if_dma_ram_rd_resp_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_rd_resp_valid(if_dma_ram_rd_resp_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_ready(if_dma_ram_rd_resp_ready[SEG_COUNT*n +: SEG_COUNT]),
/*
* Transmit data output

25
fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -78,18 +78,6 @@ srcs.append("../lib/eth/rtl/ptp_clock.v")
srcs.append("../lib/eth/rtl/ptp_clock_cdc.v")
srcs.append("../lib/eth/rtl/ptp_perout.v")
srcs.append("../lib/eth/rtl/ptp_ts_extract.v")
srcs.append("../lib/axi/rtl/axi_crossbar.v")
srcs.append("../lib/axi/rtl/axi_crossbar_addr.v")
srcs.append("../lib/axi/rtl/axi_crossbar_rd.v")
srcs.append("../lib/axi/rtl/axi_crossbar_wr.v")
srcs.append("../lib/axi/rtl/axi_dma.v")
srcs.append("../lib/axi/rtl/axi_dma_rd.v")
srcs.append("../lib/axi/rtl/axi_dma_wr.v")
srcs.append("../lib/axi/rtl/axi_ram.v")
srcs.append("../lib/axi/rtl/axi_ram_rd_if.v")
srcs.append("../lib/axi/rtl/axi_ram_wr_if.v")
srcs.append("../lib/axi/rtl/axi_register_rd.v")
srcs.append("../lib/axi/rtl/axi_register_wr.v")
srcs.append("../lib/axi/rtl/axil_interconnect.v")
srcs.append("../lib/axi/rtl/arbiter.v")
srcs.append("../lib/axi/rtl/priority_encoder.v")
@ -99,11 +87,16 @@ srcs.append("../lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/axis/rtl/axis_register.v")
srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v")
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_rd.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_mux.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_wr.v")
srcs.append("../lib/pcie/rtl/dma_psdpram.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_sink.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_source.v")
srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")

25
fpga/mqnic/VCU118/fpga_10g/fpga/Makefile
View File

@ -45,18 +45,6 @@ SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
SYN_FILES += lib/axi/rtl/axi_crossbar.v
SYN_FILES += lib/axi/rtl/axi_crossbar_addr.v
SYN_FILES += lib/axi/rtl/axi_crossbar_rd.v
SYN_FILES += lib/axi/rtl/axi_crossbar_wr.v
SYN_FILES += lib/axi/rtl/axi_dma.v
SYN_FILES += lib/axi/rtl/axi_dma_rd.v
SYN_FILES += lib/axi/rtl/axi_dma_wr.v
SYN_FILES += lib/axi/rtl/axi_ram.v
SYN_FILES += lib/axi/rtl/axi_ram_rd_if.v
SYN_FILES += lib/axi/rtl/axi_ram_wr_if.v
SYN_FILES += lib/axi/rtl/axi_register_rd.v
SYN_FILES += lib/axi/rtl/axi_register_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/arbiter.v
SYN_FILES += lib/axi/rtl/priority_encoder.v
@ -67,13 +55,18 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
SYN_FILES += lib/pcie/rtl/pcie_axi_dma_desc_mux.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files

704
fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -260,15 +260,9 @@ parameter AXIL_DATA_WIDTH = 32;
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
parameter AXIL_ADDR_WIDTH = 24;
// AXI interface parameters
parameter AXI_ID_WIDTH = 8;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = 24;
// AXI stream interface parameters
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH;
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH;
parameter AXIS_DATA_WIDTH = 256;
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8;
// PCIe DMA parameters
parameter PCIE_DMA_LEN_WIDTH = 16;
@ -333,6 +327,20 @@ parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 32768;
parameter RX_FIFO_DEPTH = 32768;
parameter MAX_TX_SIZE = 2048;
parameter MAX_RX_SIZE = 2048;
// PCIe DMA parameters
parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2;
parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT;
parameter SEG_ADDR_WIDTH = 12;
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8;
parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+$clog2(PORTS_PER_IF+1);
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH);
parameter RAM_PIPELINE = 2;
parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE;
parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE;
// AXI lite connections
wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
@ -395,42 +403,20 @@ wire [1:0] axil_ber_rresp;
wire axil_ber_rvalid;
wire axil_ber_rready;
// AXI connections
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_awid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_awaddr;
wire [7:0] axi_pcie_dma_awlen;
wire [2:0] axi_pcie_dma_awsize;
wire [1:0] axi_pcie_dma_awburst;
wire axi_pcie_dma_awlock;
wire [3:0] axi_pcie_dma_awcache;
wire [2:0] axi_pcie_dma_awprot;
wire axi_pcie_dma_awvalid;
wire axi_pcie_dma_awready;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_wdata;
wire [AXI_STRB_WIDTH-1:0] axi_pcie_dma_wstrb;
wire axi_pcie_dma_wlast;
wire axi_pcie_dma_wvalid;
wire axi_pcie_dma_wready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_bid;
wire [1:0] axi_pcie_dma_bresp;
wire axi_pcie_dma_bvalid;
wire axi_pcie_dma_bready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_arid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_araddr;
wire [7:0] axi_pcie_dma_arlen;
wire [2:0] axi_pcie_dma_arsize;
wire [1:0] axi_pcie_dma_arburst;
wire axi_pcie_dma_arlock;
wire [3:0] axi_pcie_dma_arcache;
wire [2:0] axi_pcie_dma_arprot;
wire axi_pcie_dma_arvalid;
wire axi_pcie_dma_arready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_rid;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_rdata;
wire [1:0] axi_pcie_dma_rresp;
wire axi_pcie_dma_rlast;
wire axi_pcie_dma_rvalid;
wire axi_pcie_dma_rready;
// DMA connections
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready;
// Error handling
wire [1:0] status_error_uncor_int;
@ -441,25 +427,27 @@ wire [31:0] msi_irq;
wire ext_tag_enable;
// PCIe DMA control
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_tag;
wire pcie_axi_dma_read_desc_valid;
wire pcie_axi_dma_read_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_read_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_read_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_tag;
wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_status_tag;
wire pcie_axi_dma_read_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_tag;
wire pcie_axi_dma_write_desc_valid;
wire pcie_axi_dma_write_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_write_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_write_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_tag;
wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_status_tag;
wire pcie_axi_dma_write_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1;
@ -894,23 +882,25 @@ rc_reg (
.m_axis_tuser(axis_rc_tuser_r)
);
pcie_us_axi_dma #(
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(256),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_CLIENT_TAG(1),
.PCIE_TAG_COUNT(64),
.PCIE_EXT_TAG_ENABLE(1),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.TAG_WIDTH(PCIE_DMA_TAG_WIDTH)
)
pcie_us_axi_dma_inst (
dma_if_pcie_us_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
@ -934,82 +924,56 @@ pcie_us_axi_dma_inst (
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* Tag input
*/
.s_axis_pcie_rq_tag(0),
.s_axis_pcie_rq_tag_valid(0),
/*
* AXI read descriptor input
*/
.s_axis_read_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.s_axis_read_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.s_axis_read_desc_len(pcie_axi_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_axi_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_axi_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_pcie_addr(pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(pcie_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* AXI read descriptor status output
*/
.m_axis_read_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* AXI write descriptor input
*/
.s_axis_write_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.s_axis_write_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.s_axis_write_desc_len(pcie_axi_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_axi_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_axi_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_pcie_addr(pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(pcie_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* AXI write descriptor status output
*/
.m_axis_write_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* AXI Master output
* RAM interface
*/
.m_axi_awid(axi_pcie_dma_awid),
.m_axi_awaddr(axi_pcie_dma_awaddr),
.m_axi_awlen(axi_pcie_dma_awlen),
.m_axi_awsize(axi_pcie_dma_awsize),
.m_axi_awburst(axi_pcie_dma_awburst),
.m_axi_awlock(axi_pcie_dma_awlock),
.m_axi_awcache(axi_pcie_dma_awcache),
.m_axi_awprot(axi_pcie_dma_awprot),
.m_axi_awvalid(axi_pcie_dma_awvalid),
.m_axi_awready(axi_pcie_dma_awready),
.m_axi_wdata(axi_pcie_dma_wdata),
.m_axi_wstrb(axi_pcie_dma_wstrb),
.m_axi_wlast(axi_pcie_dma_wlast),
.m_axi_wvalid(axi_pcie_dma_wvalid),
.m_axi_wready(axi_pcie_dma_wready),
.m_axi_bid(axi_pcie_dma_bid),
.m_axi_bresp(axi_pcie_dma_bresp),
.m_axi_bvalid(axi_pcie_dma_bvalid),
.m_axi_bready(axi_pcie_dma_bready),
.m_axi_arid(axi_pcie_dma_arid),
.m_axi_araddr(axi_pcie_dma_araddr),
.m_axi_arlen(axi_pcie_dma_arlen),
.m_axi_arsize(axi_pcie_dma_arsize),
.m_axi_arburst(axi_pcie_dma_arburst),
.m_axi_arlock(axi_pcie_dma_arlock),
.m_axi_arcache(axi_pcie_dma_arcache),
.m_axi_arprot(axi_pcie_dma_arprot),
.m_axi_arvalid(axi_pcie_dma_arvalid),
.m_axi_arready(axi_pcie_dma_arready),
.m_axi_rid(axi_pcie_dma_rid),
.m_axi_rdata(axi_pcie_dma_rdata),
.m_axi_rresp(axi_pcie_dma_rresp),
.m_axi_rlast(axi_pcie_dma_rlast),
.m_axi_rvalid(axi_pcie_dma_rvalid),
.m_axi_rready(axi_pcie_dma_rready),
.ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.ram_rd_resp_data(dma_ram_rd_resp_data),
.ram_rd_resp_valid(dma_ram_rd_resp_valid),
.ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* Configuration
@ -1097,22 +1061,6 @@ function [IF_AXIL_BASE_ADDR_WIDTH-1:0] calcIFAxiLiteBaseAddrs(input [31:0] if_ad
end
endfunction
parameter IF_AXI_ADDR_WIDTH = 32'd23;
parameter IF_AXI_BASE_ADDR_WIDTH = IF_COUNT*AXI_ADDR_WIDTH;
parameter IF_AXI_BASE_ADDR = calcIFAxiBaseAddrs(IF_AXI_ADDR_WIDTH);
function [IF_AXI_BASE_ADDR_WIDTH-1:0] calcIFAxiBaseAddrs(input [31:0] if_addr_width);
integer i;
begin
calcIFAxiBaseAddrs = {IF_AXI_BASE_ADDR_WIDTH{1'b0}};
for (i = 0; i < IF_COUNT; i = i + 1) begin
calcIFAxiBaseAddrs[i * AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = i * (2**if_addr_width);
end
end
endfunction
parameter IF_AXI_ID_WIDTH = AXI_ID_WIDTH+$clog2(2);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;
@ -1153,42 +1101,6 @@ wire [IF_COUNT*2-1:0] axil_if_csr_rresp;
wire [IF_COUNT-1:0] axil_if_csr_rvalid;
wire [IF_COUNT-1:0] axil_if_csr_rready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_awid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_awaddr;
wire [IF_COUNT*8-1:0] axi_if_awlen;
wire [IF_COUNT*3-1:0] axi_if_awsize;
wire [IF_COUNT*2-1:0] axi_if_awburst;
wire [IF_COUNT-1:0] axi_if_awlock;
wire [IF_COUNT*4-1:0] axi_if_awcache;
wire [IF_COUNT*3-1:0] axi_if_awprot;
wire [IF_COUNT-1:0] axi_if_awvalid;
wire [IF_COUNT-1:0] axi_if_awready;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_wdata;
wire [IF_COUNT*AXI_STRB_WIDTH-1:0] axi_if_wstrb;
wire [IF_COUNT-1:0] axi_if_wlast;
wire [IF_COUNT-1:0] axi_if_wvalid;
wire [IF_COUNT-1:0] axi_if_wready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_bid;
wire [IF_COUNT*2-1:0] axi_if_bresp;
wire [IF_COUNT-1:0] axi_if_bvalid;
wire [IF_COUNT-1:0] axi_if_bready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_arid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_araddr;
wire [IF_COUNT*8-1:0] axi_if_arlen;
wire [IF_COUNT*3-1:0] axi_if_arsize;
wire [IF_COUNT*2-1:0] axi_if_arburst;
wire [IF_COUNT-1:0] axi_if_arlock;
wire [IF_COUNT*4-1:0] axi_if_arcache;
wire [IF_COUNT*3-1:0] axi_if_arprot;
wire [IF_COUNT-1:0] axi_if_arvalid;
wire [IF_COUNT-1:0] axi_if_arready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_rid;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_rdata;
wire [IF_COUNT*2-1:0] axi_if_rresp;
wire [IF_COUNT-1:0] axi_if_rlast;
wire [IF_COUNT-1:0] axi_if_rvalid;
wire [IF_COUNT-1:0] axi_if_rready;
axil_interconnect #(
.DATA_WIDTH(AXIL_DATA_WIDTH),
.ADDR_WIDTH(AXIL_ADDR_WIDTH),
@ -1299,238 +1211,167 @@ axil_csr_interconnect_inst (
.m_axil_rready( {axil_ber_rready, axil_csr_rready})
);
axi_crossbar #(
.S_COUNT(1),
.M_COUNT(IF_COUNT),
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH),
.STRB_WIDTH(AXI_STRB_WIDTH),
.S_ID_WIDTH(AXI_ID_WIDTH),
.M_ID_WIDTH(IF_AXI_ID_WIDTH),
.AWUSER_ENABLE(0),
.WUSER_ENABLE(0),
.BUSER_ENABLE(0),
.ARUSER_ENABLE(0),
.RUSER_ENABLE(0),
.S_THREADS({2{32'd4}}),
.S_ACCEPT({2{32'd16}}),
.M_REGIONS(1),
.M_BASE_ADDR(IF_AXI_BASE_ADDR),
.M_ADDR_WIDTH({IF_COUNT{w_32(IF_AXI_ADDR_WIDTH)}}),
.M_CONNECT_READ({IF_COUNT{{2{1'b1}}}}),
.M_CONNECT_WRITE({IF_COUNT{{2{1'b1}}}}),
.M_ISSUE({IF_COUNT{32'd4}}),
.M_SECURE({IF_COUNT{1'b0}})
)
axi_crossbar_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.s_axi_awid( {axi_pcie_dma_awid}),
.s_axi_awaddr( {axi_pcie_dma_awaddr}),
.s_axi_awlen( {axi_pcie_dma_awlen}),
.s_axi_awsize( {axi_pcie_dma_awsize}),
.s_axi_awburst( {axi_pcie_dma_awburst}),
.s_axi_awlock( {axi_pcie_dma_awlock}),
.s_axi_awcache( {axi_pcie_dma_awcache}),
.s_axi_awprot( {axi_pcie_dma_awprot}),
.s_axi_awqos(0),
.s_axi_awuser(0),
.s_axi_awvalid( {axi_pcie_dma_awvalid}),
.s_axi_awready( {axi_pcie_dma_awready}),
.s_axi_wdata( {axi_pcie_dma_wdata}),
.s_axi_wstrb( {axi_pcie_dma_wstrb}),
.s_axi_wlast( {axi_pcie_dma_wlast}),
.s_axi_wuser(0),
.s_axi_wvalid( {axi_pcie_dma_wvalid}),
.s_axi_wready( {axi_pcie_dma_wready}),
.s_axi_bid( {axi_pcie_dma_bid}),
.s_axi_bresp( {axi_pcie_dma_bresp}),
.s_axi_buser(),
.s_axi_bvalid( {axi_pcie_dma_bvalid}),
.s_axi_bready( {axi_pcie_dma_bready}),
.s_axi_arid( {axi_pcie_dma_arid}),
.s_axi_araddr( {axi_pcie_dma_araddr}),
.s_axi_arlen( {axi_pcie_dma_arlen}),
.s_axi_arsize( {axi_pcie_dma_arsize}),
.s_axi_arburst( {axi_pcie_dma_arburst}),
.s_axi_arlock( {axi_pcie_dma_arlock}),
.s_axi_arcache( {axi_pcie_dma_arcache}),
.s_axi_arprot( {axi_pcie_dma_arprot}),
.s_axi_arqos(0),
.s_axi_aruser(0),
.s_axi_arvalid( {axi_pcie_dma_arvalid}),
.s_axi_arready( {axi_pcie_dma_arready}),
.s_axi_rid( {axi_pcie_dma_rid}),
.s_axi_rdata( {axi_pcie_dma_rdata}),
.s_axi_rresp( {axi_pcie_dma_rresp}),
.s_axi_rlast( {axi_pcie_dma_rlast}),
.s_axi_ruser(),
.s_axi_rvalid( {axi_pcie_dma_rvalid}),
.s_axi_rready( {axi_pcie_dma_rready}),
.m_axi_awid( {axi_if_awid}),
.m_axi_awaddr( {axi_if_awaddr}),
.m_axi_awlen( {axi_if_awlen}),
.m_axi_awsize( {axi_if_awsize}),
.m_axi_awburst( {axi_if_awburst}),
.m_axi_awlock( {axi_if_awlock}),
.m_axi_awcache( {axi_if_awcache}),
.m_axi_awprot( {axi_if_awprot}),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid( {axi_if_awvalid}),
.m_axi_awready( {axi_if_awready}),
.m_axi_wdata( {axi_if_wdata}),
.m_axi_wstrb( {axi_if_wstrb}),
.m_axi_wlast( {axi_if_wlast}),
.m_axi_wuser(),
.m_axi_wvalid( {axi_if_wvalid}),
.m_axi_wready( {axi_if_wready}),
.m_axi_bid( {axi_if_bid}),
.m_axi_bresp( {axi_if_bresp}),
.m_axi_buser(0),
.m_axi_bvalid( {axi_if_bvalid}),
.m_axi_bready( {axi_if_bready}),
.m_axi_arid( {axi_if_arid}),
.m_axi_araddr( {axi_if_araddr}),
.m_axi_arlen( {axi_if_arlen}),
.m_axi_arsize( {axi_if_arsize}),
.m_axi_arburst( {axi_if_arburst}),
.m_axi_arlock( {axi_if_arlock}),
.m_axi_arcache( {axi_if_arcache}),
.m_axi_arprot( {axi_if_arprot}),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid( {axi_if_arvalid}),
.m_axi_arready( {axi_if_arready}),
.m_axi_rid( {axi_if_rid}),
.m_axi_rdata( {axi_if_rdata}),
.m_axi_rresp( {axi_if_rresp}),
.m_axi_rlast( {axi_if_rlast}),
.m_axi_ruser(0),
.m_axi_rvalid( {axi_if_rvalid}),
.m_axi_rready( {axi_if_rready})
);
parameter IF_RAM_SEL_WIDTH = $clog2(PORTS_PER_IF+1);
parameter IF_PCIE_DMA_TAG_WIDTH = PCIE_DMA_TAG_WIDTH-$clog2(IF_COUNT);
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_pcie_addr;
wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_read_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_pcie_addr;
wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_write_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_status_valid;
pcie_axi_dma_desc_mux #
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_wr_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_BE_WIDTH-1:0] if_dma_ram_wr_cmd_be;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_wr_cmd_addr;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_wr_cmd_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_ready;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_rd_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_rd_cmd_addr;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_ready;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_rd_resp_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_ready;
dma_if_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.S_RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.M_RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_read_desc_mux_inst (
dma_if_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* Descriptor output
* Read descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_read_desc_len),
.m_axis_desc_tag(pcie_axi_dma_read_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_read_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_read_desc_ready),
.m_axis_read_desc_dma_addr(pcie_dma_read_desc_pcie_addr),
.m_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.m_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.m_axis_read_desc_len(pcie_dma_read_desc_len),
.m_axis_read_desc_tag(pcie_dma_read_desc_tag),
.m_axis_read_desc_valid(pcie_dma_read_desc_valid),
.m_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* Descriptor status input
* Read descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* Descriptor input
* Read descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_read_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_read_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_read_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(if_pcie_dma_read_desc_len),
.s_axis_read_desc_tag(if_pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(if_pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(if_pcie_dma_read_desc_ready),
/*
* Descriptor status output
* Read descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid)
);
pcie_axi_dma_desc_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_write_desc_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.m_axis_read_desc_status_tag(if_pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(if_pcie_dma_read_desc_status_valid),
/*
* Descriptor output
* Write descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_write_desc_len),
.m_axis_desc_tag(pcie_axi_dma_write_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_write_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_write_desc_ready),
.m_axis_write_desc_dma_addr(pcie_dma_write_desc_pcie_addr),
.m_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.m_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.m_axis_write_desc_len(pcie_dma_write_desc_len),
.m_axis_write_desc_tag(pcie_dma_write_desc_tag),
.m_axis_write_desc_valid(pcie_dma_write_desc_valid),
.m_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* Descriptor status input
* Write descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* Descriptor input
* Write descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_write_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_write_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_write_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(if_pcie_dma_write_desc_len),
.s_axis_write_desc_tag(if_pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(if_pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(if_pcie_dma_write_desc_ready),
/*
* Descriptor status output
* Write descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid)
.m_axis_write_desc_status_tag(if_pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(if_pcie_dma_write_desc_status_valid),
/*
* RAM interface (from DMA interface)
*/
.if_ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.if_ram_wr_cmd_be(dma_ram_wr_cmd_be),
.if_ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.if_ram_wr_cmd_data(dma_ram_wr_cmd_data),
.if_ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.if_ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.if_ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.if_ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.if_ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.if_ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.if_ram_rd_resp_data(dma_ram_rd_resp_data),
.if_ram_rd_resp_valid(dma_ram_rd_resp_valid),
.if_ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* RAM interface
*/
.ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(if_dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(if_dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready),
.ram_rd_resp_data(if_dma_ram_rd_resp_data),
.ram_rd_resp_valid(if_dma_ram_rd_resp_valid),
.ram_rd_resp_ready(if_dma_ram_rd_resp_ready)
);
// PTP clock
@ -1868,11 +1709,6 @@ generate
for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr_int;
assign if_pcie_axi_dma_read_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_read_desc_axi_addr_int | n*24'h800000;
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int;
assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
@ -1897,9 +1733,9 @@ generate
interface #(
.PORTS(PORTS_PER_IF),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1919,8 +1755,6 @@ generate
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),
.QUEUE_LOG_SIZE_WIDTH(4),
.RAM_ADDR_WIDTH(16),
.RAM_SIZE(2**15),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
@ -1928,49 +1762,57 @@ generate
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(IF_AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(IF_AXI_ID_WIDTH),
.AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE)
)
interface_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* PCIe DMA read descriptor output
* DMA read descriptor output
*/
.m_axis_pcie_axi_dma_read_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr_int),
.m_axis_pcie_axi_dma_read_desc_len(if_pcie_axi_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_tag(if_pcie_axi_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_valid(if_pcie_axi_dma_read_desc_valid[n]),
.m_axis_pcie_axi_dma_read_desc_ready(if_pcie_axi_dma_read_desc_ready[n]),
.m_axis_dma_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_read_desc_len(if_pcie_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_read_desc_tag(if_pcie_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_read_desc_valid(if_pcie_dma_read_desc_valid[n]),
.m_axis_dma_read_desc_ready(if_pcie_dma_read_desc_ready[n]),
/*
* PCIe DMA read descriptor status input
* DMA read descriptor status input
*/
.s_axis_pcie_axi_dma_read_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_read_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid[n]),
.s_axis_dma_read_desc_status_tag(if_pcie_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_read_desc_status_valid(if_pcie_dma_read_desc_status_valid[n]),
/*
* PCIe DMA write descriptor output
* DMA write descriptor output
*/
.m_axis_pcie_axi_dma_write_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr_int),
.m_axis_pcie_axi_dma_write_desc_len(if_pcie_axi_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_tag(if_pcie_axi_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_valid(if_pcie_axi_dma_write_desc_valid[n]),
.m_axis_pcie_axi_dma_write_desc_ready(if_pcie_axi_dma_write_desc_ready[n]),
.m_axis_dma_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_write_desc_len(if_pcie_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_write_desc_tag(if_pcie_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_write_desc_valid(if_pcie_dma_write_desc_valid[n]),
.m_axis_dma_write_desc_ready(if_pcie_dma_write_desc_ready[n]),
/*
* PCIe DMA write descriptor status input
* DMA write descriptor status input
*/
.s_axis_pcie_axi_dma_write_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_write_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid[n]),
.s_axis_dma_write_desc_status_tag(if_pcie_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_write_desc_status_valid(if_pcie_dma_write_desc_status_valid[n]),
/*
* AXI-Lite slave interface
@ -2019,43 +1861,21 @@ generate
.m_axil_csr_rready(axil_if_csr_rready[n]),
/*
* AXI slave inteface
* RAM interface
*/
.s_axi_awid(axi_if_awid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_awaddr(axi_if_awaddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_awlen(axi_if_awlen[n*8 +: 8]),
.s_axi_awsize(axi_if_awsize[n*3 +: 3]),
.s_axi_awburst(axi_if_awburst[n*2 +: 2]),
.s_axi_awlock(axi_if_awlock[n]),
.s_axi_awcache(axi_if_awcache[n*4 +: 4]),
.s_axi_awprot(axi_if_awprot[n*3 +: 3]),
.s_axi_awvalid(axi_if_awvalid[n]),
.s_axi_awready(axi_if_awready[n]),
.s_axi_wdata(axi_if_wdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_wstrb(axi_if_wstrb[n*AXI_STRB_WIDTH +: AXI_STRB_WIDTH]),
.s_axi_wlast(axi_if_wlast[n]),
.s_axi_wvalid(axi_if_wvalid[n]),
.s_axi_wready(axi_if_wready[n]),
.s_axi_bid(axi_if_bid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_bresp(axi_if_bresp[n*2 +: 2]),
.s_axi_bvalid(axi_if_bvalid[n]),
.s_axi_bready(axi_if_bready[n]),
.s_axi_arid(axi_if_arid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_araddr(axi_if_araddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_arlen(axi_if_arlen[n*8 +: 8]),
.s_axi_arsize(axi_if_arsize[n*3 +: 3]),
.s_axi_arburst(axi_if_arburst[n*2 +: 2]),
.s_axi_arlock(axi_if_arlock[n]),
.s_axi_arcache(axi_if_arcache[n*4 +: 4]),
.s_axi_arprot(axi_if_arprot[n*3 +: 3]),
.s_axi_arvalid(axi_if_arvalid[n]),
.s_axi_arready(axi_if_arready[n]),
.s_axi_rid(axi_if_rid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_rdata(axi_if_rdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_rresp(axi_if_rresp[n*2 +: 2]),
.s_axi_rlast(axi_if_rlast[n]),
.s_axi_rvalid(axi_if_rvalid[n]),
.s_axi_rready(axi_if_rready[n]),
.dma_ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_wr_cmd_be(if_dma_ram_wr_cmd_be[SEG_COUNT*SEG_BE_WIDTH*n +: SEG_COUNT*SEG_BE_WIDTH]),
.dma_ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_wr_cmd_data(if_dma_ram_wr_cmd_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_data(if_dma_ram_rd_resp_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_rd_resp_valid(if_dma_ram_rd_resp_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_ready(if_dma_ram_rd_resp_ready[SEG_COUNT*n +: SEG_COUNT]),
/*
* Transmit data output

25
fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py
View File

@ -78,18 +78,6 @@ srcs.append("../lib/eth/rtl/ptp_clock.v")
srcs.append("../lib/eth/rtl/ptp_clock_cdc.v")
srcs.append("../lib/eth/rtl/ptp_perout.v")
srcs.append("../lib/eth/rtl/ptp_ts_extract.v")
srcs.append("../lib/axi/rtl/axi_crossbar.v")
srcs.append("../lib/axi/rtl/axi_crossbar_addr.v")
srcs.append("../lib/axi/rtl/axi_crossbar_rd.v")
srcs.append("../lib/axi/rtl/axi_crossbar_wr.v")
srcs.append("../lib/axi/rtl/axi_dma.v")
srcs.append("../lib/axi/rtl/axi_dma_rd.v")
srcs.append("../lib/axi/rtl/axi_dma_wr.v")
srcs.append("../lib/axi/rtl/axi_ram.v")
srcs.append("../lib/axi/rtl/axi_ram_rd_if.v")
srcs.append("../lib/axi/rtl/axi_ram_wr_if.v")
srcs.append("../lib/axi/rtl/axi_register_rd.v")
srcs.append("../lib/axi/rtl/axi_register_wr.v")
srcs.append("../lib/axi/rtl/axil_interconnect.v")
srcs.append("../lib/axi/rtl/arbiter.v")
srcs.append("../lib/axi/rtl/priority_encoder.v")
@ -99,11 +87,16 @@ srcs.append("../lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/axis/rtl/axis_register.v")
srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v")
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_rd.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_mux.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_wr.v")
srcs.append("../lib/pcie/rtl/dma_psdpram.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_sink.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_source.v")
srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")

25
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
View File

@ -45,18 +45,6 @@ SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
SYN_FILES += lib/axi/rtl/axi_crossbar.v
SYN_FILES += lib/axi/rtl/axi_crossbar_addr.v
SYN_FILES += lib/axi/rtl/axi_crossbar_rd.v
SYN_FILES += lib/axi/rtl/axi_crossbar_wr.v
SYN_FILES += lib/axi/rtl/axi_dma.v
SYN_FILES += lib/axi/rtl/axi_dma_rd.v
SYN_FILES += lib/axi/rtl/axi_dma_wr.v
SYN_FILES += lib/axi/rtl/axi_ram.v
SYN_FILES += lib/axi/rtl/axi_ram_rd_if.v
SYN_FILES += lib/axi/rtl/axi_ram_wr_if.v
SYN_FILES += lib/axi/rtl/axi_register_rd.v
SYN_FILES += lib/axi/rtl/axi_register_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/arbiter.v
SYN_FILES += lib/axi/rtl/priority_encoder.v
@ -67,13 +55,18 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
SYN_FILES += lib/pcie/rtl/pcie_axi_dma_desc_mux.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files

736
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -257,15 +257,9 @@ parameter AXIL_DATA_WIDTH = 32;
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
parameter AXIL_ADDR_WIDTH = 24;
// AXI interface parameters
parameter AXI_ID_WIDTH = 8;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = 24;
// AXI stream interface parameters
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH;
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH;
parameter AXIS_DATA_WIDTH = 256;
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8;
// PCIe DMA parameters
parameter PCIE_DMA_LEN_WIDTH = 16;
@ -330,6 +324,20 @@ parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 32768;
parameter RX_FIFO_DEPTH = 32768;
parameter MAX_TX_SIZE = 2048;
parameter MAX_RX_SIZE = 2048;
// PCIe DMA parameters
parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2;
parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT;
parameter SEG_ADDR_WIDTH = 12;
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8;
parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+$clog2(PORTS_PER_IF+1);
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH);
parameter RAM_PIPELINE = 2;
parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE;
parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE;
// AXI lite connections
wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
@ -392,42 +400,20 @@ wire [1:0] axil_ber_rresp;
wire axil_ber_rvalid;
wire axil_ber_rready;
// AXI connections
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_awid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_awaddr;
wire [7:0] axi_pcie_dma_awlen;
wire [2:0] axi_pcie_dma_awsize;
wire [1:0] axi_pcie_dma_awburst;
wire axi_pcie_dma_awlock;
wire [3:0] axi_pcie_dma_awcache;
wire [2:0] axi_pcie_dma_awprot;
wire axi_pcie_dma_awvalid;
wire axi_pcie_dma_awready;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_wdata;
wire [AXI_STRB_WIDTH-1:0] axi_pcie_dma_wstrb;
wire axi_pcie_dma_wlast;
wire axi_pcie_dma_wvalid;
wire axi_pcie_dma_wready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_bid;
wire [1:0] axi_pcie_dma_bresp;
wire axi_pcie_dma_bvalid;
wire axi_pcie_dma_bready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_arid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_araddr;
wire [7:0] axi_pcie_dma_arlen;
wire [2:0] axi_pcie_dma_arsize;
wire [1:0] axi_pcie_dma_arburst;
wire axi_pcie_dma_arlock;
wire [3:0] axi_pcie_dma_arcache;
wire [2:0] axi_pcie_dma_arprot;
wire axi_pcie_dma_arvalid;
wire axi_pcie_dma_arready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_rid;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_rdata;
wire [1:0] axi_pcie_dma_rresp;
wire axi_pcie_dma_rlast;
wire axi_pcie_dma_rvalid;
wire axi_pcie_dma_rready;
// DMA connections
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready;
// Error handling
wire [1:0] status_error_uncor_int;
@ -438,25 +424,27 @@ wire [31:0] msi_irq;
wire ext_tag_enable;
// PCIe DMA control
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_tag;
wire pcie_axi_dma_read_desc_valid;
wire pcie_axi_dma_read_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_read_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_read_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_tag;
wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_status_tag;
wire pcie_axi_dma_read_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_tag;
wire pcie_axi_dma_write_desc_valid;
wire pcie_axi_dma_write_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_write_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_write_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_tag;
wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_status_tag;
wire pcie_axi_dma_write_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1;
@ -836,11 +824,11 @@ rc_reg (
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({pcie_axi_dma_read_desc_pcie_addr, pcie_axi_dma_read_desc_axi_addr, pcie_axi_dma_read_desc_tag, pcie_axi_dma_read_desc_status_tag, pcie_axi_dma_write_desc_pcie_addr, pcie_axi_dma_write_desc_axi_addr, pcie_axi_dma_write_desc_tag, pcie_axi_dma_write_desc_status_tag}),
// .probe0({pcie_dma_read_desc_pcie_addr, pcie_dma_read_desc_ram_sel, pcie_dma_read_desc_ram_addr, pcie_dma_read_desc_tag, pcie_dma_read_desc_status_tag, pcie_dma_write_desc_pcie_addr, pcie_dma_write_desc_ram_sel, pcie_dma_write_desc_ram_addr, pcie_dma_write_desc_tag, pcie_dma_write_desc_status_tag}),
// .probe1(0),
// .probe2(0),
// .probe3(0),
// .probe4({pcie_axi_dma_read_desc_valid, pcie_axi_dma_read_desc_ready, pcie_axi_dma_read_desc_len, pcie_axi_dma_read_desc_status_valid, pcie_axi_dma_write_desc_valid, pcie_axi_dma_write_desc_ready, pcie_axi_dma_write_desc_len, pcie_axi_dma_write_desc_status_valid, dbg, status_error_cor_int, status_error_uncor_int}),
// .probe4({pcie_dma_read_desc_valid, pcie_dma_read_desc_ready, pcie_dma_read_desc_len, pcie_dma_read_desc_status_valid, pcie_dma_write_desc_valid, pcie_dma_write_desc_ready, pcie_dma_write_desc_len, pcie_dma_write_desc_status_valid, status_error_cor_int, status_error_uncor_int}),
// .probe5(0)
// );
@ -854,7 +842,7 @@ rc_reg (
// .probe1(m_axis_rq_tkeep),
// .probe2(m_axis_rq_tvalid),
// .probe3(m_axis_rq_tready),
// .probe4({m_axis_rq_tuser, dbg}),
// .probe4(m_axis_rq_tuser),
// .probe5(m_axis_rq_tlast)
// );
@ -864,12 +852,26 @@ rc_reg (
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(s_axis_rc_tdata),
// .probe1(s_axis_rc_tkeep),
// .probe2(s_axis_rc_tvalid),
// .probe3(s_axis_rc_tready),
// .probe4({s_axis_rc_tuser, dbg}),
// .probe5(s_axis_rc_tlast)
// .probe0(axis_rc_tdata_r),
// .probe1(axis_rc_tkeep_r),
// .probe2(axis_rc_tvalid_r),
// .probe3(axis_rc_tready_r),
// .probe4({axis_rc_tuser_r, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.req_state_reg, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.tlp_state_reg, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.ram_mask_reg}),
// .probe5(axis_rc_tlast_r)
// );
// ila_0 ila_mem (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({dma_ram_wr_cmd_valid, dma_ram_wr_cmd_ready, dma_ram_wr_cmd_sel, if_dma_ram_wr_cmd_valid, if_dma_ram_wr_cmd_ready, if_dma_ram_wr_cmd_sel, iface[0].interface_inst.desc_dma_ram_wr_cmd_valid, iface[0].interface_inst.desc_dma_ram_wr_cmd_ready, iface[0].interface_inst.port_dma_ram_wr_cmd_valid, iface[0].interface_inst.port_dma_ram_wr_cmd_ready}),
// .probe1(0),
// .probe2(0),
// .probe3(0),
// .probe4(0),
// .probe5(0)
// );
// ila_0 ila_w (
@ -886,23 +888,25 @@ rc_reg (
// .probe5(axi_pcie_dma_wlast)
// );
pcie_us_axi_dma #(
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(256),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_CLIENT_TAG(1),
.PCIE_TAG_COUNT(64),
.PCIE_EXT_TAG_ENABLE(1),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.TAG_WIDTH(PCIE_DMA_TAG_WIDTH)
)
pcie_us_axi_dma_inst (
dma_if_pcie_us_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
@ -926,82 +930,56 @@ pcie_us_axi_dma_inst (
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* Tag input
*/
.s_axis_pcie_rq_tag(0),
.s_axis_pcie_rq_tag_valid(0),
/*
* AXI read descriptor input
*/
.s_axis_read_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.s_axis_read_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.s_axis_read_desc_len(pcie_axi_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_axi_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_axi_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_pcie_addr(pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(pcie_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* AXI read descriptor status output
*/
.m_axis_read_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* AXI write descriptor input
*/
.s_axis_write_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.s_axis_write_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.s_axis_write_desc_len(pcie_axi_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_axi_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_axi_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_pcie_addr(pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(pcie_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* AXI write descriptor status output
*/
.m_axis_write_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* AXI Master output
* RAM interface
*/
.m_axi_awid(axi_pcie_dma_awid),
.m_axi_awaddr(axi_pcie_dma_awaddr),
.m_axi_awlen(axi_pcie_dma_awlen),
.m_axi_awsize(axi_pcie_dma_awsize),
.m_axi_awburst(axi_pcie_dma_awburst),
.m_axi_awlock(axi_pcie_dma_awlock),
.m_axi_awcache(axi_pcie_dma_awcache),
.m_axi_awprot(axi_pcie_dma_awprot),
.m_axi_awvalid(axi_pcie_dma_awvalid),
.m_axi_awready(axi_pcie_dma_awready),
.m_axi_wdata(axi_pcie_dma_wdata),
.m_axi_wstrb(axi_pcie_dma_wstrb),
.m_axi_wlast(axi_pcie_dma_wlast),
.m_axi_wvalid(axi_pcie_dma_wvalid),
.m_axi_wready(axi_pcie_dma_wready),
.m_axi_bid(axi_pcie_dma_bid),
.m_axi_bresp(axi_pcie_dma_bresp),
.m_axi_bvalid(axi_pcie_dma_bvalid),
.m_axi_bready(axi_pcie_dma_bready),
.m_axi_arid(axi_pcie_dma_arid),
.m_axi_araddr(axi_pcie_dma_araddr),
.m_axi_arlen(axi_pcie_dma_arlen),
.m_axi_arsize(axi_pcie_dma_arsize),
.m_axi_arburst(axi_pcie_dma_arburst),
.m_axi_arlock(axi_pcie_dma_arlock),
.m_axi_arcache(axi_pcie_dma_arcache),
.m_axi_arprot(axi_pcie_dma_arprot),
.m_axi_arvalid(axi_pcie_dma_arvalid),
.m_axi_arready(axi_pcie_dma_arready),
.m_axi_rid(axi_pcie_dma_rid),
.m_axi_rdata(axi_pcie_dma_rdata),
.m_axi_rresp(axi_pcie_dma_rresp),
.m_axi_rlast(axi_pcie_dma_rlast),
.m_axi_rvalid(axi_pcie_dma_rvalid),
.m_axi_rready(axi_pcie_dma_rready),
.ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.ram_rd_resp_data(dma_ram_rd_resp_data),
.ram_rd_resp_valid(dma_ram_rd_resp_valid),
.ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* Configuration
@ -1089,22 +1067,6 @@ function [IF_AXIL_BASE_ADDR_WIDTH-1:0] calcIFAxiLiteBaseAddrs(input [31:0] if_ad
end
endfunction
parameter IF_AXI_ADDR_WIDTH = 32'd23;
parameter IF_AXI_BASE_ADDR_WIDTH = IF_COUNT*AXI_ADDR_WIDTH;
parameter IF_AXI_BASE_ADDR = calcIFAxiBaseAddrs(IF_AXI_ADDR_WIDTH);
function [IF_AXI_BASE_ADDR_WIDTH-1:0] calcIFAxiBaseAddrs(input [31:0] if_addr_width);
integer i;
begin
calcIFAxiBaseAddrs = {IF_AXI_BASE_ADDR_WIDTH{1'b0}};
for (i = 0; i < IF_COUNT; i = i + 1) begin
calcIFAxiBaseAddrs[i * AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = i * (2**if_addr_width);
end
end
endfunction
parameter IF_AXI_ID_WIDTH = AXI_ID_WIDTH+$clog2(2);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;
@ -1145,42 +1107,6 @@ wire [IF_COUNT*2-1:0] axil_if_csr_rresp;
wire [IF_COUNT-1:0] axil_if_csr_rvalid;
wire [IF_COUNT-1:0] axil_if_csr_rready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_awid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_awaddr;
wire [IF_COUNT*8-1:0] axi_if_awlen;
wire [IF_COUNT*3-1:0] axi_if_awsize;
wire [IF_COUNT*2-1:0] axi_if_awburst;
wire [IF_COUNT-1:0] axi_if_awlock;
wire [IF_COUNT*4-1:0] axi_if_awcache;
wire [IF_COUNT*3-1:0] axi_if_awprot;
wire [IF_COUNT-1:0] axi_if_awvalid;
wire [IF_COUNT-1:0] axi_if_awready;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_wdata;
wire [IF_COUNT*AXI_STRB_WIDTH-1:0] axi_if_wstrb;
wire [IF_COUNT-1:0] axi_if_wlast;
wire [IF_COUNT-1:0] axi_if_wvalid;
wire [IF_COUNT-1:0] axi_if_wready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_bid;
wire [IF_COUNT*2-1:0] axi_if_bresp;
wire [IF_COUNT-1:0] axi_if_bvalid;
wire [IF_COUNT-1:0] axi_if_bready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_arid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_araddr;
wire [IF_COUNT*8-1:0] axi_if_arlen;
wire [IF_COUNT*3-1:0] axi_if_arsize;
wire [IF_COUNT*2-1:0] axi_if_arburst;
wire [IF_COUNT-1:0] axi_if_arlock;
wire [IF_COUNT*4-1:0] axi_if_arcache;
wire [IF_COUNT*3-1:0] axi_if_arprot;
wire [IF_COUNT-1:0] axi_if_arvalid;
wire [IF_COUNT-1:0] axi_if_arready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_rid;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_rdata;
wire [IF_COUNT*2-1:0] axi_if_rresp;
wire [IF_COUNT-1:0] axi_if_rlast;
wire [IF_COUNT-1:0] axi_if_rvalid;
wire [IF_COUNT-1:0] axi_if_rready;
axil_interconnect #(
.DATA_WIDTH(AXIL_DATA_WIDTH),
.ADDR_WIDTH(AXIL_ADDR_WIDTH),
@ -1291,238 +1217,167 @@ axil_csr_interconnect_inst (
.m_axil_rready( {axil_ber_rready, axil_csr_rready})
);
axi_crossbar #(
.S_COUNT(1),
.M_COUNT(IF_COUNT),
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH),
.STRB_WIDTH(AXI_STRB_WIDTH),
.S_ID_WIDTH(AXI_ID_WIDTH),
.M_ID_WIDTH(IF_AXI_ID_WIDTH),
.AWUSER_ENABLE(0),
.WUSER_ENABLE(0),
.BUSER_ENABLE(0),
.ARUSER_ENABLE(0),
.RUSER_ENABLE(0),
.S_THREADS({2{32'd4}}),
.S_ACCEPT({2{32'd16}}),
.M_REGIONS(1),
.M_BASE_ADDR(IF_AXI_BASE_ADDR),
.M_ADDR_WIDTH({IF_COUNT{w_32(IF_AXI_ADDR_WIDTH)}}),
.M_CONNECT_READ({IF_COUNT{{2{1'b1}}}}),
.M_CONNECT_WRITE({IF_COUNT{{2{1'b1}}}}),
.M_ISSUE({IF_COUNT{32'd4}}),
.M_SECURE({IF_COUNT{1'b0}})
)
axi_crossbar_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.s_axi_awid( {axi_pcie_dma_awid}),
.s_axi_awaddr( {axi_pcie_dma_awaddr}),
.s_axi_awlen( {axi_pcie_dma_awlen}),
.s_axi_awsize( {axi_pcie_dma_awsize}),
.s_axi_awburst( {axi_pcie_dma_awburst}),
.s_axi_awlock( {axi_pcie_dma_awlock}),
.s_axi_awcache( {axi_pcie_dma_awcache}),
.s_axi_awprot( {axi_pcie_dma_awprot}),
.s_axi_awqos(0),
.s_axi_awuser(0),
.s_axi_awvalid( {axi_pcie_dma_awvalid}),
.s_axi_awready( {axi_pcie_dma_awready}),
.s_axi_wdata( {axi_pcie_dma_wdata}),
.s_axi_wstrb( {axi_pcie_dma_wstrb}),
.s_axi_wlast( {axi_pcie_dma_wlast}),
.s_axi_wuser(0),
.s_axi_wvalid( {axi_pcie_dma_wvalid}),
.s_axi_wready( {axi_pcie_dma_wready}),
.s_axi_bid( {axi_pcie_dma_bid}),
.s_axi_bresp( {axi_pcie_dma_bresp}),
.s_axi_buser(),
.s_axi_bvalid( {axi_pcie_dma_bvalid}),
.s_axi_bready( {axi_pcie_dma_bready}),
.s_axi_arid( {axi_pcie_dma_arid}),
.s_axi_araddr( {axi_pcie_dma_araddr}),
.s_axi_arlen( {axi_pcie_dma_arlen}),
.s_axi_arsize( {axi_pcie_dma_arsize}),
.s_axi_arburst( {axi_pcie_dma_arburst}),
.s_axi_arlock( {axi_pcie_dma_arlock}),
.s_axi_arcache( {axi_pcie_dma_arcache}),
.s_axi_arprot( {axi_pcie_dma_arprot}),
.s_axi_arqos(0),
.s_axi_aruser(0),
.s_axi_arvalid( {axi_pcie_dma_arvalid}),
.s_axi_arready( {axi_pcie_dma_arready}),
.s_axi_rid( {axi_pcie_dma_rid}),
.s_axi_rdata( {axi_pcie_dma_rdata}),
.s_axi_rresp( {axi_pcie_dma_rresp}),
.s_axi_rlast( {axi_pcie_dma_rlast}),
.s_axi_ruser(),
.s_axi_rvalid( {axi_pcie_dma_rvalid}),
.s_axi_rready( {axi_pcie_dma_rready}),
.m_axi_awid( {axi_if_awid}),
.m_axi_awaddr( {axi_if_awaddr}),
.m_axi_awlen( {axi_if_awlen}),
.m_axi_awsize( {axi_if_awsize}),
.m_axi_awburst( {axi_if_awburst}),
.m_axi_awlock( {axi_if_awlock}),
.m_axi_awcache( {axi_if_awcache}),
.m_axi_awprot( {axi_if_awprot}),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid( {axi_if_awvalid}),
.m_axi_awready( {axi_if_awready}),
.m_axi_wdata( {axi_if_wdata}),
.m_axi_wstrb( {axi_if_wstrb}),
.m_axi_wlast( {axi_if_wlast}),
.m_axi_wuser(),
.m_axi_wvalid( {axi_if_wvalid}),
.m_axi_wready( {axi_if_wready}),
.m_axi_bid( {axi_if_bid}),
.m_axi_bresp( {axi_if_bresp}),
.m_axi_buser(0),
.m_axi_bvalid( {axi_if_bvalid}),
.m_axi_bready( {axi_if_bready}),
.m_axi_arid( {axi_if_arid}),
.m_axi_araddr( {axi_if_araddr}),
.m_axi_arlen( {axi_if_arlen}),
.m_axi_arsize( {axi_if_arsize}),
.m_axi_arburst( {axi_if_arburst}),
.m_axi_arlock( {axi_if_arlock}),
.m_axi_arcache( {axi_if_arcache}),
.m_axi_arprot( {axi_if_arprot}),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid( {axi_if_arvalid}),
.m_axi_arready( {axi_if_arready}),
.m_axi_rid( {axi_if_rid}),
.m_axi_rdata( {axi_if_rdata}),
.m_axi_rresp( {axi_if_rresp}),
.m_axi_rlast( {axi_if_rlast}),
.m_axi_ruser(0),
.m_axi_rvalid( {axi_if_rvalid}),
.m_axi_rready( {axi_if_rready})
);
parameter IF_RAM_SEL_WIDTH = $clog2(PORTS_PER_IF+1);
parameter IF_PCIE_DMA_TAG_WIDTH = PCIE_DMA_TAG_WIDTH-$clog2(IF_COUNT);
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_pcie_addr;
wire [IF_COUNT*IF_RAM_SEL_WIDTH-1:0] if_pcie_dma_read_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_pcie_addr;
wire [IF_COUNT*IF_RAM_SEL_WIDTH-1:0] if_pcie_dma_write_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_status_valid;
pcie_axi_dma_desc_mux #
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_wr_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_BE_WIDTH-1:0] if_dma_ram_wr_cmd_be;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_wr_cmd_addr;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_wr_cmd_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_ready;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_rd_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_rd_cmd_addr;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_ready;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_rd_resp_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_ready;
dma_if_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.S_RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.M_RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_read_desc_mux_inst (
dma_if_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* Descriptor output
* Read descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_read_desc_len),
.m_axis_desc_tag(pcie_axi_dma_read_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_read_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_read_desc_ready),
.m_axis_read_desc_dma_addr(pcie_dma_read_desc_pcie_addr),
.m_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.m_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.m_axis_read_desc_len(pcie_dma_read_desc_len),
.m_axis_read_desc_tag(pcie_dma_read_desc_tag),
.m_axis_read_desc_valid(pcie_dma_read_desc_valid),
.m_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* Descriptor status input
* Read descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* Descriptor input
* Read descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_read_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_read_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_read_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(if_pcie_dma_read_desc_len),
.s_axis_read_desc_tag(if_pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(if_pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(if_pcie_dma_read_desc_ready),
/*
* Descriptor status output
* Read descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid)
);
pcie_axi_dma_desc_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_write_desc_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.m_axis_read_desc_status_tag(if_pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(if_pcie_dma_read_desc_status_valid),
/*
* Descriptor output
* Write descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_write_desc_len),
.m_axis_desc_tag(pcie_axi_dma_write_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_write_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_write_desc_ready),
.m_axis_write_desc_dma_addr(pcie_dma_write_desc_pcie_addr),
.m_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.m_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.m_axis_write_desc_len(pcie_dma_write_desc_len),
.m_axis_write_desc_tag(pcie_dma_write_desc_tag),
.m_axis_write_desc_valid(pcie_dma_write_desc_valid),
.m_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* Descriptor status input
* Write descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* Descriptor input
* Write descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_write_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_write_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_write_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(if_pcie_dma_write_desc_len),
.s_axis_write_desc_tag(if_pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(if_pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(if_pcie_dma_write_desc_ready),
/*
* Descriptor status output
* Write descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid)
.m_axis_write_desc_status_tag(if_pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(if_pcie_dma_write_desc_status_valid),
/*
* RAM interface (from DMA interface)
*/
.if_ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.if_ram_wr_cmd_be(dma_ram_wr_cmd_be),
.if_ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.if_ram_wr_cmd_data(dma_ram_wr_cmd_data),
.if_ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.if_ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.if_ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.if_ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.if_ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.if_ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.if_ram_rd_resp_data(dma_ram_rd_resp_data),
.if_ram_rd_resp_valid(dma_ram_rd_resp_valid),
.if_ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* RAM interface
*/
.ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(if_dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(if_dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready),
.ram_rd_resp_data(if_dma_ram_rd_resp_data),
.ram_rd_resp_valid(if_dma_ram_rd_resp_valid),
.ram_rd_resp_ready(if_dma_ram_rd_resp_ready)
);
// PTP clock
@ -1829,11 +1684,6 @@ generate
for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr_int;
assign if_pcie_axi_dma_read_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_read_desc_axi_addr_int | n*24'h800000;
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int;
assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
@ -1858,9 +1708,9 @@ generate
interface #(
.PORTS(PORTS_PER_IF),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1880,8 +1730,6 @@ generate
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),
.QUEUE_LOG_SIZE_WIDTH(4),
.RAM_ADDR_WIDTH(16),
.RAM_SIZE(2**15),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
@ -1889,49 +1737,57 @@ generate
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(IF_AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(IF_AXI_ID_WIDTH),
.AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE)
)
interface_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* PCIe DMA read descriptor output
* DMA read descriptor output
*/
.m_axis_pcie_axi_dma_read_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr_int),
.m_axis_pcie_axi_dma_read_desc_len(if_pcie_axi_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_tag(if_pcie_axi_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_valid(if_pcie_axi_dma_read_desc_valid[n]),
.m_axis_pcie_axi_dma_read_desc_ready(if_pcie_axi_dma_read_desc_ready[n]),
.m_axis_dma_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_read_desc_len(if_pcie_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_read_desc_tag(if_pcie_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_read_desc_valid(if_pcie_dma_read_desc_valid[n]),
.m_axis_dma_read_desc_ready(if_pcie_dma_read_desc_ready[n]),
/*
* PCIe DMA read descriptor status input
* DMA read descriptor status input
*/
.s_axis_pcie_axi_dma_read_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_read_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid[n]),
.s_axis_dma_read_desc_status_tag(if_pcie_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_read_desc_status_valid(if_pcie_dma_read_desc_status_valid[n]),
/*
* PCIe DMA write descriptor output
* DMA write descriptor output
*/
.m_axis_pcie_axi_dma_write_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr_int),
.m_axis_pcie_axi_dma_write_desc_len(if_pcie_axi_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_tag(if_pcie_axi_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_valid(if_pcie_axi_dma_write_desc_valid[n]),
.m_axis_pcie_axi_dma_write_desc_ready(if_pcie_axi_dma_write_desc_ready[n]),
.m_axis_dma_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_write_desc_len(if_pcie_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_write_desc_tag(if_pcie_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_write_desc_valid(if_pcie_dma_write_desc_valid[n]),
.m_axis_dma_write_desc_ready(if_pcie_dma_write_desc_ready[n]),
/*
* PCIe DMA write descriptor status input
* DMA write descriptor status input
*/
.s_axis_pcie_axi_dma_write_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_write_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid[n]),
.s_axis_dma_write_desc_status_tag(if_pcie_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_write_desc_status_valid(if_pcie_dma_write_desc_status_valid[n]),
/*
* AXI-Lite slave interface
@ -1980,43 +1836,21 @@ generate
.m_axil_csr_rready(axil_if_csr_rready[n]),
/*
* AXI slave inteface
* RAM interface
*/
.s_axi_awid(axi_if_awid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_awaddr(axi_if_awaddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_awlen(axi_if_awlen[n*8 +: 8]),
.s_axi_awsize(axi_if_awsize[n*3 +: 3]),
.s_axi_awburst(axi_if_awburst[n*2 +: 2]),
.s_axi_awlock(axi_if_awlock[n]),
.s_axi_awcache(axi_if_awcache[n*4 +: 4]),
.s_axi_awprot(axi_if_awprot[n*3 +: 3]),
.s_axi_awvalid(axi_if_awvalid[n]),
.s_axi_awready(axi_if_awready[n]),
.s_axi_wdata(axi_if_wdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_wstrb(axi_if_wstrb[n*AXI_STRB_WIDTH +: AXI_STRB_WIDTH]),
.s_axi_wlast(axi_if_wlast[n]),
.s_axi_wvalid(axi_if_wvalid[n]),
.s_axi_wready(axi_if_wready[n]),
.s_axi_bid(axi_if_bid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_bresp(axi_if_bresp[n*2 +: 2]),
.s_axi_bvalid(axi_if_bvalid[n]),
.s_axi_bready(axi_if_bready[n]),
.s_axi_arid(axi_if_arid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_araddr(axi_if_araddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_arlen(axi_if_arlen[n*8 +: 8]),
.s_axi_arsize(axi_if_arsize[n*3 +: 3]),
.s_axi_arburst(axi_if_arburst[n*2 +: 2]),
.s_axi_arlock(axi_if_arlock[n]),
.s_axi_arcache(axi_if_arcache[n*4 +: 4]),
.s_axi_arprot(axi_if_arprot[n*3 +: 3]),
.s_axi_arvalid(axi_if_arvalid[n]),
.s_axi_arready(axi_if_arready[n]),
.s_axi_rid(axi_if_rid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_rdata(axi_if_rdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_rresp(axi_if_rresp[n*2 +: 2]),
.s_axi_rlast(axi_if_rlast[n]),
.s_axi_rvalid(axi_if_rvalid[n]),
.s_axi_rready(axi_if_rready[n]),
.dma_ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_wr_cmd_be(if_dma_ram_wr_cmd_be[SEG_COUNT*SEG_BE_WIDTH*n +: SEG_COUNT*SEG_BE_WIDTH]),
.dma_ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_wr_cmd_data(if_dma_ram_wr_cmd_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_data(if_dma_ram_rd_resp_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_rd_resp_valid(if_dma_ram_rd_resp_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_ready(if_dma_ram_rd_resp_ready[SEG_COUNT*n +: SEG_COUNT]),
/*
* Transmit data output

25
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -78,18 +78,6 @@ srcs.append("../lib/eth/rtl/ptp_clock.v")
srcs.append("../lib/eth/rtl/ptp_clock_cdc.v")
srcs.append("../lib/eth/rtl/ptp_perout.v")
srcs.append("../lib/eth/rtl/ptp_ts_extract.v")
srcs.append("../lib/axi/rtl/axi_crossbar.v")
srcs.append("../lib/axi/rtl/axi_crossbar_addr.v")
srcs.append("../lib/axi/rtl/axi_crossbar_rd.v")
srcs.append("../lib/axi/rtl/axi_crossbar_wr.v")
srcs.append("../lib/axi/rtl/axi_dma.v")
srcs.append("../lib/axi/rtl/axi_dma_rd.v")
srcs.append("../lib/axi/rtl/axi_dma_wr.v")
srcs.append("../lib/axi/rtl/axi_ram.v")
srcs.append("../lib/axi/rtl/axi_ram_rd_if.v")
srcs.append("../lib/axi/rtl/axi_ram_wr_if.v")
srcs.append("../lib/axi/rtl/axi_register_rd.v")
srcs.append("../lib/axi/rtl/axi_register_wr.v")
srcs.append("../lib/axi/rtl/axil_interconnect.v")
srcs.append("../lib/axi/rtl/arbiter.v")
srcs.append("../lib/axi/rtl/priority_encoder.v")
@ -99,11 +87,16 @@ srcs.append("../lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/axis/rtl/axis_register.v")
srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v")
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_rd.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_mux.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_wr.v")
srcs.append("../lib/pcie/rtl/dma_psdpram.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_sink.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_source.v")
srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")

25
fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile
View File

@ -43,18 +43,6 @@ SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
SYN_FILES += lib/axi/rtl/axi_crossbar.v
SYN_FILES += lib/axi/rtl/axi_crossbar_addr.v
SYN_FILES += lib/axi/rtl/axi_crossbar_rd.v
SYN_FILES += lib/axi/rtl/axi_crossbar_wr.v
SYN_FILES += lib/axi/rtl/axi_dma.v
SYN_FILES += lib/axi/rtl/axi_dma_rd.v
SYN_FILES += lib/axi/rtl/axi_dma_wr.v
SYN_FILES += lib/axi/rtl/axi_ram.v
SYN_FILES += lib/axi/rtl/axi_ram_rd_if.v
SYN_FILES += lib/axi/rtl/axi_ram_wr_if.v
SYN_FILES += lib/axi/rtl/axi_register_rd.v
SYN_FILES += lib/axi/rtl/axi_register_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/arbiter.v
SYN_FILES += lib/axi/rtl/priority_encoder.v
@ -65,13 +53,18 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
SYN_FILES += lib/pcie/rtl/pcie_axi_dma_desc_mux.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files

707
fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -195,15 +195,9 @@ parameter AXIL_DATA_WIDTH = 32;
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
parameter AXIL_ADDR_WIDTH = 24;
// AXI interface parameters
parameter AXI_ID_WIDTH = 8;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = 24;
// AXI stream interface parameters
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH;
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH;
parameter AXIS_DATA_WIDTH = 256;
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8;
// PCIe DMA parameters
parameter PCIE_DMA_LEN_WIDTH = 16;
@ -268,6 +262,20 @@ parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 16384;
parameter RX_FIFO_DEPTH = 16384;
parameter MAX_TX_SIZE = 2048;
parameter MAX_RX_SIZE = 2048;
// PCIe DMA parameters
parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2;
parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT;
parameter SEG_ADDR_WIDTH = 12;
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8;
parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+$clog2(PORTS_PER_IF+1);
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH);
parameter RAM_PIPELINE = 4;
parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE;
parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE;
// AXI lite connections
wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
@ -310,42 +318,20 @@ wire [1:0] axil_csr_rresp;
wire axil_csr_rvalid;
wire axil_csr_rready;
// AXI connections
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_awid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_awaddr;
wire [7:0] axi_pcie_dma_awlen;
wire [2:0] axi_pcie_dma_awsize;
wire [1:0] axi_pcie_dma_awburst;
wire axi_pcie_dma_awlock;
wire [3:0] axi_pcie_dma_awcache;
wire [2:0] axi_pcie_dma_awprot;
wire axi_pcie_dma_awvalid;
wire axi_pcie_dma_awready;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_wdata;
wire [AXI_STRB_WIDTH-1:0] axi_pcie_dma_wstrb;
wire axi_pcie_dma_wlast;
wire axi_pcie_dma_wvalid;
wire axi_pcie_dma_wready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_bid;
wire [1:0] axi_pcie_dma_bresp;
wire axi_pcie_dma_bvalid;
wire axi_pcie_dma_bready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_arid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_araddr;
wire [7:0] axi_pcie_dma_arlen;
wire [2:0] axi_pcie_dma_arsize;
wire [1:0] axi_pcie_dma_arburst;
wire axi_pcie_dma_arlock;
wire [3:0] axi_pcie_dma_arcache;
wire [2:0] axi_pcie_dma_arprot;
wire axi_pcie_dma_arvalid;
wire axi_pcie_dma_arready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_rid;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_rdata;
wire [1:0] axi_pcie_dma_rresp;
wire axi_pcie_dma_rlast;
wire axi_pcie_dma_rvalid;
wire axi_pcie_dma_rready;
// DMA connections
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready;
// Error handling
wire [1:0] status_error_uncor_int;
@ -356,25 +342,27 @@ wire [31:0] msi_irq;
wire ext_tag_enable;
// PCIe DMA control
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_tag;
wire pcie_axi_dma_read_desc_valid;
wire pcie_axi_dma_read_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_read_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_read_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_tag;
wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_status_tag;
wire pcie_axi_dma_read_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_tag;
wire pcie_axi_dma_write_desc_valid;
wire pcie_axi_dma_write_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_write_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_write_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_tag;
wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_status_tag;
wire pcie_axi_dma_write_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1;
@ -887,23 +875,25 @@ rc_reg (
.m_axis_tuser(axis_rc_tuser_r)
);
pcie_us_axi_dma #(
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(256),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_CLIENT_TAG(1),
.PCIE_TAG_COUNT(64),
.PCIE_EXT_TAG_ENABLE(1),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.TAG_WIDTH(PCIE_DMA_TAG_WIDTH)
)
pcie_us_axi_dma_inst (
dma_if_pcie_us_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
@ -927,82 +917,56 @@ pcie_us_axi_dma_inst (
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* Tag input
*/
.s_axis_pcie_rq_tag(0),
.s_axis_pcie_rq_tag_valid(0),
/*
* AXI read descriptor input
*/
.s_axis_read_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.s_axis_read_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.s_axis_read_desc_len(pcie_axi_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_axi_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_axi_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_pcie_addr(pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(pcie_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* AXI read descriptor status output
*/
.m_axis_read_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* AXI write descriptor input
*/
.s_axis_write_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.s_axis_write_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.s_axis_write_desc_len(pcie_axi_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_axi_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_axi_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_pcie_addr(pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(pcie_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* AXI write descriptor status output
*/
.m_axis_write_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* AXI Master output
* RAM interface
*/
.m_axi_awid(axi_pcie_dma_awid),
.m_axi_awaddr(axi_pcie_dma_awaddr),
.m_axi_awlen(axi_pcie_dma_awlen),
.m_axi_awsize(axi_pcie_dma_awsize),
.m_axi_awburst(axi_pcie_dma_awburst),
.m_axi_awlock(axi_pcie_dma_awlock),
.m_axi_awcache(axi_pcie_dma_awcache),
.m_axi_awprot(axi_pcie_dma_awprot),
.m_axi_awvalid(axi_pcie_dma_awvalid),
.m_axi_awready(axi_pcie_dma_awready),
.m_axi_wdata(axi_pcie_dma_wdata),
.m_axi_wstrb(axi_pcie_dma_wstrb),
.m_axi_wlast(axi_pcie_dma_wlast),
.m_axi_wvalid(axi_pcie_dma_wvalid),
.m_axi_wready(axi_pcie_dma_wready),
.m_axi_bid(axi_pcie_dma_bid),
.m_axi_bresp(axi_pcie_dma_bresp),
.m_axi_bvalid(axi_pcie_dma_bvalid),
.m_axi_bready(axi_pcie_dma_bready),
.m_axi_arid(axi_pcie_dma_arid),
.m_axi_araddr(axi_pcie_dma_araddr),
.m_axi_arlen(axi_pcie_dma_arlen),
.m_axi_arsize(axi_pcie_dma_arsize),
.m_axi_arburst(axi_pcie_dma_arburst),
.m_axi_arlock(axi_pcie_dma_arlock),
.m_axi_arcache(axi_pcie_dma_arcache),
.m_axi_arprot(axi_pcie_dma_arprot),
.m_axi_arvalid(axi_pcie_dma_arvalid),
.m_axi_arready(axi_pcie_dma_arready),
.m_axi_rid(axi_pcie_dma_rid),
.m_axi_rdata(axi_pcie_dma_rdata),
.m_axi_rresp(axi_pcie_dma_rresp),
.m_axi_rlast(axi_pcie_dma_rlast),
.m_axi_rvalid(axi_pcie_dma_rvalid),
.m_axi_rready(axi_pcie_dma_rready),
.ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.ram_rd_resp_data(dma_ram_rd_resp_data),
.ram_rd_resp_valid(dma_ram_rd_resp_valid),
.ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* Configuration
@ -1090,22 +1054,6 @@ function [IF_AXIL_BASE_ADDR_WIDTH-1:0] calcIFAxiLiteBaseAddrs(input [31:0] if_ad
end
endfunction
parameter IF_AXI_ADDR_WIDTH = 32'd23;
parameter IF_AXI_BASE_ADDR_WIDTH = IF_COUNT*AXI_ADDR_WIDTH;
parameter IF_AXI_BASE_ADDR = calcIFAxiBaseAddrs(IF_AXI_ADDR_WIDTH);
function [IF_AXI_BASE_ADDR_WIDTH-1:0] calcIFAxiBaseAddrs(input [31:0] if_addr_width);
integer i;
begin
calcIFAxiBaseAddrs = {IF_AXI_BASE_ADDR_WIDTH{1'b0}};
for (i = 0; i < IF_COUNT; i = i + 1) begin
calcIFAxiBaseAddrs[i * AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = i * (2**if_addr_width);
end
end
endfunction
parameter IF_AXI_ID_WIDTH = AXI_ID_WIDTH+$clog2(2);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;
@ -1146,42 +1094,6 @@ wire [IF_COUNT*2-1:0] axil_if_csr_rresp;
wire [IF_COUNT-1:0] axil_if_csr_rvalid;
wire [IF_COUNT-1:0] axil_if_csr_rready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_awid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_awaddr;
wire [IF_COUNT*8-1:0] axi_if_awlen;
wire [IF_COUNT*3-1:0] axi_if_awsize;
wire [IF_COUNT*2-1:0] axi_if_awburst;
wire [IF_COUNT-1:0] axi_if_awlock;
wire [IF_COUNT*4-1:0] axi_if_awcache;
wire [IF_COUNT*3-1:0] axi_if_awprot;
wire [IF_COUNT-1:0] axi_if_awvalid;
wire [IF_COUNT-1:0] axi_if_awready;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_wdata;
wire [IF_COUNT*AXI_STRB_WIDTH-1:0] axi_if_wstrb;
wire [IF_COUNT-1:0] axi_if_wlast;
wire [IF_COUNT-1:0] axi_if_wvalid;
wire [IF_COUNT-1:0] axi_if_wready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_bid;
wire [IF_COUNT*2-1:0] axi_if_bresp;
wire [IF_COUNT-1:0] axi_if_bvalid;
wire [IF_COUNT-1:0] axi_if_bready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_arid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_araddr;
wire [IF_COUNT*8-1:0] axi_if_arlen;
wire [IF_COUNT*3-1:0] axi_if_arsize;
wire [IF_COUNT*2-1:0] axi_if_arburst;
wire [IF_COUNT-1:0] axi_if_arlock;
wire [IF_COUNT*4-1:0] axi_if_arcache;
wire [IF_COUNT*3-1:0] axi_if_arprot;
wire [IF_COUNT-1:0] axi_if_arvalid;
wire [IF_COUNT-1:0] axi_if_arready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_rid;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_rdata;
wire [IF_COUNT*2-1:0] axi_if_rresp;
wire [IF_COUNT-1:0] axi_if_rlast;
wire [IF_COUNT-1:0] axi_if_rvalid;
wire [IF_COUNT-1:0] axi_if_rready;
axil_interconnect #(
.DATA_WIDTH(AXIL_DATA_WIDTH),
.ADDR_WIDTH(AXIL_ADDR_WIDTH),
@ -1288,238 +1200,167 @@ axil_csr_interconnect_inst (
.m_axil_rready(axil_csr_rready)
);
axi_crossbar #(
.S_COUNT(1),
.M_COUNT(IF_COUNT),
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH),
.STRB_WIDTH(AXI_STRB_WIDTH),
.S_ID_WIDTH(AXI_ID_WIDTH),
.M_ID_WIDTH(IF_AXI_ID_WIDTH),
.AWUSER_ENABLE(0),
.WUSER_ENABLE(0),
.BUSER_ENABLE(0),
.ARUSER_ENABLE(0),
.RUSER_ENABLE(0),
.S_THREADS({2{32'd4}}),
.S_ACCEPT({2{32'd16}}),
.M_REGIONS(1),
.M_BASE_ADDR(IF_AXI_BASE_ADDR),
.M_ADDR_WIDTH({IF_COUNT{IF_AXI_ADDR_WIDTH}}),
.M_CONNECT_READ({IF_COUNT{{2{1'b1}}}}),
.M_CONNECT_WRITE({IF_COUNT{{2{1'b1}}}}),
.M_ISSUE({IF_COUNT{32'd4}}),
.M_SECURE({IF_COUNT{1'b0}})
)
axi_crossbar_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.s_axi_awid( {axi_pcie_dma_awid}),
.s_axi_awaddr( {axi_pcie_dma_awaddr}),
.s_axi_awlen( {axi_pcie_dma_awlen}),
.s_axi_awsize( {axi_pcie_dma_awsize}),
.s_axi_awburst( {axi_pcie_dma_awburst}),
.s_axi_awlock( {axi_pcie_dma_awlock}),
.s_axi_awcache( {axi_pcie_dma_awcache}),
.s_axi_awprot( {axi_pcie_dma_awprot}),
.s_axi_awqos(0),
.s_axi_awuser(0),
.s_axi_awvalid( {axi_pcie_dma_awvalid}),
.s_axi_awready( {axi_pcie_dma_awready}),
.s_axi_wdata( {axi_pcie_dma_wdata}),
.s_axi_wstrb( {axi_pcie_dma_wstrb}),
.s_axi_wlast( {axi_pcie_dma_wlast}),
.s_axi_wuser(0),
.s_axi_wvalid( {axi_pcie_dma_wvalid}),
.s_axi_wready( {axi_pcie_dma_wready}),
.s_axi_bid( {axi_pcie_dma_bid}),
.s_axi_bresp( {axi_pcie_dma_bresp}),
.s_axi_buser(),
.s_axi_bvalid( {axi_pcie_dma_bvalid}),
.s_axi_bready( {axi_pcie_dma_bready}),
.s_axi_arid( {axi_pcie_dma_arid}),
.s_axi_araddr( {axi_pcie_dma_araddr}),
.s_axi_arlen( {axi_pcie_dma_arlen}),
.s_axi_arsize( {axi_pcie_dma_arsize}),
.s_axi_arburst( {axi_pcie_dma_arburst}),
.s_axi_arlock( {axi_pcie_dma_arlock}),
.s_axi_arcache( {axi_pcie_dma_arcache}),
.s_axi_arprot( {axi_pcie_dma_arprot}),
.s_axi_arqos(0),
.s_axi_aruser(0),
.s_axi_arvalid( {axi_pcie_dma_arvalid}),
.s_axi_arready( {axi_pcie_dma_arready}),
.s_axi_rid( {axi_pcie_dma_rid}),
.s_axi_rdata( {axi_pcie_dma_rdata}),
.s_axi_rresp( {axi_pcie_dma_rresp}),
.s_axi_rlast( {axi_pcie_dma_rlast}),
.s_axi_ruser(),
.s_axi_rvalid( {axi_pcie_dma_rvalid}),
.s_axi_rready( {axi_pcie_dma_rready}),
.m_axi_awid( {axi_if_awid}),
.m_axi_awaddr( {axi_if_awaddr}),
.m_axi_awlen( {axi_if_awlen}),
.m_axi_awsize( {axi_if_awsize}),
.m_axi_awburst( {axi_if_awburst}),
.m_axi_awlock( {axi_if_awlock}),
.m_axi_awcache( {axi_if_awcache}),
.m_axi_awprot( {axi_if_awprot}),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid( {axi_if_awvalid}),
.m_axi_awready( {axi_if_awready}),
.m_axi_wdata( {axi_if_wdata}),
.m_axi_wstrb( {axi_if_wstrb}),
.m_axi_wlast( {axi_if_wlast}),
.m_axi_wuser(),
.m_axi_wvalid( {axi_if_wvalid}),
.m_axi_wready( {axi_if_wready}),
.m_axi_bid( {axi_if_bid}),
.m_axi_bresp( {axi_if_bresp}),
.m_axi_buser(0),
.m_axi_bvalid( {axi_if_bvalid}),
.m_axi_bready( {axi_if_bready}),
.m_axi_arid( {axi_if_arid}),
.m_axi_araddr( {axi_if_araddr}),
.m_axi_arlen( {axi_if_arlen}),
.m_axi_arsize( {axi_if_arsize}),
.m_axi_arburst( {axi_if_arburst}),
.m_axi_arlock( {axi_if_arlock}),
.m_axi_arcache( {axi_if_arcache}),
.m_axi_arprot( {axi_if_arprot}),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid( {axi_if_arvalid}),
.m_axi_arready( {axi_if_arready}),
.m_axi_rid( {axi_if_rid}),
.m_axi_rdata( {axi_if_rdata}),
.m_axi_rresp( {axi_if_rresp}),
.m_axi_rlast( {axi_if_rlast}),
.m_axi_ruser(0),
.m_axi_rvalid( {axi_if_rvalid}),
.m_axi_rready( {axi_if_rready})
);
parameter IF_RAM_SEL_WIDTH = $clog2(PORTS_PER_IF+1);
parameter IF_PCIE_DMA_TAG_WIDTH = PCIE_DMA_TAG_WIDTH-$clog2(IF_COUNT);
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_pcie_addr;
wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_read_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_pcie_addr;
wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_write_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_status_valid;
pcie_axi_dma_desc_mux #
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_wr_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_BE_WIDTH-1:0] if_dma_ram_wr_cmd_be;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_wr_cmd_addr;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_wr_cmd_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_ready;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_rd_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_rd_cmd_addr;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_ready;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_rd_resp_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_ready;
dma_if_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.S_RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.M_RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_read_desc_mux_inst (
dma_if_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* Descriptor output
* Read descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_read_desc_len),
.m_axis_desc_tag(pcie_axi_dma_read_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_read_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_read_desc_ready),
.m_axis_read_desc_dma_addr(pcie_dma_read_desc_pcie_addr),
.m_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.m_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.m_axis_read_desc_len(pcie_dma_read_desc_len),
.m_axis_read_desc_tag(pcie_dma_read_desc_tag),
.m_axis_read_desc_valid(pcie_dma_read_desc_valid),
.m_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* Descriptor status input
* Read descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* Descriptor input
* Read descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_read_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_read_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_read_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(if_pcie_dma_read_desc_len),
.s_axis_read_desc_tag(if_pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(if_pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(if_pcie_dma_read_desc_ready),
/*
* Descriptor status output
* Read descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid)
);
pcie_axi_dma_desc_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_write_desc_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.m_axis_read_desc_status_tag(if_pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(if_pcie_dma_read_desc_status_valid),
/*
* Descriptor output
* Write descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_write_desc_len),
.m_axis_desc_tag(pcie_axi_dma_write_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_write_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_write_desc_ready),
.m_axis_write_desc_dma_addr(pcie_dma_write_desc_pcie_addr),
.m_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.m_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.m_axis_write_desc_len(pcie_dma_write_desc_len),
.m_axis_write_desc_tag(pcie_dma_write_desc_tag),
.m_axis_write_desc_valid(pcie_dma_write_desc_valid),
.m_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* Descriptor status input
* Write descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* Descriptor input
* Write descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_write_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_write_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_write_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(if_pcie_dma_write_desc_len),
.s_axis_write_desc_tag(if_pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(if_pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(if_pcie_dma_write_desc_ready),
/*
* Descriptor status output
* Write descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid)
.m_axis_write_desc_status_tag(if_pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(if_pcie_dma_write_desc_status_valid),
/*
* RAM interface (from DMA interface)
*/
.if_ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.if_ram_wr_cmd_be(dma_ram_wr_cmd_be),
.if_ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.if_ram_wr_cmd_data(dma_ram_wr_cmd_data),
.if_ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.if_ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.if_ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.if_ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.if_ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.if_ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.if_ram_rd_resp_data(dma_ram_rd_resp_data),
.if_ram_rd_resp_valid(dma_ram_rd_resp_valid),
.if_ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* RAM interface
*/
.ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(if_dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(if_dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready),
.ram_rd_resp_data(if_dma_ram_rd_resp_data),
.ram_rd_resp_valid(if_dma_ram_rd_resp_valid),
.ram_rd_resp_ready(if_dma_ram_rd_resp_ready)
);
// PTP clock
@ -1652,11 +1493,6 @@ generate
for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr_int;
assign if_pcie_axi_dma_read_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_read_desc_axi_addr_int | n*24'h800000;
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int;
assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
@ -1679,12 +1515,11 @@ generate
wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
interface #
(
interface #(
.PORTS(PORTS_PER_IF),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1704,8 +1539,6 @@ generate
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),
.QUEUE_LOG_SIZE_WIDTH(4),
.RAM_ADDR_WIDTH(16),
.RAM_SIZE(2**15),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
@ -1713,49 +1546,57 @@ generate
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(IF_AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(IF_AXI_ID_WIDTH),
.AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE)
)
interface_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* PCIe DMA read descriptor output
* DMA read descriptor output
*/
.m_axis_pcie_axi_dma_read_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr_int),
.m_axis_pcie_axi_dma_read_desc_len(if_pcie_axi_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_tag(if_pcie_axi_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_valid(if_pcie_axi_dma_read_desc_valid[n]),
.m_axis_pcie_axi_dma_read_desc_ready(if_pcie_axi_dma_read_desc_ready[n]),
.m_axis_dma_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_read_desc_len(if_pcie_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_read_desc_tag(if_pcie_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_read_desc_valid(if_pcie_dma_read_desc_valid[n]),
.m_axis_dma_read_desc_ready(if_pcie_dma_read_desc_ready[n]),
/*
* PCIe DMA read descriptor status input
* DMA read descriptor status input
*/
.s_axis_pcie_axi_dma_read_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_read_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid[n]),
.s_axis_dma_read_desc_status_tag(if_pcie_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_read_desc_status_valid(if_pcie_dma_read_desc_status_valid[n]),
/*
* PCIe DMA write descriptor output
* DMA write descriptor output
*/
.m_axis_pcie_axi_dma_write_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr_int),
.m_axis_pcie_axi_dma_write_desc_len(if_pcie_axi_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_tag(if_pcie_axi_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_valid(if_pcie_axi_dma_write_desc_valid[n]),
.m_axis_pcie_axi_dma_write_desc_ready(if_pcie_axi_dma_write_desc_ready[n]),
.m_axis_dma_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_write_desc_len(if_pcie_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_write_desc_tag(if_pcie_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_write_desc_valid(if_pcie_dma_write_desc_valid[n]),
.m_axis_dma_write_desc_ready(if_pcie_dma_write_desc_ready[n]),
/*
* PCIe DMA write descriptor status input
* DMA write descriptor status input
*/
.s_axis_pcie_axi_dma_write_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_write_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid[n]),
.s_axis_dma_write_desc_status_tag(if_pcie_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_write_desc_status_valid(if_pcie_dma_write_desc_status_valid[n]),
/*
* AXI-Lite slave interface
@ -1804,43 +1645,21 @@ generate
.m_axil_csr_rready(axil_if_csr_rready[n]),
/*
* AXI slave inteface
* RAM interface
*/
.s_axi_awid(axi_if_awid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_awaddr(axi_if_awaddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_awlen(axi_if_awlen[n*8 +: 8]),
.s_axi_awsize(axi_if_awsize[n*3 +: 3]),
.s_axi_awburst(axi_if_awburst[n*2 +: 2]),
.s_axi_awlock(axi_if_awlock[n]),
.s_axi_awcache(axi_if_awcache[n*4 +: 4]),
.s_axi_awprot(axi_if_awprot[n*3 +: 3]),
.s_axi_awvalid(axi_if_awvalid[n]),
.s_axi_awready(axi_if_awready[n]),
.s_axi_wdata(axi_if_wdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_wstrb(axi_if_wstrb[n*AXI_STRB_WIDTH +: AXI_STRB_WIDTH]),
.s_axi_wlast(axi_if_wlast[n]),
.s_axi_wvalid(axi_if_wvalid[n]),
.s_axi_wready(axi_if_wready[n]),
.s_axi_bid(axi_if_bid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_bresp(axi_if_bresp[n*2 +: 2]),
.s_axi_bvalid(axi_if_bvalid[n]),
.s_axi_bready(axi_if_bready[n]),
.s_axi_arid(axi_if_arid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_araddr(axi_if_araddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_arlen(axi_if_arlen[n*8 +: 8]),
.s_axi_arsize(axi_if_arsize[n*3 +: 3]),
.s_axi_arburst(axi_if_arburst[n*2 +: 2]),
.s_axi_arlock(axi_if_arlock[n]),
.s_axi_arcache(axi_if_arcache[n*4 +: 4]),
.s_axi_arprot(axi_if_arprot[n*3 +: 3]),
.s_axi_arvalid(axi_if_arvalid[n]),
.s_axi_arready(axi_if_arready[n]),
.s_axi_rid(axi_if_rid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_rdata(axi_if_rdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_rresp(axi_if_rresp[n*2 +: 2]),
.s_axi_rlast(axi_if_rlast[n]),
.s_axi_rvalid(axi_if_rvalid[n]),
.s_axi_rready(axi_if_rready[n]),
.dma_ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_wr_cmd_be(if_dma_ram_wr_cmd_be[SEG_COUNT*SEG_BE_WIDTH*n +: SEG_COUNT*SEG_BE_WIDTH]),
.dma_ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_wr_cmd_data(if_dma_ram_wr_cmd_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_data(if_dma_ram_rd_resp_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_rd_resp_valid(if_dma_ram_rd_resp_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_ready(if_dma_ram_rd_resp_ready[SEG_COUNT*n +: SEG_COUNT]),
/*
* Transmit data output

25
fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -76,18 +76,6 @@ srcs.append("../lib/eth/rtl/ptp_clock.v")
srcs.append("../lib/eth/rtl/ptp_clock_cdc.v")
srcs.append("../lib/eth/rtl/ptp_perout.v")
srcs.append("../lib/eth/rtl/ptp_ts_extract.v")
srcs.append("../lib/axi/rtl/axi_crossbar.v")
srcs.append("../lib/axi/rtl/axi_crossbar_addr.v")
srcs.append("../lib/axi/rtl/axi_crossbar_rd.v")
srcs.append("../lib/axi/rtl/axi_crossbar_wr.v")
srcs.append("../lib/axi/rtl/axi_dma.v")
srcs.append("../lib/axi/rtl/axi_dma_rd.v")
srcs.append("../lib/axi/rtl/axi_dma_wr.v")
srcs.append("../lib/axi/rtl/axi_ram.v")
srcs.append("../lib/axi/rtl/axi_ram_rd_if.v")
srcs.append("../lib/axi/rtl/axi_ram_wr_if.v")
srcs.append("../lib/axi/rtl/axi_register_rd.v")
srcs.append("../lib/axi/rtl/axi_register_wr.v")
srcs.append("../lib/axi/rtl/axil_interconnect.v")
srcs.append("../lib/axi/rtl/arbiter.v")
srcs.append("../lib/axi/rtl/priority_encoder.v")
@ -97,11 +85,16 @@ srcs.append("../lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/axis/rtl/axis_register.v")
srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v")
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_rd.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_mux.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_wr.v")
srcs.append("../lib/pcie/rtl/dma_psdpram.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_sink.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_source.v")
srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")

25
fpga/mqnic_tdma/VCU108/fpga_10g/fpga/Makefile
View File

@ -45,18 +45,6 @@ SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
SYN_FILES += lib/axi/rtl/axi_crossbar.v
SYN_FILES += lib/axi/rtl/axi_crossbar_addr.v
SYN_FILES += lib/axi/rtl/axi_crossbar_rd.v
SYN_FILES += lib/axi/rtl/axi_crossbar_wr.v
SYN_FILES += lib/axi/rtl/axi_dma.v
SYN_FILES += lib/axi/rtl/axi_dma_rd.v
SYN_FILES += lib/axi/rtl/axi_dma_wr.v
SYN_FILES += lib/axi/rtl/axi_ram.v
SYN_FILES += lib/axi/rtl/axi_ram_rd_if.v
SYN_FILES += lib/axi/rtl/axi_ram_wr_if.v
SYN_FILES += lib/axi/rtl/axi_register_rd.v
SYN_FILES += lib/axi/rtl/axi_register_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/arbiter.v
SYN_FILES += lib/axi/rtl/priority_encoder.v
@ -67,13 +55,18 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
SYN_FILES += lib/pcie/rtl/pcie_axi_dma_desc_mux.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files

707
fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -223,15 +223,9 @@ parameter AXIL_DATA_WIDTH = 32;
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
parameter AXIL_ADDR_WIDTH = 24;
// AXI interface parameters
parameter AXI_ID_WIDTH = 8;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = 24;
// AXI stream interface parameters
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH;
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH;
parameter AXIS_DATA_WIDTH = 256;
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8;
// PCIe DMA parameters
parameter PCIE_DMA_LEN_WIDTH = 16;
@ -296,6 +290,20 @@ parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 32768;
parameter RX_FIFO_DEPTH = 32768;
parameter MAX_TX_SIZE = 2048;
parameter MAX_RX_SIZE = 2048;
// PCIe DMA parameters
parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2;
parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT;
parameter SEG_ADDR_WIDTH = 12;
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8;
parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+$clog2(PORTS_PER_IF+1);
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH);
parameter RAM_PIPELINE = 2;
parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE;
parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE;
// AXI lite connections
wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
@ -358,42 +366,20 @@ wire [1:0] axil_ber_rresp;
wire axil_ber_rvalid;
wire axil_ber_rready;
// AXI connections
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_awid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_awaddr;
wire [7:0] axi_pcie_dma_awlen;
wire [2:0] axi_pcie_dma_awsize;
wire [1:0] axi_pcie_dma_awburst;
wire axi_pcie_dma_awlock;
wire [3:0] axi_pcie_dma_awcache;
wire [2:0] axi_pcie_dma_awprot;
wire axi_pcie_dma_awvalid;
wire axi_pcie_dma_awready;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_wdata;
wire [AXI_STRB_WIDTH-1:0] axi_pcie_dma_wstrb;
wire axi_pcie_dma_wlast;
wire axi_pcie_dma_wvalid;
wire axi_pcie_dma_wready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_bid;
wire [1:0] axi_pcie_dma_bresp;
wire axi_pcie_dma_bvalid;
wire axi_pcie_dma_bready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_arid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_araddr;
wire [7:0] axi_pcie_dma_arlen;
wire [2:0] axi_pcie_dma_arsize;
wire [1:0] axi_pcie_dma_arburst;
wire axi_pcie_dma_arlock;
wire [3:0] axi_pcie_dma_arcache;
wire [2:0] axi_pcie_dma_arprot;
wire axi_pcie_dma_arvalid;
wire axi_pcie_dma_arready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_rid;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_rdata;
wire [1:0] axi_pcie_dma_rresp;
wire axi_pcie_dma_rlast;
wire axi_pcie_dma_rvalid;
wire axi_pcie_dma_rready;
// DMA connections
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready;
// Error handling
wire [1:0] status_error_uncor_int;
@ -404,25 +390,27 @@ wire [31:0] msi_irq;
wire ext_tag_enable;
// PCIe DMA control
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_tag;
wire pcie_axi_dma_read_desc_valid;
wire pcie_axi_dma_read_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_read_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_read_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_tag;
wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_status_tag;
wire pcie_axi_dma_read_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_tag;
wire pcie_axi_dma_write_desc_valid;
wire pcie_axi_dma_write_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_write_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_write_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_tag;
wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_status_tag;
wire pcie_axi_dma_write_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1;
@ -908,23 +896,25 @@ rc_reg (
.m_axis_tuser(axis_rc_tuser_r)
);
pcie_us_axi_dma #(
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(256),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_CLIENT_TAG(1),
.PCIE_TAG_COUNT(64),
.PCIE_EXT_TAG_ENABLE(1),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.TAG_WIDTH(PCIE_DMA_TAG_WIDTH)
)
pcie_us_axi_dma_inst (
dma_if_pcie_us_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
@ -948,82 +938,56 @@ pcie_us_axi_dma_inst (
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* Tag input
*/
.s_axis_pcie_rq_tag(0),
.s_axis_pcie_rq_tag_valid(0),
/*
* AXI read descriptor input
*/
.s_axis_read_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.s_axis_read_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.s_axis_read_desc_len(pcie_axi_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_axi_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_axi_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_pcie_addr(pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(pcie_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* AXI read descriptor status output
*/
.m_axis_read_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* AXI write descriptor input
*/
.s_axis_write_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.s_axis_write_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.s_axis_write_desc_len(pcie_axi_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_axi_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_axi_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_pcie_addr(pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(pcie_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* AXI write descriptor status output
*/
.m_axis_write_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* AXI Master output
* RAM interface
*/
.m_axi_awid(axi_pcie_dma_awid),
.m_axi_awaddr(axi_pcie_dma_awaddr),
.m_axi_awlen(axi_pcie_dma_awlen),
.m_axi_awsize(axi_pcie_dma_awsize),
.m_axi_awburst(axi_pcie_dma_awburst),
.m_axi_awlock(axi_pcie_dma_awlock),
.m_axi_awcache(axi_pcie_dma_awcache),
.m_axi_awprot(axi_pcie_dma_awprot),
.m_axi_awvalid(axi_pcie_dma_awvalid),
.m_axi_awready(axi_pcie_dma_awready),
.m_axi_wdata(axi_pcie_dma_wdata),
.m_axi_wstrb(axi_pcie_dma_wstrb),
.m_axi_wlast(axi_pcie_dma_wlast),
.m_axi_wvalid(axi_pcie_dma_wvalid),
.m_axi_wready(axi_pcie_dma_wready),
.m_axi_bid(axi_pcie_dma_bid),
.m_axi_bresp(axi_pcie_dma_bresp),
.m_axi_bvalid(axi_pcie_dma_bvalid),
.m_axi_bready(axi_pcie_dma_bready),
.m_axi_arid(axi_pcie_dma_arid),
.m_axi_araddr(axi_pcie_dma_araddr),
.m_axi_arlen(axi_pcie_dma_arlen),
.m_axi_arsize(axi_pcie_dma_arsize),
.m_axi_arburst(axi_pcie_dma_arburst),
.m_axi_arlock(axi_pcie_dma_arlock),
.m_axi_arcache(axi_pcie_dma_arcache),
.m_axi_arprot(axi_pcie_dma_arprot),
.m_axi_arvalid(axi_pcie_dma_arvalid),
.m_axi_arready(axi_pcie_dma_arready),
.m_axi_rid(axi_pcie_dma_rid),
.m_axi_rdata(axi_pcie_dma_rdata),
.m_axi_rresp(axi_pcie_dma_rresp),
.m_axi_rlast(axi_pcie_dma_rlast),
.m_axi_rvalid(axi_pcie_dma_rvalid),
.m_axi_rready(axi_pcie_dma_rready),
.ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.ram_rd_resp_data(dma_ram_rd_resp_data),
.ram_rd_resp_valid(dma_ram_rd_resp_valid),
.ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* Configuration
@ -1111,22 +1075,6 @@ function [IF_AXIL_BASE_ADDR_WIDTH-1:0] calcIFAxiLiteBaseAddrs(input [31:0] if_ad
end
endfunction
parameter IF_AXI_ADDR_WIDTH = 32'd23;
parameter IF_AXI_BASE_ADDR_WIDTH = IF_COUNT*AXI_ADDR_WIDTH;
parameter IF_AXI_BASE_ADDR = calcIFAxiBaseAddrs(IF_AXI_ADDR_WIDTH);
function [IF_AXI_BASE_ADDR_WIDTH-1:0] calcIFAxiBaseAddrs(input [31:0] if_addr_width);
integer i;
begin
calcIFAxiBaseAddrs = {IF_AXI_BASE_ADDR_WIDTH{1'b0}};
for (i = 0; i < IF_COUNT; i = i + 1) begin
calcIFAxiBaseAddrs[i * AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = i * (2**if_addr_width);
end
end
endfunction
parameter IF_AXI_ID_WIDTH = AXI_ID_WIDTH+$clog2(2);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;
@ -1167,42 +1115,6 @@ wire [IF_COUNT*2-1:0] axil_if_csr_rresp;
wire [IF_COUNT-1:0] axil_if_csr_rvalid;
wire [IF_COUNT-1:0] axil_if_csr_rready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_awid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_awaddr;
wire [IF_COUNT*8-1:0] axi_if_awlen;
wire [IF_COUNT*3-1:0] axi_if_awsize;
wire [IF_COUNT*2-1:0] axi_if_awburst;
wire [IF_COUNT-1:0] axi_if_awlock;
wire [IF_COUNT*4-1:0] axi_if_awcache;
wire [IF_COUNT*3-1:0] axi_if_awprot;
wire [IF_COUNT-1:0] axi_if_awvalid;
wire [IF_COUNT-1:0] axi_if_awready;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_wdata;
wire [IF_COUNT*AXI_STRB_WIDTH-1:0] axi_if_wstrb;
wire [IF_COUNT-1:0] axi_if_wlast;
wire [IF_COUNT-1:0] axi_if_wvalid;
wire [IF_COUNT-1:0] axi_if_wready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_bid;
wire [IF_COUNT*2-1:0] axi_if_bresp;
wire [IF_COUNT-1:0] axi_if_bvalid;
wire [IF_COUNT-1:0] axi_if_bready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_arid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_araddr;
wire [IF_COUNT*8-1:0] axi_if_arlen;
wire [IF_COUNT*3-1:0] axi_if_arsize;
wire [IF_COUNT*2-1:0] axi_if_arburst;
wire [IF_COUNT-1:0] axi_if_arlock;
wire [IF_COUNT*4-1:0] axi_if_arcache;
wire [IF_COUNT*3-1:0] axi_if_arprot;
wire [IF_COUNT-1:0] axi_if_arvalid;
wire [IF_COUNT-1:0] axi_if_arready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_rid;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_rdata;
wire [IF_COUNT*2-1:0] axi_if_rresp;
wire [IF_COUNT-1:0] axi_if_rlast;
wire [IF_COUNT-1:0] axi_if_rvalid;
wire [IF_COUNT-1:0] axi_if_rready;
axil_interconnect #(
.DATA_WIDTH(AXIL_DATA_WIDTH),
.ADDR_WIDTH(AXIL_ADDR_WIDTH),
@ -1313,238 +1225,167 @@ axil_csr_interconnect_inst (
.m_axil_rready( {axil_ber_rready, axil_csr_rready})
);
axi_crossbar #(
.S_COUNT(1),
.M_COUNT(IF_COUNT),
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH),
.STRB_WIDTH(AXI_STRB_WIDTH),
.S_ID_WIDTH(AXI_ID_WIDTH),
.M_ID_WIDTH(IF_AXI_ID_WIDTH),
.AWUSER_ENABLE(0),
.WUSER_ENABLE(0),
.BUSER_ENABLE(0),
.ARUSER_ENABLE(0),
.RUSER_ENABLE(0),
.S_THREADS({2{32'd4}}),
.S_ACCEPT({2{32'd16}}),
.M_REGIONS(1),
.M_BASE_ADDR(IF_AXI_BASE_ADDR),
.M_ADDR_WIDTH({IF_COUNT{IF_AXI_ADDR_WIDTH}}),
.M_CONNECT_READ({IF_COUNT{{2{1'b1}}}}),
.M_CONNECT_WRITE({IF_COUNT{{2{1'b1}}}}),
.M_ISSUE({IF_COUNT{32'd4}}),
.M_SECURE({IF_COUNT{1'b0}})
)
axi_crossbar_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.s_axi_awid( {axi_pcie_dma_awid}),
.s_axi_awaddr( {axi_pcie_dma_awaddr}),
.s_axi_awlen( {axi_pcie_dma_awlen}),
.s_axi_awsize( {axi_pcie_dma_awsize}),
.s_axi_awburst( {axi_pcie_dma_awburst}),
.s_axi_awlock( {axi_pcie_dma_awlock}),
.s_axi_awcache( {axi_pcie_dma_awcache}),
.s_axi_awprot( {axi_pcie_dma_awprot}),
.s_axi_awqos(0),
.s_axi_awuser(0),
.s_axi_awvalid( {axi_pcie_dma_awvalid}),
.s_axi_awready( {axi_pcie_dma_awready}),
.s_axi_wdata( {axi_pcie_dma_wdata}),
.s_axi_wstrb( {axi_pcie_dma_wstrb}),
.s_axi_wlast( {axi_pcie_dma_wlast}),
.s_axi_wuser(0),
.s_axi_wvalid( {axi_pcie_dma_wvalid}),
.s_axi_wready( {axi_pcie_dma_wready}),
.s_axi_bid( {axi_pcie_dma_bid}),
.s_axi_bresp( {axi_pcie_dma_bresp}),
.s_axi_buser(),
.s_axi_bvalid( {axi_pcie_dma_bvalid}),
.s_axi_bready( {axi_pcie_dma_bready}),
.s_axi_arid( {axi_pcie_dma_arid}),
.s_axi_araddr( {axi_pcie_dma_araddr}),
.s_axi_arlen( {axi_pcie_dma_arlen}),
.s_axi_arsize( {axi_pcie_dma_arsize}),
.s_axi_arburst( {axi_pcie_dma_arburst}),
.s_axi_arlock( {axi_pcie_dma_arlock}),
.s_axi_arcache( {axi_pcie_dma_arcache}),
.s_axi_arprot( {axi_pcie_dma_arprot}),
.s_axi_arqos(0),
.s_axi_aruser(0),
.s_axi_arvalid( {axi_pcie_dma_arvalid}),
.s_axi_arready( {axi_pcie_dma_arready}),
.s_axi_rid( {axi_pcie_dma_rid}),
.s_axi_rdata( {axi_pcie_dma_rdata}),
.s_axi_rresp( {axi_pcie_dma_rresp}),
.s_axi_rlast( {axi_pcie_dma_rlast}),
.s_axi_ruser(),
.s_axi_rvalid( {axi_pcie_dma_rvalid}),
.s_axi_rready( {axi_pcie_dma_rready}),
.m_axi_awid( {axi_if_awid}),
.m_axi_awaddr( {axi_if_awaddr}),
.m_axi_awlen( {axi_if_awlen}),
.m_axi_awsize( {axi_if_awsize}),
.m_axi_awburst( {axi_if_awburst}),
.m_axi_awlock( {axi_if_awlock}),
.m_axi_awcache( {axi_if_awcache}),
.m_axi_awprot( {axi_if_awprot}),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid( {axi_if_awvalid}),
.m_axi_awready( {axi_if_awready}),
.m_axi_wdata( {axi_if_wdata}),
.m_axi_wstrb( {axi_if_wstrb}),
.m_axi_wlast( {axi_if_wlast}),
.m_axi_wuser(),
.m_axi_wvalid( {axi_if_wvalid}),
.m_axi_wready( {axi_if_wready}),
.m_axi_bid( {axi_if_bid}),
.m_axi_bresp( {axi_if_bresp}),
.m_axi_buser(0),
.m_axi_bvalid( {axi_if_bvalid}),
.m_axi_bready( {axi_if_bready}),
.m_axi_arid( {axi_if_arid}),
.m_axi_araddr( {axi_if_araddr}),
.m_axi_arlen( {axi_if_arlen}),
.m_axi_arsize( {axi_if_arsize}),
.m_axi_arburst( {axi_if_arburst}),
.m_axi_arlock( {axi_if_arlock}),
.m_axi_arcache( {axi_if_arcache}),
.m_axi_arprot( {axi_if_arprot}),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid( {axi_if_arvalid}),
.m_axi_arready( {axi_if_arready}),
.m_axi_rid( {axi_if_rid}),
.m_axi_rdata( {axi_if_rdata}),
.m_axi_rresp( {axi_if_rresp}),
.m_axi_rlast( {axi_if_rlast}),
.m_axi_ruser(0),
.m_axi_rvalid( {axi_if_rvalid}),
.m_axi_rready( {axi_if_rready})
);
parameter IF_RAM_SEL_WIDTH = $clog2(PORTS_PER_IF+1);
parameter IF_PCIE_DMA_TAG_WIDTH = PCIE_DMA_TAG_WIDTH-$clog2(IF_COUNT);
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_pcie_addr;
wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_read_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_pcie_addr;
wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_write_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_status_valid;
pcie_axi_dma_desc_mux #
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_wr_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_BE_WIDTH-1:0] if_dma_ram_wr_cmd_be;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_wr_cmd_addr;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_wr_cmd_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_ready;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_rd_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_rd_cmd_addr;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_ready;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_rd_resp_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_ready;
dma_if_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.S_RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.M_RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_read_desc_mux_inst (
dma_if_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* Descriptor output
* Read descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_read_desc_len),
.m_axis_desc_tag(pcie_axi_dma_read_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_read_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_read_desc_ready),
.m_axis_read_desc_dma_addr(pcie_dma_read_desc_pcie_addr),
.m_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.m_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.m_axis_read_desc_len(pcie_dma_read_desc_len),
.m_axis_read_desc_tag(pcie_dma_read_desc_tag),
.m_axis_read_desc_valid(pcie_dma_read_desc_valid),
.m_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* Descriptor status input
* Read descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* Descriptor input
* Read descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_read_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_read_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_read_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(if_pcie_dma_read_desc_len),
.s_axis_read_desc_tag(if_pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(if_pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(if_pcie_dma_read_desc_ready),
/*
* Descriptor status output
* Read descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid)
);
pcie_axi_dma_desc_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_write_desc_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.m_axis_read_desc_status_tag(if_pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(if_pcie_dma_read_desc_status_valid),
/*
* Descriptor output
* Write descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_write_desc_len),
.m_axis_desc_tag(pcie_axi_dma_write_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_write_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_write_desc_ready),
.m_axis_write_desc_dma_addr(pcie_dma_write_desc_pcie_addr),
.m_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.m_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.m_axis_write_desc_len(pcie_dma_write_desc_len),
.m_axis_write_desc_tag(pcie_dma_write_desc_tag),
.m_axis_write_desc_valid(pcie_dma_write_desc_valid),
.m_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* Descriptor status input
* Write descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* Descriptor input
* Write descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_write_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_write_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_write_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(if_pcie_dma_write_desc_len),
.s_axis_write_desc_tag(if_pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(if_pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(if_pcie_dma_write_desc_ready),
/*
* Descriptor status output
* Write descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid)
.m_axis_write_desc_status_tag(if_pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(if_pcie_dma_write_desc_status_valid),
/*
* RAM interface (from DMA interface)
*/
.if_ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.if_ram_wr_cmd_be(dma_ram_wr_cmd_be),
.if_ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.if_ram_wr_cmd_data(dma_ram_wr_cmd_data),
.if_ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.if_ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.if_ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.if_ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.if_ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.if_ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.if_ram_rd_resp_data(dma_ram_rd_resp_data),
.if_ram_rd_resp_valid(dma_ram_rd_resp_valid),
.if_ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* RAM interface
*/
.ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(if_dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(if_dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready),
.ram_rd_resp_data(if_dma_ram_rd_resp_data),
.ram_rd_resp_valid(if_dma_ram_rd_resp_valid),
.ram_rd_resp_ready(if_dma_ram_rd_resp_ready)
);
// PTP clock
@ -1802,11 +1643,6 @@ generate
for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr_int;
assign if_pcie_axi_dma_read_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_read_desc_axi_addr_int | n*24'h800000;
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int;
assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
@ -1829,12 +1665,11 @@ generate
wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
interface #
(
interface #(
.PORTS(PORTS_PER_IF),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1854,8 +1689,6 @@ generate
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),
.QUEUE_LOG_SIZE_WIDTH(4),
.RAM_ADDR_WIDTH(16),
.RAM_SIZE(2**15),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
@ -1863,49 +1696,57 @@ generate
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(IF_AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(IF_AXI_ID_WIDTH),
.AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE)
)
interface_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* PCIe DMA read descriptor output
* DMA read descriptor output
*/
.m_axis_pcie_axi_dma_read_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr_int),
.m_axis_pcie_axi_dma_read_desc_len(if_pcie_axi_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_tag(if_pcie_axi_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_valid(if_pcie_axi_dma_read_desc_valid[n]),
.m_axis_pcie_axi_dma_read_desc_ready(if_pcie_axi_dma_read_desc_ready[n]),
.m_axis_dma_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_read_desc_len(if_pcie_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_read_desc_tag(if_pcie_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_read_desc_valid(if_pcie_dma_read_desc_valid[n]),
.m_axis_dma_read_desc_ready(if_pcie_dma_read_desc_ready[n]),
/*
* PCIe DMA read descriptor status input
* DMA read descriptor status input
*/
.s_axis_pcie_axi_dma_read_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_read_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid[n]),
.s_axis_dma_read_desc_status_tag(if_pcie_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_read_desc_status_valid(if_pcie_dma_read_desc_status_valid[n]),
/*
* PCIe DMA write descriptor output
* DMA write descriptor output
*/
.m_axis_pcie_axi_dma_write_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr_int),
.m_axis_pcie_axi_dma_write_desc_len(if_pcie_axi_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_tag(if_pcie_axi_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_valid(if_pcie_axi_dma_write_desc_valid[n]),
.m_axis_pcie_axi_dma_write_desc_ready(if_pcie_axi_dma_write_desc_ready[n]),
.m_axis_dma_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_write_desc_len(if_pcie_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_write_desc_tag(if_pcie_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_write_desc_valid(if_pcie_dma_write_desc_valid[n]),
.m_axis_dma_write_desc_ready(if_pcie_dma_write_desc_ready[n]),
/*
* PCIe DMA write descriptor status input
* DMA write descriptor status input
*/
.s_axis_pcie_axi_dma_write_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_write_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid[n]),
.s_axis_dma_write_desc_status_tag(if_pcie_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_write_desc_status_valid(if_pcie_dma_write_desc_status_valid[n]),
/*
* AXI-Lite slave interface
@ -1954,43 +1795,21 @@ generate
.m_axil_csr_rready(axil_if_csr_rready[n]),
/*
* AXI slave inteface
* RAM interface
*/
.s_axi_awid(axi_if_awid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_awaddr(axi_if_awaddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_awlen(axi_if_awlen[n*8 +: 8]),
.s_axi_awsize(axi_if_awsize[n*3 +: 3]),
.s_axi_awburst(axi_if_awburst[n*2 +: 2]),
.s_axi_awlock(axi_if_awlock[n]),
.s_axi_awcache(axi_if_awcache[n*4 +: 4]),
.s_axi_awprot(axi_if_awprot[n*3 +: 3]),
.s_axi_awvalid(axi_if_awvalid[n]),
.s_axi_awready(axi_if_awready[n]),
.s_axi_wdata(axi_if_wdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_wstrb(axi_if_wstrb[n*AXI_STRB_WIDTH +: AXI_STRB_WIDTH]),
.s_axi_wlast(axi_if_wlast[n]),
.s_axi_wvalid(axi_if_wvalid[n]),
.s_axi_wready(axi_if_wready[n]),
.s_axi_bid(axi_if_bid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_bresp(axi_if_bresp[n*2 +: 2]),
.s_axi_bvalid(axi_if_bvalid[n]),
.s_axi_bready(axi_if_bready[n]),
.s_axi_arid(axi_if_arid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_araddr(axi_if_araddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_arlen(axi_if_arlen[n*8 +: 8]),
.s_axi_arsize(axi_if_arsize[n*3 +: 3]),
.s_axi_arburst(axi_if_arburst[n*2 +: 2]),
.s_axi_arlock(axi_if_arlock[n]),
.s_axi_arcache(axi_if_arcache[n*4 +: 4]),
.s_axi_arprot(axi_if_arprot[n*3 +: 3]),
.s_axi_arvalid(axi_if_arvalid[n]),
.s_axi_arready(axi_if_arready[n]),
.s_axi_rid(axi_if_rid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_rdata(axi_if_rdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_rresp(axi_if_rresp[n*2 +: 2]),
.s_axi_rlast(axi_if_rlast[n]),
.s_axi_rvalid(axi_if_rvalid[n]),
.s_axi_rready(axi_if_rready[n]),
.dma_ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_wr_cmd_be(if_dma_ram_wr_cmd_be[SEG_COUNT*SEG_BE_WIDTH*n +: SEG_COUNT*SEG_BE_WIDTH]),
.dma_ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_wr_cmd_data(if_dma_ram_wr_cmd_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_data(if_dma_ram_rd_resp_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_rd_resp_valid(if_dma_ram_rd_resp_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_ready(if_dma_ram_rd_resp_ready[SEG_COUNT*n +: SEG_COUNT]),
/*
* Transmit data output

25
fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -78,18 +78,6 @@ srcs.append("../lib/eth/rtl/ptp_clock.v")
srcs.append("../lib/eth/rtl/ptp_clock_cdc.v")
srcs.append("../lib/eth/rtl/ptp_perout.v")
srcs.append("../lib/eth/rtl/ptp_ts_extract.v")
srcs.append("../lib/axi/rtl/axi_crossbar.v")
srcs.append("../lib/axi/rtl/axi_crossbar_addr.v")
srcs.append("../lib/axi/rtl/axi_crossbar_rd.v")
srcs.append("../lib/axi/rtl/axi_crossbar_wr.v")
srcs.append("../lib/axi/rtl/axi_dma.v")
srcs.append("../lib/axi/rtl/axi_dma_rd.v")
srcs.append("../lib/axi/rtl/axi_dma_wr.v")
srcs.append("../lib/axi/rtl/axi_ram.v")
srcs.append("../lib/axi/rtl/axi_ram_rd_if.v")
srcs.append("../lib/axi/rtl/axi_ram_wr_if.v")
srcs.append("../lib/axi/rtl/axi_register_rd.v")
srcs.append("../lib/axi/rtl/axi_register_wr.v")
srcs.append("../lib/axi/rtl/axil_interconnect.v")
srcs.append("../lib/axi/rtl/arbiter.v")
srcs.append("../lib/axi/rtl/priority_encoder.v")
@ -99,11 +87,16 @@ srcs.append("../lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/axis/rtl/axis_register.v")
srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v")
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_rd.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_mux.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_wr.v")
srcs.append("../lib/pcie/rtl/dma_psdpram.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_sink.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_source.v")
srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")

25
fpga/mqnic_tdma/VCU118/fpga_10g/fpga/Makefile
View File

@ -45,18 +45,6 @@ SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
SYN_FILES += lib/axi/rtl/axi_crossbar.v
SYN_FILES += lib/axi/rtl/axi_crossbar_addr.v
SYN_FILES += lib/axi/rtl/axi_crossbar_rd.v
SYN_FILES += lib/axi/rtl/axi_crossbar_wr.v
SYN_FILES += lib/axi/rtl/axi_dma.v
SYN_FILES += lib/axi/rtl/axi_dma_rd.v
SYN_FILES += lib/axi/rtl/axi_dma_wr.v
SYN_FILES += lib/axi/rtl/axi_ram.v
SYN_FILES += lib/axi/rtl/axi_ram_rd_if.v
SYN_FILES += lib/axi/rtl/axi_ram_wr_if.v
SYN_FILES += lib/axi/rtl/axi_register_rd.v
SYN_FILES += lib/axi/rtl/axi_register_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/arbiter.v
SYN_FILES += lib/axi/rtl/priority_encoder.v
@ -67,13 +55,18 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
SYN_FILES += lib/pcie/rtl/pcie_axi_dma_desc_mux.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files

704
fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -260,15 +260,9 @@ parameter AXIL_DATA_WIDTH = 32;
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
parameter AXIL_ADDR_WIDTH = 24;
// AXI interface parameters
parameter AXI_ID_WIDTH = 8;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = 24;
// AXI stream interface parameters
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH;
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH;
parameter AXIS_DATA_WIDTH = 256;
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8;
// PCIe DMA parameters
parameter PCIE_DMA_LEN_WIDTH = 16;
@ -333,6 +327,20 @@ parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 32768;
parameter RX_FIFO_DEPTH = 32768;
parameter MAX_TX_SIZE = 2048;
parameter MAX_RX_SIZE = 2048;
// PCIe DMA parameters
parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2;
parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT;
parameter SEG_ADDR_WIDTH = 12;
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8;
parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+$clog2(PORTS_PER_IF+1);
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH);
parameter RAM_PIPELINE = 2;
parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE;
parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE;
// AXI lite connections
wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
@ -395,42 +403,20 @@ wire [1:0] axil_ber_rresp;
wire axil_ber_rvalid;
wire axil_ber_rready;
// AXI connections
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_awid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_awaddr;
wire [7:0] axi_pcie_dma_awlen;
wire [2:0] axi_pcie_dma_awsize;
wire [1:0] axi_pcie_dma_awburst;
wire axi_pcie_dma_awlock;
wire [3:0] axi_pcie_dma_awcache;
wire [2:0] axi_pcie_dma_awprot;
wire axi_pcie_dma_awvalid;
wire axi_pcie_dma_awready;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_wdata;
wire [AXI_STRB_WIDTH-1:0] axi_pcie_dma_wstrb;
wire axi_pcie_dma_wlast;
wire axi_pcie_dma_wvalid;
wire axi_pcie_dma_wready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_bid;
wire [1:0] axi_pcie_dma_bresp;
wire axi_pcie_dma_bvalid;
wire axi_pcie_dma_bready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_arid;
wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_araddr;
wire [7:0] axi_pcie_dma_arlen;
wire [2:0] axi_pcie_dma_arsize;
wire [1:0] axi_pcie_dma_arburst;
wire axi_pcie_dma_arlock;
wire [3:0] axi_pcie_dma_arcache;
wire [2:0] axi_pcie_dma_arprot;
wire axi_pcie_dma_arvalid;
wire axi_pcie_dma_arready;
wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_rid;
wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_rdata;
wire [1:0] axi_pcie_dma_rresp;
wire axi_pcie_dma_rlast;
wire axi_pcie_dma_rvalid;
wire axi_pcie_dma_rready;
// DMA connections
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready;
// Error handling
wire [1:0] status_error_uncor_int;
@ -441,25 +427,27 @@ wire [31:0] msi_irq;
wire ext_tag_enable;
// PCIe DMA control
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_tag;
wire pcie_axi_dma_read_desc_valid;
wire pcie_axi_dma_read_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_read_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_read_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_read_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_tag;
wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_status_tag;
wire pcie_axi_dma_read_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_axi_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_tag;
wire pcie_axi_dma_write_desc_valid;
wire pcie_axi_dma_write_desc_ready;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
wire [RAM_SEL_WIDTH-1:0] pcie_dma_write_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] pcie_dma_write_desc_ram_addr;
wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_write_desc_len;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_tag;
wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_status_tag;
wire pcie_axi_dma_write_desc_status_valid;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1;
@ -894,23 +882,25 @@ rc_reg (
.m_axis_tuser(axis_rc_tuser_r)
);
pcie_us_axi_dma #(
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(256),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_CLIENT_TAG(1),
.PCIE_TAG_COUNT(64),
.PCIE_EXT_TAG_ENABLE(1),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.TAG_WIDTH(PCIE_DMA_TAG_WIDTH)
)
pcie_us_axi_dma_inst (
dma_if_pcie_us_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
@ -934,82 +924,56 @@ pcie_us_axi_dma_inst (
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* Tag input
*/
.s_axis_pcie_rq_tag(0),
.s_axis_pcie_rq_tag_valid(0),
/*
* AXI read descriptor input
*/
.s_axis_read_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.s_axis_read_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.s_axis_read_desc_len(pcie_axi_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_axi_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_axi_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_pcie_addr(pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(pcie_dma_read_desc_len),
.s_axis_read_desc_tag(pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* AXI read descriptor status output
*/
.m_axis_read_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* AXI write descriptor input
*/
.s_axis_write_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.s_axis_write_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.s_axis_write_desc_len(pcie_axi_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_axi_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_axi_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_pcie_addr(pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(pcie_dma_write_desc_len),
.s_axis_write_desc_tag(pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* AXI write descriptor status output
*/
.m_axis_write_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* AXI Master output
* RAM interface
*/
.m_axi_awid(axi_pcie_dma_awid),
.m_axi_awaddr(axi_pcie_dma_awaddr),
.m_axi_awlen(axi_pcie_dma_awlen),
.m_axi_awsize(axi_pcie_dma_awsize),
.m_axi_awburst(axi_pcie_dma_awburst),
.m_axi_awlock(axi_pcie_dma_awlock),
.m_axi_awcache(axi_pcie_dma_awcache),
.m_axi_awprot(axi_pcie_dma_awprot),
.m_axi_awvalid(axi_pcie_dma_awvalid),
.m_axi_awready(axi_pcie_dma_awready),
.m_axi_wdata(axi_pcie_dma_wdata),
.m_axi_wstrb(axi_pcie_dma_wstrb),
.m_axi_wlast(axi_pcie_dma_wlast),
.m_axi_wvalid(axi_pcie_dma_wvalid),
.m_axi_wready(axi_pcie_dma_wready),
.m_axi_bid(axi_pcie_dma_bid),
.m_axi_bresp(axi_pcie_dma_bresp),
.m_axi_bvalid(axi_pcie_dma_bvalid),
.m_axi_bready(axi_pcie_dma_bready),
.m_axi_arid(axi_pcie_dma_arid),
.m_axi_araddr(axi_pcie_dma_araddr),
.m_axi_arlen(axi_pcie_dma_arlen),
.m_axi_arsize(axi_pcie_dma_arsize),
.m_axi_arburst(axi_pcie_dma_arburst),
.m_axi_arlock(axi_pcie_dma_arlock),
.m_axi_arcache(axi_pcie_dma_arcache),
.m_axi_arprot(axi_pcie_dma_arprot),
.m_axi_arvalid(axi_pcie_dma_arvalid),
.m_axi_arready(axi_pcie_dma_arready),
.m_axi_rid(axi_pcie_dma_rid),
.m_axi_rdata(axi_pcie_dma_rdata),
.m_axi_rresp(axi_pcie_dma_rresp),
.m_axi_rlast(axi_pcie_dma_rlast),
.m_axi_rvalid(axi_pcie_dma_rvalid),
.m_axi_rready(axi_pcie_dma_rready),
.ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.ram_rd_resp_data(dma_ram_rd_resp_data),
.ram_rd_resp_valid(dma_ram_rd_resp_valid),
.ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* Configuration
@ -1097,22 +1061,6 @@ function [IF_AXIL_BASE_ADDR_WIDTH-1:0] calcIFAxiLiteBaseAddrs(input [31:0] if_ad
end
endfunction
parameter IF_AXI_ADDR_WIDTH = 32'd23;
parameter IF_AXI_BASE_ADDR_WIDTH = IF_COUNT*AXI_ADDR_WIDTH;
parameter IF_AXI_BASE_ADDR = calcIFAxiBaseAddrs(IF_AXI_ADDR_WIDTH);
function [IF_AXI_BASE_ADDR_WIDTH-1:0] calcIFAxiBaseAddrs(input [31:0] if_addr_width);
integer i;
begin
calcIFAxiBaseAddrs = {IF_AXI_BASE_ADDR_WIDTH{1'b0}};
for (i = 0; i < IF_COUNT; i = i + 1) begin
calcIFAxiBaseAddrs[i * AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = i * (2**if_addr_width);
end
end
endfunction
parameter IF_AXI_ID_WIDTH = AXI_ID_WIDTH+$clog2(2);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;
@ -1153,42 +1101,6 @@ wire [IF_COUNT*2-1:0] axil_if_csr_rresp;
wire [IF_COUNT-1:0] axil_if_csr_rvalid;
wire [IF_COUNT-1:0] axil_if_csr_rready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_awid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_awaddr;
wire [IF_COUNT*8-1:0] axi_if_awlen;
wire [IF_COUNT*3-1:0] axi_if_awsize;
wire [IF_COUNT*2-1:0] axi_if_awburst;
wire [IF_COUNT-1:0] axi_if_awlock;
wire [IF_COUNT*4-1:0] axi_if_awcache;
wire [IF_COUNT*3-1:0] axi_if_awprot;
wire [IF_COUNT-1:0] axi_if_awvalid;
wire [IF_COUNT-1:0] axi_if_awready;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_wdata;
wire [IF_COUNT*AXI_STRB_WIDTH-1:0] axi_if_wstrb;
wire [IF_COUNT-1:0] axi_if_wlast;
wire [IF_COUNT-1:0] axi_if_wvalid;
wire [IF_COUNT-1:0] axi_if_wready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_bid;
wire [IF_COUNT*2-1:0] axi_if_bresp;
wire [IF_COUNT-1:0] axi_if_bvalid;
wire [IF_COUNT-1:0] axi_if_bready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_arid;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_araddr;
wire [IF_COUNT*8-1:0] axi_if_arlen;
wire [IF_COUNT*3-1:0] axi_if_arsize;
wire [IF_COUNT*2-1:0] axi_if_arburst;
wire [IF_COUNT-1:0] axi_if_arlock;
wire [IF_COUNT*4-1:0] axi_if_arcache;
wire [IF_COUNT*3-1:0] axi_if_arprot;
wire [IF_COUNT-1:0] axi_if_arvalid;
wire [IF_COUNT-1:0] axi_if_arready;
wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_rid;
wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_rdata;
wire [IF_COUNT*2-1:0] axi_if_rresp;
wire [IF_COUNT-1:0] axi_if_rlast;
wire [IF_COUNT-1:0] axi_if_rvalid;
wire [IF_COUNT-1:0] axi_if_rready;
axil_interconnect #(
.DATA_WIDTH(AXIL_DATA_WIDTH),
.ADDR_WIDTH(AXIL_ADDR_WIDTH),
@ -1299,238 +1211,167 @@ axil_csr_interconnect_inst (
.m_axil_rready( {axil_ber_rready, axil_csr_rready})
);
axi_crossbar #(
.S_COUNT(1),
.M_COUNT(IF_COUNT),
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH),
.STRB_WIDTH(AXI_STRB_WIDTH),
.S_ID_WIDTH(AXI_ID_WIDTH),
.M_ID_WIDTH(IF_AXI_ID_WIDTH),
.AWUSER_ENABLE(0),
.WUSER_ENABLE(0),
.BUSER_ENABLE(0),
.ARUSER_ENABLE(0),
.RUSER_ENABLE(0),
.S_THREADS({2{32'd4}}),
.S_ACCEPT({2{32'd16}}),
.M_REGIONS(1),
.M_BASE_ADDR(IF_AXI_BASE_ADDR),
.M_ADDR_WIDTH({IF_COUNT{w_32(IF_AXI_ADDR_WIDTH)}}),
.M_CONNECT_READ({IF_COUNT{{2{1'b1}}}}),
.M_CONNECT_WRITE({IF_COUNT{{2{1'b1}}}}),
.M_ISSUE({IF_COUNT{32'd4}}),
.M_SECURE({IF_COUNT{1'b0}})
)
axi_crossbar_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.s_axi_awid( {axi_pcie_dma_awid}),
.s_axi_awaddr( {axi_pcie_dma_awaddr}),
.s_axi_awlen( {axi_pcie_dma_awlen}),
.s_axi_awsize( {axi_pcie_dma_awsize}),
.s_axi_awburst( {axi_pcie_dma_awburst}),
.s_axi_awlock( {axi_pcie_dma_awlock}),
.s_axi_awcache( {axi_pcie_dma_awcache}),
.s_axi_awprot( {axi_pcie_dma_awprot}),
.s_axi_awqos(0),
.s_axi_awuser(0),
.s_axi_awvalid( {axi_pcie_dma_awvalid}),
.s_axi_awready( {axi_pcie_dma_awready}),
.s_axi_wdata( {axi_pcie_dma_wdata}),
.s_axi_wstrb( {axi_pcie_dma_wstrb}),
.s_axi_wlast( {axi_pcie_dma_wlast}),
.s_axi_wuser(0),
.s_axi_wvalid( {axi_pcie_dma_wvalid}),
.s_axi_wready( {axi_pcie_dma_wready}),
.s_axi_bid( {axi_pcie_dma_bid}),
.s_axi_bresp( {axi_pcie_dma_bresp}),
.s_axi_buser(),
.s_axi_bvalid( {axi_pcie_dma_bvalid}),
.s_axi_bready( {axi_pcie_dma_bready}),
.s_axi_arid( {axi_pcie_dma_arid}),
.s_axi_araddr( {axi_pcie_dma_araddr}),
.s_axi_arlen( {axi_pcie_dma_arlen}),
.s_axi_arsize( {axi_pcie_dma_arsize}),
.s_axi_arburst( {axi_pcie_dma_arburst}),
.s_axi_arlock( {axi_pcie_dma_arlock}),
.s_axi_arcache( {axi_pcie_dma_arcache}),
.s_axi_arprot( {axi_pcie_dma_arprot}),
.s_axi_arqos(0),
.s_axi_aruser(0),
.s_axi_arvalid( {axi_pcie_dma_arvalid}),
.s_axi_arready( {axi_pcie_dma_arready}),
.s_axi_rid( {axi_pcie_dma_rid}),
.s_axi_rdata( {axi_pcie_dma_rdata}),
.s_axi_rresp( {axi_pcie_dma_rresp}),
.s_axi_rlast( {axi_pcie_dma_rlast}),
.s_axi_ruser(),
.s_axi_rvalid( {axi_pcie_dma_rvalid}),
.s_axi_rready( {axi_pcie_dma_rready}),
.m_axi_awid( {axi_if_awid}),
.m_axi_awaddr( {axi_if_awaddr}),
.m_axi_awlen( {axi_if_awlen}),
.m_axi_awsize( {axi_if_awsize}),
.m_axi_awburst( {axi_if_awburst}),
.m_axi_awlock( {axi_if_awlock}),
.m_axi_awcache( {axi_if_awcache}),
.m_axi_awprot( {axi_if_awprot}),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid( {axi_if_awvalid}),
.m_axi_awready( {axi_if_awready}),
.m_axi_wdata( {axi_if_wdata}),
.m_axi_wstrb( {axi_if_wstrb}),
.m_axi_wlast( {axi_if_wlast}),
.m_axi_wuser(),
.m_axi_wvalid( {axi_if_wvalid}),
.m_axi_wready( {axi_if_wready}),
.m_axi_bid( {axi_if_bid}),
.m_axi_bresp( {axi_if_bresp}),
.m_axi_buser(0),
.m_axi_bvalid( {axi_if_bvalid}),
.m_axi_bready( {axi_if_bready}),
.m_axi_arid( {axi_if_arid}),
.m_axi_araddr( {axi_if_araddr}),
.m_axi_arlen( {axi_if_arlen}),
.m_axi_arsize( {axi_if_arsize}),
.m_axi_arburst( {axi_if_arburst}),
.m_axi_arlock( {axi_if_arlock}),
.m_axi_arcache( {axi_if_arcache}),
.m_axi_arprot( {axi_if_arprot}),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid( {axi_if_arvalid}),
.m_axi_arready( {axi_if_arready}),
.m_axi_rid( {axi_if_rid}),
.m_axi_rdata( {axi_if_rdata}),
.m_axi_rresp( {axi_if_rresp}),
.m_axi_rlast( {axi_if_rlast}),
.m_axi_ruser(0),
.m_axi_rvalid( {axi_if_rvalid}),
.m_axi_rready( {axi_if_rready})
);
parameter IF_RAM_SEL_WIDTH = $clog2(PORTS_PER_IF+1);
parameter IF_PCIE_DMA_TAG_WIDTH = PCIE_DMA_TAG_WIDTH-$clog2(IF_COUNT);
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_pcie_addr;
wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_read_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_read_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_pcie_addr;
wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_ready;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_pcie_addr;
wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_write_desc_ram_sel;
wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_ram_addr;
wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_write_desc_len;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_status_valid;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_status_tag;
wire [IF_COUNT-1:0] if_pcie_dma_write_desc_status_valid;
pcie_axi_dma_desc_mux #
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_wr_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_BE_WIDTH-1:0] if_dma_ram_wr_cmd_be;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_wr_cmd_addr;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_wr_cmd_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_ready;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_rd_cmd_sel;
wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_rd_cmd_addr;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_ready;
wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_rd_resp_data;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_valid;
wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_ready;
dma_if_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.S_RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.M_RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_read_desc_mux_inst (
dma_if_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* Descriptor output
* Read descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_read_desc_len),
.m_axis_desc_tag(pcie_axi_dma_read_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_read_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_read_desc_ready),
.m_axis_read_desc_dma_addr(pcie_dma_read_desc_pcie_addr),
.m_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
.m_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
.m_axis_read_desc_len(pcie_dma_read_desc_len),
.m_axis_read_desc_tag(pcie_dma_read_desc_tag),
.m_axis_read_desc_valid(pcie_dma_read_desc_valid),
.m_axis_read_desc_ready(pcie_dma_read_desc_ready),
/*
* Descriptor status input
* Read descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_read_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_read_desc_status_valid),
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/*
* Descriptor input
* Read descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_read_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_read_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_read_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_read_desc_ready),
.s_axis_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr),
.s_axis_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr),
.s_axis_read_desc_len(if_pcie_dma_read_desc_len),
.s_axis_read_desc_tag(if_pcie_dma_read_desc_tag),
.s_axis_read_desc_valid(if_pcie_dma_read_desc_valid),
.s_axis_read_desc_ready(if_pcie_dma_read_desc_ready),
/*
* Descriptor status output
* Read descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid)
);
pcie_axi_dma_desc_mux #
(
.PORTS(IF_COUNT),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
.ARB_TYPE("ROUND_ROBIN"),
.LSB_PRIORITY("HIGH")
)
pcie_axi_dma_write_desc_mux_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.m_axis_read_desc_status_tag(if_pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_valid(if_pcie_dma_read_desc_status_valid),
/*
* Descriptor output
* Write descriptor output (to DMA interface)
*/
.m_axis_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr),
.m_axis_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr),
.m_axis_desc_len(pcie_axi_dma_write_desc_len),
.m_axis_desc_tag(pcie_axi_dma_write_desc_tag),
.m_axis_desc_valid(pcie_axi_dma_write_desc_valid),
.m_axis_desc_ready(pcie_axi_dma_write_desc_ready),
.m_axis_write_desc_dma_addr(pcie_dma_write_desc_pcie_addr),
.m_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
.m_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
.m_axis_write_desc_len(pcie_dma_write_desc_len),
.m_axis_write_desc_tag(pcie_dma_write_desc_tag),
.m_axis_write_desc_valid(pcie_dma_write_desc_valid),
.m_axis_write_desc_ready(pcie_dma_write_desc_ready),
/*
* Descriptor status input
* Write descriptor status input (from DMA interface)
*/
.s_axis_desc_status_tag(pcie_axi_dma_write_desc_status_tag),
.s_axis_desc_status_valid(pcie_axi_dma_write_desc_status_valid),
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/*
* Descriptor input
* Write descriptor input
*/
.s_axis_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr),
.s_axis_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr),
.s_axis_desc_len(if_pcie_axi_dma_write_desc_len),
.s_axis_desc_tag(if_pcie_axi_dma_write_desc_tag),
.s_axis_desc_valid(if_pcie_axi_dma_write_desc_valid),
.s_axis_desc_ready(if_pcie_axi_dma_write_desc_ready),
.s_axis_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr),
.s_axis_write_desc_len(if_pcie_dma_write_desc_len),
.s_axis_write_desc_tag(if_pcie_dma_write_desc_tag),
.s_axis_write_desc_valid(if_pcie_dma_write_desc_valid),
.s_axis_write_desc_ready(if_pcie_dma_write_desc_ready),
/*
* Descriptor status output
* Write descriptor status output
*/
.m_axis_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag),
.m_axis_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid)
.m_axis_write_desc_status_tag(if_pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_valid(if_pcie_dma_write_desc_status_valid),
/*
* RAM interface (from DMA interface)
*/
.if_ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.if_ram_wr_cmd_be(dma_ram_wr_cmd_be),
.if_ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.if_ram_wr_cmd_data(dma_ram_wr_cmd_data),
.if_ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.if_ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.if_ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.if_ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.if_ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.if_ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.if_ram_rd_resp_data(dma_ram_rd_resp_data),
.if_ram_rd_resp_valid(dma_ram_rd_resp_valid),
.if_ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* RAM interface
*/
.ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(if_dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(if_dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready),
.ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready),
.ram_rd_resp_data(if_dma_ram_rd_resp_data),
.ram_rd_resp_valid(if_dma_ram_rd_resp_valid),
.ram_rd_resp_ready(if_dma_ram_rd_resp_ready)
);
// PTP clock
@ -1868,11 +1709,6 @@ generate
for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr_int;
assign if_pcie_axi_dma_read_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_read_desc_axi_addr_int | n*24'h800000;
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int;
assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
@ -1897,9 +1733,9 @@ generate
interface #(
.PORTS(PORTS_PER_IF),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1919,8 +1755,6 @@ generate
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),
.QUEUE_LOG_SIZE_WIDTH(4),
.RAM_ADDR_WIDTH(16),
.RAM_SIZE(2**15),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
@ -1928,49 +1762,57 @@ generate
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(IF_AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(IF_AXI_ID_WIDTH),
.AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE)
)
interface_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* PCIe DMA read descriptor output
* DMA read descriptor output
*/
.m_axis_pcie_axi_dma_read_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr_int),
.m_axis_pcie_axi_dma_read_desc_len(if_pcie_axi_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_tag(if_pcie_axi_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_read_desc_valid(if_pcie_axi_dma_read_desc_valid[n]),
.m_axis_pcie_axi_dma_read_desc_ready(if_pcie_axi_dma_read_desc_ready[n]),
.m_axis_dma_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_read_desc_len(if_pcie_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_read_desc_tag(if_pcie_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_read_desc_valid(if_pcie_dma_read_desc_valid[n]),
.m_axis_dma_read_desc_ready(if_pcie_dma_read_desc_ready[n]),
/*
* PCIe DMA read descriptor status input
* DMA read descriptor status input
*/
.s_axis_pcie_axi_dma_read_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_read_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid[n]),
.s_axis_dma_read_desc_status_tag(if_pcie_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_read_desc_status_valid(if_pcie_dma_read_desc_status_valid[n]),
/*
* PCIe DMA write descriptor output
* DMA write descriptor output
*/
.m_axis_pcie_axi_dma_write_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr_int),
.m_axis_pcie_axi_dma_write_desc_len(if_pcie_axi_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_tag(if_pcie_axi_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_pcie_axi_dma_write_desc_valid(if_pcie_axi_dma_write_desc_valid[n]),
.m_axis_pcie_axi_dma_write_desc_ready(if_pcie_axi_dma_write_desc_ready[n]),
.m_axis_dma_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.m_axis_dma_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
.m_axis_dma_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
.m_axis_dma_write_desc_len(if_pcie_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
.m_axis_dma_write_desc_tag(if_pcie_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.m_axis_dma_write_desc_valid(if_pcie_dma_write_desc_valid[n]),
.m_axis_dma_write_desc_ready(if_pcie_dma_write_desc_ready[n]),
/*
* PCIe DMA write descriptor status input
* DMA write descriptor status input
*/
.s_axis_pcie_axi_dma_write_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_pcie_axi_dma_write_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid[n]),
.s_axis_dma_write_desc_status_tag(if_pcie_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_dma_write_desc_status_valid(if_pcie_dma_write_desc_status_valid[n]),
/*
* AXI-Lite slave interface
@ -2019,43 +1861,21 @@ generate
.m_axil_csr_rready(axil_if_csr_rready[n]),
/*
* AXI slave inteface
* RAM interface
*/
.s_axi_awid(axi_if_awid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_awaddr(axi_if_awaddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_awlen(axi_if_awlen[n*8 +: 8]),
.s_axi_awsize(axi_if_awsize[n*3 +: 3]),
.s_axi_awburst(axi_if_awburst[n*2 +: 2]),
.s_axi_awlock(axi_if_awlock[n]),
.s_axi_awcache(axi_if_awcache[n*4 +: 4]),
.s_axi_awprot(axi_if_awprot[n*3 +: 3]),
.s_axi_awvalid(axi_if_awvalid[n]),
.s_axi_awready(axi_if_awready[n]),
.s_axi_wdata(axi_if_wdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_wstrb(axi_if_wstrb[n*AXI_STRB_WIDTH +: AXI_STRB_WIDTH]),
.s_axi_wlast(axi_if_wlast[n]),
.s_axi_wvalid(axi_if_wvalid[n]),
.s_axi_wready(axi_if_wready[n]),
.s_axi_bid(axi_if_bid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_bresp(axi_if_bresp[n*2 +: 2]),
.s_axi_bvalid(axi_if_bvalid[n]),
.s_axi_bready(axi_if_bready[n]),
.s_axi_arid(axi_if_arid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_araddr(axi_if_araddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
.s_axi_arlen(axi_if_arlen[n*8 +: 8]),
.s_axi_arsize(axi_if_arsize[n*3 +: 3]),
.s_axi_arburst(axi_if_arburst[n*2 +: 2]),
.s_axi_arlock(axi_if_arlock[n]),
.s_axi_arcache(axi_if_arcache[n*4 +: 4]),
.s_axi_arprot(axi_if_arprot[n*3 +: 3]),
.s_axi_arvalid(axi_if_arvalid[n]),
.s_axi_arready(axi_if_arready[n]),
.s_axi_rid(axi_if_rid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]),
.s_axi_rdata(axi_if_rdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
.s_axi_rresp(axi_if_rresp[n*2 +: 2]),
.s_axi_rlast(axi_if_rlast[n]),
.s_axi_rvalid(axi_if_rvalid[n]),
.s_axi_rready(axi_if_rready[n]),
.dma_ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_wr_cmd_be(if_dma_ram_wr_cmd_be[SEG_COUNT*SEG_BE_WIDTH*n +: SEG_COUNT*SEG_BE_WIDTH]),
.dma_ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_wr_cmd_data(if_dma_ram_wr_cmd_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
.dma_ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
.dma_ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_data(if_dma_ram_rd_resp_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
.dma_ram_rd_resp_valid(if_dma_ram_rd_resp_valid[SEG_COUNT*n +: SEG_COUNT]),
.dma_ram_rd_resp_ready(if_dma_ram_rd_resp_ready[SEG_COUNT*n +: SEG_COUNT]),
/*
* Transmit data output

25
fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py
View File

@ -78,18 +78,6 @@ srcs.append("../lib/eth/rtl/ptp_clock.v")
srcs.append("../lib/eth/rtl/ptp_clock_cdc.v")
srcs.append("../lib/eth/rtl/ptp_perout.v")
srcs.append("../lib/eth/rtl/ptp_ts_extract.v")
srcs.append("../lib/axi/rtl/axi_crossbar.v")
srcs.append("../lib/axi/rtl/axi_crossbar_addr.v")
srcs.append("../lib/axi/rtl/axi_crossbar_rd.v")
srcs.append("../lib/axi/rtl/axi_crossbar_wr.v")
srcs.append("../lib/axi/rtl/axi_dma.v")
srcs.append("../lib/axi/rtl/axi_dma_rd.v")
srcs.append("../lib/axi/rtl/axi_dma_wr.v")
srcs.append("../lib/axi/rtl/axi_ram.v")
srcs.append("../lib/axi/rtl/axi_ram_rd_if.v")
srcs.append("../lib/axi/rtl/axi_ram_wr_if.v")
srcs.append("../lib/axi/rtl/axi_register_rd.v")
srcs.append("../lib/axi/rtl/axi_register_wr.v")
srcs.append("../lib/axi/rtl/axil_interconnect.v")
srcs.append("../lib/axi/rtl/arbiter.v")
srcs.append("../lib/axi/rtl/priority_encoder.v")
@ -99,11 +87,16 @@ srcs.append("../lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/axis/rtl/axis_register.v")
srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v")
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_rd.v")
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_wr.v")
srcs.append("../lib/pcie/rtl/dma_if_mux.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_rd.v")
srcs.append("../lib/pcie/rtl/dma_if_mux_wr.v")
srcs.append("../lib/pcie/rtl/dma_psdpram.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_sink.v")
srcs.append("../lib/pcie/rtl/dma_client_axis_source.v")
srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")