From 8ff4312601d06683543bce6ac0c4937a79d9111a Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 31 May 2017 18:37:33 -0700 Subject: [PATCH] Update MAC modules to use new modules --- rtl/eth_mac_1g.v | 20 ++++- rtl/eth_mac_1g_fifo.v | 12 +++ tb/test_eth_mac_1g.py | 179 ++++++++++++++++++++++++------------- tb/test_eth_mac_1g.v | 12 +++ tb/test_eth_mac_1g_fifo.py | 176 ++++++++++++++++++++++-------------- tb/test_eth_mac_1g_fifo.v | 12 +++ 6 files changed, 279 insertions(+), 132 deletions(-) diff --git a/rtl/eth_mac_1g.v b/rtl/eth_mac_1g.v index ecd7b1738..b46e31606 100644 --- a/rtl/eth_mac_1g.v +++ b/rtl/eth_mac_1g.v @@ -67,6 +67,14 @@ module eth_mac_1g # output wire gmii_tx_en, output wire gmii_tx_er, + /* + * Control + */ + input wire rx_clk_enable, + input wire tx_clk_enable, + input wire rx_mii_select, + input wire tx_mii_select, + /* * Status */ @@ -79,8 +87,8 @@ module eth_mac_1g # input wire [7:0] ifg_delay ); -eth_mac_1g_rx -eth_mac_1g_rx_inst ( +axis_gmii_rx +axis_gmii_rx_inst ( .clk(rx_clk), .rst(rx_rst), .gmii_rxd(gmii_rxd), @@ -90,15 +98,17 @@ eth_mac_1g_rx_inst ( .output_axis_tvalid(rx_axis_tvalid), .output_axis_tlast(rx_axis_tlast), .output_axis_tuser(rx_axis_tuser), + .clk_enable(rx_clk_enable), + .mii_select(rx_mii_select), .error_bad_frame(rx_error_bad_frame), .error_bad_fcs(rx_error_bad_fcs) ); -eth_mac_1g_tx #( +axis_gmii_tx #( .ENABLE_PADDING(ENABLE_PADDING), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH) ) -eth_mac_1g_tx_inst ( +axis_gmii_tx_inst ( .clk(tx_clk), .rst(tx_rst), .input_axis_tdata(tx_axis_tdata), @@ -109,6 +119,8 @@ eth_mac_1g_tx_inst ( .gmii_txd(gmii_txd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), + .clk_enable(tx_clk_enable), + .mii_select(tx_mii_select), .ifg_delay(ifg_delay) ); diff --git a/rtl/eth_mac_1g_fifo.v b/rtl/eth_mac_1g_fifo.v index 7d137ab30..b06ad34f3 100644 --- a/rtl/eth_mac_1g_fifo.v +++ b/rtl/eth_mac_1g_fifo.v @@ -72,6 +72,14 @@ module eth_mac_1g_fifo # output wire gmii_tx_en, output wire gmii_tx_er, + /* + * Control + */ + input wire rx_clk_enable, + input wire tx_clk_enable, + input wire rx_mii_select, + input wire tx_mii_select, + /* * Status */ @@ -157,6 +165,10 @@ eth_mac_1g_inst ( .gmii_txd(gmii_txd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), + .rx_clk_enable(rx_clk_enable), + .tx_clk_enable(tx_clk_enable), + .rx_mii_select(rx_mii_select), + .tx_mii_select(tx_mii_select), .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), .ifg_delay(ifg_delay) diff --git a/tb/test_eth_mac_1g.py b/tb/test_eth_mac_1g.py index 6f918e260..41050629a 100755 --- a/tb/test_eth_mac_1g.py +++ b/tb/test_eth_mac_1g.py @@ -37,8 +37,8 @@ srcs = [] srcs.append("../rtl/%s.v" % module) srcs.append("../rtl/lfsr.v") -srcs.append("../rtl/eth_mac_1g_rx.v") -srcs.append("../rtl/eth_mac_1g_tx.v") +srcs.append("../rtl/axis_gmii_rx.v") +srcs.append("../rtl/axis_gmii_tx.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) @@ -67,6 +67,10 @@ def bench(): gmii_rxd = Signal(intbv(0)[8:]) gmii_rx_dv = Signal(bool(0)) gmii_rx_er = Signal(bool(0)) + rx_clk_enable = Signal(bool(1)) + tx_clk_enable = Signal(bool(1)) + rx_mii_select = Signal(bool(0)) + tx_mii_select = Signal(bool(0)) ifg_delay = Signal(intbv(0)[8:]) # Outputs @@ -92,6 +96,8 @@ def bench(): txd=gmii_rxd, tx_en=gmii_rx_dv, tx_er=gmii_rx_er, + clk_enable=rx_clk_enable, + mii_select=rx_mii_select, name='gmii_source' ) @@ -103,6 +109,8 @@ def bench(): rxd=gmii_txd, rx_dv=gmii_tx_en, rx_er=gmii_tx_er, + clk_enable=tx_clk_enable, + mii_select=tx_mii_select, name='gmii_sink' ) @@ -166,6 +174,12 @@ def bench(): gmii_tx_en=gmii_tx_en, gmii_tx_er=gmii_tx_er, + rx_clk_enable=rx_clk_enable, + tx_clk_enable=tx_clk_enable, + + rx_mii_select=rx_mii_select, + tx_mii_select=tx_mii_select, + rx_error_bad_frame=rx_error_bad_frame, rx_error_bad_fcs=rx_error_bad_fcs, @@ -178,6 +192,30 @@ def bench(): tx_clk.next = not tx_clk rx_clk.next = not rx_clk + rx_error_bad_frame_asserted = Signal(bool(0)) + rx_error_bad_fcs_asserted = Signal(bool(0)) + + @always(clk.posedge) + def monitor(): + if (rx_error_bad_frame): + rx_error_bad_frame_asserted.next = 1 + if (rx_error_bad_fcs): + rx_error_bad_fcs_asserted.next = 1 + + clk_enable_rate = Signal(int(0)) + clk_enable_div = Signal(int(0)) + + @always(clk.posedge) + def clk_enable_gen(): + if clk_enable_div.next > 0: + rx_clk_enable.next = 0 + tx_clk_enable.next = 0 + clk_enable_div.next = clk_enable_div - 1 + else: + rx_clk_enable.next = 1 + tx_clk_enable.next = 1 + clk_enable_div.next = clk_enable_rate - 1 + @instance def check(): yield delay(100) @@ -197,84 +235,99 @@ def bench(): # testbench stimulus - yield clk.posedge - print("test 1: test rx packet") - current_test.next = 1 + for rate, mii in [(1, 0), (10, 0), (5, 1)]: + clk_enable_rate.next = rate + rx_mii_select.next = mii + tx_mii_select.next = mii - test_frame = eth_ep.EthFrame() - test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 - test_frame.eth_src_mac = 0x5A5152535455 - test_frame.eth_type = 0x8000 - test_frame.payload = bytearray(range(32)) - test_frame.update_fcs() + yield clk.posedge + print("test 1: test rx packet") + current_test.next = 1 - axis_frame = test_frame.build_axis_fcs() + test_frame = eth_ep.EthFrame() + test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame.eth_src_mac = 0x5A5152535455 + test_frame.eth_type = 0x8000 + test_frame.payload = bytearray(range(32)) + test_frame.update_fcs() - gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame)) - yield clk.posedge - yield clk.posedge + axis_frame = test_frame.build_axis_fcs() - while gmii_rx_dv or rx_axis_tvalid: + gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame)) + yield clk.posedge yield clk.posedge - yield clk.posedge - yield clk.posedge - - rx_frame = axis_sink.recv() - - eth_frame = eth_ep.EthFrame() - eth_frame.parse_axis(rx_frame) - eth_frame.update_fcs() - - assert eth_frame == test_frame - - yield delay(100) - - yield clk.posedge - print("test 2: test tx packet") - current_test.next = 2 - - test_frame = eth_ep.EthFrame() - test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 - test_frame.eth_src_mac = 0x5A5152535455 - test_frame.eth_type = 0x8000 - test_frame.payload = bytearray(range(32)) - test_frame.update_fcs() - - axis_frame = test_frame.build_axis() - - axis_source.send(axis_frame) - yield clk.posedge - yield clk.posedge - - while gmii_tx_en or tx_axis_tvalid: + while not rx_clk_enable or not tx_clk_enable or not (gmii_rx_dv or gmii_tx_en): + yield clk.posedge yield clk.posedge - yield clk.posedge - yield clk.posedge + while not rx_clk_enable or not tx_clk_enable or gmii_rx_dv or gmii_tx_en or tx_axis_tvalid or rx_axis_tvalid: + yield clk.posedge - rx_frame = gmii_sink.recv() + yield clk.posedge + yield clk.posedge + yield clk.posedge - assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5') + rx_frame = axis_sink.recv() - eth_frame = eth_ep.EthFrame() - eth_frame.parse_axis_fcs(rx_frame.data[8:]) + eth_frame = eth_ep.EthFrame() + eth_frame.parse_axis(rx_frame) + eth_frame.update_fcs() - print(hex(eth_frame.eth_fcs)) - print(hex(eth_frame.calc_fcs())) + assert eth_frame == test_frame - assert len(eth_frame.payload.data) == 46 - assert eth_frame.eth_fcs == eth_frame.calc_fcs() - assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac - assert eth_frame.eth_src_mac == test_frame.eth_src_mac - assert eth_frame.eth_type == test_frame.eth_type - assert eth_frame.payload.data.index(test_frame.payload.data) == 0 + yield delay(100) - yield delay(100) + yield clk.posedge + print("test 2: test tx packet") + current_test.next = 2 + + test_frame = eth_ep.EthFrame() + test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame.eth_src_mac = 0x5A5152535455 + test_frame.eth_type = 0x8000 + test_frame.payload = bytearray(range(32)) + test_frame.update_fcs() + + axis_frame = test_frame.build_axis() + + axis_source.send(axis_frame) + yield clk.posedge + yield clk.posedge + + while not rx_clk_enable or not tx_clk_enable or not (gmii_rx_dv or gmii_tx_en): + yield clk.posedge + yield clk.posedge + + while not rx_clk_enable or not tx_clk_enable or gmii_rx_dv or gmii_tx_en or tx_axis_tvalid or rx_axis_tvalid: + yield clk.posedge + + yield clk.posedge + yield clk.posedge + yield clk.posedge + + rx_frame = gmii_sink.recv() + + assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5') + + eth_frame = eth_ep.EthFrame() + eth_frame.parse_axis_fcs(rx_frame.data[8:]) + + print(hex(eth_frame.eth_fcs)) + print(hex(eth_frame.calc_fcs())) + + assert len(eth_frame.payload.data) == 46 + assert eth_frame.eth_fcs == eth_frame.calc_fcs() + assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac + assert eth_frame.eth_src_mac == test_frame.eth_src_mac + assert eth_frame.eth_type == test_frame.eth_type + assert eth_frame.payload.data.index(test_frame.payload.data) == 0 + + yield delay(100) raise StopSimulation - return dut, axis_source_logic, axis_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, check + return dut, monitor, axis_source_logic, axis_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, clk_enable_gen, check def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_1g.v b/tb/test_eth_mac_1g.v index 4264110a9..dff830707 100644 --- a/tb/test_eth_mac_1g.v +++ b/tb/test_eth_mac_1g.v @@ -51,6 +51,10 @@ reg tx_axis_tuser = 0; reg [7:0] gmii_rxd = 0; reg gmii_rx_dv = 0; reg gmii_rx_er = 0; +reg rx_clk_enable = 1; +reg tx_clk_enable = 1; +reg rx_mii_select = 0; +reg tx_mii_select = 0; reg [7:0] ifg_delay = 0; // Outputs @@ -82,6 +86,10 @@ initial begin gmii_rxd, gmii_rx_dv, gmii_rx_er, + rx_clk_enable, + tx_clk_enable, + rx_mii_select, + tx_mii_select, ifg_delay ); $to_myhdl( @@ -126,6 +134,10 @@ UUT ( .gmii_txd(gmii_txd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), + .rx_clk_enable(rx_clk_enable), + .tx_clk_enable(tx_clk_enable), + .rx_mii_select(rx_mii_select), + .tx_mii_select(tx_mii_select), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), .ifg_delay(ifg_delay) diff --git a/tb/test_eth_mac_1g_fifo.py b/tb/test_eth_mac_1g_fifo.py index 228f562cf..d9a2e94ac 100755 --- a/tb/test_eth_mac_1g_fifo.py +++ b/tb/test_eth_mac_1g_fifo.py @@ -37,8 +37,8 @@ srcs = [] srcs.append("../rtl/%s.v" % module) srcs.append("../rtl/lfsr.v") -srcs.append("../rtl/eth_mac_1g_rx.v") -srcs.append("../rtl/eth_mac_1g_tx.v") +srcs.append("../rtl/axis_gmii_rx.v") +srcs.append("../rtl/axis_gmii_tx.v") srcs.append("../rtl/eth_mac_1g.v") srcs.append("../lib/axis/rtl/axis_async_frame_fifo.v") srcs.append("%s.v" % testbench) @@ -74,6 +74,10 @@ def bench(): gmii_rxd = Signal(intbv(0)[8:]) gmii_rx_dv = Signal(bool(0)) gmii_rx_er = Signal(bool(0)) + rx_clk_enable = Signal(bool(1)) + tx_clk_enable = Signal(bool(1)) + rx_mii_select = Signal(bool(0)) + tx_mii_select = Signal(bool(0)) ifg_delay = Signal(intbv(0)[8:]) # Outputs @@ -106,6 +110,8 @@ def bench(): txd=gmii_rxd, tx_en=gmii_rx_dv, tx_er=gmii_rx_er, + clk_enable=rx_clk_enable, + mii_select=rx_mii_select, name='gmii_source' ) @@ -117,6 +123,8 @@ def bench(): rxd=gmii_txd, rx_dv=gmii_tx_en, rx_er=gmii_tx_er, + clk_enable=tx_clk_enable, + mii_select=tx_mii_select, name='gmii_sink' ) @@ -185,6 +193,12 @@ def bench(): gmii_tx_en=gmii_tx_en, gmii_tx_er=gmii_tx_er, + rx_clk_enable=rx_clk_enable, + tx_clk_enable=tx_clk_enable, + + rx_mii_select=rx_mii_select, + tx_mii_select=tx_mii_select, + tx_fifo_overflow=tx_fifo_overflow, tx_fifo_bad_frame=tx_fifo_bad_frame, tx_fifo_good_frame=tx_fifo_good_frame, @@ -204,6 +218,30 @@ def bench(): rx_clk.next = not rx_clk logic_clk.next = not logic_clk + rx_error_bad_frame_asserted = Signal(bool(0)) + rx_error_bad_fcs_asserted = Signal(bool(0)) + + @always(clk.posedge) + def monitor(): + if (rx_error_bad_frame): + rx_error_bad_frame_asserted.next = 1 + if (rx_error_bad_fcs): + rx_error_bad_fcs_asserted.next = 1 + + clk_enable_rate = Signal(int(0)) + clk_enable_div = Signal(int(0)) + + @always(clk.posedge) + def clk_enable_gen(): + if clk_enable_div.next > 0: + rx_clk_enable.next = 0 + tx_clk_enable.next = 0 + clk_enable_div.next = clk_enable_div - 1 + else: + rx_clk_enable.next = 1 + tx_clk_enable.next = 1 + clk_enable_div.next = clk_enable_rate - 1 + @instance def check(): yield delay(100) @@ -225,94 +263,102 @@ def bench(): # testbench stimulus - yield clk.posedge - print("test 1: test rx packet") - current_test.next = 1 + for rate, mii in [(1, 0), (10, 0), (5, 1)]: + clk_enable_rate.next = rate + rx_mii_select.next = mii + tx_mii_select.next = mii - test_frame = eth_ep.EthFrame() - test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 - test_frame.eth_src_mac = 0x5A5152535455 - test_frame.eth_type = 0x8000 - test_frame.payload = bytearray(range(32)) - test_frame.update_fcs() + yield clk.posedge + print("test 1: test rx packet") + current_test.next = 1 - axis_frame = test_frame.build_axis_fcs() + test_frame = eth_ep.EthFrame() + test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame.eth_src_mac = 0x5A5152535455 + test_frame.eth_type = 0x8000 + test_frame.payload = bytearray(range(32)) + test_frame.update_fcs() - gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame)) - yield clk.posedge - yield clk.posedge + axis_frame = test_frame.build_axis_fcs() - while gmii_rx_dv: + gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame)) + yield clk.posedge yield clk.posedge - yield delay(100) - - while rx_axis_tvalid: + while not rx_clk_enable or not tx_clk_enable or not (gmii_rx_dv or gmii_tx_en): + yield clk.posedge yield clk.posedge - yield clk.posedge - yield clk.posedge + while not rx_clk_enable or not tx_clk_enable or gmii_rx_dv or gmii_tx_en or tx_axis_tvalid or rx_axis_tvalid: + yield clk.posedge - rx_frame = axis_sink.recv() + yield delay(100) - eth_frame = eth_ep.EthFrame() - eth_frame.parse_axis(rx_frame) - eth_frame.update_fcs() + while rx_axis_tvalid: + yield clk.posedge - assert eth_frame == test_frame - - yield delay(100) - - yield clk.posedge - print("test 2: test tx packet") - current_test.next = 2 - - test_frame = eth_ep.EthFrame() - test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 - test_frame.eth_src_mac = 0x5A5152535455 - test_frame.eth_type = 0x8000 - test_frame.payload = bytearray(range(32)) - test_frame.update_fcs() - - axis_frame = test_frame.build_axis() - - axis_source.send(axis_frame) - yield clk.posedge - yield clk.posedge - - while tx_axis_tvalid: + yield clk.posedge yield clk.posedge - yield delay(100) + rx_frame = axis_sink.recv() - while gmii_tx_en: + eth_frame = eth_ep.EthFrame() + eth_frame.parse_axis(rx_frame) + eth_frame.update_fcs() + + assert eth_frame == test_frame + + yield delay(100) + + yield clk.posedge + print("test 2: test tx packet") + current_test.next = 2 + + test_frame = eth_ep.EthFrame() + test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame.eth_src_mac = 0x5A5152535455 + test_frame.eth_type = 0x8000 + test_frame.payload = bytearray(range(32)) + test_frame.update_fcs() + + axis_frame = test_frame.build_axis() + + axis_source.send(axis_frame) + yield clk.posedge yield clk.posedge - yield clk.posedge - yield clk.posedge + while not rx_clk_enable or not tx_clk_enable or not (gmii_rx_dv or gmii_tx_en): + yield clk.posedge + yield clk.posedge - rx_frame = gmii_sink.recv() + while not rx_clk_enable or not tx_clk_enable or gmii_rx_dv or gmii_tx_en or tx_axis_tvalid or rx_axis_tvalid: + yield clk.posedge - assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5') + yield clk.posedge + yield clk.posedge - eth_frame = eth_ep.EthFrame() - eth_frame.parse_axis_fcs(rx_frame.data[8:]) + rx_frame = gmii_sink.recv() - print(hex(eth_frame.eth_fcs)) - print(hex(eth_frame.calc_fcs())) + assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5') - assert len(eth_frame.payload.data) == 46 - assert eth_frame.eth_fcs == eth_frame.calc_fcs() - assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac - assert eth_frame.eth_src_mac == test_frame.eth_src_mac - assert eth_frame.eth_type == test_frame.eth_type - assert eth_frame.payload.data.index(test_frame.payload.data) == 0 + eth_frame = eth_ep.EthFrame() + eth_frame.parse_axis_fcs(rx_frame.data[8:]) - yield delay(100) + print(hex(eth_frame.eth_fcs)) + print(hex(eth_frame.calc_fcs())) + + assert len(eth_frame.payload.data) == 46 + assert eth_frame.eth_fcs == eth_frame.calc_fcs() + assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac + assert eth_frame.eth_src_mac == test_frame.eth_src_mac + assert eth_frame.eth_type == test_frame.eth_type + assert eth_frame.payload.data.index(test_frame.payload.data) == 0 + + yield delay(100) raise StopSimulation - return dut, axis_source_logic, axis_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, check + return dut, monitor, axis_source_logic, axis_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, clk_enable_gen, check def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_1g_fifo.v b/tb/test_eth_mac_1g_fifo.v index 9887daaa8..e835388a4 100644 --- a/tb/test_eth_mac_1g_fifo.v +++ b/tb/test_eth_mac_1g_fifo.v @@ -56,6 +56,10 @@ reg rx_axis_tready = 0; reg [7:0] gmii_rxd = 0; reg gmii_rx_dv = 0; reg gmii_rx_er = 0; +reg rx_clk_enable = 1; +reg tx_clk_enable = 1; +reg rx_mii_select = 0; +reg tx_mii_select = 0; reg [7:0] ifg_delay = 0; // Outputs @@ -96,6 +100,10 @@ initial begin gmii_rxd, gmii_rx_dv, gmii_rx_er, + rx_clk_enable, + tx_clk_enable, + rx_mii_select, + tx_mii_select, ifg_delay ); $to_myhdl( @@ -151,6 +159,10 @@ UUT ( .gmii_txd(gmii_txd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), + .rx_clk_enable(rx_clk_enable), + .tx_clk_enable(tx_clk_enable), + .rx_mii_select(rx_mii_select), + .tx_mii_select(tx_mii_select), .tx_fifo_overflow(tx_fifo_overflow), .tx_fifo_bad_frame(tx_fifo_bad_frame), .tx_fifo_good_frame(tx_fifo_good_frame),