Update MAC modules to use new modules

rtl/eth_mac_1g.v

@@ -67,6 +67,14 @@ module eth_mac_1g #
     output wire        gmii_tx_en,
     output wire        gmii_tx_er,
 
+    /*
+     * Control
+     */
+    input  wire        rx_clk_enable,
+    input  wire        tx_clk_enable,
+    input  wire        rx_mii_select,
+    input  wire        tx_mii_select,
+
     /*
      * Status
      */
@@ -79,8 +87,8 @@ module eth_mac_1g #
     input  wire [7:0]  ifg_delay
 );
 
-eth_mac_1g_rx
+axis_gmii_rx
-eth_mac_1g_rx_inst (
+axis_gmii_rx_inst (
     .clk(rx_clk),
     .rst(rx_rst),
     .gmii_rxd(gmii_rxd),
@@ -90,15 +98,17 @@ eth_mac_1g_rx_inst (
     .output_axis_tvalid(rx_axis_tvalid),
     .output_axis_tlast(rx_axis_tlast),
     .output_axis_tuser(rx_axis_tuser),
+    .clk_enable(rx_clk_enable),
+    .mii_select(rx_mii_select),
     .error_bad_frame(rx_error_bad_frame),
     .error_bad_fcs(rx_error_bad_fcs)
 );
 
-eth_mac_1g_tx #(
+axis_gmii_tx #(
     .ENABLE_PADDING(ENABLE_PADDING),
     .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
 )
-eth_mac_1g_tx_inst (
+axis_gmii_tx_inst (
     .clk(tx_clk),
     .rst(tx_rst),
     .input_axis_tdata(tx_axis_tdata),
@@ -109,6 +119,8 @@ eth_mac_1g_tx_inst (
     .gmii_txd(gmii_txd),
     .gmii_tx_en(gmii_tx_en),
     .gmii_tx_er(gmii_tx_er),
+    .clk_enable(tx_clk_enable),
+    .mii_select(tx_mii_select),
     .ifg_delay(ifg_delay)
 );
 

rtl/eth_mac_1g_fifo.v

@@ -72,6 +72,14 @@ module eth_mac_1g_fifo #
     output wire        gmii_tx_en,
     output wire        gmii_tx_er,
 
+    /*
+     * Control
+     */
+    input  wire        rx_clk_enable,
+    input  wire        tx_clk_enable,
+    input  wire        rx_mii_select,
+    input  wire        tx_mii_select,
+
     /*
      * Status
      */
@@ -157,6 +165,10 @@ eth_mac_1g_inst (
     .gmii_txd(gmii_txd),
     .gmii_tx_en(gmii_tx_en),
     .gmii_tx_er(gmii_tx_er),
+    .rx_clk_enable(rx_clk_enable),
+    .tx_clk_enable(tx_clk_enable),
+    .rx_mii_select(rx_mii_select),
+    .tx_mii_select(tx_mii_select),
     .rx_error_bad_frame(rx_error_bad_frame_int),
     .rx_error_bad_fcs(rx_error_bad_fcs_int),
     .ifg_delay(ifg_delay)

tb/test_eth_mac_1g.py

@@ -37,8 +37,8 @@ srcs = []
 
 srcs.append("../rtl/%s.v" % module)
 srcs.append("../rtl/lfsr.v")
-srcs.append("../rtl/eth_mac_1g_rx.v")
+srcs.append("../rtl/axis_gmii_rx.v")
-srcs.append("../rtl/eth_mac_1g_tx.v")
+srcs.append("../rtl/axis_gmii_tx.v")
 srcs.append("%s.v" % testbench)
 
 src = ' '.join(srcs)
@@ -67,6 +67,10 @@ def bench():
     gmii_rxd = Signal(intbv(0)[8:])
     gmii_rx_dv = Signal(bool(0))
     gmii_rx_er = Signal(bool(0))
+    rx_clk_enable = Signal(bool(1))
+    tx_clk_enable = Signal(bool(1))
+    rx_mii_select = Signal(bool(0))
+    tx_mii_select = Signal(bool(0))
     ifg_delay = Signal(intbv(0)[8:])
 
     # Outputs
@@ -92,6 +96,8 @@ def bench():
         txd=gmii_rxd,
         tx_en=gmii_rx_dv,
         tx_er=gmii_rx_er,
+        clk_enable=rx_clk_enable,
+        mii_select=rx_mii_select,
         name='gmii_source'
     )
 
@@ -103,6 +109,8 @@ def bench():
         rxd=gmii_txd,
         rx_dv=gmii_tx_en,
         rx_er=gmii_tx_er,
+        clk_enable=tx_clk_enable,
+        mii_select=tx_mii_select,
         name='gmii_sink'
     )
 
@@ -166,6 +174,12 @@ def bench():
         gmii_tx_en=gmii_tx_en,
         gmii_tx_er=gmii_tx_er,
 
+        rx_clk_enable=rx_clk_enable,
+        tx_clk_enable=tx_clk_enable,
+
+        rx_mii_select=rx_mii_select,
+        tx_mii_select=tx_mii_select,
+
         rx_error_bad_frame=rx_error_bad_frame,
         rx_error_bad_fcs=rx_error_bad_fcs,
 
@@ -178,6 +192,30 @@ def bench():
         tx_clk.next = not tx_clk
         rx_clk.next = not rx_clk
 
+    rx_error_bad_frame_asserted = Signal(bool(0))
+    rx_error_bad_fcs_asserted = Signal(bool(0))
+
+    @always(clk.posedge)
+    def monitor():
+        if (rx_error_bad_frame):
+            rx_error_bad_frame_asserted.next = 1
+        if (rx_error_bad_fcs):
+            rx_error_bad_fcs_asserted.next = 1
+
+    clk_enable_rate = Signal(int(0))
+    clk_enable_div = Signal(int(0))
+
+    @always(clk.posedge)
+    def clk_enable_gen():
+        if clk_enable_div.next > 0:
+            rx_clk_enable.next = 0
+            tx_clk_enable.next = 0
+            clk_enable_div.next = clk_enable_div - 1
+        else:
+            rx_clk_enable.next = 1
+            tx_clk_enable.next = 1
+            clk_enable_div.next = clk_enable_rate - 1
+
     @instance
     def check():
         yield delay(100)
@@ -197,6 +235,11 @@ def bench():
 
         # testbench stimulus
 
+        for rate, mii in [(1, 0), (10, 0), (5, 1)]:
+            clk_enable_rate.next = rate
+            rx_mii_select.next = mii
+            tx_mii_select.next = mii
+
             yield clk.posedge
             print("test 1: test rx packet")
             current_test.next = 1
@@ -214,9 +257,14 @@ def bench():
             yield clk.posedge
             yield clk.posedge
 
-        while gmii_rx_dv or rx_axis_tvalid:
+            while not rx_clk_enable or not tx_clk_enable or not (gmii_rx_dv or gmii_tx_en):
+                yield clk.posedge
             yield clk.posedge
 
+            while not rx_clk_enable or not tx_clk_enable or gmii_rx_dv or gmii_tx_en or tx_axis_tvalid or rx_axis_tvalid:
+                yield clk.posedge
+
+            yield clk.posedge
             yield clk.posedge
             yield clk.posedge
 
@@ -247,9 +295,14 @@ def bench():
             yield clk.posedge
             yield clk.posedge
 
-        while gmii_tx_en or tx_axis_tvalid:
+            while not rx_clk_enable or not tx_clk_enable or not (gmii_rx_dv or gmii_tx_en):
+                yield clk.posedge
             yield clk.posedge
 
+            while not rx_clk_enable or not tx_clk_enable or gmii_rx_dv or gmii_tx_en or tx_axis_tvalid or rx_axis_tvalid:
+                yield clk.posedge
+
+            yield clk.posedge
             yield clk.posedge
             yield clk.posedge
 
@@ -274,7 +327,7 @@ def bench():
 
         raise StopSimulation
 
-    return dut, axis_source_logic, axis_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, check
+    return dut, monitor, axis_source_logic, axis_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, clk_enable_gen, check
 
 def test_bench():
     sim = Simulation(bench())

tb/test_eth_mac_1g.v

@@ -51,6 +51,10 @@ reg tx_axis_tuser = 0;
 reg [7:0] gmii_rxd = 0;
 reg gmii_rx_dv = 0;
 reg gmii_rx_er = 0;
+reg rx_clk_enable = 1;
+reg tx_clk_enable = 1;
+reg rx_mii_select = 0;
+reg tx_mii_select = 0;
 reg [7:0] ifg_delay = 0;
 
 // Outputs
@@ -82,6 +86,10 @@ initial begin
         gmii_rxd,
         gmii_rx_dv,
         gmii_rx_er,
+        rx_clk_enable,
+        tx_clk_enable,
+        rx_mii_select,
+        tx_mii_select,
         ifg_delay
     );
     $to_myhdl(
@@ -126,6 +134,10 @@ UUT (
     .gmii_txd(gmii_txd),
     .gmii_tx_en(gmii_tx_en),
     .gmii_tx_er(gmii_tx_er),
+    .rx_clk_enable(rx_clk_enable),
+    .tx_clk_enable(tx_clk_enable),
+    .rx_mii_select(rx_mii_select),
+    .tx_mii_select(tx_mii_select),
     .rx_error_bad_frame(rx_error_bad_frame),
     .rx_error_bad_fcs(rx_error_bad_fcs),
     .ifg_delay(ifg_delay)

tb/test_eth_mac_1g_fifo.py

@@ -37,8 +37,8 @@ srcs = []
 
 srcs.append("../rtl/%s.v" % module)
 srcs.append("../rtl/lfsr.v")
-srcs.append("../rtl/eth_mac_1g_rx.v")
+srcs.append("../rtl/axis_gmii_rx.v")
-srcs.append("../rtl/eth_mac_1g_tx.v")
+srcs.append("../rtl/axis_gmii_tx.v")
 srcs.append("../rtl/eth_mac_1g.v")
 srcs.append("../lib/axis/rtl/axis_async_frame_fifo.v")
 srcs.append("%s.v" % testbench)
@@ -74,6 +74,10 @@ def bench():
     gmii_rxd = Signal(intbv(0)[8:])
     gmii_rx_dv = Signal(bool(0))
     gmii_rx_er = Signal(bool(0))
+    rx_clk_enable = Signal(bool(1))
+    tx_clk_enable = Signal(bool(1))
+    rx_mii_select = Signal(bool(0))
+    tx_mii_select = Signal(bool(0))
     ifg_delay = Signal(intbv(0)[8:])
 
     # Outputs
@@ -106,6 +110,8 @@ def bench():
         txd=gmii_rxd,
         tx_en=gmii_rx_dv,
         tx_er=gmii_rx_er,
+        clk_enable=rx_clk_enable,
+        mii_select=rx_mii_select,
         name='gmii_source'
     )
 
@@ -117,6 +123,8 @@ def bench():
         rxd=gmii_txd,
         rx_dv=gmii_tx_en,
         rx_er=gmii_tx_er,
+        clk_enable=tx_clk_enable,
+        mii_select=tx_mii_select,
         name='gmii_sink'
     )
 
@@ -185,6 +193,12 @@ def bench():
         gmii_tx_en=gmii_tx_en,
         gmii_tx_er=gmii_tx_er,
 
+        rx_clk_enable=rx_clk_enable,
+        tx_clk_enable=tx_clk_enable,
+
+        rx_mii_select=rx_mii_select,
+        tx_mii_select=tx_mii_select,
+
         tx_fifo_overflow=tx_fifo_overflow,
         tx_fifo_bad_frame=tx_fifo_bad_frame,
         tx_fifo_good_frame=tx_fifo_good_frame,
@@ -204,6 +218,30 @@ def bench():
         rx_clk.next = not rx_clk
         logic_clk.next = not logic_clk
 
+    rx_error_bad_frame_asserted = Signal(bool(0))
+    rx_error_bad_fcs_asserted = Signal(bool(0))
+
+    @always(clk.posedge)
+    def monitor():
+        if (rx_error_bad_frame):
+            rx_error_bad_frame_asserted.next = 1
+        if (rx_error_bad_fcs):
+            rx_error_bad_fcs_asserted.next = 1
+
+    clk_enable_rate = Signal(int(0))
+    clk_enable_div = Signal(int(0))
+
+    @always(clk.posedge)
+    def clk_enable_gen():
+        if clk_enable_div.next > 0:
+            rx_clk_enable.next = 0
+            tx_clk_enable.next = 0
+            clk_enable_div.next = clk_enable_div - 1
+        else:
+            rx_clk_enable.next = 1
+            tx_clk_enable.next = 1
+            clk_enable_div.next = clk_enable_rate - 1
+
     @instance
     def check():
         yield delay(100)
@@ -225,6 +263,11 @@ def bench():
 
         # testbench stimulus
 
+        for rate, mii in [(1, 0), (10, 0), (5, 1)]:
+            clk_enable_rate.next = rate
+            rx_mii_select.next = mii
+            tx_mii_select.next = mii
+
             yield clk.posedge
             print("test 1: test rx packet")
             current_test.next = 1
@@ -242,7 +285,11 @@ def bench():
             yield clk.posedge
             yield clk.posedge
 
-        while gmii_rx_dv:
+            while not rx_clk_enable or not tx_clk_enable or not (gmii_rx_dv or gmii_tx_en):
+                yield clk.posedge
+            yield clk.posedge
+
+            while not rx_clk_enable or not tx_clk_enable or gmii_rx_dv or gmii_tx_en or tx_axis_tvalid or rx_axis_tvalid:
                 yield clk.posedge
 
             yield delay(100)
@@ -280,12 +327,11 @@ def bench():
             yield clk.posedge
             yield clk.posedge
 
-        while tx_axis_tvalid:
+            while not rx_clk_enable or not tx_clk_enable or not (gmii_rx_dv or gmii_tx_en):
+                yield clk.posedge
             yield clk.posedge
 
-        yield delay(100)
+            while not rx_clk_enable or not tx_clk_enable or gmii_rx_dv or gmii_tx_en or tx_axis_tvalid or rx_axis_tvalid:
-
-        while gmii_tx_en:
                 yield clk.posedge
 
             yield clk.posedge
@@ -312,7 +358,7 @@ def bench():
 
         raise StopSimulation
 
-    return dut, axis_source_logic, axis_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, check
+    return dut, monitor, axis_source_logic, axis_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, clk_enable_gen, check
 
 def test_bench():
     sim = Simulation(bench())

tb/test_eth_mac_1g_fifo.v

@@ -56,6 +56,10 @@ reg rx_axis_tready = 0;
 reg [7:0] gmii_rxd = 0;
 reg gmii_rx_dv = 0;
 reg gmii_rx_er = 0;
+reg rx_clk_enable = 1;
+reg tx_clk_enable = 1;
+reg rx_mii_select = 0;
+reg tx_mii_select = 0;
 reg [7:0] ifg_delay = 0;
 
 // Outputs
@@ -96,6 +100,10 @@ initial begin
         gmii_rxd,
         gmii_rx_dv,
         gmii_rx_er,
+        rx_clk_enable,
+        tx_clk_enable,
+        rx_mii_select,
+        tx_mii_select,
         ifg_delay
     );
     $to_myhdl(
@@ -151,6 +159,10 @@ UUT (
     .gmii_txd(gmii_txd),
     .gmii_tx_en(gmii_tx_en),
     .gmii_tx_er(gmii_tx_er),
+    .rx_clk_enable(rx_clk_enable),
+    .tx_clk_enable(tx_clk_enable),
+    .rx_mii_select(rx_mii_select),
+    .tx_mii_select(tx_mii_select),
     .tx_fifo_overflow(tx_fifo_overflow),
     .tx_fifo_bad_frame(tx_fifo_bad_frame),
     .tx_fifo_good_frame(tx_fifo_good_frame),