Add default_nettype none and resetall directives

example/ADM_PCIE_9V3/fpga_axi/rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -363,3 +365,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_axi/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -262,3 +264,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_axi/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_axi/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -414,3 +416,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_axi/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -1120,3 +1122,5 @@ pcie_us_msi_inst (
 );
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_axi/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -50,3 +52,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_axi/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/AU200/fpga_axi/rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -363,3 +365,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/AU200/fpga_axi/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -262,3 +264,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

example/AU200/fpga_axi/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/AU200/fpga_axi/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -422,3 +424,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/AU200/fpga_axi/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -1117,3 +1119,5 @@ pcie_us_msi_inst (
 );
 
 endmodule
+
+`resetall

example/AU200/fpga_axi/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -50,3 +52,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/AU200/fpga_axi/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/AU250/fpga_axi/rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -363,3 +365,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/AU250/fpga_axi/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -262,3 +264,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

example/AU250/fpga_axi/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/AU250/fpga_axi/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -422,3 +424,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/AU250/fpga_axi/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -1117,3 +1119,5 @@ pcie_us_msi_inst (
 );
 
 endmodule
+
+`resetall

example/AU250/fpga_axi/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -50,3 +52,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/AU250/fpga_axi/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/AU280/fpga_axi/rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -363,3 +365,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/AU280/fpga_axi/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -262,3 +264,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

example/AU280/fpga_axi/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -401,3 +403,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/AU280/fpga_axi/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -1109,3 +1111,5 @@ pcie_us_msi_inst (
 );
 
 endmodule
+
+`resetall

example/AU280/fpga_axi/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -50,3 +52,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/AU280/fpga_axi/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/AU50/fpga_axi/rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -363,3 +365,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/AU50/fpga_axi/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -262,3 +264,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

example/AU50/fpga_axi/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -410,3 +412,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/AU50/fpga_axi/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -1120,3 +1122,5 @@ pcie_us_msi_inst (
 );
 
 endmodule
+
+`resetall

example/AU50/fpga_axi/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -50,3 +52,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/AU50/fpga_axi/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ExaNIC_X10/fpga_axi/rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -363,3 +365,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ExaNIC_X10/fpga_axi/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -262,3 +264,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

example/ExaNIC_X10/fpga_axi/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ExaNIC_X10/fpga_axi/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -409,3 +411,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/ExaNIC_X10/fpga_axi/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -1122,3 +1124,5 @@ pcie_us_msi_inst (
 );
 
 endmodule
+
+`resetall

example/ExaNIC_X10/fpga_axi/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -50,3 +52,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ExaNIC_X10/fpga_axi/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ExaNIC_X25/fpga_axi/rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -363,3 +365,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ExaNIC_X25/fpga_axi/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -262,3 +264,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

example/ExaNIC_X25/fpga_axi/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ExaNIC_X25/fpga_axi/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -408,3 +410,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/ExaNIC_X25/fpga_axi/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -1120,3 +1122,5 @@ pcie_us_msi_inst (
 );
 
 endmodule
+
+`resetall

example/ExaNIC_X25/fpga_axi/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -50,3 +52,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ExaNIC_X25/fpga_axi/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/VCU108/fpga_axi/rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -363,3 +365,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/VCU108/fpga_axi/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -262,3 +264,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

example/VCU108/fpga_axi/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/VCU108/fpga_axi/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -439,3 +441,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/VCU108/fpga_axi/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -1112,3 +1114,5 @@ pcie_us_msi_inst (
 );
 
 endmodule
+
+`resetall

example/VCU108/fpga_axi/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -50,3 +52,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/VCU108/fpga_axi/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/VCU118/fpga_axi/rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -363,3 +365,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/VCU118/fpga_axi/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -262,3 +264,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

example/VCU118/fpga_axi/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/VCU118/fpga_axi/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -453,3 +455,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/VCU118/fpga_axi/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -1122,3 +1124,5 @@ pcie_us_msi_inst (
 );
 
 endmodule
+
+`resetall

example/VCU118/fpga_axi/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -50,3 +52,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/VCU118/fpga_axi/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/VCU1525/fpga_axi/rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -363,3 +365,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/VCU1525/fpga_axi/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -262,3 +264,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

example/VCU1525/fpga_axi/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/VCU1525/fpga_axi/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -422,3 +424,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/VCU1525/fpga_axi/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -1117,3 +1119,5 @@ pcie_us_msi_inst (
 );
 
 endmodule
+
+`resetall

example/VCU1525/fpga_axi/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -50,3 +52,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/VCU1525/fpga_axi/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ZCU106/fpga_axi/rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -363,3 +365,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ZCU106/fpga_axi/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -262,3 +264,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

example/ZCU106/fpga_axi/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ZCU106/fpga_axi/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -444,3 +446,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/ZCU106/fpga_axi/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -1122,3 +1124,5 @@ pcie_us_msi_inst (
 );
 
 endmodule
+
+`resetall

example/ZCU106/fpga_axi/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -50,3 +52,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ZCU106/fpga_axi/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/fb2CG/fpga_axi/rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -363,3 +365,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/fb2CG/fpga_axi/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -262,3 +264,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

example/fb2CG/fpga_axi/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -449,3 +451,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/fb2CG/fpga_axi/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -1122,3 +1124,5 @@ pcie_us_msi_inst (
 );
 
 endmodule
+
+`resetall

example/fb2CG/fpga_axi/rtl/led_sreg_driver.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * LED shift register driver
@@ -133,3 +135,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/fb2CG/fpga_axi/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -50,3 +52,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/fb2CG/fpga_axi/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/arbiter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Arbiter module
@@ -153,3 +155,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axis_arb_mux.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream arbitrated multiplexer
@@ -248,3 +250,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/dma_client_axis_sink.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI stream sink DMA client
@@ -629,3 +631,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

rtl/dma_client_axis_source.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI stream source DMA client
@@ -562,3 +564,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/dma_if_axi.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI DMA interface
@@ -324,3 +326,5 @@ dma_if_axi_wr_inst (
 );
 
 endmodule
+
+`resetall

rtl/dma_if_axi_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI DMA read interface
@@ -853,3 +855,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

rtl/dma_if_axi_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI DMA write interface
@@ -966,3 +968,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/dma_if_desc_mux.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * DMA interface descriptor mux
@@ -299,3 +301,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/dma_if_mux.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * DMA interface mux
@@ -334,3 +336,5 @@ dma_if_mux_wr_inst (
 );
 
 endmodule
+
+`resetall

rtl/dma_if_mux_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * DMA interface mux (read)
@@ -216,3 +218,5 @@ dma_ram_demux_inst (
 );
 
 endmodule
+
+`resetall

rtl/dma_if_mux_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * DMA interface mux (write)
@@ -215,3 +217,5 @@ dma_ram_demux_inst (
 );
 
 endmodule
+
+`resetall

rtl/dma_if_pcie.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * PCIe DMA interface
@@ -476,3 +478,5 @@ dma_if_pcie_wr_inst (
 );
 
 endmodule
+
+`resetall

rtl/dma_if_pcie_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * PCIe DMA read interface
@@ -1606,3 +1608,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

rtl/dma_if_pcie_us.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Ultrascale PCIe DMA interface
@@ -406,3 +408,5 @@ dma_if_pcie_us_wr_inst (
 );
 
 endmodule
+
+`resetall

rtl/dma_if_pcie_us_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Ultrascale PCIe DMA read interface
@@ -1827,3 +1829,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

rtl/dma_if_pcie_us_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Ultrascale PCIe DMA write interface
@@ -1390,3 +1392,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/dma_if_pcie_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * PCIe DMA write interface
@@ -1125,3 +1127,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/dma_psdpram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * DMA parallel simple dual port RAM
@@ -158,3 +160,5 @@ generate
 endgenerate
 
 endmodule
+
+`resetall