From 20c542051d3112034deb81a02b646e791db03ad5 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 22 Aug 2023 17:14:52 -0700 Subject: [PATCH 01/19] Use cfg prefix for configuration signals Signed-off-by: Alex Forencich --- example/520N_MX/fpga_10g/rtl/fpga_core.v | 2 +- example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 2 +- example/ATLYS/fpga/rtl/fpga_core.v | 2 +- example/AU200/fpga_25g/rtl/fpga_core.v | 2 +- example/AU250/fpga_25g/rtl/fpga_core.v | 2 +- example/AU280/fpga_25g/rtl/fpga_core.v | 2 +- example/AU50/fpga_25g/rtl/fpga_core.v | 2 +- example/Arty/fpga/rtl/fpga_core.v | 2 +- example/C10LP/fpga/rtl/fpga_core.v | 2 +- example/DE2-115/fpga/rtl/fpga_core.v | 2 +- example/DE5-Net/fpga/rtl/fpga_core.v | 2 +- example/ExaNIC_X10/fpga/rtl/fpga_core.v | 2 +- example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v | 2 +- example/HTG640/fpga/rtl/fpga_core.v | 2 +- example/HTG640/fpga_cxpt16/rtl/fpga_core.v | 2 +- example/HTG9200/fpga_25g/rtl/fpga_core.v | 2 +- .../HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v | 2 +- example/KC705/fpga_gmii/rtl/fpga_core.v | 2 +- example/KC705/fpga_rgmii/rtl/fpga_core.v | 2 +- example/KC705/fpga_sgmii/rtl/fpga_core.v | 2 +- example/ML605/fpga_gmii/rtl/fpga_core.v | 2 +- example/ML605/fpga_rgmii/rtl/fpga_core.v | 2 +- example/ML605/fpga_sgmii/rtl/fpga_core.v | 2 +- example/NetFPGA_SUME/fpga/rtl/fpga_core.v | 2 +- example/NexysVideo/fpga/rtl/fpga_core.v | 2 +- example/RV901T/fpga/rtl/fpga_core.v | 2 +- example/S10MX_DK/fpga_10g/rtl/fpga_core.v | 2 +- example/VCU108/fpga_10g/rtl/fpga_core.v | 4 ++-- example/VCU108/fpga_1g/rtl/fpga_core.v | 2 +- example/VCU118/fpga_1g/rtl/fpga_core.v | 2 +- example/VCU118/fpga_25g/rtl/fpga_core.v | 4 ++-- .../VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v | 4 ++-- example/VCU1525/fpga_25g/rtl/fpga_core.v | 2 +- example/ZCU102/fpga/rtl/fpga_core.v | 2 +- example/ZCU106/fpga/rtl/fpga_core.v | 2 +- example/fb2CG/fpga_25g/rtl/fpga_core.v | 2 +- rtl/axis_baser_tx_64.v | 4 ++-- rtl/axis_gmii_tx.v | 6 +++--- rtl/axis_xgmii_tx_32.v | 4 ++-- rtl/axis_xgmii_tx_64.v | 4 ++-- rtl/eth_mac_10g.v | 6 +++--- rtl/eth_mac_10g_fifo.v | 4 ++-- rtl/eth_mac_1g.v | 4 ++-- rtl/eth_mac_1g_fifo.v | 4 ++-- rtl/eth_mac_1g_gmii.v | 4 ++-- rtl/eth_mac_1g_gmii_fifo.v | 4 ++-- rtl/eth_mac_1g_rgmii.v | 4 ++-- rtl/eth_mac_1g_rgmii_fifo.v | 4 ++-- rtl/eth_mac_mii.v | 4 ++-- rtl/eth_mac_mii_fifo.v | 4 ++-- rtl/eth_mac_phy_10g.v | 12 ++++++------ rtl/eth_mac_phy_10g_fifo.v | 12 ++++++------ rtl/eth_mac_phy_10g_rx.v | 4 ++-- rtl/eth_mac_phy_10g_tx.v | 8 ++++---- rtl/eth_phy_10g.v | 8 ++++---- rtl/eth_phy_10g_rx.v | 4 ++-- rtl/eth_phy_10g_rx_if.v | 8 ++++---- rtl/eth_phy_10g_tx.v | 4 ++-- rtl/eth_phy_10g_tx_if.v | 4 ++-- tb/axis_baser_tx_64/test_axis_baser_tx_64.py | 6 +++--- tb/axis_gmii_tx/test_axis_gmii_tx.py | 4 ++-- tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py | 6 +++--- tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py | 6 +++--- tb/eth_mac_10g/test_eth_mac_10g.py | 12 ++++++------ tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py | 8 +++++--- tb/eth_mac_1g/test_eth_mac_1g.py | 10 +++++----- tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py | 6 +++--- tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py | 6 +++--- tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py | 6 +++--- tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py | 6 +++--- .../test_eth_mac_1g_rgmii_fifo.py | 6 +++--- tb/eth_mac_mii/test_eth_mac_mii.py | 6 +++--- tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py | 6 +++--- tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py | 11 ++++++----- tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py | 11 ++++++----- tb/eth_phy_10g/test_eth_phy_10g.py | 4 ++-- 76 files changed, 163 insertions(+), 159 deletions(-) diff --git a/example/520N_MX/fpga_10g/rtl/fpga_core.v b/example/520N_MX/fpga_10g/rtl/fpga_core.v index edaf3e722..7011d5470 100644 --- a/example/520N_MX/fpga_10g/rtl/fpga_core.v +++ b/example/520N_MX/fpga_10g/rtl/fpga_core.v @@ -497,7 +497,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 670416bba..5cacb65cc 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -419,7 +419,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/ATLYS/fpga/rtl/fpga_core.v b/example/ATLYS/fpga/rtl/fpga_core.v index a20960129..5ef8fa732 100644 --- a/example/ATLYS/fpga/rtl/fpga_core.v +++ b/example/ATLYS/fpga/rtl/fpga_core.v @@ -356,7 +356,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/AU200/fpga_25g/rtl/fpga_core.v b/example/AU200/fpga_25g/rtl/fpga_core.v index c8c2c444c..916766566 100644 --- a/example/AU200/fpga_25g/rtl/fpga_core.v +++ b/example/AU200/fpga_25g/rtl/fpga_core.v @@ -422,7 +422,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/AU250/fpga_25g/rtl/fpga_core.v b/example/AU250/fpga_25g/rtl/fpga_core.v index c8c2c444c..916766566 100644 --- a/example/AU250/fpga_25g/rtl/fpga_core.v +++ b/example/AU250/fpga_25g/rtl/fpga_core.v @@ -422,7 +422,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/AU280/fpga_25g/rtl/fpga_core.v b/example/AU280/fpga_25g/rtl/fpga_core.v index 3e970d846..1ae8f5fc1 100644 --- a/example/AU280/fpga_25g/rtl/fpga_core.v +++ b/example/AU280/fpga_25g/rtl/fpga_core.v @@ -407,7 +407,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/AU50/fpga_25g/rtl/fpga_core.v b/example/AU50/fpga_25g/rtl/fpga_core.v index a59896f6a..4730761a5 100644 --- a/example/AU50/fpga_25g/rtl/fpga_core.v +++ b/example/AU50/fpga_25g/rtl/fpga_core.v @@ -374,7 +374,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/Arty/fpga/rtl/fpga_core.v b/example/Arty/fpga/rtl/fpga_core.v index 13ba63b7d..e9629f475 100644 --- a/example/Arty/fpga/rtl/fpga_core.v +++ b/example/Arty/fpga/rtl/fpga_core.v @@ -363,7 +363,7 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/C10LP/fpga/rtl/fpga_core.v b/example/C10LP/fpga/rtl/fpga_core.v index 83fc9401d..ea2f8f3ff 100644 --- a/example/C10LP/fpga/rtl/fpga_core.v +++ b/example/C10LP/fpga/rtl/fpga_core.v @@ -340,7 +340,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/DE2-115/fpga/rtl/fpga_core.v b/example/DE2-115/fpga/rtl/fpga_core.v index 8ce5a6f4e..0934b1ea6 100644 --- a/example/DE2-115/fpga/rtl/fpga_core.v +++ b/example/DE2-115/fpga/rtl/fpga_core.v @@ -448,7 +448,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/DE5-Net/fpga/rtl/fpga_core.v b/example/DE5-Net/fpga/rtl/fpga_core.v index 10e425152..b75ec1009 100644 --- a/example/DE5-Net/fpga/rtl/fpga_core.v +++ b/example/DE5-Net/fpga/rtl/fpga_core.v @@ -372,7 +372,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/ExaNIC_X10/fpga/rtl/fpga_core.v b/example/ExaNIC_X10/fpga/rtl/fpga_core.v index ba26330d9..637cf2890 100644 --- a/example/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/example/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -352,7 +352,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v b/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v index ba26330d9..637cf2890 100644 --- a/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v +++ b/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v @@ -352,7 +352,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/HTG640/fpga/rtl/fpga_core.v b/example/HTG640/fpga/rtl/fpga_core.v index d3423eeb3..79bec3ee2 100644 --- a/example/HTG640/fpga/rtl/fpga_core.v +++ b/example/HTG640/fpga/rtl/fpga_core.v @@ -516,7 +516,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/HTG640/fpga_cxpt16/rtl/fpga_core.v b/example/HTG640/fpga_cxpt16/rtl/fpga_core.v index b4a7cf74a..ff3c0ee58 100644 --- a/example/HTG640/fpga_cxpt16/rtl/fpga_core.v +++ b/example/HTG640/fpga_cxpt16/rtl/fpga_core.v @@ -308,7 +308,7 @@ eth_mac_fifo_inst ( .rx_fifo_overflow(), .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/HTG9200/fpga_25g/rtl/fpga_core.v b/example/HTG9200/fpga_25g/rtl/fpga_core.v index 784790234..324804cb4 100644 --- a/example/HTG9200/fpga_25g/rtl/fpga_core.v +++ b/example/HTG9200/fpga_25g/rtl/fpga_core.v @@ -715,7 +715,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v index cfafade3c..a2b77fd0d 100644 --- a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v @@ -967,7 +967,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/KC705/fpga_gmii/rtl/fpga_core.v b/example/KC705/fpga_gmii/rtl/fpga_core.v index 0e0b46ff4..5cf47ee7f 100644 --- a/example/KC705/fpga_gmii/rtl/fpga_core.v +++ b/example/KC705/fpga_gmii/rtl/fpga_core.v @@ -360,7 +360,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/KC705/fpga_rgmii/rtl/fpga_core.v b/example/KC705/fpga_rgmii/rtl/fpga_core.v index 1505d3309..78ba7980f 100644 --- a/example/KC705/fpga_rgmii/rtl/fpga_core.v +++ b/example/KC705/fpga_rgmii/rtl/fpga_core.v @@ -357,7 +357,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/KC705/fpga_sgmii/rtl/fpga_core.v b/example/KC705/fpga_sgmii/rtl/fpga_core.v index fe73ad5bb..e688c77ec 100644 --- a/example/KC705/fpga_sgmii/rtl/fpga_core.v +++ b/example/KC705/fpga_sgmii/rtl/fpga_core.v @@ -357,7 +357,7 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/ML605/fpga_gmii/rtl/fpga_core.v b/example/ML605/fpga_gmii/rtl/fpga_core.v index 1bae139a1..a9d79878e 100644 --- a/example/ML605/fpga_gmii/rtl/fpga_core.v +++ b/example/ML605/fpga_gmii/rtl/fpga_core.v @@ -369,7 +369,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/ML605/fpga_rgmii/rtl/fpga_core.v b/example/ML605/fpga_rgmii/rtl/fpga_core.v index 1fcb6fa35..44f99672f 100644 --- a/example/ML605/fpga_rgmii/rtl/fpga_core.v +++ b/example/ML605/fpga_rgmii/rtl/fpga_core.v @@ -366,7 +366,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/ML605/fpga_sgmii/rtl/fpga_core.v b/example/ML605/fpga_sgmii/rtl/fpga_core.v index 565a41239..be8a81da5 100644 --- a/example/ML605/fpga_sgmii/rtl/fpga_core.v +++ b/example/ML605/fpga_sgmii/rtl/fpga_core.v @@ -366,7 +366,7 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/NetFPGA_SUME/fpga/rtl/fpga_core.v b/example/NetFPGA_SUME/fpga/rtl/fpga_core.v index f80f8a340..5e11592ba 100644 --- a/example/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/example/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -385,7 +385,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/NexysVideo/fpga/rtl/fpga_core.v b/example/NexysVideo/fpga/rtl/fpga_core.v index 5f94b5309..63b5feff5 100644 --- a/example/NexysVideo/fpga/rtl/fpga_core.v +++ b/example/NexysVideo/fpga/rtl/fpga_core.v @@ -355,7 +355,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/RV901T/fpga/rtl/fpga_core.v b/example/RV901T/fpga/rtl/fpga_core.v index 2cac60e2c..0e1242759 100644 --- a/example/RV901T/fpga/rtl/fpga_core.v +++ b/example/RV901T/fpga/rtl/fpga_core.v @@ -344,7 +344,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); assign phy_1_tx_clk = 1'b0; diff --git a/example/S10MX_DK/fpga_10g/rtl/fpga_core.v b/example/S10MX_DK/fpga_10g/rtl/fpga_core.v index 59e53f9c4..496164892 100644 --- a/example/S10MX_DK/fpga_10g/rtl/fpga_core.v +++ b/example/S10MX_DK/fpga_10g/rtl/fpga_core.v @@ -411,7 +411,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/VCU108/fpga_10g/rtl/fpga_core.v b/example/VCU108/fpga_10g/rtl/fpga_core.v index 2083ae212..63266daa9 100644 --- a/example/VCU108/fpga_10g/rtl/fpga_core.v +++ b/example/VCU108/fpga_10g/rtl/fpga_core.v @@ -418,7 +418,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); // 1G interface for debugging @@ -497,7 +497,7 @@ eth_mac_1g_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); axis_adapter #( diff --git a/example/VCU108/fpga_1g/rtl/fpga_core.v b/example/VCU108/fpga_1g/rtl/fpga_core.v index 8db7f7591..52ad016c8 100644 --- a/example/VCU108/fpga_1g/rtl/fpga_core.v +++ b/example/VCU108/fpga_1g/rtl/fpga_core.v @@ -357,7 +357,7 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/VCU118/fpga_1g/rtl/fpga_core.v b/example/VCU118/fpga_1g/rtl/fpga_core.v index 8db7f7591..52ad016c8 100644 --- a/example/VCU118/fpga_1g/rtl/fpga_core.v +++ b/example/VCU118/fpga_1g/rtl/fpga_core.v @@ -357,7 +357,7 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/VCU118/fpga_25g/rtl/fpga_core.v b/example/VCU118/fpga_25g/rtl/fpga_core.v index 5521ff960..1d1ea1729 100644 --- a/example/VCU118/fpga_25g/rtl/fpga_core.v +++ b/example/VCU118/fpga_25g/rtl/fpga_core.v @@ -459,7 +459,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); // 1G interface for debugging @@ -538,7 +538,7 @@ eth_mac_1g_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); axis_adapter #( diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v index 6d5e2beba..d3b97112a 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v @@ -709,7 +709,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); // 1G interface for debugging @@ -788,7 +788,7 @@ eth_mac_1g_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); axis_adapter #( diff --git a/example/VCU1525/fpga_25g/rtl/fpga_core.v b/example/VCU1525/fpga_25g/rtl/fpga_core.v index c8c2c444c..916766566 100644 --- a/example/VCU1525/fpga_25g/rtl/fpga_core.v +++ b/example/VCU1525/fpga_25g/rtl/fpga_core.v @@ -422,7 +422,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/ZCU102/fpga/rtl/fpga_core.v b/example/ZCU102/fpga/rtl/fpga_core.v index 85a8c0bcf..e992b8c05 100644 --- a/example/ZCU102/fpga/rtl/fpga_core.v +++ b/example/ZCU102/fpga/rtl/fpga_core.v @@ -384,7 +384,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/ZCU106/fpga/rtl/fpga_core.v b/example/ZCU106/fpga/rtl/fpga_core.v index 2c6f0193c..a70357d23 100644 --- a/example/ZCU106/fpga/rtl/fpga_core.v +++ b/example/ZCU106/fpga/rtl/fpga_core.v @@ -364,7 +364,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/fb2CG/fpga_25g/rtl/fpga_core.v b/example/fb2CG/fpga_25g/rtl/fpga_core.v index 18f1e32f2..560e993dd 100644 --- a/example/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/example/fb2CG/fpga_25g/rtl/fpga_core.v @@ -420,7 +420,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/rtl/axis_baser_tx_64.v b/rtl/axis_baser_tx_64.v index 3a2523655..d878db11b 100644 --- a/rtl/axis_baser_tx_64.v +++ b/rtl/axis_baser_tx_64.v @@ -79,7 +79,7 @@ module axis_baser_tx_64 # /* * Configuration */ - input wire [7:0] ifg_delay, + input wire [7:0] cfg_ifg, /* * Status @@ -530,7 +530,7 @@ always @* begin output_data_next = fcs_output_data_0; output_type_next = fcs_output_type_0; - ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg; + ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg; if (s_empty_reg <= 4) begin state_next = STATE_FCS_2; end else begin diff --git a/rtl/axis_gmii_tx.v b/rtl/axis_gmii_tx.v index 36c4c210c..d24c81a7d 100644 --- a/rtl/axis_gmii_tx.v +++ b/rtl/axis_gmii_tx.v @@ -80,7 +80,7 @@ module axis_gmii_tx # /* * Configuration */ - input wire [7:0] ifg_delay, + input wire [7:0] cfg_ifg, /* * Status @@ -386,7 +386,7 @@ always @* begin if (s_axis_tvalid) begin if (s_axis_tlast) begin s_axis_tready_next = 1'b0; - if (frame_ptr_reg < ifg_delay-1) begin + if (frame_ptr_reg < cfg_ifg-1) begin state_next = STATE_IFG; end else begin state_next = STATE_IDLE; @@ -404,7 +404,7 @@ always @* begin mii_odd_next = 1'b1; frame_ptr_next = frame_ptr_reg + 1; - if (frame_ptr_reg < ifg_delay-1) begin + if (frame_ptr_reg < cfg_ifg-1) begin state_next = STATE_IFG; end else begin state_next = STATE_IDLE; diff --git a/rtl/axis_xgmii_tx_32.v b/rtl/axis_xgmii_tx_32.v index 673438662..ef6781b5a 100644 --- a/rtl/axis_xgmii_tx_32.v +++ b/rtl/axis_xgmii_tx_32.v @@ -77,7 +77,7 @@ module axis_xgmii_tx_32 # /* * Configuration */ - input wire [7:0] ifg_delay, + input wire [7:0] cfg_ifg, /* * Status @@ -414,7 +414,7 @@ always @* begin xgmii_txd_next = fcs_output_txd_0; xgmii_txc_next = fcs_output_txc_0; - ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + deficit_idle_count_reg; + ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + deficit_idle_count_reg; state_next = STATE_FCS_2; end STATE_FCS_2: begin diff --git a/rtl/axis_xgmii_tx_64.v b/rtl/axis_xgmii_tx_64.v index 060ec412d..0606db81e 100644 --- a/rtl/axis_xgmii_tx_64.v +++ b/rtl/axis_xgmii_tx_64.v @@ -79,7 +79,7 @@ module axis_xgmii_tx_64 # /* * Configuration */ - input wire [7:0] ifg_delay, + input wire [7:0] cfg_ifg, /* * Status @@ -479,7 +479,7 @@ always @* begin xgmii_txd_next = fcs_output_txd_0; xgmii_txc_next = fcs_output_txc_0; - ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg; + ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg; if (s_empty_reg <= 4) begin state_next = STATE_FCS_2; end else begin diff --git a/rtl/eth_mac_10g.v b/rtl/eth_mac_10g.v index b34b91d2b..27d330cbb 100644 --- a/rtl/eth_mac_10g.v +++ b/rtl/eth_mac_10g.v @@ -150,7 +150,7 @@ module eth_mac_10g # /* * Configuration */ - input wire [7:0] ifg_delay, + input wire [7:0] cfg_ifg, input wire [47:0] cfg_mcf_rx_eth_dst_mcast, input wire cfg_mcf_rx_check_eth_dst_mcast, input wire [47:0] cfg_mcf_rx_eth_dst_ucast, @@ -274,7 +274,7 @@ axis_xgmii_tx_inst ( .m_axis_ptp_ts(tx_axis_ptp_ts), .m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag), .m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid), - .ifg_delay(ifg_delay), + .cfg_ifg(cfg_ifg), .start_packet(tx_start_packet), .error_underflow(tx_error_underflow) ); @@ -336,7 +336,7 @@ axis_xgmii_tx_inst ( .m_axis_ptp_ts(tx_axis_ptp_ts), .m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag), .m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid), - .ifg_delay(ifg_delay), + .cfg_ifg(cfg_ifg), .start_packet(tx_start_packet[0]), .error_underflow(tx_error_underflow) ); diff --git a/rtl/eth_mac_10g_fifo.v b/rtl/eth_mac_10g_fifo.v index a99b968b8..3acc04edd 100644 --- a/rtl/eth_mac_10g_fifo.v +++ b/rtl/eth_mac_10g_fifo.v @@ -133,7 +133,7 @@ module eth_mac_10g_fifo # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); parameter KEEP_WIDTH = DATA_WIDTH/8; @@ -382,7 +382,7 @@ eth_mac_10g_inst ( .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_1g.v b/rtl/eth_mac_1g.v index 2f3c3605f..49b8cc7ae 100644 --- a/rtl/eth_mac_1g.v +++ b/rtl/eth_mac_1g.v @@ -153,7 +153,7 @@ module eth_mac_1g # /* * Configuration */ - input wire [7:0] ifg_delay, + input wire [7:0] cfg_ifg, input wire [47:0] cfg_mcf_rx_eth_dst_mcast, input wire cfg_mcf_rx_check_eth_dst_mcast, input wire [47:0] cfg_mcf_rx_eth_dst_ucast, @@ -253,7 +253,7 @@ axis_gmii_tx_inst ( .m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid), .clk_enable(tx_clk_enable), .mii_select(tx_mii_select), - .ifg_delay(ifg_delay), + .cfg_ifg(cfg_ifg), .start_packet(tx_start_packet), .error_underflow(tx_error_underflow) ); diff --git a/rtl/eth_mac_1g_fifo.v b/rtl/eth_mac_1g_fifo.v index fc6bf7e0e..e5a629daf 100644 --- a/rtl/eth_mac_1g_fifo.v +++ b/rtl/eth_mac_1g_fifo.v @@ -113,7 +113,7 @@ module eth_mac_1g_fifo # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire [7:0] tx_fifo_axis_tdata; @@ -219,7 +219,7 @@ eth_mac_1g_inst ( .tx_error_underflow(tx_error_underflow_int), .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_1g_gmii.v b/rtl/eth_mac_1g_gmii.v index 6b1196924..bc6912c2b 100644 --- a/rtl/eth_mac_1g_gmii.v +++ b/rtl/eth_mac_1g_gmii.v @@ -96,7 +96,7 @@ module eth_mac_1g_gmii # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire [7:0] mac_gmii_rxd; @@ -244,7 +244,7 @@ eth_mac_1g_inst ( .tx_error_underflow(tx_error_underflow), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); endmodule diff --git a/rtl/eth_mac_1g_gmii_fifo.v b/rtl/eth_mac_1g_gmii_fifo.v index 2c6763047..fa44aae40 100644 --- a/rtl/eth_mac_1g_gmii_fifo.v +++ b/rtl/eth_mac_1g_gmii_fifo.v @@ -118,7 +118,7 @@ module eth_mac_1g_gmii_fifo # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire tx_clk; @@ -246,7 +246,7 @@ eth_mac_1g_gmii_inst ( .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), .speed(speed_int), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_1g_rgmii.v b/rtl/eth_mac_1g_rgmii.v index a6aaaded8..43218a7fa 100644 --- a/rtl/eth_mac_1g_rgmii.v +++ b/rtl/eth_mac_1g_rgmii.v @@ -95,7 +95,7 @@ module eth_mac_1g_rgmii # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire [7:0] mac_gmii_rxd; @@ -244,7 +244,7 @@ eth_mac_1g_inst ( .tx_error_underflow(tx_error_underflow), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); endmodule diff --git a/rtl/eth_mac_1g_rgmii_fifo.v b/rtl/eth_mac_1g_rgmii_fifo.v index bf97dc594..e7c2418b8 100644 --- a/rtl/eth_mac_1g_rgmii_fifo.v +++ b/rtl/eth_mac_1g_rgmii_fifo.v @@ -117,7 +117,7 @@ module eth_mac_1g_rgmii_fifo # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire tx_clk; @@ -244,7 +244,7 @@ eth_mac_1g_rgmii_inst ( .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), .speed(speed_int), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_mii.v b/rtl/eth_mac_mii.v index 8c1a47231..f83e223b4 100644 --- a/rtl/eth_mac_mii.v +++ b/rtl/eth_mac_mii.v @@ -91,7 +91,7 @@ module eth_mac_mii # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire [3:0] mac_mii_rxd; @@ -162,7 +162,7 @@ eth_mac_1g_inst ( .rx_start_packet(rx_start_packet), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); endmodule diff --git a/rtl/eth_mac_mii_fifo.v b/rtl/eth_mac_mii_fifo.v index 9384ac149..5f315fd5a 100644 --- a/rtl/eth_mac_mii_fifo.v +++ b/rtl/eth_mac_mii_fifo.v @@ -111,7 +111,7 @@ module eth_mac_mii_fifo # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire tx_clk; @@ -223,7 +223,7 @@ eth_mac_1g_mii_inst ( .tx_error_underflow(tx_error_underflow_int), .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_phy_10g.v b/rtl/eth_mac_phy_10g.v index 46267b7f6..a176ce9f9 100644 --- a/rtl/eth_mac_phy_10g.v +++ b/rtl/eth_mac_phy_10g.v @@ -120,9 +120,9 @@ module eth_mac_phy_10g # /* * Configuration */ - input wire [7:0] ifg_delay, - input wire tx_prbs31_enable, - input wire rx_prbs31_enable + input wire [7:0] cfg_ifg, + input wire cfg_tx_prbs31_enable, + input wire cfg_rx_prbs31_enable ); eth_mac_phy_10g_rx #( @@ -163,7 +163,7 @@ eth_mac_phy_10g_rx_inst ( .rx_block_lock(rx_block_lock), .rx_high_ber(rx_high_ber), .rx_status(rx_status), - .rx_prbs31_enable(rx_prbs31_enable) + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) ); eth_mac_phy_10g_tx #( @@ -203,8 +203,8 @@ eth_mac_phy_10g_tx_inst ( .m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid), .tx_start_packet(tx_start_packet), .tx_error_underflow(tx_error_underflow), - .ifg_delay(ifg_delay), - .tx_prbs31_enable(tx_prbs31_enable) + .cfg_ifg(cfg_ifg), + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) ); endmodule diff --git a/rtl/eth_mac_phy_10g_fifo.v b/rtl/eth_mac_phy_10g_fifo.v index 6205cdca1..220a3396d 100644 --- a/rtl/eth_mac_phy_10g_fifo.v +++ b/rtl/eth_mac_phy_10g_fifo.v @@ -147,9 +147,9 @@ module eth_mac_phy_10g_fifo # /* * Configuration */ - input wire [7:0] ifg_delay, - input wire tx_prbs31_enable, - input wire rx_prbs31_enable + input wire [7:0] cfg_ifg, + input wire cfg_tx_prbs31_enable, + input wire cfg_rx_prbs31_enable ); parameter KEEP_WIDTH = DATA_WIDTH/8; @@ -425,10 +425,10 @@ eth_mac_phy_10g_inst ( .rx_high_ber(rx_high_ber_int), .rx_status(rx_status_int), - .ifg_delay(ifg_delay), + .cfg_ifg(cfg_ifg), - .tx_prbs31_enable(tx_prbs31_enable), - .rx_prbs31_enable(rx_prbs31_enable) + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_phy_10g_rx.v b/rtl/eth_mac_phy_10g_rx.v index fb079ade7..3f498f0bc 100644 --- a/rtl/eth_mac_phy_10g_rx.v +++ b/rtl/eth_mac_phy_10g_rx.v @@ -90,7 +90,7 @@ module eth_mac_phy_10g_rx # /* * Configuration */ - input wire rx_prbs31_enable + input wire cfg_rx_prbs31_enable ); // bus width assertions @@ -138,7 +138,7 @@ eth_phy_10g_rx_if_inst ( .rx_block_lock(rx_block_lock), .rx_high_ber(rx_high_ber), .rx_status(rx_status), - .rx_prbs31_enable(rx_prbs31_enable) + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) ); axis_baser_rx_64 #( diff --git a/rtl/eth_mac_phy_10g_tx.v b/rtl/eth_mac_phy_10g_tx.v index 38d39c3db..91c992014 100644 --- a/rtl/eth_mac_phy_10g_tx.v +++ b/rtl/eth_mac_phy_10g_tx.v @@ -89,8 +89,8 @@ module eth_mac_phy_10g_tx # /* * Configuration */ - input wire [7:0] ifg_delay, - input wire tx_prbs31_enable + input wire [7:0] cfg_ifg, + input wire cfg_tx_prbs31_enable ); // bus width assertions @@ -147,7 +147,7 @@ axis_baser_tx_inst ( .m_axis_ptp_ts_valid(m_axis_ptp_ts_valid), .start_packet(tx_start_packet), .error_underflow(tx_error_underflow), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); eth_phy_10g_tx_if #( @@ -165,7 +165,7 @@ eth_phy_10g_tx_if_inst ( .encoded_tx_hdr(encoded_tx_hdr), .serdes_tx_data(serdes_tx_data), .serdes_tx_hdr(serdes_tx_hdr), - .tx_prbs31_enable(tx_prbs31_enable) + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) ); endmodule diff --git a/rtl/eth_phy_10g.v b/rtl/eth_phy_10g.v index 7fe6d82e9..c26af2195 100644 --- a/rtl/eth_phy_10g.v +++ b/rtl/eth_phy_10g.v @@ -83,8 +83,8 @@ module eth_phy_10g # /* * Configuration */ - input wire tx_prbs31_enable, - input wire rx_prbs31_enable + input wire cfg_tx_prbs31_enable, + input wire cfg_rx_prbs31_enable ); eth_phy_10g_rx #( @@ -114,7 +114,7 @@ eth_phy_10g_rx_inst ( .rx_block_lock(rx_block_lock), .rx_high_ber(rx_high_ber), .rx_status(rx_status), - .rx_prbs31_enable(rx_prbs31_enable) + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) ); eth_phy_10g_tx #( @@ -134,7 +134,7 @@ eth_phy_10g_tx_inst ( .serdes_tx_data(serdes_tx_data), .serdes_tx_hdr(serdes_tx_hdr), .tx_bad_block(tx_bad_block), - .tx_prbs31_enable(tx_prbs31_enable) + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) ); endmodule diff --git a/rtl/eth_phy_10g_rx.v b/rtl/eth_phy_10g_rx.v index 1b1695e50..f9030dd3e 100644 --- a/rtl/eth_phy_10g_rx.v +++ b/rtl/eth_phy_10g_rx.v @@ -75,7 +75,7 @@ module eth_phy_10g_rx # /* * Configuration */ - input wire rx_prbs31_enable + input wire cfg_rx_prbs31_enable ); // bus width assertions @@ -125,7 +125,7 @@ eth_phy_10g_rx_if_inst ( .rx_block_lock(rx_block_lock), .rx_high_ber(rx_high_ber), .rx_status(rx_status), - .rx_prbs31_enable(rx_prbs31_enable) + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) ); xgmii_baser_dec_64 #( diff --git a/rtl/eth_phy_10g_rx_if.v b/rtl/eth_phy_10g_rx_if.v index 531c197ed..26eb8ed04 100644 --- a/rtl/eth_phy_10g_rx_if.v +++ b/rtl/eth_phy_10g_rx_if.v @@ -74,7 +74,7 @@ module eth_phy_10g_rx_if # /* * Configuration */ - input wire rx_prbs31_enable + input wire cfg_rx_prbs31_enable ); // bus width assertions @@ -206,7 +206,7 @@ always @(posedge clk) begin encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data; encoded_rx_hdr_reg <= serdes_rx_hdr_int; - if (PRBS31_ENABLE && rx_prbs31_enable) begin + if (PRBS31_ENABLE && cfg_rx_prbs31_enable) begin prbs31_state_reg <= prbs31_state; rx_error_count_1_reg <= rx_error_count_1_temp; @@ -222,8 +222,8 @@ assign rx_error_count = rx_error_count_reg; wire serdes_rx_bitslip_int; wire serdes_rx_reset_req_int; -assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_ENABLE && rx_prbs31_enable); -assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_ENABLE && rx_prbs31_enable); +assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_ENABLE && cfg_rx_prbs31_enable); +assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_ENABLE && cfg_rx_prbs31_enable); eth_phy_10g_rx_frame_sync #( .HDR_WIDTH(HDR_WIDTH), diff --git a/rtl/eth_phy_10g_tx.v b/rtl/eth_phy_10g_tx.v index 692ce4e7d..43d7a6c02 100644 --- a/rtl/eth_phy_10g_tx.v +++ b/rtl/eth_phy_10g_tx.v @@ -65,7 +65,7 @@ module eth_phy_10g_tx # /* * Configuration */ - input wire tx_prbs31_enable + input wire cfg_tx_prbs31_enable ); // bus width assertions @@ -119,7 +119,7 @@ eth_phy_10g_tx_if_inst ( .encoded_tx_hdr(encoded_tx_hdr), .serdes_tx_data(serdes_tx_data), .serdes_tx_hdr(serdes_tx_hdr), - .tx_prbs31_enable(tx_prbs31_enable) + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) ); endmodule diff --git a/rtl/eth_phy_10g_tx_if.v b/rtl/eth_phy_10g_tx_if.v index d61474e7f..2c5314365 100644 --- a/rtl/eth_phy_10g_tx_if.v +++ b/rtl/eth_phy_10g_tx_if.v @@ -59,7 +59,7 @@ module eth_phy_10g_tx_if # /* * Configuration */ - input wire tx_prbs31_enable + input wire cfg_tx_prbs31_enable ); // bus width assertions @@ -167,7 +167,7 @@ prbs31_gen_inst ( always @(posedge clk) begin scrambler_state_reg <= scrambler_state; - if (PRBS31_ENABLE && tx_prbs31_enable) begin + if (PRBS31_ENABLE && cfg_tx_prbs31_enable) begin prbs31_state_reg <= prbs31_state; serdes_tx_data_reg <= ~prbs31_data[DATA_WIDTH+HDR_WIDTH-1:HDR_WIDTH]; diff --git a/tb/axis_baser_tx_64/test_axis_baser_tx_64.py b/tb/axis_baser_tx_64/test_axis_baser_tx_64.py index 7888712a5..4b3cb87ab 100644 --- a/tb/axis_baser_tx_64/test_axis_baser_tx_64.py +++ b/tb/axis_baser_tx_64/test_axis_baser_tx_64.py @@ -73,7 +73,7 @@ class TB: self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -91,7 +91,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -135,7 +135,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): byte_width = tb.source.width // 8 - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/axis_gmii_tx/test_axis_gmii_tx.py b/tb/axis_gmii_tx/test_axis_gmii_tx.py index 93fad4bd9..7176204a4 100644 --- a/tb/axis_gmii_tx/test_axis_gmii_tx.py +++ b/tb/axis_gmii_tx/test_axis_gmii_tx.py @@ -67,7 +67,7 @@ class TB: dut.clk_enable.setimmediatevalue(1) dut.mii_select.setimmediatevalue(0) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -103,7 +103,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_ tb = TB(dut) - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.mii_select.value = mii_sel if enable_gen is not None: diff --git a/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py b/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py index da8c52f3d..790af2da9 100644 --- a/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py +++ b/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py @@ -62,7 +62,7 @@ class TB: self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -80,7 +80,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -120,7 +120,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): byte_width = tb.source.width // 8 - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py b/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py index 29189b382..df6708826 100644 --- a/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py +++ b/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py @@ -62,7 +62,7 @@ class TB: self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -80,7 +80,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -124,7 +124,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): byte_width = tb.source.width // 8 - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_10g/test_eth_mac_10g.py b/tb/eth_mac_10g/test_eth_mac_10g.py index c4363d464..842ecfa9a 100644 --- a/tb/eth_mac_10g/test_eth_mac_10g.py +++ b/tb/eth_mac_10g/test_eth_mac_10g.py @@ -88,7 +88,7 @@ class TB: dut.tx_lfc_pause_en.setimmediatevalue(0) dut.tx_pause_req.setimmediatevalue(0) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0) dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0) dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0) @@ -141,7 +141,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -185,7 +185,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -230,7 +230,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): byte_width = tb.axis_source.width // 8 tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -313,7 +313,7 @@ async def run_test_lfc(dut, ifg=12): tb = TB(dut) tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -456,7 +456,7 @@ async def run_test_pfc(dut, ifg=12): tb = TB(dut) tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py index eadfe14fa..dc35847f0 100644 --- a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py +++ b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py @@ -75,6 +75,8 @@ class TB: dut.ptp_sample_clk.setimmediatevalue(0) dut.ptp_ts_step.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) + async def reset(self): self.dut.logic_rst.setimmediatevalue(0) self.dut.rx_rst.setimmediatevalue(0) @@ -98,7 +100,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -146,7 +148,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -195,7 +197,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): byte_width = tb.axis_source.width // 8 tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_1g/test_eth_mac_1g.py b/tb/eth_mac_1g/test_eth_mac_1g.py index ab0a48919..1a7a50a07 100644 --- a/tb/eth_mac_1g/test_eth_mac_1g.py +++ b/tb/eth_mac_1g/test_eth_mac_1g.py @@ -95,7 +95,7 @@ class TB: dut.rx_mii_select.setimmediatevalue(0) dut.tx_mii_select.setimmediatevalue(0) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0) dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0) dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0) @@ -184,7 +184,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab tb = TB(dut) tb.gmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel @@ -230,7 +230,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab tb = TB(dut) tb.gmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel @@ -273,7 +273,7 @@ async def run_test_lfc(dut, ifg=12, enable_gen=None, mii_sel=True): tb = TB(dut) tb.gmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel @@ -422,7 +422,7 @@ async def run_test_pfc(dut, ifg=12, enable_gen=None, mii_sel=True): tb = TB(dut) tb.gmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel diff --git a/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py b/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py index 8cb333bbb..c37e8c268 100644 --- a/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py +++ b/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py @@ -66,7 +66,7 @@ class TB: dut.tx_clk_enable.setimmediatevalue(1) dut.rx_mii_select.setimmediatevalue(0) dut.tx_mii_select.setimmediatevalue(0) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.logic_rst.setimmediatevalue(0) @@ -127,7 +127,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab tb = TB(dut) tb.gmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel @@ -160,7 +160,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab tb = TB(dut) tb.gmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel diff --git a/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py b/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py index 295427efc..e0e3cd32a 100644 --- a/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py +++ b/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py @@ -53,7 +53,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.gtx_rst.setimmediatevalue(0) @@ -75,7 +75,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.gmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.set_speed(speed) @@ -114,7 +114,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.gmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.set_speed(speed) diff --git a/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py b/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py index 7ed984a0a..c080369f5 100644 --- a/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py +++ b/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py @@ -54,7 +54,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.logic_clk, dut.logic_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.gtx_rst.setimmediatevalue(0) @@ -79,7 +79,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.gmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.set_speed(speed) @@ -118,7 +118,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.gmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.set_speed(speed) diff --git a/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py b/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py index 52328b873..c19ad0298 100644 --- a/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py +++ b/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py @@ -50,7 +50,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) dut.gtx_clk.setimmediatevalue(0) dut.gtx_clk90.setimmediatevalue(0) @@ -86,7 +86,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.rgmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -123,7 +123,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.rgmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py b/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py index 3e162174f..a6cbcea56 100644 --- a/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py +++ b/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py @@ -53,7 +53,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.logic_clk, dut.logic_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) dut.gtx_clk.setimmediatevalue(0) dut.gtx_clk90.setimmediatevalue(0) @@ -92,7 +92,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.rgmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -129,7 +129,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.rgmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_mii/test_eth_mac_mii.py b/tb/eth_mac_mii/test_eth_mac_mii.py index b144a509c..f038895ab 100644 --- a/tb/eth_mac_mii/test_eth_mac_mii.py +++ b/tb/eth_mac_mii/test_eth_mac_mii.py @@ -50,7 +50,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -69,7 +69,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.mii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -96,7 +96,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.mii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py b/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py index d154fb859..6da182e21 100644 --- a/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py +++ b/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py @@ -53,7 +53,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.logic_clk, dut.logic_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.logic_rst.setimmediatevalue(0) @@ -72,7 +72,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.mii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -99,7 +99,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.mii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py b/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py index bda5fec48..74b07ba94 100644 --- a/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py +++ b/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py @@ -83,8 +83,9 @@ class TB: self.tx_ptp_clock = PtpClockSimTime(ts_64=dut.tx_ptp_ts, clock=dut.tx_clk) self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) - dut.tx_prbs31_enable.setimmediatevalue(0) - dut.rx_prbs31_enable.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_prbs31_enable.setimmediatevalue(0) + dut.cfg_rx_prbs31_enable.setimmediatevalue(0) async def reset(self): self.dut.rx_rst.setimmediatevalue(0) @@ -106,7 +107,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.serdes_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -159,7 +160,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.serdes_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -204,7 +205,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): byte_width = tb.axis_source.width // 8 tb.serdes_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py index 70abb425b..b470e789e 100644 --- a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py +++ b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py @@ -86,8 +86,9 @@ class TB: dut.ptp_sample_clk.setimmediatevalue(0) dut.ptp_ts_step.setimmediatevalue(0) - dut.tx_prbs31_enable.setimmediatevalue(0) - dut.rx_prbs31_enable.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_prbs31_enable.setimmediatevalue(0) + dut.cfg_rx_prbs31_enable.setimmediatevalue(0) async def reset(self): self.dut.logic_rst.setimmediatevalue(0) @@ -112,7 +113,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.serdes_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -167,7 +168,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.serdes_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -216,7 +217,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): byte_width = tb.axis_source.width // 8 tb.serdes_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_phy_10g/test_eth_phy_10g.py b/tb/eth_phy_10g/test_eth_phy_10g.py index 73275f61e..6280adaff 100644 --- a/tb/eth_phy_10g/test_eth_phy_10g.py +++ b/tb/eth_phy_10g/test_eth_phy_10g.py @@ -64,8 +64,8 @@ class TB: self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip) self.serdes_sink = BaseRSerdesSink(dut.serdes_tx_data, dut.serdes_tx_hdr, dut.tx_clk) - dut.tx_prbs31_enable.setimmediatevalue(0) - dut.rx_prbs31_enable.setimmediatevalue(0) + dut.cfg_tx_prbs31_enable.setimmediatevalue(0) + dut.cfg_rx_prbs31_enable.setimmediatevalue(0) async def reset(self): self.dut.tx_rst.setimmediatevalue(0) From fa05d4ff3ce90db4bef17e7d5b67947c08d935a1 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 24 Aug 2023 01:24:33 -0700 Subject: [PATCH 02/19] Add TX and RX enable inputs to MACs Signed-off-by: Alex Forencich --- example/520N_MX/fpga_10g/rtl/fpga_core.v | 4 +++- example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 4 +++- example/ATLYS/fpga/rtl/fpga_core.v | 4 +++- example/AU200/fpga_25g/rtl/fpga_core.v | 4 +++- example/AU250/fpga_25g/rtl/fpga_core.v | 4 +++- example/AU280/fpga_25g/rtl/fpga_core.v | 4 +++- example/AU50/fpga_25g/rtl/fpga_core.v | 4 +++- example/Arty/fpga/rtl/fpga_core.v | 4 +++- example/C10LP/fpga/rtl/fpga_core.v | 4 +++- example/DE2-115/fpga/rtl/fpga_core.v | 4 +++- example/DE5-Net/fpga/rtl/fpga_core.v | 4 +++- example/ExaNIC_X10/fpga/rtl/fpga_core.v | 4 +++- example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v | 4 +++- example/HTG640/fpga/rtl/fpga_core.v | 4 +++- example/HTG640/fpga_cxpt16/rtl/fpga_core.v | 4 +++- example/HTG9200/fpga_25g/rtl/fpga_core.v | 4 +++- .../fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v | 4 +++- example/KC705/fpga_gmii/rtl/fpga_core.v | 4 +++- example/KC705/fpga_rgmii/rtl/fpga_core.v | 4 +++- example/KC705/fpga_sgmii/rtl/fpga_core.v | 4 +++- example/ML605/fpga_gmii/rtl/fpga_core.v | 4 +++- example/ML605/fpga_rgmii/rtl/fpga_core.v | 4 +++- example/ML605/fpga_sgmii/rtl/fpga_core.v | 4 +++- example/NetFPGA_SUME/fpga/rtl/fpga_core.v | 4 +++- example/NexysVideo/fpga/rtl/fpga_core.v | 4 +++- example/RV901T/fpga/rtl/fpga_core.v | 4 +++- example/S10MX_DK/fpga_10g/rtl/fpga_core.v | 4 +++- example/VCU108/fpga_10g/rtl/fpga_core.v | 8 ++++++-- example/VCU108/fpga_1g/rtl/fpga_core.v | 4 +++- example/VCU118/fpga_1g/rtl/fpga_core.v | 4 +++- example/VCU118/fpga_25g/rtl/fpga_core.v | 8 ++++++-- .../fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v | 8 ++++++-- example/VCU1525/fpga_25g/rtl/fpga_core.v | 4 +++- example/ZCU102/fpga/rtl/fpga_core.v | 4 +++- example/ZCU106/fpga/rtl/fpga_core.v | 4 +++- example/fb2CG/fpga_25g/rtl/fpga_core.v | 4 +++- rtl/axis_baser_rx_64.v | 7 ++++++- rtl/axis_baser_tx_64.v | 3 ++- rtl/axis_gmii_rx.v | 7 ++++++- rtl/axis_gmii_tx.v | 3 ++- rtl/axis_xgmii_rx_32.v | 7 ++++++- rtl/axis_xgmii_rx_64.v | 7 ++++++- rtl/axis_xgmii_tx_32.v | 3 ++- rtl/axis_xgmii_tx_64.v | 17 +++++++++-------- rtl/eth_mac_10g.v | 6 ++++++ rtl/eth_mac_10g_fifo.v | 8 ++++++-- rtl/eth_mac_1g.v | 4 ++++ rtl/eth_mac_1g_fifo.v | 8 ++++++-- rtl/eth_mac_1g_gmii.v | 8 ++++++-- rtl/eth_mac_1g_gmii_fifo.v | 8 ++++++-- rtl/eth_mac_1g_rgmii.v | 8 ++++++-- rtl/eth_mac_1g_rgmii_fifo.v | 8 ++++++-- rtl/eth_mac_mii.v | 8 ++++++-- rtl/eth_mac_mii_fifo.v | 8 ++++++-- rtl/eth_mac_phy_10g.v | 4 ++++ rtl/eth_mac_phy_10g_fifo.v | 4 ++++ rtl/eth_mac_phy_10g_rx.v | 4 +++- rtl/eth_mac_phy_10g_tx.v | 4 +++- tb/axis_baser_rx_64/test_axis_baser_rx_64.py | 3 +++ tb/axis_baser_tx_64/test_axis_baser_tx_64.py | 3 +++ tb/axis_gmii_rx/test_axis_gmii_rx.py | 2 ++ tb/axis_gmii_tx/test_axis_gmii_tx.py | 2 ++ tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py | 3 +++ tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py | 3 +++ tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py | 3 +++ tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py | 3 +++ tb/eth_mac_10g/test_eth_mac_10g.py | 9 +++++++++ tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py | 5 +++++ tb/eth_mac_1g/test_eth_mac_1g.py | 8 ++++++++ tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py | 4 ++++ tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py | 4 ++++ .../test_eth_mac_1g_gmii_fifo.py | 4 ++++ tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py | 4 ++++ .../test_eth_mac_1g_rgmii_fifo.py | 4 ++++ tb/eth_mac_mii/test_eth_mac_mii.py | 4 ++++ tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py | 4 ++++ tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py | 5 +++++ .../test_eth_mac_phy_10g_fifo.py | 5 +++++ 78 files changed, 310 insertions(+), 72 deletions(-) diff --git a/example/520N_MX/fpga_10g/rtl/fpga_core.v b/example/520N_MX/fpga_10g/rtl/fpga_core.v index 7011d5470..6607b8a1c 100644 --- a/example/520N_MX/fpga_10g/rtl/fpga_core.v +++ b/example/520N_MX/fpga_10g/rtl/fpga_core.v @@ -497,7 +497,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 5cacb65cc..07b0570d6 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -419,7 +419,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/ATLYS/fpga/rtl/fpga_core.v b/example/ATLYS/fpga/rtl/fpga_core.v index 5ef8fa732..589d89ae3 100644 --- a/example/ATLYS/fpga/rtl/fpga_core.v +++ b/example/ATLYS/fpga/rtl/fpga_core.v @@ -356,7 +356,9 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/AU200/fpga_25g/rtl/fpga_core.v b/example/AU200/fpga_25g/rtl/fpga_core.v index 916766566..27d8e5cd5 100644 --- a/example/AU200/fpga_25g/rtl/fpga_core.v +++ b/example/AU200/fpga_25g/rtl/fpga_core.v @@ -422,7 +422,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/AU250/fpga_25g/rtl/fpga_core.v b/example/AU250/fpga_25g/rtl/fpga_core.v index 916766566..27d8e5cd5 100644 --- a/example/AU250/fpga_25g/rtl/fpga_core.v +++ b/example/AU250/fpga_25g/rtl/fpga_core.v @@ -422,7 +422,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/AU280/fpga_25g/rtl/fpga_core.v b/example/AU280/fpga_25g/rtl/fpga_core.v index 1ae8f5fc1..ee706700d 100644 --- a/example/AU280/fpga_25g/rtl/fpga_core.v +++ b/example/AU280/fpga_25g/rtl/fpga_core.v @@ -407,7 +407,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/AU50/fpga_25g/rtl/fpga_core.v b/example/AU50/fpga_25g/rtl/fpga_core.v index 4730761a5..30dff9a3d 100644 --- a/example/AU50/fpga_25g/rtl/fpga_core.v +++ b/example/AU50/fpga_25g/rtl/fpga_core.v @@ -374,7 +374,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/Arty/fpga/rtl/fpga_core.v b/example/Arty/fpga/rtl/fpga_core.v index e9629f475..2b4957765 100644 --- a/example/Arty/fpga/rtl/fpga_core.v +++ b/example/Arty/fpga/rtl/fpga_core.v @@ -363,7 +363,9 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/C10LP/fpga/rtl/fpga_core.v b/example/C10LP/fpga/rtl/fpga_core.v index ea2f8f3ff..11c880d0e 100644 --- a/example/C10LP/fpga/rtl/fpga_core.v +++ b/example/C10LP/fpga/rtl/fpga_core.v @@ -340,7 +340,9 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/DE2-115/fpga/rtl/fpga_core.v b/example/DE2-115/fpga/rtl/fpga_core.v index 0934b1ea6..bcc99b837 100644 --- a/example/DE2-115/fpga/rtl/fpga_core.v +++ b/example/DE2-115/fpga/rtl/fpga_core.v @@ -448,7 +448,9 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/DE5-Net/fpga/rtl/fpga_core.v b/example/DE5-Net/fpga/rtl/fpga_core.v index b75ec1009..39f61e299 100644 --- a/example/DE5-Net/fpga/rtl/fpga_core.v +++ b/example/DE5-Net/fpga/rtl/fpga_core.v @@ -372,7 +372,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/ExaNIC_X10/fpga/rtl/fpga_core.v b/example/ExaNIC_X10/fpga/rtl/fpga_core.v index 637cf2890..f66c392b1 100644 --- a/example/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/example/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -352,7 +352,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v b/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v index 637cf2890..f66c392b1 100644 --- a/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v +++ b/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v @@ -352,7 +352,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/HTG640/fpga/rtl/fpga_core.v b/example/HTG640/fpga/rtl/fpga_core.v index 79bec3ee2..d2d7787c5 100644 --- a/example/HTG640/fpga/rtl/fpga_core.v +++ b/example/HTG640/fpga/rtl/fpga_core.v @@ -516,7 +516,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/HTG640/fpga_cxpt16/rtl/fpga_core.v b/example/HTG640/fpga_cxpt16/rtl/fpga_core.v index ff3c0ee58..82185aac0 100644 --- a/example/HTG640/fpga_cxpt16/rtl/fpga_core.v +++ b/example/HTG640/fpga_cxpt16/rtl/fpga_core.v @@ -308,7 +308,9 @@ eth_mac_fifo_inst ( .rx_fifo_overflow(), .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b0), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/HTG9200/fpga_25g/rtl/fpga_core.v b/example/HTG9200/fpga_25g/rtl/fpga_core.v index 324804cb4..1bd42ad42 100644 --- a/example/HTG9200/fpga_25g/rtl/fpga_core.v +++ b/example/HTG9200/fpga_25g/rtl/fpga_core.v @@ -715,7 +715,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v index a2b77fd0d..aa80fb279 100644 --- a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v @@ -967,7 +967,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/KC705/fpga_gmii/rtl/fpga_core.v b/example/KC705/fpga_gmii/rtl/fpga_core.v index 5cf47ee7f..41d39ee2e 100644 --- a/example/KC705/fpga_gmii/rtl/fpga_core.v +++ b/example/KC705/fpga_gmii/rtl/fpga_core.v @@ -360,7 +360,9 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/KC705/fpga_rgmii/rtl/fpga_core.v b/example/KC705/fpga_rgmii/rtl/fpga_core.v index 78ba7980f..3d3e22ccb 100644 --- a/example/KC705/fpga_rgmii/rtl/fpga_core.v +++ b/example/KC705/fpga_rgmii/rtl/fpga_core.v @@ -357,7 +357,9 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/KC705/fpga_sgmii/rtl/fpga_core.v b/example/KC705/fpga_sgmii/rtl/fpga_core.v index e688c77ec..12747a77c 100644 --- a/example/KC705/fpga_sgmii/rtl/fpga_core.v +++ b/example/KC705/fpga_sgmii/rtl/fpga_core.v @@ -357,7 +357,9 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/ML605/fpga_gmii/rtl/fpga_core.v b/example/ML605/fpga_gmii/rtl/fpga_core.v index a9d79878e..682c4ddc8 100644 --- a/example/ML605/fpga_gmii/rtl/fpga_core.v +++ b/example/ML605/fpga_gmii/rtl/fpga_core.v @@ -369,7 +369,9 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/ML605/fpga_rgmii/rtl/fpga_core.v b/example/ML605/fpga_rgmii/rtl/fpga_core.v index 44f99672f..1d94a8893 100644 --- a/example/ML605/fpga_rgmii/rtl/fpga_core.v +++ b/example/ML605/fpga_rgmii/rtl/fpga_core.v @@ -366,7 +366,9 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/ML605/fpga_sgmii/rtl/fpga_core.v b/example/ML605/fpga_sgmii/rtl/fpga_core.v index be8a81da5..ea568efc7 100644 --- a/example/ML605/fpga_sgmii/rtl/fpga_core.v +++ b/example/ML605/fpga_sgmii/rtl/fpga_core.v @@ -366,7 +366,9 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/NetFPGA_SUME/fpga/rtl/fpga_core.v b/example/NetFPGA_SUME/fpga/rtl/fpga_core.v index 5e11592ba..a63719c31 100644 --- a/example/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/example/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -385,7 +385,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/NexysVideo/fpga/rtl/fpga_core.v b/example/NexysVideo/fpga/rtl/fpga_core.v index 63b5feff5..6deb022af 100644 --- a/example/NexysVideo/fpga/rtl/fpga_core.v +++ b/example/NexysVideo/fpga/rtl/fpga_core.v @@ -355,7 +355,9 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/RV901T/fpga/rtl/fpga_core.v b/example/RV901T/fpga/rtl/fpga_core.v index 0e1242759..b7970e083 100644 --- a/example/RV901T/fpga/rtl/fpga_core.v +++ b/example/RV901T/fpga/rtl/fpga_core.v @@ -344,7 +344,9 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); assign phy_1_tx_clk = 1'b0; diff --git a/example/S10MX_DK/fpga_10g/rtl/fpga_core.v b/example/S10MX_DK/fpga_10g/rtl/fpga_core.v index 496164892..517076420 100644 --- a/example/S10MX_DK/fpga_10g/rtl/fpga_core.v +++ b/example/S10MX_DK/fpga_10g/rtl/fpga_core.v @@ -411,7 +411,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/VCU108/fpga_10g/rtl/fpga_core.v b/example/VCU108/fpga_10g/rtl/fpga_core.v index 63266daa9..b35139a71 100644 --- a/example/VCU108/fpga_10g/rtl/fpga_core.v +++ b/example/VCU108/fpga_10g/rtl/fpga_core.v @@ -418,7 +418,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); // 1G interface for debugging @@ -497,7 +499,9 @@ eth_mac_1g_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); axis_adapter #( diff --git a/example/VCU108/fpga_1g/rtl/fpga_core.v b/example/VCU108/fpga_1g/rtl/fpga_core.v index 52ad016c8..03499ac55 100644 --- a/example/VCU108/fpga_1g/rtl/fpga_core.v +++ b/example/VCU108/fpga_1g/rtl/fpga_core.v @@ -357,7 +357,9 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/VCU118/fpga_1g/rtl/fpga_core.v b/example/VCU118/fpga_1g/rtl/fpga_core.v index 52ad016c8..03499ac55 100644 --- a/example/VCU118/fpga_1g/rtl/fpga_core.v +++ b/example/VCU118/fpga_1g/rtl/fpga_core.v @@ -357,7 +357,9 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx diff --git a/example/VCU118/fpga_25g/rtl/fpga_core.v b/example/VCU118/fpga_25g/rtl/fpga_core.v index 1d1ea1729..91691226d 100644 --- a/example/VCU118/fpga_25g/rtl/fpga_core.v +++ b/example/VCU118/fpga_25g/rtl/fpga_core.v @@ -459,7 +459,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); // 1G interface for debugging @@ -538,7 +540,9 @@ eth_mac_1g_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); axis_adapter #( diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v index d3b97112a..ac5e91e97 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v @@ -709,7 +709,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); // 1G interface for debugging @@ -788,7 +790,9 @@ eth_mac_1g_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); axis_adapter #( diff --git a/example/VCU1525/fpga_25g/rtl/fpga_core.v b/example/VCU1525/fpga_25g/rtl/fpga_core.v index 916766566..27d8e5cd5 100644 --- a/example/VCU1525/fpga_25g/rtl/fpga_core.v +++ b/example/VCU1525/fpga_25g/rtl/fpga_core.v @@ -422,7 +422,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/ZCU102/fpga/rtl/fpga_core.v b/example/ZCU102/fpga/rtl/fpga_core.v index e992b8c05..cea742245 100644 --- a/example/ZCU102/fpga/rtl/fpga_core.v +++ b/example/ZCU102/fpga/rtl/fpga_core.v @@ -384,7 +384,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/ZCU106/fpga/rtl/fpga_core.v b/example/ZCU106/fpga/rtl/fpga_core.v index a70357d23..d5625c213 100644 --- a/example/ZCU106/fpga/rtl/fpga_core.v +++ b/example/ZCU106/fpga/rtl/fpga_core.v @@ -364,7 +364,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/example/fb2CG/fpga_25g/rtl/fpga_core.v b/example/fb2CG/fpga_25g/rtl/fpga_core.v index 560e993dd..23a703e02 100644 --- a/example/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/example/fb2CG/fpga_25g/rtl/fpga_core.v @@ -420,7 +420,9 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .cfg_ifg(8'd12) + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) ); eth_axis_rx #( diff --git a/rtl/axis_baser_rx_64.v b/rtl/axis_baser_rx_64.v index e22b9986f..714c9194a 100644 --- a/rtl/axis_baser_rx_64.v +++ b/rtl/axis_baser_rx_64.v @@ -66,6 +66,11 @@ module axis_baser_rx_64 # */ input wire [PTP_TS_WIDTH-1:0] ptp_ts, + /* + * Configuration + */ + input wire cfg_rx_enable, + /* * Status */ @@ -285,7 +290,7 @@ always @* begin m_axis_tuser_next[1 +: PTP_TS_WIDTH] = (PTP_TS_WIDTH != 96 || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg; end - if (input_type_d1 == INPUT_TYPE_START_0) begin + if (input_type_d1 == INPUT_TYPE_START_0 && cfg_rx_enable) begin // start condition reset_crc = 1'b0; state_next = STATE_PAYLOAD; diff --git a/rtl/axis_baser_tx_64.v b/rtl/axis_baser_tx_64.v index d878db11b..234b85dd2 100644 --- a/rtl/axis_baser_tx_64.v +++ b/rtl/axis_baser_tx_64.v @@ -80,6 +80,7 @@ module axis_baser_tx_64 # * Configuration */ input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, /* * Status @@ -397,7 +398,7 @@ always @* begin s_tdata_next = s_axis_tdata_masked; s_empty_next = keep2empty(s_axis_tkeep); - if (s_axis_tvalid) begin + if (s_axis_tvalid && cfg_tx_enable) begin // XGMII start and preamble if (swap_lanes_reg) begin // lanes swapped diff --git a/rtl/axis_gmii_rx.v b/rtl/axis_gmii_rx.v index 64ff1d77f..9b4f30d66 100644 --- a/rtl/axis_gmii_rx.v +++ b/rtl/axis_gmii_rx.v @@ -68,6 +68,11 @@ module axis_gmii_rx # input wire clk_enable, input wire mii_select, + /* + * Configuration + */ + input wire cfg_rx_enable, + /* * Status */ @@ -186,7 +191,7 @@ always @* begin // idle state - wait for packet reset_crc = 1'b1; - if (gmii_rx_dv_d4 && !gmii_rx_er_d4 && gmii_rxd_d4 == ETH_SFD) begin + if (gmii_rx_dv_d4 && !gmii_rx_er_d4 && gmii_rxd_d4 == ETH_SFD && cfg_rx_enable) begin state_next = STATE_PAYLOAD; end else begin state_next = STATE_IDLE; diff --git a/rtl/axis_gmii_tx.v b/rtl/axis_gmii_tx.v index d24c81a7d..674589324 100644 --- a/rtl/axis_gmii_tx.v +++ b/rtl/axis_gmii_tx.v @@ -81,6 +81,7 @@ module axis_gmii_tx # * Configuration */ input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, /* * Status @@ -240,7 +241,7 @@ always @* begin frame_min_count_next = MIN_FRAME_LENGTH-4-1; - if (s_axis_tvalid) begin + if (s_axis_tvalid && cfg_tx_enable) begin mii_odd_next = 1'b1; gmii_txd_next = ETH_PRE; gmii_tx_en_next = 1'b1; diff --git a/rtl/axis_xgmii_rx_32.v b/rtl/axis_xgmii_rx_32.v index 6a5aa92f5..0241ad569 100644 --- a/rtl/axis_xgmii_rx_32.v +++ b/rtl/axis_xgmii_rx_32.v @@ -64,6 +64,11 @@ module axis_xgmii_rx_32 # */ input wire [PTP_TS_WIDTH-1:0] ptp_ts, + /* + * Configuration + */ + input wire cfg_rx_enable, + /* * Status */ @@ -244,7 +249,7 @@ always @* begin // idle state - wait for packet reset_crc = 1'b1; - if (xgmii_start_d2) begin + if (xgmii_start_d2 && cfg_rx_enable) begin // start condition if (control_masked) begin // control or error characters in first data word diff --git a/rtl/axis_xgmii_rx_64.v b/rtl/axis_xgmii_rx_64.v index 8d3f8b9db..32856b368 100644 --- a/rtl/axis_xgmii_rx_64.v +++ b/rtl/axis_xgmii_rx_64.v @@ -66,6 +66,11 @@ module axis_xgmii_rx_64 # */ input wire [PTP_TS_WIDTH-1:0] ptp_ts, + /* + * Configuration + */ + input wire cfg_rx_enable, + /* * Status */ @@ -270,7 +275,7 @@ always @* begin // idle state - wait for packet reset_crc = 1'b1; - if (xgmii_start_d1) begin + if (xgmii_start_d1 && cfg_rx_enable) begin // start condition if (PTP_TS_ENABLE) begin diff --git a/rtl/axis_xgmii_tx_32.v b/rtl/axis_xgmii_tx_32.v index ef6781b5a..a5933061a 100644 --- a/rtl/axis_xgmii_tx_32.v +++ b/rtl/axis_xgmii_tx_32.v @@ -78,6 +78,7 @@ module axis_xgmii_tx_32 # * Configuration */ input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, /* * Status @@ -308,7 +309,7 @@ always @* begin s_tdata_next = s_axis_tdata_masked; s_empty_next = keep2empty(s_axis_tkeep); - if (s_axis_tvalid) begin + if (s_axis_tvalid && cfg_tx_enable) begin // XGMII start and preamble xgmii_txd_next = {{3{ETH_PRE}}, XGMII_START}; xgmii_txc_next = 4'b0001; diff --git a/rtl/axis_xgmii_tx_64.v b/rtl/axis_xgmii_tx_64.v index 0606db81e..c7ee3fd5b 100644 --- a/rtl/axis_xgmii_tx_64.v +++ b/rtl/axis_xgmii_tx_64.v @@ -80,6 +80,7 @@ module axis_xgmii_tx_64 # * Configuration */ input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, /* * Status @@ -335,7 +336,7 @@ always @* begin // idle state - wait for data frame_min_count_next = MIN_FRAME_LENGTH-4-CTRL_WIDTH; reset_crc = 1'b1; - s_axis_tready_next = 1'b1; + s_axis_tready_next = cfg_tx_enable; // XGMII idle xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}}; @@ -344,7 +345,7 @@ always @* begin s_tdata_next = s_axis_tdata_masked; s_empty_next = keep2empty(s_axis_tkeep); - if (s_axis_tvalid) begin + if (s_axis_tvalid && s_axis_tready) begin // XGMII start and preamble if (swap_lanes_reg) begin // lanes swapped @@ -505,14 +506,14 @@ always @* begin ifg_count_next = 8'd0; swap_lanes_next = 1'b0; end - s_axis_tready_next = 1'b1; + s_axis_tready_next = cfg_tx_enable; state_next = STATE_IDLE; end end else begin if (ifg_count_next > 8'd4) begin state_next = STATE_IFG; end else begin - s_axis_tready_next = 1'b1; + s_axis_tready_next = cfg_tx_enable; swap_lanes_next = ifg_count_next != 0; state_next = STATE_IDLE; end @@ -538,14 +539,14 @@ always @* begin ifg_count_next = 8'd0; swap_lanes_next = 1'b0; end - s_axis_tready_next = 1'b1; + s_axis_tready_next = cfg_tx_enable; state_next = STATE_IDLE; end end else begin if (ifg_count_next > 8'd4) begin state_next = STATE_IFG; end else begin - s_axis_tready_next = 1'b1; + s_axis_tready_next = cfg_tx_enable; swap_lanes_next = ifg_count_next != 0; state_next = STATE_IDLE; end @@ -577,14 +578,14 @@ always @* begin ifg_count_next = 8'd0; swap_lanes_next = 1'b0; end - s_axis_tready_next = 1'b1; + s_axis_tready_next = cfg_tx_enable; state_next = STATE_IDLE; end end else begin if (ifg_count_next > 8'd4) begin state_next = STATE_IFG; end else begin - s_axis_tready_next = 1'b1; + s_axis_tready_next = cfg_tx_enable; swap_lanes_next = ifg_count_next != 0; state_next = STATE_IDLE; end diff --git a/rtl/eth_mac_10g.v b/rtl/eth_mac_10g.v index 27d330cbb..c64f5aae2 100644 --- a/rtl/eth_mac_10g.v +++ b/rtl/eth_mac_10g.v @@ -151,6 +151,8 @@ module eth_mac_10g # * Configuration */ input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, + input wire cfg_rx_enable, input wire [47:0] cfg_mcf_rx_eth_dst_mcast, input wire cfg_mcf_rx_check_eth_dst_mcast, input wire [47:0] cfg_mcf_rx_eth_dst_ucast, @@ -238,6 +240,7 @@ axis_xgmii_rx_inst ( .m_axis_tlast(rx_axis_tlast_int), .m_axis_tuser(rx_axis_tuser_int), .ptp_ts(rx_ptp_ts), + .cfg_rx_enable(cfg_rx_enable), .start_packet(rx_start_packet), .error_bad_frame(rx_error_bad_frame), .error_bad_fcs(rx_error_bad_fcs) @@ -275,6 +278,7 @@ axis_xgmii_tx_inst ( .m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag), .m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid), .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), .start_packet(tx_start_packet), .error_underflow(tx_error_underflow) ); @@ -300,6 +304,7 @@ axis_xgmii_rx_inst ( .m_axis_tlast(rx_axis_tlast_int), .m_axis_tuser(rx_axis_tuser_int), .ptp_ts(rx_ptp_ts), + .cfg_rx_enable(cfg_rx_enable), .start_packet(rx_start_packet[0]), .error_bad_frame(rx_error_bad_frame), .error_bad_fcs(rx_error_bad_fcs) @@ -337,6 +342,7 @@ axis_xgmii_tx_inst ( .m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag), .m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid), .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), .start_packet(tx_start_packet[0]), .error_underflow(tx_error_underflow) ); diff --git a/rtl/eth_mac_10g_fifo.v b/rtl/eth_mac_10g_fifo.v index 3acc04edd..7bba80a28 100644 --- a/rtl/eth_mac_10g_fifo.v +++ b/rtl/eth_mac_10g_fifo.v @@ -133,7 +133,9 @@ module eth_mac_10g_fifo # /* * Configuration */ - input wire [7:0] cfg_ifg + input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, + input wire cfg_rx_enable ); parameter KEEP_WIDTH = DATA_WIDTH/8; @@ -382,7 +384,9 @@ eth_mac_10g_inst ( .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), - .cfg_ifg(cfg_ifg) + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_rx_enable(cfg_rx_enable) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_1g.v b/rtl/eth_mac_1g.v index 49b8cc7ae..84eae7e16 100644 --- a/rtl/eth_mac_1g.v +++ b/rtl/eth_mac_1g.v @@ -154,6 +154,8 @@ module eth_mac_1g # * Configuration */ input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, + input wire cfg_rx_enable, input wire [47:0] cfg_mcf_rx_eth_dst_mcast, input wire cfg_mcf_rx_check_eth_dst_mcast, input wire [47:0] cfg_mcf_rx_eth_dst_ucast, @@ -220,6 +222,7 @@ axis_gmii_rx_inst ( .ptp_ts(rx_ptp_ts), .clk_enable(rx_clk_enable), .mii_select(rx_mii_select), + .cfg_rx_enable(cfg_rx_enable), .start_packet(rx_start_packet), .error_bad_frame(rx_error_bad_frame), .error_bad_fcs(rx_error_bad_fcs) @@ -254,6 +257,7 @@ axis_gmii_tx_inst ( .clk_enable(tx_clk_enable), .mii_select(tx_mii_select), .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), .start_packet(tx_start_packet), .error_underflow(tx_error_underflow) ); diff --git a/rtl/eth_mac_1g_fifo.v b/rtl/eth_mac_1g_fifo.v index e5a629daf..d8b03e86c 100644 --- a/rtl/eth_mac_1g_fifo.v +++ b/rtl/eth_mac_1g_fifo.v @@ -113,7 +113,9 @@ module eth_mac_1g_fifo # /* * Configuration */ - input wire [7:0] cfg_ifg + input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, + input wire cfg_rx_enable ); wire [7:0] tx_fifo_axis_tdata; @@ -219,7 +221,9 @@ eth_mac_1g_inst ( .tx_error_underflow(tx_error_underflow_int), .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), - .cfg_ifg(cfg_ifg) + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_rx_enable(cfg_rx_enable) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_1g_gmii.v b/rtl/eth_mac_1g_gmii.v index bc6912c2b..3ab6f0710 100644 --- a/rtl/eth_mac_1g_gmii.v +++ b/rtl/eth_mac_1g_gmii.v @@ -96,7 +96,9 @@ module eth_mac_1g_gmii # /* * Configuration */ - input wire [7:0] cfg_ifg + input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, + input wire cfg_rx_enable ); wire [7:0] mac_gmii_rxd; @@ -244,7 +246,9 @@ eth_mac_1g_inst ( .tx_error_underflow(tx_error_underflow), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), - .cfg_ifg(cfg_ifg) + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_rx_enable(cfg_rx_enable) ); endmodule diff --git a/rtl/eth_mac_1g_gmii_fifo.v b/rtl/eth_mac_1g_gmii_fifo.v index fa44aae40..5d2b23f42 100644 --- a/rtl/eth_mac_1g_gmii_fifo.v +++ b/rtl/eth_mac_1g_gmii_fifo.v @@ -118,7 +118,9 @@ module eth_mac_1g_gmii_fifo # /* * Configuration */ - input wire [7:0] cfg_ifg + input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, + input wire cfg_rx_enable ); wire tx_clk; @@ -246,7 +248,9 @@ eth_mac_1g_gmii_inst ( .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), .speed(speed_int), - .cfg_ifg(cfg_ifg) + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_rx_enable(cfg_rx_enable) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_1g_rgmii.v b/rtl/eth_mac_1g_rgmii.v index 43218a7fa..3f966d9b3 100644 --- a/rtl/eth_mac_1g_rgmii.v +++ b/rtl/eth_mac_1g_rgmii.v @@ -95,7 +95,9 @@ module eth_mac_1g_rgmii # /* * Configuration */ - input wire [7:0] cfg_ifg + input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, + input wire cfg_rx_enable ); wire [7:0] mac_gmii_rxd; @@ -244,7 +246,9 @@ eth_mac_1g_inst ( .tx_error_underflow(tx_error_underflow), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), - .cfg_ifg(cfg_ifg) + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_rx_enable(cfg_rx_enable) ); endmodule diff --git a/rtl/eth_mac_1g_rgmii_fifo.v b/rtl/eth_mac_1g_rgmii_fifo.v index e7c2418b8..c63af55f4 100644 --- a/rtl/eth_mac_1g_rgmii_fifo.v +++ b/rtl/eth_mac_1g_rgmii_fifo.v @@ -117,7 +117,9 @@ module eth_mac_1g_rgmii_fifo # /* * Configuration */ - input wire [7:0] cfg_ifg + input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, + input wire cfg_rx_enable ); wire tx_clk; @@ -244,7 +246,9 @@ eth_mac_1g_rgmii_inst ( .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), .speed(speed_int), - .cfg_ifg(cfg_ifg) + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_rx_enable(cfg_rx_enable) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_mii.v b/rtl/eth_mac_mii.v index f83e223b4..37e0766f1 100644 --- a/rtl/eth_mac_mii.v +++ b/rtl/eth_mac_mii.v @@ -91,7 +91,9 @@ module eth_mac_mii # /* * Configuration */ - input wire [7:0] cfg_ifg + input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, + input wire cfg_rx_enable ); wire [3:0] mac_mii_rxd; @@ -162,7 +164,9 @@ eth_mac_1g_inst ( .rx_start_packet(rx_start_packet), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), - .cfg_ifg(cfg_ifg) + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_rx_enable(cfg_rx_enable) ); endmodule diff --git a/rtl/eth_mac_mii_fifo.v b/rtl/eth_mac_mii_fifo.v index 5f315fd5a..f6d836919 100644 --- a/rtl/eth_mac_mii_fifo.v +++ b/rtl/eth_mac_mii_fifo.v @@ -111,7 +111,9 @@ module eth_mac_mii_fifo # /* * Configuration */ - input wire [7:0] cfg_ifg + input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, + input wire cfg_rx_enable ); wire tx_clk; @@ -223,7 +225,9 @@ eth_mac_1g_mii_inst ( .tx_error_underflow(tx_error_underflow_int), .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), - .cfg_ifg(cfg_ifg) + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_rx_enable(cfg_rx_enable) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_phy_10g.v b/rtl/eth_mac_phy_10g.v index a176ce9f9..be2a4408c 100644 --- a/rtl/eth_mac_phy_10g.v +++ b/rtl/eth_mac_phy_10g.v @@ -121,6 +121,8 @@ module eth_mac_phy_10g # * Configuration */ input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, + input wire cfg_rx_enable, input wire cfg_tx_prbs31_enable, input wire cfg_rx_prbs31_enable ); @@ -163,6 +165,7 @@ eth_mac_phy_10g_rx_inst ( .rx_block_lock(rx_block_lock), .rx_high_ber(rx_high_ber), .rx_status(rx_status), + .cfg_rx_enable(cfg_rx_enable), .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) ); @@ -204,6 +207,7 @@ eth_mac_phy_10g_tx_inst ( .tx_start_packet(tx_start_packet), .tx_error_underflow(tx_error_underflow), .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) ); diff --git a/rtl/eth_mac_phy_10g_fifo.v b/rtl/eth_mac_phy_10g_fifo.v index 220a3396d..25c1a7ac4 100644 --- a/rtl/eth_mac_phy_10g_fifo.v +++ b/rtl/eth_mac_phy_10g_fifo.v @@ -148,6 +148,8 @@ module eth_mac_phy_10g_fifo # * Configuration */ input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, + input wire cfg_rx_enable, input wire cfg_tx_prbs31_enable, input wire cfg_rx_prbs31_enable ); @@ -426,6 +428,8 @@ eth_mac_phy_10g_inst ( .rx_status(rx_status_int), .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_rx_enable(cfg_rx_enable), .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) diff --git a/rtl/eth_mac_phy_10g_rx.v b/rtl/eth_mac_phy_10g_rx.v index 3f498f0bc..28bf99408 100644 --- a/rtl/eth_mac_phy_10g_rx.v +++ b/rtl/eth_mac_phy_10g_rx.v @@ -90,6 +90,7 @@ module eth_mac_phy_10g_rx # /* * Configuration */ + input wire cfg_rx_enable, input wire cfg_rx_prbs31_enable ); @@ -165,7 +166,8 @@ axis_baser_rx_inst ( .start_packet(rx_start_packet), .error_bad_frame(rx_error_bad_frame), .error_bad_fcs(rx_error_bad_fcs), - .rx_bad_block(rx_bad_block) + .rx_bad_block(rx_bad_block), + .cfg_rx_enable(cfg_rx_enable) ); endmodule diff --git a/rtl/eth_mac_phy_10g_tx.v b/rtl/eth_mac_phy_10g_tx.v index 91c992014..e84ee649a 100644 --- a/rtl/eth_mac_phy_10g_tx.v +++ b/rtl/eth_mac_phy_10g_tx.v @@ -90,6 +90,7 @@ module eth_mac_phy_10g_tx # * Configuration */ input wire [7:0] cfg_ifg, + input wire cfg_tx_enable, input wire cfg_tx_prbs31_enable ); @@ -147,7 +148,8 @@ axis_baser_tx_inst ( .m_axis_ptp_ts_valid(m_axis_ptp_ts_valid), .start_packet(tx_start_packet), .error_underflow(tx_error_underflow), - .cfg_ifg(cfg_ifg) + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable) ); eth_phy_10g_tx_if #( diff --git a/tb/axis_baser_rx_64/test_axis_baser_rx_64.py b/tb/axis_baser_rx_64/test_axis_baser_rx_64.py index 38a2e29c3..8d6330ade 100644 --- a/tb/axis_baser_rx_64/test_axis_baser_rx_64.py +++ b/tb/axis_baser_rx_64/test_axis_baser_rx_64.py @@ -64,6 +64,8 @@ class TB: self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + dut.cfg_rx_enable.setimmediatevalue(0) + async def reset(self): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) @@ -81,6 +83,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.source.ifg = ifg + tb.dut.cfg_rx_enable.value = 1 await tb.reset() diff --git a/tb/axis_baser_tx_64/test_axis_baser_tx_64.py b/tb/axis_baser_tx_64/test_axis_baser_tx_64.py index 4b3cb87ab..1c11aa066 100644 --- a/tb/axis_baser_tx_64/test_axis_baser_tx_64.py +++ b/tb/axis_baser_tx_64/test_axis_baser_tx_64.py @@ -74,6 +74,7 @@ class TB: self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -92,6 +93,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() @@ -136,6 +138,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): byte_width = tb.source.width // 8 tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() diff --git a/tb/axis_gmii_rx/test_axis_gmii_rx.py b/tb/axis_gmii_rx/test_axis_gmii_rx.py index 07605cf7e..ed2c381c4 100644 --- a/tb/axis_gmii_rx/test_axis_gmii_rx.py +++ b/tb/axis_gmii_rx/test_axis_gmii_rx.py @@ -59,6 +59,7 @@ class TB: dut.clk_enable.setimmediatevalue(1) dut.mii_select.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -96,6 +97,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_ tb.source.ifg = ifg tb.dut.mii_select.value = mii_sel + tb.dut.cfg_rx_enable.value = 1 if enable_gen is not None: tb.set_enable_generator(enable_gen()) diff --git a/tb/axis_gmii_tx/test_axis_gmii_tx.py b/tb/axis_gmii_tx/test_axis_gmii_tx.py index 7176204a4..0fb466c59 100644 --- a/tb/axis_gmii_tx/test_axis_gmii_tx.py +++ b/tb/axis_gmii_tx/test_axis_gmii_tx.py @@ -68,6 +68,7 @@ class TB: dut.clk_enable.setimmediatevalue(1) dut.mii_select.setimmediatevalue(0) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -104,6 +105,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_ tb = TB(dut) tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 tb.dut.mii_select.value = mii_sel if enable_gen is not None: diff --git a/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py b/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py index d77a31310..b50138b02 100644 --- a/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py +++ b/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py @@ -53,6 +53,8 @@ class TB: self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + dut.cfg_rx_enable.setimmediatevalue(0) + async def reset(self): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) @@ -70,6 +72,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.source.ifg = ifg + tb.dut.cfg_rx_enable.value = 1 await tb.reset() diff --git a/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py b/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py index 0bd4cf6b9..b5b29735d 100644 --- a/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py +++ b/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py @@ -53,6 +53,8 @@ class TB: self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + dut.cfg_rx_enable.setimmediatevalue(0) + async def reset(self): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) @@ -70,6 +72,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.source.ifg = ifg + tb.dut.cfg_rx_enable.value = 1 await tb.reset() diff --git a/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py b/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py index 790af2da9..6ce0161d7 100644 --- a/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py +++ b/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py @@ -63,6 +63,7 @@ class TB: self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -81,6 +82,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() @@ -121,6 +123,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): byte_width = tb.source.width // 8 tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() diff --git a/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py b/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py index df6708826..54cbf3ed9 100644 --- a/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py +++ b/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py @@ -63,6 +63,7 @@ class TB: self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -81,6 +82,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() @@ -125,6 +127,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): byte_width = tb.source.width // 8 tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() diff --git a/tb/eth_mac_10g/test_eth_mac_10g.py b/tb/eth_mac_10g/test_eth_mac_10g.py index 842ecfa9a..a4c19be2a 100644 --- a/tb/eth_mac_10g/test_eth_mac_10g.py +++ b/tb/eth_mac_10g/test_eth_mac_10g.py @@ -89,6 +89,8 @@ class TB: dut.tx_pause_req.setimmediatevalue(0) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0) dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0) dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0) @@ -142,6 +144,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.xgmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 await tb.reset() @@ -186,6 +189,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.xgmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() @@ -231,6 +235,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): tb.xgmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() @@ -314,6 +319,8 @@ async def run_test_lfc(dut, ifg=12): tb.xgmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 + tb.dut.cfg_rx_enable.value = 1 await tb.reset() @@ -457,6 +464,8 @@ async def run_test_pfc(dut, ifg=12): tb.xgmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 + tb.dut.cfg_rx_enable.value = 1 await tb.reset() diff --git a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py index dc35847f0..5a3343087 100644 --- a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py +++ b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py @@ -76,6 +76,8 @@ class TB: dut.ptp_ts_step.setimmediatevalue(0) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) async def reset(self): self.dut.logic_rst.setimmediatevalue(0) @@ -101,6 +103,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.xgmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 await tb.reset() @@ -149,6 +152,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.xgmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() @@ -198,6 +202,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): tb.xgmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() diff --git a/tb/eth_mac_1g/test_eth_mac_1g.py b/tb/eth_mac_1g/test_eth_mac_1g.py index 1a7a50a07..af2173d52 100644 --- a/tb/eth_mac_1g/test_eth_mac_1g.py +++ b/tb/eth_mac_1g/test_eth_mac_1g.py @@ -96,6 +96,8 @@ class TB: dut.tx_mii_select.setimmediatevalue(0) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0) dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0) dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0) @@ -185,6 +187,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab tb.gmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel @@ -231,6 +234,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab tb.gmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel @@ -274,6 +278,8 @@ async def run_test_lfc(dut, ifg=12, enable_gen=None, mii_sel=True): tb.gmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 + tb.dut.cfg_rx_enable.value = 1 tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel @@ -423,6 +429,8 @@ async def run_test_pfc(dut, ifg=12, enable_gen=None, mii_sel=True): tb.gmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 + tb.dut.cfg_rx_enable.value = 1 tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel diff --git a/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py b/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py index c37e8c268..09109685e 100644 --- a/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py +++ b/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py @@ -67,6 +67,8 @@ class TB: dut.rx_mii_select.setimmediatevalue(0) dut.tx_mii_select.setimmediatevalue(0) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) async def reset(self): self.dut.logic_rst.setimmediatevalue(0) @@ -128,6 +130,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab tb.gmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel @@ -161,6 +164,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab tb.gmii_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel diff --git a/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py b/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py index e0e3cd32a..135bf8d45 100644 --- a/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py +++ b/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py @@ -54,6 +54,8 @@ class TB: self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) async def reset(self): self.dut.gtx_rst.setimmediatevalue(0) @@ -76,6 +78,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb.gmii_phy.rx.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 tb.set_speed(speed) @@ -115,6 +118,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb.gmii_phy.rx.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 tb.set_speed(speed) diff --git a/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py b/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py index c080369f5..1879de718 100644 --- a/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py +++ b/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py @@ -55,6 +55,8 @@ class TB: self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) async def reset(self): self.dut.gtx_rst.setimmediatevalue(0) @@ -80,6 +82,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb.gmii_phy.rx.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 tb.set_speed(speed) @@ -119,6 +122,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb.gmii_phy.rx.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 tb.set_speed(speed) diff --git a/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py b/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py index c19ad0298..ffc4132d7 100644 --- a/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py +++ b/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py @@ -51,6 +51,8 @@ class TB: self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) dut.gtx_clk.setimmediatevalue(0) dut.gtx_clk90.setimmediatevalue(0) @@ -87,6 +89,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb.rgmii_phy.rx.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 await tb.reset() @@ -124,6 +127,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb.rgmii_phy.rx.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() diff --git a/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py b/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py index a6cbcea56..9eb15c404 100644 --- a/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py +++ b/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py @@ -54,6 +54,8 @@ class TB: self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) dut.gtx_clk.setimmediatevalue(0) dut.gtx_clk90.setimmediatevalue(0) @@ -93,6 +95,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb.rgmii_phy.rx.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 await tb.reset() @@ -130,6 +133,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb.rgmii_phy.rx.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() diff --git a/tb/eth_mac_mii/test_eth_mac_mii.py b/tb/eth_mac_mii/test_eth_mac_mii.py index f038895ab..cf6734b81 100644 --- a/tb/eth_mac_mii/test_eth_mac_mii.py +++ b/tb/eth_mac_mii/test_eth_mac_mii.py @@ -51,6 +51,8 @@ class TB: self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -70,6 +72,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb.mii_phy.rx.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 await tb.reset() @@ -97,6 +100,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb.mii_phy.rx.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() diff --git a/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py b/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py index 6da182e21..297f0f3a5 100644 --- a/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py +++ b/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py @@ -54,6 +54,8 @@ class TB: self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) async def reset(self): self.dut.logic_rst.setimmediatevalue(0) @@ -73,6 +75,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb.mii_phy.rx.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 await tb.reset() @@ -100,6 +103,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb.mii_phy.rx.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() diff --git a/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py b/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py index 74b07ba94..13f8f51d5 100644 --- a/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py +++ b/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py @@ -84,6 +84,8 @@ class TB: self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) dut.cfg_tx_prbs31_enable.setimmediatevalue(0) dut.cfg_rx_prbs31_enable.setimmediatevalue(0) @@ -108,6 +110,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.serdes_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 await tb.reset() @@ -161,6 +164,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.serdes_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() @@ -206,6 +210,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): tb.serdes_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() diff --git a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py index b470e789e..d6883df76 100644 --- a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py +++ b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py @@ -87,6 +87,8 @@ class TB: dut.ptp_ts_step.setimmediatevalue(0) dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) dut.cfg_tx_prbs31_enable.setimmediatevalue(0) dut.cfg_rx_prbs31_enable.setimmediatevalue(0) @@ -114,6 +116,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.serdes_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 await tb.reset() @@ -169,6 +172,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.serdes_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() @@ -218,6 +222,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): tb.serdes_source.ifg = ifg tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 await tb.reset() From aaeeb05ac0387a9a9cfd01846143d5dc52653119 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 25 Aug 2023 00:09:38 -0700 Subject: [PATCH 03/19] Fix PHY configuration connections Signed-off-by: Alex Forencich --- .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 32 +-- .../AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/AU200/fpga_25g/rtl/fpga.v | 32 +-- .../AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/AU250/fpga_25g/rtl/fpga.v | 32 +-- .../AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/AU280/fpga_25g/rtl/fpga.v | 32 +-- .../AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/AU50/fpga_25g/rtl/fpga.v | 16 +- .../fpga/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/ExaNIC_X10/fpga/rtl/fpga.v | 8 +- .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/ExaNIC_X25/fpga_25g/rtl/fpga.v | 8 +- .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/HTG9200/fpga_25g/rtl/fpga.v | 144 +++++------ .../rtl/eth_xcvr_phy_wrapper.v | 8 +- .../HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v | 240 +++++++++--------- .../fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/VCU108/fpga_10g/rtl/fpga.v | 16 +- .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/VCU118/fpga_25g/rtl/fpga.v | 32 +-- .../rtl/eth_xcvr_phy_wrapper.v | 8 +- .../VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v | 128 +++++----- .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/VCU1525/fpga_25g/rtl/fpga.v | 32 +-- .../ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/ZCU102/fpga/rtl/fpga.v | 16 +- .../ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/ZCU106/fpga/rtl/fpga.v | 8 +- .../fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 8 +- example/fb2CG/fpga_25g/rtl/fpga.v | 32 +-- 32 files changed, 468 insertions(+), 468 deletions(-) diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index acac5e3f9..c898dcabe 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index da8329b27..9e6aacf4c 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -318,8 +318,8 @@ qsfp_0_phy_0_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_0_rx_block_lock_0), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -368,8 +368,8 @@ qsfp_0_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_0_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -418,8 +418,8 @@ qsfp_0_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_0_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -468,8 +468,8 @@ qsfp_0_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_0_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 1 @@ -573,8 +573,8 @@ qsfp_1_phy_0_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_0), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -623,8 +623,8 @@ qsfp_1_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -673,8 +673,8 @@ qsfp_1_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -723,8 +723,8 @@ qsfp_1_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); assign front_led[0] = qsfp_0_rx_block_lock_0; diff --git a/example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index acac5e3f9..c898dcabe 100644 --- a/example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/AU200/fpga_25g/rtl/fpga.v b/example/AU200/fpga_25g/rtl/fpga.v index 61fbca2c0..fa17cb4cc 100644 --- a/example/AU200/fpga_25g/rtl/fpga.v +++ b/example/AU200/fpga_25g/rtl/fpga.v @@ -428,8 +428,8 @@ qsfp0_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -475,8 +475,8 @@ qsfp0_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -522,8 +522,8 @@ qsfp0_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -569,8 +569,8 @@ qsfp0_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP1 @@ -675,8 +675,8 @@ qsfp1_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -722,8 +722,8 @@ qsfp1_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -769,8 +769,8 @@ qsfp1_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -816,8 +816,8 @@ qsfp1_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); fpga_core diff --git a/example/AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index acac5e3f9..c898dcabe 100644 --- a/example/AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/AU250/fpga_25g/rtl/fpga.v b/example/AU250/fpga_25g/rtl/fpga.v index 61fbca2c0..fa17cb4cc 100644 --- a/example/AU250/fpga_25g/rtl/fpga.v +++ b/example/AU250/fpga_25g/rtl/fpga.v @@ -428,8 +428,8 @@ qsfp0_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -475,8 +475,8 @@ qsfp0_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -522,8 +522,8 @@ qsfp0_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -569,8 +569,8 @@ qsfp0_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP1 @@ -675,8 +675,8 @@ qsfp1_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -722,8 +722,8 @@ qsfp1_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -769,8 +769,8 @@ qsfp1_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -816,8 +816,8 @@ qsfp1_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); fpga_core diff --git a/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index acac5e3f9..c898dcabe 100644 --- a/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/AU280/fpga_25g/rtl/fpga.v b/example/AU280/fpga_25g/rtl/fpga.v index 8e1b33802..e67a86339 100644 --- a/example/AU280/fpga_25g/rtl/fpga.v +++ b/example/AU280/fpga_25g/rtl/fpga.v @@ -305,8 +305,8 @@ qsfp0_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -352,8 +352,8 @@ qsfp0_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -399,8 +399,8 @@ qsfp0_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -446,8 +446,8 @@ qsfp0_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP1 @@ -549,8 +549,8 @@ qsfp1_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -596,8 +596,8 @@ qsfp1_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -643,8 +643,8 @@ qsfp1_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -690,8 +690,8 @@ qsfp1_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); fpga_core diff --git a/example/AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index acac5e3f9..c898dcabe 100644 --- a/example/AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/AU50/fpga_25g/rtl/fpga.v b/example/AU50/fpga_25g/rtl/fpga.v index 0149e3c45..d032b7332 100644 --- a/example/AU50/fpga_25g/rtl/fpga.v +++ b/example/AU50/fpga_25g/rtl/fpga.v @@ -273,8 +273,8 @@ qsfp_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -320,8 +320,8 @@ qsfp_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -367,8 +367,8 @@ qsfp_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -414,8 +414,8 @@ qsfp_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); fpga_core diff --git a/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v b/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v index 2a34f8e0d..d5109f8d6 100644 --- a/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -298,8 +298,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/ExaNIC_X10/fpga/rtl/fpga.v b/example/ExaNIC_X10/fpga/rtl/fpga.v index 836dbeba8..447a2d555 100644 --- a/example/ExaNIC_X10/fpga/rtl/fpga.v +++ b/example/ExaNIC_X10/fpga/rtl/fpga.v @@ -260,8 +260,8 @@ sfp_1_phy_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(sfp_1_rx_block_lock), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -307,8 +307,8 @@ sfp_2_phy_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(sfp_2_rx_block_lock), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); assign sfp_1_led[0] = sfp_1_rx_block_lock; diff --git a/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index bbdbf9dde..6baa85e78 100644 --- a/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -298,8 +298,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/ExaNIC_X25/fpga_25g/rtl/fpga.v b/example/ExaNIC_X25/fpga_25g/rtl/fpga.v index 0860f7765..ae3d0ec6b 100644 --- a/example/ExaNIC_X25/fpga_25g/rtl/fpga.v +++ b/example/ExaNIC_X25/fpga_25g/rtl/fpga.v @@ -260,8 +260,8 @@ sfp_1_phy_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(sfp_1_rx_block_lock), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -307,8 +307,8 @@ sfp_2_phy_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(sfp_2_rx_block_lock), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); assign sfp_1_led[0] = sfp_1_rx_block_lock; diff --git a/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index acac5e3f9..c898dcabe 100644 --- a/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/HTG9200/fpga_25g/rtl/fpga.v b/example/HTG9200/fpga_25g/rtl/fpga.v index 70be6b273..35d3872ba 100644 --- a/example/HTG9200/fpga_25g/rtl/fpga.v +++ b/example/HTG9200/fpga_25g/rtl/fpga.v @@ -489,8 +489,8 @@ qsfp_1_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -536,8 +536,8 @@ qsfp_1_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -583,8 +583,8 @@ qsfp_1_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -630,8 +630,8 @@ qsfp_1_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 2 @@ -732,8 +732,8 @@ qsfp_2_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_2_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -779,8 +779,8 @@ qsfp_2_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_2_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -826,8 +826,8 @@ qsfp_2_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_2_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -873,8 +873,8 @@ qsfp_2_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_2_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 3 @@ -975,8 +975,8 @@ qsfp_3_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_3_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1022,8 +1022,8 @@ qsfp_3_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_3_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1069,8 +1069,8 @@ qsfp_3_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_3_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1116,8 +1116,8 @@ qsfp_3_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_3_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 4 @@ -1218,8 +1218,8 @@ qsfp_4_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_4_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1265,8 +1265,8 @@ qsfp_4_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_4_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1312,8 +1312,8 @@ qsfp_4_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_4_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1359,8 +1359,8 @@ qsfp_4_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_4_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 5 @@ -1461,8 +1461,8 @@ qsfp_5_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_5_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1508,8 +1508,8 @@ qsfp_5_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_5_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1555,8 +1555,8 @@ qsfp_5_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_5_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1602,8 +1602,8 @@ qsfp_5_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_5_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 6 @@ -1704,8 +1704,8 @@ qsfp_6_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_6_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1751,8 +1751,8 @@ qsfp_6_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_6_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1798,8 +1798,8 @@ qsfp_6_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_6_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1845,8 +1845,8 @@ qsfp_6_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_6_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 7 @@ -1947,8 +1947,8 @@ qsfp_7_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_7_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1994,8 +1994,8 @@ qsfp_7_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_7_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2041,8 +2041,8 @@ qsfp_7_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_7_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2088,8 +2088,8 @@ qsfp_7_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_7_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 8 @@ -2190,8 +2190,8 @@ qsfp_8_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_8_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2237,8 +2237,8 @@ qsfp_8_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_8_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2284,8 +2284,8 @@ qsfp_8_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_8_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2331,8 +2331,8 @@ qsfp_8_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_8_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 9 @@ -2433,8 +2433,8 @@ qsfp_9_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_9_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2480,8 +2480,8 @@ qsfp_9_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_9_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2527,8 +2527,8 @@ qsfp_9_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_9_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2574,8 +2574,8 @@ qsfp_9_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_9_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); fpga_core diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v index acac5e3f9..c898dcabe 100644 --- a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v index 637495b66..8fa8b2978 100644 --- a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v @@ -601,8 +601,8 @@ qsfp_1_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -648,8 +648,8 @@ qsfp_1_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -695,8 +695,8 @@ qsfp_1_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -742,8 +742,8 @@ qsfp_1_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 2 @@ -844,8 +844,8 @@ qsfp_2_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_2_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -891,8 +891,8 @@ qsfp_2_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_2_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -938,8 +938,8 @@ qsfp_2_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_2_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -985,8 +985,8 @@ qsfp_2_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_2_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 3 @@ -1087,8 +1087,8 @@ qsfp_3_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_3_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1134,8 +1134,8 @@ qsfp_3_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_3_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1181,8 +1181,8 @@ qsfp_3_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_3_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1228,8 +1228,8 @@ qsfp_3_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_3_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 4 @@ -1330,8 +1330,8 @@ qsfp_4_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_4_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1377,8 +1377,8 @@ qsfp_4_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_4_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1424,8 +1424,8 @@ qsfp_4_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_4_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1471,8 +1471,8 @@ qsfp_4_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_4_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 5 @@ -1573,8 +1573,8 @@ qsfp_5_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_5_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1620,8 +1620,8 @@ qsfp_5_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_5_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1667,8 +1667,8 @@ qsfp_5_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_5_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1714,8 +1714,8 @@ qsfp_5_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_5_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 6 @@ -1816,8 +1816,8 @@ qsfp_6_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_6_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1863,8 +1863,8 @@ qsfp_6_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_6_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1910,8 +1910,8 @@ qsfp_6_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_6_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1957,8 +1957,8 @@ qsfp_6_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_6_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 7 @@ -2059,8 +2059,8 @@ qsfp_7_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_7_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2106,8 +2106,8 @@ qsfp_7_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_7_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2153,8 +2153,8 @@ qsfp_7_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_7_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2200,8 +2200,8 @@ qsfp_7_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_7_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 8 @@ -2302,8 +2302,8 @@ qsfp_8_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_8_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2349,8 +2349,8 @@ qsfp_8_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_8_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2396,8 +2396,8 @@ qsfp_8_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_8_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2443,8 +2443,8 @@ qsfp_8_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_8_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP 9 @@ -2545,8 +2545,8 @@ qsfp_9_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_9_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2592,8 +2592,8 @@ qsfp_9_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_9_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2639,8 +2639,8 @@ qsfp_9_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_9_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2686,8 +2686,8 @@ qsfp_9_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_9_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP 1 @@ -2790,8 +2790,8 @@ fmc_qsfp_1_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2837,8 +2837,8 @@ fmc_qsfp_1_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2884,8 +2884,8 @@ fmc_qsfp_1_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2931,8 +2931,8 @@ fmc_qsfp_1_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP 2 @@ -3035,8 +3035,8 @@ fmc_qsfp_2_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -3082,8 +3082,8 @@ fmc_qsfp_2_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -3129,8 +3129,8 @@ fmc_qsfp_2_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -3176,8 +3176,8 @@ fmc_qsfp_2_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP 3 @@ -3280,8 +3280,8 @@ fmc_qsfp_3_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -3327,8 +3327,8 @@ fmc_qsfp_3_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -3374,8 +3374,8 @@ fmc_qsfp_3_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -3421,8 +3421,8 @@ fmc_qsfp_3_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP 4 @@ -3525,8 +3525,8 @@ fmc_qsfp_4_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -3572,8 +3572,8 @@ fmc_qsfp_4_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -3619,8 +3619,8 @@ fmc_qsfp_4_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -3666,8 +3666,8 @@ fmc_qsfp_4_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP 5 @@ -3770,8 +3770,8 @@ fmc_qsfp_5_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -3817,8 +3817,8 @@ fmc_qsfp_5_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -3864,8 +3864,8 @@ fmc_qsfp_5_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -3911,8 +3911,8 @@ fmc_qsfp_5_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP 6 @@ -4015,8 +4015,8 @@ fmc_qsfp_6_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -4062,8 +4062,8 @@ fmc_qsfp_6_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -4109,8 +4109,8 @@ fmc_qsfp_6_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -4156,8 +4156,8 @@ fmc_qsfp_6_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); fpga_core diff --git a/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index acac5e3f9..c898dcabe 100644 --- a/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/VCU108/fpga_10g/rtl/fpga.v b/example/VCU108/fpga_10g/rtl/fpga.v index 7327fbb6d..1d41c176c 100644 --- a/example/VCU108/fpga_10g/rtl/fpga.v +++ b/example/VCU108/fpga_10g/rtl/fpga.v @@ -368,8 +368,8 @@ qsfp_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -415,8 +415,8 @@ qsfp_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -462,8 +462,8 @@ qsfp_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -509,8 +509,8 @@ qsfp_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // SGMII interface to PHY diff --git a/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index acac5e3f9..c898dcabe 100644 --- a/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/VCU118/fpga_25g/rtl/fpga.v b/example/VCU118/fpga_25g/rtl/fpga.v index 9a9154f1e..30b580ab2 100644 --- a/example/VCU118/fpga_25g/rtl/fpga.v +++ b/example/VCU118/fpga_25g/rtl/fpga.v @@ -403,8 +403,8 @@ qsfp1_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -453,8 +453,8 @@ qsfp1_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -503,8 +503,8 @@ qsfp1_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -553,8 +553,8 @@ qsfp1_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP2 @@ -650,8 +650,8 @@ qsfp2_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp2_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -700,8 +700,8 @@ qsfp2_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp2_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -750,8 +750,8 @@ qsfp2_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp2_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -800,8 +800,8 @@ qsfp2_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp2_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // SGMII interface to PHY diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v index acac5e3f9..c898dcabe 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v index eacf0b8e5..7e8b9d95e 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v @@ -585,8 +585,8 @@ qsfp1_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -635,8 +635,8 @@ qsfp1_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -685,8 +685,8 @@ qsfp1_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -735,8 +735,8 @@ qsfp1_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP2 @@ -832,8 +832,8 @@ qsfp2_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp2_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -882,8 +882,8 @@ qsfp2_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp2_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -932,8 +932,8 @@ qsfp2_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp2_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -982,8 +982,8 @@ qsfp2_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp2_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP1 @@ -1086,8 +1086,8 @@ fmcp_qsfp1_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1133,8 +1133,8 @@ fmcp_qsfp1_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1180,8 +1180,8 @@ fmcp_qsfp1_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1227,8 +1227,8 @@ fmcp_qsfp1_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP2 @@ -1331,8 +1331,8 @@ fmcp_qsfp2_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1378,8 +1378,8 @@ fmcp_qsfp2_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1425,8 +1425,8 @@ fmcp_qsfp2_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1472,8 +1472,8 @@ fmcp_qsfp2_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP3 @@ -1576,8 +1576,8 @@ fmcp_qsfp3_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1623,8 +1623,8 @@ fmcp_qsfp3_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1670,8 +1670,8 @@ fmcp_qsfp3_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1717,8 +1717,8 @@ fmcp_qsfp3_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP4 @@ -1821,8 +1821,8 @@ fmcp_qsfp4_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1868,8 +1868,8 @@ fmcp_qsfp4_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1915,8 +1915,8 @@ fmcp_qsfp4_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -1962,8 +1962,8 @@ fmcp_qsfp4_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP5 @@ -2066,8 +2066,8 @@ fmcp_qsfp5_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2113,8 +2113,8 @@ fmcp_qsfp5_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2160,8 +2160,8 @@ fmcp_qsfp5_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2207,8 +2207,8 @@ fmcp_qsfp5_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP6 @@ -2311,8 +2311,8 @@ fmcp_qsfp6_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2358,8 +2358,8 @@ fmcp_qsfp6_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2405,8 +2405,8 @@ fmcp_qsfp6_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -2452,8 +2452,8 @@ fmcp_qsfp6_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // SGMII interface to PHY diff --git a/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index acac5e3f9..c898dcabe 100644 --- a/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/VCU1525/fpga_25g/rtl/fpga.v b/example/VCU1525/fpga_25g/rtl/fpga.v index 61fbca2c0..fa17cb4cc 100644 --- a/example/VCU1525/fpga_25g/rtl/fpga.v +++ b/example/VCU1525/fpga_25g/rtl/fpga.v @@ -428,8 +428,8 @@ qsfp0_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -475,8 +475,8 @@ qsfp0_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -522,8 +522,8 @@ qsfp0_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -569,8 +569,8 @@ qsfp0_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp0_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP1 @@ -675,8 +675,8 @@ qsfp1_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -722,8 +722,8 @@ qsfp1_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -769,8 +769,8 @@ qsfp1_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -816,8 +816,8 @@ qsfp1_phy_4_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp1_rx_block_lock_4), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); fpga_core diff --git a/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v b/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v index bbbfd08d6..84908a1f2 100644 --- a/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/ZCU102/fpga/rtl/fpga.v b/example/ZCU102/fpga/rtl/fpga.v index 58a0ed8af..ddf539a18 100644 --- a/example/ZCU102/fpga/rtl/fpga.v +++ b/example/ZCU102/fpga/rtl/fpga.v @@ -343,8 +343,8 @@ sfp0_phy_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(sfp0_rx_block_lock), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -390,8 +390,8 @@ sfp1_phy_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(sfp1_rx_block_lock), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -437,8 +437,8 @@ sfp2_phy_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(sfp2_rx_block_lock), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -484,8 +484,8 @@ sfp3_phy_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(sfp3_rx_block_lock), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); fpga_core diff --git a/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v b/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v index bbbfd08d6..84908a1f2 100644 --- a/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/ZCU106/fpga/rtl/fpga.v b/example/ZCU106/fpga/rtl/fpga.v index 10bd47d76..4023fed12 100644 --- a/example/ZCU106/fpga/rtl/fpga.v +++ b/example/ZCU106/fpga/rtl/fpga.v @@ -304,8 +304,8 @@ sfp0_phy_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(sfp0_rx_block_lock), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -351,8 +351,8 @@ sfp1_phy_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(sfp1_rx_block_lock), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); fpga_core diff --git a/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index acac5e3f9..c898dcabe 100644 --- a/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable ); wire phy_rx_reset_req; @@ -290,8 +290,8 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); endmodule diff --git a/example/fb2CG/fpga_25g/rtl/fpga.v b/example/fb2CG/fpga_25g/rtl/fpga.v index 19cb236ff..b34def624 100644 --- a/example/fb2CG/fpga_25g/rtl/fpga.v +++ b/example/fb2CG/fpga_25g/rtl/fpga.v @@ -364,8 +364,8 @@ qsfp_0_phy_0_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_0_rx_block_lock_0), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -411,8 +411,8 @@ qsfp_0_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_0_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -458,8 +458,8 @@ qsfp_0_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_0_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -505,8 +505,8 @@ qsfp_0_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_0_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); // QSFP1 @@ -633,8 +633,8 @@ qsfp_1_phy_0_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_0), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -680,8 +680,8 @@ qsfp_1_phy_1_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_1), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -727,8 +727,8 @@ qsfp_1_phy_2_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_2), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); eth_xcvr_phy_wrapper #( @@ -774,8 +774,8 @@ qsfp_1_phy_3_inst ( .phy_rx_sequence_error(), .phy_rx_block_lock(qsfp_1_rx_block_lock_3), .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() + .phy_cfg_tx_prbs31_enable(1'b0), + .phy_cfg_rx_prbs31_enable(1'b0) ); assign led_green[0] = qsfp_0_rx_block_lock_0; From 75c2cc0acc05b0a98ccf25efdeafbe7c0dd85423 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 25 Aug 2023 01:24:26 -0700 Subject: [PATCH 04/19] Use quad wrappers in HTG9200 example designs Signed-off-by: Alex Forencich --- example/HTG9200/fpga_25g/fpga/Makefile | 1 + example/HTG9200/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++ .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/HTG9200/fpga_25g/rtl/fpga.v | 2385 ++++------ .../fpga_fmc_htg_6qsfp_25g/fpga/Makefile | 1 + .../fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile | 1 + .../rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++ .../rtl/eth_xcvr_phy_wrapper.v | 18 +- .../HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v | 3915 ++++++----------- 10 files changed, 2824 insertions(+), 4306 deletions(-) create mode 100644 example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/HTG9200/fpga_25g/fpga/Makefile b/example/HTG9200/fpga_25g/fpga/Makefile index 578e97b42..1ec3cbda9 100644 --- a/example/HTG9200/fpga_25g/fpga/Makefile +++ b/example/HTG9200/fpga_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/i2c_master.v diff --git a/example/HTG9200/fpga_25g/fpga_10g/Makefile b/example/HTG9200/fpga_25g/fpga_10g/Makefile index 578e97b42..1ec3cbda9 100644 --- a/example/HTG9200/fpga_25g/fpga_10g/Makefile +++ b/example/HTG9200/fpga_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/i2c_master.v diff --git a/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/HTG9200/fpga_25g/rtl/fpga.v b/example/HTG9200/fpga_25g/rtl/fpga.v index 35d3872ba..7fb1723b7 100644 --- a/example/HTG9200/fpga_25g/rtl/fpga.v +++ b/example/HTG9200/fpga_25g/rtl/fpga.v @@ -442,196 +442,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_1_qpll0lock; -wire qsfp_1_qpll0outclk; -wire qsfp_1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_1_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_1_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_1_tx_p), + .xcvr_txn(qsfp_1_tx_n), + .xcvr_rxp(qsfp_1_rx_p), + .xcvr_rxn(qsfp_1_rx_n), - // Serial data - .xcvr_txp(qsfp_1_tx_p[0]), - .xcvr_txn(qsfp_1_tx_n[0]), - .xcvr_rxp(qsfp_1_rx_p[0]), - .xcvr_rxn(qsfp_1_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_1_tx_clk_1_int), + .phy_1_tx_rst(qsfp_1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_1_txd_1_int), + .phy_1_xgmii_txc(qsfp_1_txc_1_int), + .phy_1_rx_clk(qsfp_1_rx_clk_1_int), + .phy_1_rx_rst(qsfp_1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_1_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_1_int), - .phy_tx_rst(qsfp_1_tx_rst_1_int), - .phy_xgmii_txd(qsfp_1_txd_1_int), - .phy_xgmii_txc(qsfp_1_txc_1_int), - .phy_rx_clk(qsfp_1_rx_clk_1_int), - .phy_rx_rst(qsfp_1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_1_rxd_1_int), - .phy_xgmii_rxc(qsfp_1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_1_tx_clk_2_int), + .phy_2_tx_rst(qsfp_1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_1_txd_2_int), + .phy_2_xgmii_txc(qsfp_1_txc_2_int), + .phy_2_rx_clk(qsfp_1_rx_clk_2_int), + .phy_2_rx_rst(qsfp_1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_1_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_1_tx_clk_3_int), + .phy_3_tx_rst(qsfp_1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_1_txd_3_int), + .phy_3_xgmii_txc(qsfp_1_txc_3_int), + .phy_3_rx_clk(qsfp_1_rx_clk_3_int), + .phy_3_rx_rst(qsfp_1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_1_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_p[1]), - .xcvr_txn(qsfp_1_tx_n[1]), - .xcvr_rxp(qsfp_1_rx_p[1]), - .xcvr_rxn(qsfp_1_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_2_int), - .phy_tx_rst(qsfp_1_tx_rst_2_int), - .phy_xgmii_txd(qsfp_1_txd_2_int), - .phy_xgmii_txc(qsfp_1_txc_2_int), - .phy_rx_clk(qsfp_1_rx_clk_2_int), - .phy_rx_rst(qsfp_1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_1_rxd_2_int), - .phy_xgmii_rxc(qsfp_1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_p[2]), - .xcvr_txn(qsfp_1_tx_n[2]), - .xcvr_rxp(qsfp_1_rx_p[2]), - .xcvr_rxn(qsfp_1_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_3_int), - .phy_tx_rst(qsfp_1_tx_rst_3_int), - .phy_xgmii_txd(qsfp_1_txd_3_int), - .phy_xgmii_txc(qsfp_1_txc_3_int), - .phy_rx_clk(qsfp_1_rx_clk_3_int), - .phy_rx_rst(qsfp_1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_1_rxd_3_int), - .phy_xgmii_rxc(qsfp_1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_p[3]), - .xcvr_txn(qsfp_1_tx_n[3]), - .xcvr_rxp(qsfp_1_rx_p[3]), - .xcvr_rxn(qsfp_1_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_4_int), - .phy_tx_rst(qsfp_1_tx_rst_4_int), - .phy_xgmii_txd(qsfp_1_txd_4_int), - .phy_xgmii_txc(qsfp_1_txc_4_int), - .phy_rx_clk(qsfp_1_rx_clk_4_int), - .phy_rx_rst(qsfp_1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_1_rxd_4_int), - .phy_xgmii_rxc(qsfp_1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_1_tx_clk_4_int), + .phy_4_tx_rst(qsfp_1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_1_txd_4_int), + .phy_4_xgmii_txc(qsfp_1_txc_4_int), + .phy_4_rx_clk(qsfp_1_rx_clk_4_int), + .phy_4_rx_rst(qsfp_1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_1_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 2 @@ -685,196 +592,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_2_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_2_qpll0lock; -wire qsfp_2_qpll0outclk; -wire qsfp_2_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_2_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_2_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_2_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_2_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_2_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_2_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_2_tx_p), + .xcvr_txn(qsfp_2_tx_n), + .xcvr_rxp(qsfp_2_rx_p), + .xcvr_rxn(qsfp_2_rx_n), - // Serial data - .xcvr_txp(qsfp_2_tx_p[0]), - .xcvr_txn(qsfp_2_tx_n[0]), - .xcvr_rxp(qsfp_2_rx_p[0]), - .xcvr_rxn(qsfp_2_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_2_tx_clk_1_int), + .phy_1_tx_rst(qsfp_2_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_2_txd_1_int), + .phy_1_xgmii_txc(qsfp_2_txc_1_int), + .phy_1_rx_clk(qsfp_2_rx_clk_1_int), + .phy_1_rx_rst(qsfp_2_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_2_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_2_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_2_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_2_tx_clk_1_int), - .phy_tx_rst(qsfp_2_tx_rst_1_int), - .phy_xgmii_txd(qsfp_2_txd_1_int), - .phy_xgmii_txc(qsfp_2_txc_1_int), - .phy_rx_clk(qsfp_2_rx_clk_1_int), - .phy_rx_rst(qsfp_2_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_2_rxd_1_int), - .phy_xgmii_rxc(qsfp_2_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_2_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_2_tx_clk_2_int), + .phy_2_tx_rst(qsfp_2_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_2_txd_2_int), + .phy_2_xgmii_txc(qsfp_2_txc_2_int), + .phy_2_rx_clk(qsfp_2_rx_clk_2_int), + .phy_2_rx_rst(qsfp_2_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_2_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_2_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_2_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_2_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_2_tx_clk_3_int), + .phy_3_tx_rst(qsfp_2_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_2_txd_3_int), + .phy_3_xgmii_txc(qsfp_2_txc_3_int), + .phy_3_rx_clk(qsfp_2_rx_clk_3_int), + .phy_3_rx_rst(qsfp_2_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_2_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_2_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_2_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_2_tx_p[1]), - .xcvr_txn(qsfp_2_tx_n[1]), - .xcvr_rxp(qsfp_2_rx_p[1]), - .xcvr_rxn(qsfp_2_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_2_tx_clk_2_int), - .phy_tx_rst(qsfp_2_tx_rst_2_int), - .phy_xgmii_txd(qsfp_2_txd_2_int), - .phy_xgmii_txc(qsfp_2_txc_2_int), - .phy_rx_clk(qsfp_2_rx_clk_2_int), - .phy_rx_rst(qsfp_2_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_2_rxd_2_int), - .phy_xgmii_rxc(qsfp_2_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_2_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_2_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_2_tx_p[2]), - .xcvr_txn(qsfp_2_tx_n[2]), - .xcvr_rxp(qsfp_2_rx_p[2]), - .xcvr_rxn(qsfp_2_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_2_tx_clk_3_int), - .phy_tx_rst(qsfp_2_tx_rst_3_int), - .phy_xgmii_txd(qsfp_2_txd_3_int), - .phy_xgmii_txc(qsfp_2_txc_3_int), - .phy_rx_clk(qsfp_2_rx_clk_3_int), - .phy_rx_rst(qsfp_2_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_2_rxd_3_int), - .phy_xgmii_rxc(qsfp_2_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_2_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_2_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_2_tx_p[3]), - .xcvr_txn(qsfp_2_tx_n[3]), - .xcvr_rxp(qsfp_2_rx_p[3]), - .xcvr_rxn(qsfp_2_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_2_tx_clk_4_int), - .phy_tx_rst(qsfp_2_tx_rst_4_int), - .phy_xgmii_txd(qsfp_2_txd_4_int), - .phy_xgmii_txc(qsfp_2_txc_4_int), - .phy_rx_clk(qsfp_2_rx_clk_4_int), - .phy_rx_rst(qsfp_2_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_2_rxd_4_int), - .phy_xgmii_rxc(qsfp_2_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_2_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_2_tx_clk_4_int), + .phy_4_tx_rst(qsfp_2_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_2_txd_4_int), + .phy_4_xgmii_txc(qsfp_2_txc_4_int), + .phy_4_rx_clk(qsfp_2_rx_clk_4_int), + .phy_4_rx_rst(qsfp_2_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_2_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_2_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_2_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 3 @@ -928,196 +742,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_3_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_3_qpll0lock; -wire qsfp_3_qpll0outclk; -wire qsfp_3_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_3_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_3_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_3_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_3_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_3_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_3_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_3_tx_p), + .xcvr_txn(qsfp_3_tx_n), + .xcvr_rxp(qsfp_3_rx_p), + .xcvr_rxn(qsfp_3_rx_n), - // Serial data - .xcvr_txp(qsfp_3_tx_p[0]), - .xcvr_txn(qsfp_3_tx_n[0]), - .xcvr_rxp(qsfp_3_rx_p[0]), - .xcvr_rxn(qsfp_3_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_3_tx_clk_1_int), + .phy_1_tx_rst(qsfp_3_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_3_txd_1_int), + .phy_1_xgmii_txc(qsfp_3_txc_1_int), + .phy_1_rx_clk(qsfp_3_rx_clk_1_int), + .phy_1_rx_rst(qsfp_3_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_3_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_3_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_3_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_3_tx_clk_1_int), - .phy_tx_rst(qsfp_3_tx_rst_1_int), - .phy_xgmii_txd(qsfp_3_txd_1_int), - .phy_xgmii_txc(qsfp_3_txc_1_int), - .phy_rx_clk(qsfp_3_rx_clk_1_int), - .phy_rx_rst(qsfp_3_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_3_rxd_1_int), - .phy_xgmii_rxc(qsfp_3_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_3_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_3_tx_clk_2_int), + .phy_2_tx_rst(qsfp_3_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_3_txd_2_int), + .phy_2_xgmii_txc(qsfp_3_txc_2_int), + .phy_2_rx_clk(qsfp_3_rx_clk_2_int), + .phy_2_rx_rst(qsfp_3_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_3_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_3_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_3_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_3_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_3_tx_clk_3_int), + .phy_3_tx_rst(qsfp_3_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_3_txd_3_int), + .phy_3_xgmii_txc(qsfp_3_txc_3_int), + .phy_3_rx_clk(qsfp_3_rx_clk_3_int), + .phy_3_rx_rst(qsfp_3_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_3_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_3_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_3_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_3_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_3_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_3_tx_p[1]), - .xcvr_txn(qsfp_3_tx_n[1]), - .xcvr_rxp(qsfp_3_rx_p[1]), - .xcvr_rxn(qsfp_3_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_3_tx_clk_2_int), - .phy_tx_rst(qsfp_3_tx_rst_2_int), - .phy_xgmii_txd(qsfp_3_txd_2_int), - .phy_xgmii_txc(qsfp_3_txc_2_int), - .phy_rx_clk(qsfp_3_rx_clk_2_int), - .phy_rx_rst(qsfp_3_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_3_rxd_2_int), - .phy_xgmii_rxc(qsfp_3_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_3_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_3_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_3_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_3_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_3_tx_p[2]), - .xcvr_txn(qsfp_3_tx_n[2]), - .xcvr_rxp(qsfp_3_rx_p[2]), - .xcvr_rxn(qsfp_3_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_3_tx_clk_3_int), - .phy_tx_rst(qsfp_3_tx_rst_3_int), - .phy_xgmii_txd(qsfp_3_txd_3_int), - .phy_xgmii_txc(qsfp_3_txc_3_int), - .phy_rx_clk(qsfp_3_rx_clk_3_int), - .phy_rx_rst(qsfp_3_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_3_rxd_3_int), - .phy_xgmii_rxc(qsfp_3_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_3_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_3_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_3_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_3_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_3_tx_p[3]), - .xcvr_txn(qsfp_3_tx_n[3]), - .xcvr_rxp(qsfp_3_rx_p[3]), - .xcvr_rxn(qsfp_3_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_3_tx_clk_4_int), - .phy_tx_rst(qsfp_3_tx_rst_4_int), - .phy_xgmii_txd(qsfp_3_txd_4_int), - .phy_xgmii_txc(qsfp_3_txc_4_int), - .phy_rx_clk(qsfp_3_rx_clk_4_int), - .phy_rx_rst(qsfp_3_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_3_rxd_4_int), - .phy_xgmii_rxc(qsfp_3_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_3_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_3_tx_clk_4_int), + .phy_4_tx_rst(qsfp_3_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_3_txd_4_int), + .phy_4_xgmii_txc(qsfp_3_txc_4_int), + .phy_4_rx_clk(qsfp_3_rx_clk_4_int), + .phy_4_rx_rst(qsfp_3_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_3_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_3_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_3_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 4 @@ -1171,196 +892,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_4_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_4_qpll0lock; -wire qsfp_4_qpll0outclk; -wire qsfp_4_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_4_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_4_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_4_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_4_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_4_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_4_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_4_tx_p), + .xcvr_txn(qsfp_4_tx_n), + .xcvr_rxp(qsfp_4_rx_p), + .xcvr_rxn(qsfp_4_rx_n), - // Serial data - .xcvr_txp(qsfp_4_tx_p[0]), - .xcvr_txn(qsfp_4_tx_n[0]), - .xcvr_rxp(qsfp_4_rx_p[0]), - .xcvr_rxn(qsfp_4_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_4_tx_clk_1_int), + .phy_1_tx_rst(qsfp_4_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_4_txd_1_int), + .phy_1_xgmii_txc(qsfp_4_txc_1_int), + .phy_1_rx_clk(qsfp_4_rx_clk_1_int), + .phy_1_rx_rst(qsfp_4_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_4_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_4_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_4_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_4_tx_clk_1_int), - .phy_tx_rst(qsfp_4_tx_rst_1_int), - .phy_xgmii_txd(qsfp_4_txd_1_int), - .phy_xgmii_txc(qsfp_4_txc_1_int), - .phy_rx_clk(qsfp_4_rx_clk_1_int), - .phy_rx_rst(qsfp_4_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_4_rxd_1_int), - .phy_xgmii_rxc(qsfp_4_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_4_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_4_tx_clk_2_int), + .phy_2_tx_rst(qsfp_4_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_4_txd_2_int), + .phy_2_xgmii_txc(qsfp_4_txc_2_int), + .phy_2_rx_clk(qsfp_4_rx_clk_2_int), + .phy_2_rx_rst(qsfp_4_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_4_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_4_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_4_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_4_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_4_tx_clk_3_int), + .phy_3_tx_rst(qsfp_4_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_4_txd_3_int), + .phy_3_xgmii_txc(qsfp_4_txc_3_int), + .phy_3_rx_clk(qsfp_4_rx_clk_3_int), + .phy_3_rx_rst(qsfp_4_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_4_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_4_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_4_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_4_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_4_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_4_tx_p[1]), - .xcvr_txn(qsfp_4_tx_n[1]), - .xcvr_rxp(qsfp_4_rx_p[1]), - .xcvr_rxn(qsfp_4_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_4_tx_clk_2_int), - .phy_tx_rst(qsfp_4_tx_rst_2_int), - .phy_xgmii_txd(qsfp_4_txd_2_int), - .phy_xgmii_txc(qsfp_4_txc_2_int), - .phy_rx_clk(qsfp_4_rx_clk_2_int), - .phy_rx_rst(qsfp_4_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_4_rxd_2_int), - .phy_xgmii_rxc(qsfp_4_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_4_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_4_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_4_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_4_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_4_tx_p[2]), - .xcvr_txn(qsfp_4_tx_n[2]), - .xcvr_rxp(qsfp_4_rx_p[2]), - .xcvr_rxn(qsfp_4_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_4_tx_clk_3_int), - .phy_tx_rst(qsfp_4_tx_rst_3_int), - .phy_xgmii_txd(qsfp_4_txd_3_int), - .phy_xgmii_txc(qsfp_4_txc_3_int), - .phy_rx_clk(qsfp_4_rx_clk_3_int), - .phy_rx_rst(qsfp_4_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_4_rxd_3_int), - .phy_xgmii_rxc(qsfp_4_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_4_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_4_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_4_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_4_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_4_tx_p[3]), - .xcvr_txn(qsfp_4_tx_n[3]), - .xcvr_rxp(qsfp_4_rx_p[3]), - .xcvr_rxn(qsfp_4_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_4_tx_clk_4_int), - .phy_tx_rst(qsfp_4_tx_rst_4_int), - .phy_xgmii_txd(qsfp_4_txd_4_int), - .phy_xgmii_txc(qsfp_4_txc_4_int), - .phy_rx_clk(qsfp_4_rx_clk_4_int), - .phy_rx_rst(qsfp_4_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_4_rxd_4_int), - .phy_xgmii_rxc(qsfp_4_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_4_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_4_tx_clk_4_int), + .phy_4_tx_rst(qsfp_4_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_4_txd_4_int), + .phy_4_xgmii_txc(qsfp_4_txc_4_int), + .phy_4_rx_clk(qsfp_4_rx_clk_4_int), + .phy_4_rx_rst(qsfp_4_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_4_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_4_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_4_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 5 @@ -1414,196 +1042,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_5_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_5_qpll0lock; -wire qsfp_5_qpll0outclk; -wire qsfp_5_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_5_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_5_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_5_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_5_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_5_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_5_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_5_tx_p), + .xcvr_txn(qsfp_5_tx_n), + .xcvr_rxp(qsfp_5_rx_p), + .xcvr_rxn(qsfp_5_rx_n), - // Serial data - .xcvr_txp(qsfp_5_tx_p[0]), - .xcvr_txn(qsfp_5_tx_n[0]), - .xcvr_rxp(qsfp_5_rx_p[0]), - .xcvr_rxn(qsfp_5_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_5_tx_clk_1_int), + .phy_1_tx_rst(qsfp_5_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_5_txd_1_int), + .phy_1_xgmii_txc(qsfp_5_txc_1_int), + .phy_1_rx_clk(qsfp_5_rx_clk_1_int), + .phy_1_rx_rst(qsfp_5_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_5_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_5_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_5_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_5_tx_clk_1_int), - .phy_tx_rst(qsfp_5_tx_rst_1_int), - .phy_xgmii_txd(qsfp_5_txd_1_int), - .phy_xgmii_txc(qsfp_5_txc_1_int), - .phy_rx_clk(qsfp_5_rx_clk_1_int), - .phy_rx_rst(qsfp_5_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_5_rxd_1_int), - .phy_xgmii_rxc(qsfp_5_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_5_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_5_tx_clk_2_int), + .phy_2_tx_rst(qsfp_5_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_5_txd_2_int), + .phy_2_xgmii_txc(qsfp_5_txc_2_int), + .phy_2_rx_clk(qsfp_5_rx_clk_2_int), + .phy_2_rx_rst(qsfp_5_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_5_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_5_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_5_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_5_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_5_tx_clk_3_int), + .phy_3_tx_rst(qsfp_5_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_5_txd_3_int), + .phy_3_xgmii_txc(qsfp_5_txc_3_int), + .phy_3_rx_clk(qsfp_5_rx_clk_3_int), + .phy_3_rx_rst(qsfp_5_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_5_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_5_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_5_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_5_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_5_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_5_tx_p[1]), - .xcvr_txn(qsfp_5_tx_n[1]), - .xcvr_rxp(qsfp_5_rx_p[1]), - .xcvr_rxn(qsfp_5_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_5_tx_clk_2_int), - .phy_tx_rst(qsfp_5_tx_rst_2_int), - .phy_xgmii_txd(qsfp_5_txd_2_int), - .phy_xgmii_txc(qsfp_5_txc_2_int), - .phy_rx_clk(qsfp_5_rx_clk_2_int), - .phy_rx_rst(qsfp_5_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_5_rxd_2_int), - .phy_xgmii_rxc(qsfp_5_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_5_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_5_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_5_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_5_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_5_tx_p[2]), - .xcvr_txn(qsfp_5_tx_n[2]), - .xcvr_rxp(qsfp_5_rx_p[2]), - .xcvr_rxn(qsfp_5_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_5_tx_clk_3_int), - .phy_tx_rst(qsfp_5_tx_rst_3_int), - .phy_xgmii_txd(qsfp_5_txd_3_int), - .phy_xgmii_txc(qsfp_5_txc_3_int), - .phy_rx_clk(qsfp_5_rx_clk_3_int), - .phy_rx_rst(qsfp_5_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_5_rxd_3_int), - .phy_xgmii_rxc(qsfp_5_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_5_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_5_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_5_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_5_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_5_tx_p[3]), - .xcvr_txn(qsfp_5_tx_n[3]), - .xcvr_rxp(qsfp_5_rx_p[3]), - .xcvr_rxn(qsfp_5_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_5_tx_clk_4_int), - .phy_tx_rst(qsfp_5_tx_rst_4_int), - .phy_xgmii_txd(qsfp_5_txd_4_int), - .phy_xgmii_txc(qsfp_5_txc_4_int), - .phy_rx_clk(qsfp_5_rx_clk_4_int), - .phy_rx_rst(qsfp_5_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_5_rxd_4_int), - .phy_xgmii_rxc(qsfp_5_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_5_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_5_tx_clk_4_int), + .phy_4_tx_rst(qsfp_5_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_5_txd_4_int), + .phy_4_xgmii_txc(qsfp_5_txc_4_int), + .phy_4_rx_clk(qsfp_5_rx_clk_4_int), + .phy_4_rx_rst(qsfp_5_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_5_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_5_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_5_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 6 @@ -1657,196 +1192,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_6_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_6_qpll0lock; -wire qsfp_6_qpll0outclk; -wire qsfp_6_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_6_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_6_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_6_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_6_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_6_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_6_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_6_tx_p), + .xcvr_txn(qsfp_6_tx_n), + .xcvr_rxp(qsfp_6_rx_p), + .xcvr_rxn(qsfp_6_rx_n), - // Serial data - .xcvr_txp(qsfp_6_tx_p[0]), - .xcvr_txn(qsfp_6_tx_n[0]), - .xcvr_rxp(qsfp_6_rx_p[0]), - .xcvr_rxn(qsfp_6_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_6_tx_clk_1_int), + .phy_1_tx_rst(qsfp_6_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_6_txd_1_int), + .phy_1_xgmii_txc(qsfp_6_txc_1_int), + .phy_1_rx_clk(qsfp_6_rx_clk_1_int), + .phy_1_rx_rst(qsfp_6_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_6_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_6_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_6_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_6_tx_clk_1_int), - .phy_tx_rst(qsfp_6_tx_rst_1_int), - .phy_xgmii_txd(qsfp_6_txd_1_int), - .phy_xgmii_txc(qsfp_6_txc_1_int), - .phy_rx_clk(qsfp_6_rx_clk_1_int), - .phy_rx_rst(qsfp_6_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_6_rxd_1_int), - .phy_xgmii_rxc(qsfp_6_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_6_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_6_tx_clk_2_int), + .phy_2_tx_rst(qsfp_6_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_6_txd_2_int), + .phy_2_xgmii_txc(qsfp_6_txc_2_int), + .phy_2_rx_clk(qsfp_6_rx_clk_2_int), + .phy_2_rx_rst(qsfp_6_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_6_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_6_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_6_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_6_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_6_tx_clk_3_int), + .phy_3_tx_rst(qsfp_6_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_6_txd_3_int), + .phy_3_xgmii_txc(qsfp_6_txc_3_int), + .phy_3_rx_clk(qsfp_6_rx_clk_3_int), + .phy_3_rx_rst(qsfp_6_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_6_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_6_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_6_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_6_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_6_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_6_tx_p[1]), - .xcvr_txn(qsfp_6_tx_n[1]), - .xcvr_rxp(qsfp_6_rx_p[1]), - .xcvr_rxn(qsfp_6_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_6_tx_clk_2_int), - .phy_tx_rst(qsfp_6_tx_rst_2_int), - .phy_xgmii_txd(qsfp_6_txd_2_int), - .phy_xgmii_txc(qsfp_6_txc_2_int), - .phy_rx_clk(qsfp_6_rx_clk_2_int), - .phy_rx_rst(qsfp_6_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_6_rxd_2_int), - .phy_xgmii_rxc(qsfp_6_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_6_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_6_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_6_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_6_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_6_tx_p[2]), - .xcvr_txn(qsfp_6_tx_n[2]), - .xcvr_rxp(qsfp_6_rx_p[2]), - .xcvr_rxn(qsfp_6_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_6_tx_clk_3_int), - .phy_tx_rst(qsfp_6_tx_rst_3_int), - .phy_xgmii_txd(qsfp_6_txd_3_int), - .phy_xgmii_txc(qsfp_6_txc_3_int), - .phy_rx_clk(qsfp_6_rx_clk_3_int), - .phy_rx_rst(qsfp_6_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_6_rxd_3_int), - .phy_xgmii_rxc(qsfp_6_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_6_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_6_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_6_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_6_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_6_tx_p[3]), - .xcvr_txn(qsfp_6_tx_n[3]), - .xcvr_rxp(qsfp_6_rx_p[3]), - .xcvr_rxn(qsfp_6_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_6_tx_clk_4_int), - .phy_tx_rst(qsfp_6_tx_rst_4_int), - .phy_xgmii_txd(qsfp_6_txd_4_int), - .phy_xgmii_txc(qsfp_6_txc_4_int), - .phy_rx_clk(qsfp_6_rx_clk_4_int), - .phy_rx_rst(qsfp_6_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_6_rxd_4_int), - .phy_xgmii_rxc(qsfp_6_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_6_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_6_tx_clk_4_int), + .phy_4_tx_rst(qsfp_6_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_6_txd_4_int), + .phy_4_xgmii_txc(qsfp_6_txc_4_int), + .phy_4_rx_clk(qsfp_6_rx_clk_4_int), + .phy_4_rx_rst(qsfp_6_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_6_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_6_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_6_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 7 @@ -1900,196 +1342,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_7_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_7_qpll0lock; -wire qsfp_7_qpll0outclk; -wire qsfp_7_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_7_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_7_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_7_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_7_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_7_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_7_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_7_tx_p), + .xcvr_txn(qsfp_7_tx_n), + .xcvr_rxp(qsfp_7_rx_p), + .xcvr_rxn(qsfp_7_rx_n), - // Serial data - .xcvr_txp(qsfp_7_tx_p[0]), - .xcvr_txn(qsfp_7_tx_n[0]), - .xcvr_rxp(qsfp_7_rx_p[0]), - .xcvr_rxn(qsfp_7_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_7_tx_clk_1_int), + .phy_1_tx_rst(qsfp_7_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_7_txd_1_int), + .phy_1_xgmii_txc(qsfp_7_txc_1_int), + .phy_1_rx_clk(qsfp_7_rx_clk_1_int), + .phy_1_rx_rst(qsfp_7_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_7_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_7_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_7_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_7_tx_clk_1_int), - .phy_tx_rst(qsfp_7_tx_rst_1_int), - .phy_xgmii_txd(qsfp_7_txd_1_int), - .phy_xgmii_txc(qsfp_7_txc_1_int), - .phy_rx_clk(qsfp_7_rx_clk_1_int), - .phy_rx_rst(qsfp_7_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_7_rxd_1_int), - .phy_xgmii_rxc(qsfp_7_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_7_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_7_tx_clk_2_int), + .phy_2_tx_rst(qsfp_7_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_7_txd_2_int), + .phy_2_xgmii_txc(qsfp_7_txc_2_int), + .phy_2_rx_clk(qsfp_7_rx_clk_2_int), + .phy_2_rx_rst(qsfp_7_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_7_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_7_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_7_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_7_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_7_tx_clk_3_int), + .phy_3_tx_rst(qsfp_7_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_7_txd_3_int), + .phy_3_xgmii_txc(qsfp_7_txc_3_int), + .phy_3_rx_clk(qsfp_7_rx_clk_3_int), + .phy_3_rx_rst(qsfp_7_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_7_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_7_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_7_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_7_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_7_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_7_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_7_tx_p[1]), - .xcvr_txn(qsfp_7_tx_n[1]), - .xcvr_rxp(qsfp_7_rx_p[1]), - .xcvr_rxn(qsfp_7_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_7_tx_clk_2_int), - .phy_tx_rst(qsfp_7_tx_rst_2_int), - .phy_xgmii_txd(qsfp_7_txd_2_int), - .phy_xgmii_txc(qsfp_7_txc_2_int), - .phy_rx_clk(qsfp_7_rx_clk_2_int), - .phy_rx_rst(qsfp_7_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_7_rxd_2_int), - .phy_xgmii_rxc(qsfp_7_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_7_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_7_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_7_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_7_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_7_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_7_tx_p[2]), - .xcvr_txn(qsfp_7_tx_n[2]), - .xcvr_rxp(qsfp_7_rx_p[2]), - .xcvr_rxn(qsfp_7_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_7_tx_clk_3_int), - .phy_tx_rst(qsfp_7_tx_rst_3_int), - .phy_xgmii_txd(qsfp_7_txd_3_int), - .phy_xgmii_txc(qsfp_7_txc_3_int), - .phy_rx_clk(qsfp_7_rx_clk_3_int), - .phy_rx_rst(qsfp_7_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_7_rxd_3_int), - .phy_xgmii_rxc(qsfp_7_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_7_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_7_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_7_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_7_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_7_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_7_tx_p[3]), - .xcvr_txn(qsfp_7_tx_n[3]), - .xcvr_rxp(qsfp_7_rx_p[3]), - .xcvr_rxn(qsfp_7_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_7_tx_clk_4_int), - .phy_tx_rst(qsfp_7_tx_rst_4_int), - .phy_xgmii_txd(qsfp_7_txd_4_int), - .phy_xgmii_txc(qsfp_7_txc_4_int), - .phy_rx_clk(qsfp_7_rx_clk_4_int), - .phy_rx_rst(qsfp_7_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_7_rxd_4_int), - .phy_xgmii_rxc(qsfp_7_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_7_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_7_tx_clk_4_int), + .phy_4_tx_rst(qsfp_7_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_7_txd_4_int), + .phy_4_xgmii_txc(qsfp_7_txc_4_int), + .phy_4_rx_clk(qsfp_7_rx_clk_4_int), + .phy_4_rx_rst(qsfp_7_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_7_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_7_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_7_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 8 @@ -2143,196 +1492,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_8_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_8_qpll0lock; -wire qsfp_8_qpll0outclk; -wire qsfp_8_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_8_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_8_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_8_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_8_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_8_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_8_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_8_tx_p), + .xcvr_txn(qsfp_8_tx_n), + .xcvr_rxp(qsfp_8_rx_p), + .xcvr_rxn(qsfp_8_rx_n), - // Serial data - .xcvr_txp(qsfp_8_tx_p[0]), - .xcvr_txn(qsfp_8_tx_n[0]), - .xcvr_rxp(qsfp_8_rx_p[0]), - .xcvr_rxn(qsfp_8_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_8_tx_clk_1_int), + .phy_1_tx_rst(qsfp_8_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_8_txd_1_int), + .phy_1_xgmii_txc(qsfp_8_txc_1_int), + .phy_1_rx_clk(qsfp_8_rx_clk_1_int), + .phy_1_rx_rst(qsfp_8_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_8_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_8_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_8_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_8_tx_clk_1_int), - .phy_tx_rst(qsfp_8_tx_rst_1_int), - .phy_xgmii_txd(qsfp_8_txd_1_int), - .phy_xgmii_txc(qsfp_8_txc_1_int), - .phy_rx_clk(qsfp_8_rx_clk_1_int), - .phy_rx_rst(qsfp_8_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_8_rxd_1_int), - .phy_xgmii_rxc(qsfp_8_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_8_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_8_tx_clk_2_int), + .phy_2_tx_rst(qsfp_8_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_8_txd_2_int), + .phy_2_xgmii_txc(qsfp_8_txc_2_int), + .phy_2_rx_clk(qsfp_8_rx_clk_2_int), + .phy_2_rx_rst(qsfp_8_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_8_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_8_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_8_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_8_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_8_tx_clk_3_int), + .phy_3_tx_rst(qsfp_8_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_8_txd_3_int), + .phy_3_xgmii_txc(qsfp_8_txc_3_int), + .phy_3_rx_clk(qsfp_8_rx_clk_3_int), + .phy_3_rx_rst(qsfp_8_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_8_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_8_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_8_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_8_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_8_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_8_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_8_tx_p[1]), - .xcvr_txn(qsfp_8_tx_n[1]), - .xcvr_rxp(qsfp_8_rx_p[1]), - .xcvr_rxn(qsfp_8_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_8_tx_clk_2_int), - .phy_tx_rst(qsfp_8_tx_rst_2_int), - .phy_xgmii_txd(qsfp_8_txd_2_int), - .phy_xgmii_txc(qsfp_8_txc_2_int), - .phy_rx_clk(qsfp_8_rx_clk_2_int), - .phy_rx_rst(qsfp_8_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_8_rxd_2_int), - .phy_xgmii_rxc(qsfp_8_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_8_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_8_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_8_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_8_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_8_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_8_tx_p[2]), - .xcvr_txn(qsfp_8_tx_n[2]), - .xcvr_rxp(qsfp_8_rx_p[2]), - .xcvr_rxn(qsfp_8_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_8_tx_clk_3_int), - .phy_tx_rst(qsfp_8_tx_rst_3_int), - .phy_xgmii_txd(qsfp_8_txd_3_int), - .phy_xgmii_txc(qsfp_8_txc_3_int), - .phy_rx_clk(qsfp_8_rx_clk_3_int), - .phy_rx_rst(qsfp_8_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_8_rxd_3_int), - .phy_xgmii_rxc(qsfp_8_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_8_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_8_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_8_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_8_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_8_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_8_tx_p[3]), - .xcvr_txn(qsfp_8_tx_n[3]), - .xcvr_rxp(qsfp_8_rx_p[3]), - .xcvr_rxn(qsfp_8_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_8_tx_clk_4_int), - .phy_tx_rst(qsfp_8_tx_rst_4_int), - .phy_xgmii_txd(qsfp_8_txd_4_int), - .phy_xgmii_txc(qsfp_8_txc_4_int), - .phy_rx_clk(qsfp_8_rx_clk_4_int), - .phy_rx_rst(qsfp_8_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_8_rxd_4_int), - .phy_xgmii_rxc(qsfp_8_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_8_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_8_tx_clk_4_int), + .phy_4_tx_rst(qsfp_8_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_8_txd_4_int), + .phy_4_xgmii_txc(qsfp_8_txc_4_int), + .phy_4_rx_clk(qsfp_8_rx_clk_4_int), + .phy_4_rx_rst(qsfp_8_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_8_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_8_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_8_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 9 @@ -2386,196 +1642,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_9_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_9_qpll0lock; -wire qsfp_9_qpll0outclk; -wire qsfp_9_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_9_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_9_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_9_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_9_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_9_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_9_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_9_tx_p), + .xcvr_txn(qsfp_9_tx_n), + .xcvr_rxp(qsfp_9_rx_p), + .xcvr_rxn(qsfp_9_rx_n), - // Serial data - .xcvr_txp(qsfp_9_tx_p[0]), - .xcvr_txn(qsfp_9_tx_n[0]), - .xcvr_rxp(qsfp_9_rx_p[0]), - .xcvr_rxn(qsfp_9_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_9_tx_clk_1_int), + .phy_1_tx_rst(qsfp_9_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_9_txd_1_int), + .phy_1_xgmii_txc(qsfp_9_txc_1_int), + .phy_1_rx_clk(qsfp_9_rx_clk_1_int), + .phy_1_rx_rst(qsfp_9_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_9_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_9_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_9_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_9_tx_clk_1_int), - .phy_tx_rst(qsfp_9_tx_rst_1_int), - .phy_xgmii_txd(qsfp_9_txd_1_int), - .phy_xgmii_txc(qsfp_9_txc_1_int), - .phy_rx_clk(qsfp_9_rx_clk_1_int), - .phy_rx_rst(qsfp_9_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_9_rxd_1_int), - .phy_xgmii_rxc(qsfp_9_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_9_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_9_tx_clk_2_int), + .phy_2_tx_rst(qsfp_9_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_9_txd_2_int), + .phy_2_xgmii_txc(qsfp_9_txc_2_int), + .phy_2_rx_clk(qsfp_9_rx_clk_2_int), + .phy_2_rx_rst(qsfp_9_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_9_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_9_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_9_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_9_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_9_tx_clk_3_int), + .phy_3_tx_rst(qsfp_9_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_9_txd_3_int), + .phy_3_xgmii_txc(qsfp_9_txc_3_int), + .phy_3_rx_clk(qsfp_9_rx_clk_3_int), + .phy_3_rx_rst(qsfp_9_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_9_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_9_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_9_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_9_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_9_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_9_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_9_tx_p[1]), - .xcvr_txn(qsfp_9_tx_n[1]), - .xcvr_rxp(qsfp_9_rx_p[1]), - .xcvr_rxn(qsfp_9_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_9_tx_clk_2_int), - .phy_tx_rst(qsfp_9_tx_rst_2_int), - .phy_xgmii_txd(qsfp_9_txd_2_int), - .phy_xgmii_txc(qsfp_9_txc_2_int), - .phy_rx_clk(qsfp_9_rx_clk_2_int), - .phy_rx_rst(qsfp_9_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_9_rxd_2_int), - .phy_xgmii_rxc(qsfp_9_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_9_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_9_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_9_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_9_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_9_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_9_tx_p[2]), - .xcvr_txn(qsfp_9_tx_n[2]), - .xcvr_rxp(qsfp_9_rx_p[2]), - .xcvr_rxn(qsfp_9_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_9_tx_clk_3_int), - .phy_tx_rst(qsfp_9_tx_rst_3_int), - .phy_xgmii_txd(qsfp_9_txd_3_int), - .phy_xgmii_txc(qsfp_9_txc_3_int), - .phy_rx_clk(qsfp_9_rx_clk_3_int), - .phy_rx_rst(qsfp_9_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_9_rxd_3_int), - .phy_xgmii_rxc(qsfp_9_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_9_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_9_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_9_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_9_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_9_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_9_tx_p[3]), - .xcvr_txn(qsfp_9_tx_n[3]), - .xcvr_rxp(qsfp_9_rx_p[3]), - .xcvr_rxn(qsfp_9_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_9_tx_clk_4_int), - .phy_tx_rst(qsfp_9_tx_rst_4_int), - .phy_xgmii_txd(qsfp_9_txd_4_int), - .phy_xgmii_txc(qsfp_9_txc_4_int), - .phy_rx_clk(qsfp_9_rx_clk_4_int), - .phy_rx_rst(qsfp_9_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_9_rxd_4_int), - .phy_xgmii_rxc(qsfp_9_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_9_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_9_tx_clk_4_int), + .phy_4_tx_rst(qsfp_9_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_9_txd_4_int), + .phy_4_xgmii_txc(qsfp_9_txc_4_int), + .phy_4_rx_clk(qsfp_9_rx_clk_4_int), + .phy_4_rx_rst(qsfp_9_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_9_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_9_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_9_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); fpga_core diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/Makefile b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/Makefile index 578e97b42..1ec3cbda9 100644 --- a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/Makefile +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/i2c_master.v diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile index 578e97b42..1ec3cbda9 100644 --- a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/i2c_master.v diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v index 8fa8b2978..2b0110227 100644 --- a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v @@ -554,196 +554,99 @@ OBUFDS obufds_fmc_refclk_inst ( .OB(fmc_sync_c2m_n) ); -wire qsfp_1_qpll0lock; -wire qsfp_1_qpll0outclk; -wire qsfp_1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_1_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(qsfp_1_gtpowergood), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_1_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_1_tx_p), + .xcvr_txn(qsfp_1_tx_n), + .xcvr_rxp(qsfp_1_rx_p), + .xcvr_rxn(qsfp_1_rx_n), - // Serial data - .xcvr_txp(qsfp_1_tx_p[0]), - .xcvr_txn(qsfp_1_tx_n[0]), - .xcvr_rxp(qsfp_1_rx_p[0]), - .xcvr_rxn(qsfp_1_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_1_tx_clk_1_int), + .phy_1_tx_rst(qsfp_1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_1_txd_1_int), + .phy_1_xgmii_txc(qsfp_1_txc_1_int), + .phy_1_rx_clk(qsfp_1_rx_clk_1_int), + .phy_1_rx_rst(qsfp_1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_1_int), - .phy_tx_rst(qsfp_1_tx_rst_1_int), - .phy_xgmii_txd(qsfp_1_txd_1_int), - .phy_xgmii_txc(qsfp_1_txc_1_int), - .phy_rx_clk(qsfp_1_rx_clk_1_int), - .phy_rx_rst(qsfp_1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_1_rxd_1_int), - .phy_xgmii_rxc(qsfp_1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_1_tx_clk_2_int), + .phy_2_tx_rst(qsfp_1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_1_txd_2_int), + .phy_2_xgmii_txc(qsfp_1_txc_2_int), + .phy_2_rx_clk(qsfp_1_rx_clk_2_int), + .phy_2_rx_rst(qsfp_1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_1_tx_clk_3_int), + .phy_3_tx_rst(qsfp_1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_1_txd_3_int), + .phy_3_xgmii_txc(qsfp_1_txc_3_int), + .phy_3_rx_clk(qsfp_1_rx_clk_3_int), + .phy_3_rx_rst(qsfp_1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_p[1]), - .xcvr_txn(qsfp_1_tx_n[1]), - .xcvr_rxp(qsfp_1_rx_p[1]), - .xcvr_rxn(qsfp_1_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_2_int), - .phy_tx_rst(qsfp_1_tx_rst_2_int), - .phy_xgmii_txd(qsfp_1_txd_2_int), - .phy_xgmii_txc(qsfp_1_txc_2_int), - .phy_rx_clk(qsfp_1_rx_clk_2_int), - .phy_rx_rst(qsfp_1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_1_rxd_2_int), - .phy_xgmii_rxc(qsfp_1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_p[2]), - .xcvr_txn(qsfp_1_tx_n[2]), - .xcvr_rxp(qsfp_1_rx_p[2]), - .xcvr_rxn(qsfp_1_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_3_int), - .phy_tx_rst(qsfp_1_tx_rst_3_int), - .phy_xgmii_txd(qsfp_1_txd_3_int), - .phy_xgmii_txc(qsfp_1_txc_3_int), - .phy_rx_clk(qsfp_1_rx_clk_3_int), - .phy_rx_rst(qsfp_1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_1_rxd_3_int), - .phy_xgmii_rxc(qsfp_1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_p[3]), - .xcvr_txn(qsfp_1_tx_n[3]), - .xcvr_rxp(qsfp_1_rx_p[3]), - .xcvr_rxn(qsfp_1_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_4_int), - .phy_tx_rst(qsfp_1_tx_rst_4_int), - .phy_xgmii_txd(qsfp_1_txd_4_int), - .phy_xgmii_txc(qsfp_1_txc_4_int), - .phy_rx_clk(qsfp_1_rx_clk_4_int), - .phy_rx_rst(qsfp_1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_1_rxd_4_int), - .phy_xgmii_rxc(qsfp_1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_1_tx_clk_4_int), + .phy_4_tx_rst(qsfp_1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_1_txd_4_int), + .phy_4_xgmii_txc(qsfp_1_txc_4_int), + .phy_4_rx_clk(qsfp_1_rx_clk_4_int), + .phy_4_rx_rst(qsfp_1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 2 @@ -797,196 +700,99 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_2_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_2_qpll0lock; -wire qsfp_2_qpll0outclk; -wire qsfp_2_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_2_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_2_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_2_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_2_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_2_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_2_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_2_tx_p), + .xcvr_txn(qsfp_2_tx_n), + .xcvr_rxp(qsfp_2_rx_p), + .xcvr_rxn(qsfp_2_rx_n), - // Serial data - .xcvr_txp(qsfp_2_tx_p[0]), - .xcvr_txn(qsfp_2_tx_n[0]), - .xcvr_rxp(qsfp_2_rx_p[0]), - .xcvr_rxn(qsfp_2_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_2_tx_clk_1_int), + .phy_1_tx_rst(qsfp_2_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_2_txd_1_int), + .phy_1_xgmii_txc(qsfp_2_txc_1_int), + .phy_1_rx_clk(qsfp_2_rx_clk_1_int), + .phy_1_rx_rst(qsfp_2_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_2_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_2_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_2_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_2_tx_clk_1_int), - .phy_tx_rst(qsfp_2_tx_rst_1_int), - .phy_xgmii_txd(qsfp_2_txd_1_int), - .phy_xgmii_txc(qsfp_2_txc_1_int), - .phy_rx_clk(qsfp_2_rx_clk_1_int), - .phy_rx_rst(qsfp_2_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_2_rxd_1_int), - .phy_xgmii_rxc(qsfp_2_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_2_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_2_tx_clk_2_int), + .phy_2_tx_rst(qsfp_2_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_2_txd_2_int), + .phy_2_xgmii_txc(qsfp_2_txc_2_int), + .phy_2_rx_clk(qsfp_2_rx_clk_2_int), + .phy_2_rx_rst(qsfp_2_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_2_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_2_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_2_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_2_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_2_tx_clk_3_int), + .phy_3_tx_rst(qsfp_2_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_2_txd_3_int), + .phy_3_xgmii_txc(qsfp_2_txc_3_int), + .phy_3_rx_clk(qsfp_2_rx_clk_3_int), + .phy_3_rx_rst(qsfp_2_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_2_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_2_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_2_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_2_tx_p[1]), - .xcvr_txn(qsfp_2_tx_n[1]), - .xcvr_rxp(qsfp_2_rx_p[1]), - .xcvr_rxn(qsfp_2_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_2_tx_clk_2_int), - .phy_tx_rst(qsfp_2_tx_rst_2_int), - .phy_xgmii_txd(qsfp_2_txd_2_int), - .phy_xgmii_txc(qsfp_2_txc_2_int), - .phy_rx_clk(qsfp_2_rx_clk_2_int), - .phy_rx_rst(qsfp_2_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_2_rxd_2_int), - .phy_xgmii_rxc(qsfp_2_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_2_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_2_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_2_tx_p[2]), - .xcvr_txn(qsfp_2_tx_n[2]), - .xcvr_rxp(qsfp_2_rx_p[2]), - .xcvr_rxn(qsfp_2_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_2_tx_clk_3_int), - .phy_tx_rst(qsfp_2_tx_rst_3_int), - .phy_xgmii_txd(qsfp_2_txd_3_int), - .phy_xgmii_txc(qsfp_2_txc_3_int), - .phy_rx_clk(qsfp_2_rx_clk_3_int), - .phy_rx_rst(qsfp_2_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_2_rxd_3_int), - .phy_xgmii_rxc(qsfp_2_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_2_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_2_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_2_tx_p[3]), - .xcvr_txn(qsfp_2_tx_n[3]), - .xcvr_rxp(qsfp_2_rx_p[3]), - .xcvr_rxn(qsfp_2_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_2_tx_clk_4_int), - .phy_tx_rst(qsfp_2_tx_rst_4_int), - .phy_xgmii_txd(qsfp_2_txd_4_int), - .phy_xgmii_txc(qsfp_2_txc_4_int), - .phy_rx_clk(qsfp_2_rx_clk_4_int), - .phy_rx_rst(qsfp_2_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_2_rxd_4_int), - .phy_xgmii_rxc(qsfp_2_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_2_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_2_tx_clk_4_int), + .phy_4_tx_rst(qsfp_2_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_2_txd_4_int), + .phy_4_xgmii_txc(qsfp_2_txc_4_int), + .phy_4_rx_clk(qsfp_2_rx_clk_4_int), + .phy_4_rx_rst(qsfp_2_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_2_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_2_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_2_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 3 @@ -1040,196 +846,99 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_3_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_3_qpll0lock; -wire qsfp_3_qpll0outclk; -wire qsfp_3_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_3_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_3_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_3_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_3_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_3_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_3_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_3_tx_p), + .xcvr_txn(qsfp_3_tx_n), + .xcvr_rxp(qsfp_3_rx_p), + .xcvr_rxn(qsfp_3_rx_n), - // Serial data - .xcvr_txp(qsfp_3_tx_p[0]), - .xcvr_txn(qsfp_3_tx_n[0]), - .xcvr_rxp(qsfp_3_rx_p[0]), - .xcvr_rxn(qsfp_3_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_3_tx_clk_1_int), + .phy_1_tx_rst(qsfp_3_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_3_txd_1_int), + .phy_1_xgmii_txc(qsfp_3_txc_1_int), + .phy_1_rx_clk(qsfp_3_rx_clk_1_int), + .phy_1_rx_rst(qsfp_3_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_3_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_3_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_3_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_3_tx_clk_1_int), - .phy_tx_rst(qsfp_3_tx_rst_1_int), - .phy_xgmii_txd(qsfp_3_txd_1_int), - .phy_xgmii_txc(qsfp_3_txc_1_int), - .phy_rx_clk(qsfp_3_rx_clk_1_int), - .phy_rx_rst(qsfp_3_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_3_rxd_1_int), - .phy_xgmii_rxc(qsfp_3_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_3_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_3_tx_clk_2_int), + .phy_2_tx_rst(qsfp_3_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_3_txd_2_int), + .phy_2_xgmii_txc(qsfp_3_txc_2_int), + .phy_2_rx_clk(qsfp_3_rx_clk_2_int), + .phy_2_rx_rst(qsfp_3_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_3_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_3_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_3_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_3_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_3_tx_clk_3_int), + .phy_3_tx_rst(qsfp_3_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_3_txd_3_int), + .phy_3_xgmii_txc(qsfp_3_txc_3_int), + .phy_3_rx_clk(qsfp_3_rx_clk_3_int), + .phy_3_rx_rst(qsfp_3_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_3_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_3_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_3_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_3_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_3_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_3_tx_p[1]), - .xcvr_txn(qsfp_3_tx_n[1]), - .xcvr_rxp(qsfp_3_rx_p[1]), - .xcvr_rxn(qsfp_3_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_3_tx_clk_2_int), - .phy_tx_rst(qsfp_3_tx_rst_2_int), - .phy_xgmii_txd(qsfp_3_txd_2_int), - .phy_xgmii_txc(qsfp_3_txc_2_int), - .phy_rx_clk(qsfp_3_rx_clk_2_int), - .phy_rx_rst(qsfp_3_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_3_rxd_2_int), - .phy_xgmii_rxc(qsfp_3_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_3_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_3_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_3_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_3_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_3_tx_p[2]), - .xcvr_txn(qsfp_3_tx_n[2]), - .xcvr_rxp(qsfp_3_rx_p[2]), - .xcvr_rxn(qsfp_3_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_3_tx_clk_3_int), - .phy_tx_rst(qsfp_3_tx_rst_3_int), - .phy_xgmii_txd(qsfp_3_txd_3_int), - .phy_xgmii_txc(qsfp_3_txc_3_int), - .phy_rx_clk(qsfp_3_rx_clk_3_int), - .phy_rx_rst(qsfp_3_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_3_rxd_3_int), - .phy_xgmii_rxc(qsfp_3_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_3_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_3_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_3_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_3_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_3_tx_p[3]), - .xcvr_txn(qsfp_3_tx_n[3]), - .xcvr_rxp(qsfp_3_rx_p[3]), - .xcvr_rxn(qsfp_3_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_3_tx_clk_4_int), - .phy_tx_rst(qsfp_3_tx_rst_4_int), - .phy_xgmii_txd(qsfp_3_txd_4_int), - .phy_xgmii_txc(qsfp_3_txc_4_int), - .phy_rx_clk(qsfp_3_rx_clk_4_int), - .phy_rx_rst(qsfp_3_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_3_rxd_4_int), - .phy_xgmii_rxc(qsfp_3_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_3_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_3_tx_clk_4_int), + .phy_4_tx_rst(qsfp_3_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_3_txd_4_int), + .phy_4_xgmii_txc(qsfp_3_txc_4_int), + .phy_4_rx_clk(qsfp_3_rx_clk_4_int), + .phy_4_rx_rst(qsfp_3_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_3_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_3_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_3_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 4 @@ -1283,196 +992,99 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_4_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_4_qpll0lock; -wire qsfp_4_qpll0outclk; -wire qsfp_4_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_4_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_4_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_4_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_4_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_4_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_4_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_4_tx_p), + .xcvr_txn(qsfp_4_tx_n), + .xcvr_rxp(qsfp_4_rx_p), + .xcvr_rxn(qsfp_4_rx_n), - // Serial data - .xcvr_txp(qsfp_4_tx_p[0]), - .xcvr_txn(qsfp_4_tx_n[0]), - .xcvr_rxp(qsfp_4_rx_p[0]), - .xcvr_rxn(qsfp_4_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_4_tx_clk_1_int), + .phy_1_tx_rst(qsfp_4_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_4_txd_1_int), + .phy_1_xgmii_txc(qsfp_4_txc_1_int), + .phy_1_rx_clk(qsfp_4_rx_clk_1_int), + .phy_1_rx_rst(qsfp_4_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_4_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_4_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_4_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_4_tx_clk_1_int), - .phy_tx_rst(qsfp_4_tx_rst_1_int), - .phy_xgmii_txd(qsfp_4_txd_1_int), - .phy_xgmii_txc(qsfp_4_txc_1_int), - .phy_rx_clk(qsfp_4_rx_clk_1_int), - .phy_rx_rst(qsfp_4_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_4_rxd_1_int), - .phy_xgmii_rxc(qsfp_4_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_4_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_4_tx_clk_2_int), + .phy_2_tx_rst(qsfp_4_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_4_txd_2_int), + .phy_2_xgmii_txc(qsfp_4_txc_2_int), + .phy_2_rx_clk(qsfp_4_rx_clk_2_int), + .phy_2_rx_rst(qsfp_4_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_4_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_4_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_4_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_4_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_4_tx_clk_3_int), + .phy_3_tx_rst(qsfp_4_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_4_txd_3_int), + .phy_3_xgmii_txc(qsfp_4_txc_3_int), + .phy_3_rx_clk(qsfp_4_rx_clk_3_int), + .phy_3_rx_rst(qsfp_4_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_4_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_4_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_4_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_4_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_4_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_4_tx_p[1]), - .xcvr_txn(qsfp_4_tx_n[1]), - .xcvr_rxp(qsfp_4_rx_p[1]), - .xcvr_rxn(qsfp_4_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_4_tx_clk_2_int), - .phy_tx_rst(qsfp_4_tx_rst_2_int), - .phy_xgmii_txd(qsfp_4_txd_2_int), - .phy_xgmii_txc(qsfp_4_txc_2_int), - .phy_rx_clk(qsfp_4_rx_clk_2_int), - .phy_rx_rst(qsfp_4_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_4_rxd_2_int), - .phy_xgmii_rxc(qsfp_4_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_4_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_4_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_4_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_4_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_4_tx_p[2]), - .xcvr_txn(qsfp_4_tx_n[2]), - .xcvr_rxp(qsfp_4_rx_p[2]), - .xcvr_rxn(qsfp_4_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_4_tx_clk_3_int), - .phy_tx_rst(qsfp_4_tx_rst_3_int), - .phy_xgmii_txd(qsfp_4_txd_3_int), - .phy_xgmii_txc(qsfp_4_txc_3_int), - .phy_rx_clk(qsfp_4_rx_clk_3_int), - .phy_rx_rst(qsfp_4_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_4_rxd_3_int), - .phy_xgmii_rxc(qsfp_4_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_4_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_4_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_4_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_4_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_4_tx_p[3]), - .xcvr_txn(qsfp_4_tx_n[3]), - .xcvr_rxp(qsfp_4_rx_p[3]), - .xcvr_rxn(qsfp_4_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_4_tx_clk_4_int), - .phy_tx_rst(qsfp_4_tx_rst_4_int), - .phy_xgmii_txd(qsfp_4_txd_4_int), - .phy_xgmii_txc(qsfp_4_txc_4_int), - .phy_rx_clk(qsfp_4_rx_clk_4_int), - .phy_rx_rst(qsfp_4_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_4_rxd_4_int), - .phy_xgmii_rxc(qsfp_4_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_4_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_4_tx_clk_4_int), + .phy_4_tx_rst(qsfp_4_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_4_txd_4_int), + .phy_4_xgmii_txc(qsfp_4_txc_4_int), + .phy_4_rx_clk(qsfp_4_rx_clk_4_int), + .phy_4_rx_rst(qsfp_4_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_4_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_4_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_4_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 5 @@ -1526,196 +1138,99 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_5_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_5_qpll0lock; -wire qsfp_5_qpll0outclk; -wire qsfp_5_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_5_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_5_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_5_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_5_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_5_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_5_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_5_tx_p), + .xcvr_txn(qsfp_5_tx_n), + .xcvr_rxp(qsfp_5_rx_p), + .xcvr_rxn(qsfp_5_rx_n), - // Serial data - .xcvr_txp(qsfp_5_tx_p[0]), - .xcvr_txn(qsfp_5_tx_n[0]), - .xcvr_rxp(qsfp_5_rx_p[0]), - .xcvr_rxn(qsfp_5_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_5_tx_clk_1_int), + .phy_1_tx_rst(qsfp_5_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_5_txd_1_int), + .phy_1_xgmii_txc(qsfp_5_txc_1_int), + .phy_1_rx_clk(qsfp_5_rx_clk_1_int), + .phy_1_rx_rst(qsfp_5_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_5_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_5_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_5_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_5_tx_clk_1_int), - .phy_tx_rst(qsfp_5_tx_rst_1_int), - .phy_xgmii_txd(qsfp_5_txd_1_int), - .phy_xgmii_txc(qsfp_5_txc_1_int), - .phy_rx_clk(qsfp_5_rx_clk_1_int), - .phy_rx_rst(qsfp_5_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_5_rxd_1_int), - .phy_xgmii_rxc(qsfp_5_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_5_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_5_tx_clk_2_int), + .phy_2_tx_rst(qsfp_5_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_5_txd_2_int), + .phy_2_xgmii_txc(qsfp_5_txc_2_int), + .phy_2_rx_clk(qsfp_5_rx_clk_2_int), + .phy_2_rx_rst(qsfp_5_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_5_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_5_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_5_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_5_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_5_tx_clk_3_int), + .phy_3_tx_rst(qsfp_5_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_5_txd_3_int), + .phy_3_xgmii_txc(qsfp_5_txc_3_int), + .phy_3_rx_clk(qsfp_5_rx_clk_3_int), + .phy_3_rx_rst(qsfp_5_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_5_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_5_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_5_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_5_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_5_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_5_tx_p[1]), - .xcvr_txn(qsfp_5_tx_n[1]), - .xcvr_rxp(qsfp_5_rx_p[1]), - .xcvr_rxn(qsfp_5_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_5_tx_clk_2_int), - .phy_tx_rst(qsfp_5_tx_rst_2_int), - .phy_xgmii_txd(qsfp_5_txd_2_int), - .phy_xgmii_txc(qsfp_5_txc_2_int), - .phy_rx_clk(qsfp_5_rx_clk_2_int), - .phy_rx_rst(qsfp_5_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_5_rxd_2_int), - .phy_xgmii_rxc(qsfp_5_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_5_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_5_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_5_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_5_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_5_tx_p[2]), - .xcvr_txn(qsfp_5_tx_n[2]), - .xcvr_rxp(qsfp_5_rx_p[2]), - .xcvr_rxn(qsfp_5_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_5_tx_clk_3_int), - .phy_tx_rst(qsfp_5_tx_rst_3_int), - .phy_xgmii_txd(qsfp_5_txd_3_int), - .phy_xgmii_txc(qsfp_5_txc_3_int), - .phy_rx_clk(qsfp_5_rx_clk_3_int), - .phy_rx_rst(qsfp_5_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_5_rxd_3_int), - .phy_xgmii_rxc(qsfp_5_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_5_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_5_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_5_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_5_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_5_tx_p[3]), - .xcvr_txn(qsfp_5_tx_n[3]), - .xcvr_rxp(qsfp_5_rx_p[3]), - .xcvr_rxn(qsfp_5_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_5_tx_clk_4_int), - .phy_tx_rst(qsfp_5_tx_rst_4_int), - .phy_xgmii_txd(qsfp_5_txd_4_int), - .phy_xgmii_txc(qsfp_5_txc_4_int), - .phy_rx_clk(qsfp_5_rx_clk_4_int), - .phy_rx_rst(qsfp_5_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_5_rxd_4_int), - .phy_xgmii_rxc(qsfp_5_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_5_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_5_tx_clk_4_int), + .phy_4_tx_rst(qsfp_5_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_5_txd_4_int), + .phy_4_xgmii_txc(qsfp_5_txc_4_int), + .phy_4_rx_clk(qsfp_5_rx_clk_4_int), + .phy_4_rx_rst(qsfp_5_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_5_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_5_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_5_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 6 @@ -1769,196 +1284,99 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_6_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_6_qpll0lock; -wire qsfp_6_qpll0outclk; -wire qsfp_6_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_6_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_6_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_6_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_6_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_6_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_6_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_6_tx_p), + .xcvr_txn(qsfp_6_tx_n), + .xcvr_rxp(qsfp_6_rx_p), + .xcvr_rxn(qsfp_6_rx_n), - // Serial data - .xcvr_txp(qsfp_6_tx_p[0]), - .xcvr_txn(qsfp_6_tx_n[0]), - .xcvr_rxp(qsfp_6_rx_p[0]), - .xcvr_rxn(qsfp_6_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_6_tx_clk_1_int), + .phy_1_tx_rst(qsfp_6_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_6_txd_1_int), + .phy_1_xgmii_txc(qsfp_6_txc_1_int), + .phy_1_rx_clk(qsfp_6_rx_clk_1_int), + .phy_1_rx_rst(qsfp_6_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_6_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_6_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_6_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_6_tx_clk_1_int), - .phy_tx_rst(qsfp_6_tx_rst_1_int), - .phy_xgmii_txd(qsfp_6_txd_1_int), - .phy_xgmii_txc(qsfp_6_txc_1_int), - .phy_rx_clk(qsfp_6_rx_clk_1_int), - .phy_rx_rst(qsfp_6_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_6_rxd_1_int), - .phy_xgmii_rxc(qsfp_6_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_6_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_6_tx_clk_2_int), + .phy_2_tx_rst(qsfp_6_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_6_txd_2_int), + .phy_2_xgmii_txc(qsfp_6_txc_2_int), + .phy_2_rx_clk(qsfp_6_rx_clk_2_int), + .phy_2_rx_rst(qsfp_6_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_6_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_6_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_6_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_6_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_6_tx_clk_3_int), + .phy_3_tx_rst(qsfp_6_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_6_txd_3_int), + .phy_3_xgmii_txc(qsfp_6_txc_3_int), + .phy_3_rx_clk(qsfp_6_rx_clk_3_int), + .phy_3_rx_rst(qsfp_6_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_6_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_6_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_6_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_6_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_6_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_6_tx_p[1]), - .xcvr_txn(qsfp_6_tx_n[1]), - .xcvr_rxp(qsfp_6_rx_p[1]), - .xcvr_rxn(qsfp_6_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_6_tx_clk_2_int), - .phy_tx_rst(qsfp_6_tx_rst_2_int), - .phy_xgmii_txd(qsfp_6_txd_2_int), - .phy_xgmii_txc(qsfp_6_txc_2_int), - .phy_rx_clk(qsfp_6_rx_clk_2_int), - .phy_rx_rst(qsfp_6_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_6_rxd_2_int), - .phy_xgmii_rxc(qsfp_6_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_6_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_6_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_6_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_6_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_6_tx_p[2]), - .xcvr_txn(qsfp_6_tx_n[2]), - .xcvr_rxp(qsfp_6_rx_p[2]), - .xcvr_rxn(qsfp_6_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_6_tx_clk_3_int), - .phy_tx_rst(qsfp_6_tx_rst_3_int), - .phy_xgmii_txd(qsfp_6_txd_3_int), - .phy_xgmii_txc(qsfp_6_txc_3_int), - .phy_rx_clk(qsfp_6_rx_clk_3_int), - .phy_rx_rst(qsfp_6_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_6_rxd_3_int), - .phy_xgmii_rxc(qsfp_6_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_6_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_6_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_6_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_6_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_6_tx_p[3]), - .xcvr_txn(qsfp_6_tx_n[3]), - .xcvr_rxp(qsfp_6_rx_p[3]), - .xcvr_rxn(qsfp_6_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_6_tx_clk_4_int), - .phy_tx_rst(qsfp_6_tx_rst_4_int), - .phy_xgmii_txd(qsfp_6_txd_4_int), - .phy_xgmii_txc(qsfp_6_txc_4_int), - .phy_rx_clk(qsfp_6_rx_clk_4_int), - .phy_rx_rst(qsfp_6_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_6_rxd_4_int), - .phy_xgmii_rxc(qsfp_6_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_6_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_6_tx_clk_4_int), + .phy_4_tx_rst(qsfp_6_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_6_txd_4_int), + .phy_4_xgmii_txc(qsfp_6_txc_4_int), + .phy_4_rx_clk(qsfp_6_rx_clk_4_int), + .phy_4_rx_rst(qsfp_6_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_6_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_6_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_6_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 7 @@ -2012,196 +1430,99 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_7_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_7_qpll0lock; -wire qsfp_7_qpll0outclk; -wire qsfp_7_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_7_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_7_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_7_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_7_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_7_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_7_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_7_tx_p), + .xcvr_txn(qsfp_7_tx_n), + .xcvr_rxp(qsfp_7_rx_p), + .xcvr_rxn(qsfp_7_rx_n), - // Serial data - .xcvr_txp(qsfp_7_tx_p[0]), - .xcvr_txn(qsfp_7_tx_n[0]), - .xcvr_rxp(qsfp_7_rx_p[0]), - .xcvr_rxn(qsfp_7_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_7_tx_clk_1_int), + .phy_1_tx_rst(qsfp_7_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_7_txd_1_int), + .phy_1_xgmii_txc(qsfp_7_txc_1_int), + .phy_1_rx_clk(qsfp_7_rx_clk_1_int), + .phy_1_rx_rst(qsfp_7_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_7_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_7_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_7_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_7_tx_clk_1_int), - .phy_tx_rst(qsfp_7_tx_rst_1_int), - .phy_xgmii_txd(qsfp_7_txd_1_int), - .phy_xgmii_txc(qsfp_7_txc_1_int), - .phy_rx_clk(qsfp_7_rx_clk_1_int), - .phy_rx_rst(qsfp_7_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_7_rxd_1_int), - .phy_xgmii_rxc(qsfp_7_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_7_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_7_tx_clk_2_int), + .phy_2_tx_rst(qsfp_7_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_7_txd_2_int), + .phy_2_xgmii_txc(qsfp_7_txc_2_int), + .phy_2_rx_clk(qsfp_7_rx_clk_2_int), + .phy_2_rx_rst(qsfp_7_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_7_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_7_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_7_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_7_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_7_tx_clk_3_int), + .phy_3_tx_rst(qsfp_7_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_7_txd_3_int), + .phy_3_xgmii_txc(qsfp_7_txc_3_int), + .phy_3_rx_clk(qsfp_7_rx_clk_3_int), + .phy_3_rx_rst(qsfp_7_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_7_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_7_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_7_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_7_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_7_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_7_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_7_tx_p[1]), - .xcvr_txn(qsfp_7_tx_n[1]), - .xcvr_rxp(qsfp_7_rx_p[1]), - .xcvr_rxn(qsfp_7_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_7_tx_clk_2_int), - .phy_tx_rst(qsfp_7_tx_rst_2_int), - .phy_xgmii_txd(qsfp_7_txd_2_int), - .phy_xgmii_txc(qsfp_7_txc_2_int), - .phy_rx_clk(qsfp_7_rx_clk_2_int), - .phy_rx_rst(qsfp_7_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_7_rxd_2_int), - .phy_xgmii_rxc(qsfp_7_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_7_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_7_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_7_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_7_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_7_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_7_tx_p[2]), - .xcvr_txn(qsfp_7_tx_n[2]), - .xcvr_rxp(qsfp_7_rx_p[2]), - .xcvr_rxn(qsfp_7_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_7_tx_clk_3_int), - .phy_tx_rst(qsfp_7_tx_rst_3_int), - .phy_xgmii_txd(qsfp_7_txd_3_int), - .phy_xgmii_txc(qsfp_7_txc_3_int), - .phy_rx_clk(qsfp_7_rx_clk_3_int), - .phy_rx_rst(qsfp_7_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_7_rxd_3_int), - .phy_xgmii_rxc(qsfp_7_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_7_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_7_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_7_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_7_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_7_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_7_tx_p[3]), - .xcvr_txn(qsfp_7_tx_n[3]), - .xcvr_rxp(qsfp_7_rx_p[3]), - .xcvr_rxn(qsfp_7_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_7_tx_clk_4_int), - .phy_tx_rst(qsfp_7_tx_rst_4_int), - .phy_xgmii_txd(qsfp_7_txd_4_int), - .phy_xgmii_txc(qsfp_7_txc_4_int), - .phy_rx_clk(qsfp_7_rx_clk_4_int), - .phy_rx_rst(qsfp_7_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_7_rxd_4_int), - .phy_xgmii_rxc(qsfp_7_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_7_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_7_tx_clk_4_int), + .phy_4_tx_rst(qsfp_7_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_7_txd_4_int), + .phy_4_xgmii_txc(qsfp_7_txc_4_int), + .phy_4_rx_clk(qsfp_7_rx_clk_4_int), + .phy_4_rx_rst(qsfp_7_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_7_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_7_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_7_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 8 @@ -2255,196 +1576,99 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_8_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_8_qpll0lock; -wire qsfp_8_qpll0outclk; -wire qsfp_8_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_8_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_8_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_8_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_8_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_8_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_8_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_8_tx_p), + .xcvr_txn(qsfp_8_tx_n), + .xcvr_rxp(qsfp_8_rx_p), + .xcvr_rxn(qsfp_8_rx_n), - // Serial data - .xcvr_txp(qsfp_8_tx_p[0]), - .xcvr_txn(qsfp_8_tx_n[0]), - .xcvr_rxp(qsfp_8_rx_p[0]), - .xcvr_rxn(qsfp_8_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_8_tx_clk_1_int), + .phy_1_tx_rst(qsfp_8_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_8_txd_1_int), + .phy_1_xgmii_txc(qsfp_8_txc_1_int), + .phy_1_rx_clk(qsfp_8_rx_clk_1_int), + .phy_1_rx_rst(qsfp_8_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_8_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_8_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_8_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_8_tx_clk_1_int), - .phy_tx_rst(qsfp_8_tx_rst_1_int), - .phy_xgmii_txd(qsfp_8_txd_1_int), - .phy_xgmii_txc(qsfp_8_txc_1_int), - .phy_rx_clk(qsfp_8_rx_clk_1_int), - .phy_rx_rst(qsfp_8_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_8_rxd_1_int), - .phy_xgmii_rxc(qsfp_8_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_8_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_8_tx_clk_2_int), + .phy_2_tx_rst(qsfp_8_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_8_txd_2_int), + .phy_2_xgmii_txc(qsfp_8_txc_2_int), + .phy_2_rx_clk(qsfp_8_rx_clk_2_int), + .phy_2_rx_rst(qsfp_8_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_8_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_8_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_8_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_8_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_8_tx_clk_3_int), + .phy_3_tx_rst(qsfp_8_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_8_txd_3_int), + .phy_3_xgmii_txc(qsfp_8_txc_3_int), + .phy_3_rx_clk(qsfp_8_rx_clk_3_int), + .phy_3_rx_rst(qsfp_8_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_8_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_8_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_8_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_8_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_8_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_8_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_8_tx_p[1]), - .xcvr_txn(qsfp_8_tx_n[1]), - .xcvr_rxp(qsfp_8_rx_p[1]), - .xcvr_rxn(qsfp_8_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_8_tx_clk_2_int), - .phy_tx_rst(qsfp_8_tx_rst_2_int), - .phy_xgmii_txd(qsfp_8_txd_2_int), - .phy_xgmii_txc(qsfp_8_txc_2_int), - .phy_rx_clk(qsfp_8_rx_clk_2_int), - .phy_rx_rst(qsfp_8_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_8_rxd_2_int), - .phy_xgmii_rxc(qsfp_8_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_8_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_8_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_8_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_8_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_8_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_8_tx_p[2]), - .xcvr_txn(qsfp_8_tx_n[2]), - .xcvr_rxp(qsfp_8_rx_p[2]), - .xcvr_rxn(qsfp_8_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_8_tx_clk_3_int), - .phy_tx_rst(qsfp_8_tx_rst_3_int), - .phy_xgmii_txd(qsfp_8_txd_3_int), - .phy_xgmii_txc(qsfp_8_txc_3_int), - .phy_rx_clk(qsfp_8_rx_clk_3_int), - .phy_rx_rst(qsfp_8_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_8_rxd_3_int), - .phy_xgmii_rxc(qsfp_8_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_8_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_8_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_8_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_8_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_8_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_8_tx_p[3]), - .xcvr_txn(qsfp_8_tx_n[3]), - .xcvr_rxp(qsfp_8_rx_p[3]), - .xcvr_rxn(qsfp_8_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_8_tx_clk_4_int), - .phy_tx_rst(qsfp_8_tx_rst_4_int), - .phy_xgmii_txd(qsfp_8_txd_4_int), - .phy_xgmii_txc(qsfp_8_txc_4_int), - .phy_rx_clk(qsfp_8_rx_clk_4_int), - .phy_rx_rst(qsfp_8_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_8_rxd_4_int), - .phy_xgmii_rxc(qsfp_8_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_8_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_8_tx_clk_4_int), + .phy_4_tx_rst(qsfp_8_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_8_txd_4_int), + .phy_4_xgmii_txc(qsfp_8_txc_4_int), + .phy_4_rx_clk(qsfp_8_rx_clk_4_int), + .phy_4_rx_rst(qsfp_8_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_8_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_8_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_8_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 9 @@ -2498,196 +1722,99 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_9_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_9_qpll0lock; -wire qsfp_9_qpll0outclk; -wire qsfp_9_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_9_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_9_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_9_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_9_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_9_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_9_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_9_tx_p), + .xcvr_txn(qsfp_9_tx_n), + .xcvr_rxp(qsfp_9_rx_p), + .xcvr_rxn(qsfp_9_rx_n), - // Serial data - .xcvr_txp(qsfp_9_tx_p[0]), - .xcvr_txn(qsfp_9_tx_n[0]), - .xcvr_rxp(qsfp_9_rx_p[0]), - .xcvr_rxn(qsfp_9_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_9_tx_clk_1_int), + .phy_1_tx_rst(qsfp_9_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_9_txd_1_int), + .phy_1_xgmii_txc(qsfp_9_txc_1_int), + .phy_1_rx_clk(qsfp_9_rx_clk_1_int), + .phy_1_rx_rst(qsfp_9_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_9_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_9_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_9_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_9_tx_clk_1_int), - .phy_tx_rst(qsfp_9_tx_rst_1_int), - .phy_xgmii_txd(qsfp_9_txd_1_int), - .phy_xgmii_txc(qsfp_9_txc_1_int), - .phy_rx_clk(qsfp_9_rx_clk_1_int), - .phy_rx_rst(qsfp_9_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_9_rxd_1_int), - .phy_xgmii_rxc(qsfp_9_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_9_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_9_tx_clk_2_int), + .phy_2_tx_rst(qsfp_9_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_9_txd_2_int), + .phy_2_xgmii_txc(qsfp_9_txc_2_int), + .phy_2_rx_clk(qsfp_9_rx_clk_2_int), + .phy_2_rx_rst(qsfp_9_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_9_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_9_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_9_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_9_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), + .phy_3_tx_clk(qsfp_9_tx_clk_3_int), + .phy_3_tx_rst(qsfp_9_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_9_txd_3_int), + .phy_3_xgmii_txc(qsfp_9_txc_3_int), + .phy_3_rx_clk(qsfp_9_rx_clk_3_int), + .phy_3_rx_rst(qsfp_9_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_9_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_9_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_9_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_9_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_9_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_9_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_9_tx_p[1]), - .xcvr_txn(qsfp_9_tx_n[1]), - .xcvr_rxp(qsfp_9_rx_p[1]), - .xcvr_rxn(qsfp_9_rx_n[1]), - - // PHY connections - .phy_tx_clk(qsfp_9_tx_clk_2_int), - .phy_tx_rst(qsfp_9_tx_rst_2_int), - .phy_xgmii_txd(qsfp_9_txd_2_int), - .phy_xgmii_txc(qsfp_9_txc_2_int), - .phy_rx_clk(qsfp_9_rx_clk_2_int), - .phy_rx_rst(qsfp_9_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_9_rxd_2_int), - .phy_xgmii_rxc(qsfp_9_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_9_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_9_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_9_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_9_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_9_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_9_tx_p[2]), - .xcvr_txn(qsfp_9_tx_n[2]), - .xcvr_rxp(qsfp_9_rx_p[2]), - .xcvr_rxn(qsfp_9_rx_n[2]), - - // PHY connections - .phy_tx_clk(qsfp_9_tx_clk_3_int), - .phy_tx_rst(qsfp_9_tx_rst_3_int), - .phy_xgmii_txd(qsfp_9_txd_3_int), - .phy_xgmii_txc(qsfp_9_txc_3_int), - .phy_rx_clk(qsfp_9_rx_clk_3_int), - .phy_rx_rst(qsfp_9_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_9_rxd_3_int), - .phy_xgmii_rxc(qsfp_9_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_9_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_9_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_9_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_9_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_9_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_9_tx_p[3]), - .xcvr_txn(qsfp_9_tx_n[3]), - .xcvr_rxp(qsfp_9_rx_p[3]), - .xcvr_rxn(qsfp_9_rx_n[3]), - - // PHY connections - .phy_tx_clk(qsfp_9_tx_clk_4_int), - .phy_tx_rst(qsfp_9_tx_rst_4_int), - .phy_xgmii_txd(qsfp_9_txd_4_int), - .phy_xgmii_txc(qsfp_9_txc_4_int), - .phy_rx_clk(qsfp_9_rx_clk_4_int), - .phy_rx_rst(qsfp_9_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_9_rxd_4_int), - .phy_xgmii_rxc(qsfp_9_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_9_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_9_tx_clk_4_int), + .phy_4_tx_rst(qsfp_9_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_9_txd_4_int), + .phy_4_xgmii_txc(qsfp_9_txc_4_int), + .phy_4_rx_clk(qsfp_9_rx_clk_4_int), + .phy_4_rx_rst(qsfp_9_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_9_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_9_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_9_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP 1 @@ -2743,196 +1870,99 @@ IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_1_mgt_refclk_inst ( .ODIV2 () ); -wire fmc_qsfp_1_qpll0lock; -wire fmc_qsfp_1_qpll0outclk; -wire fmc_qsfp_1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmc_qsfp_1_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmc_qsfp_1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmc_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmc_qsfp_1_mgt_refclk), - .xcvr_qpll0lock_out(fmc_qsfp_1_qpll0lock), - .xcvr_qpll0outclk_out(fmc_qsfp_1_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmc_qsfp_1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmc_qsfp_1_tx_p), + .xcvr_txn(fmc_qsfp_1_tx_n), + .xcvr_rxp(fmc_qsfp_1_rx_p), + .xcvr_rxn(fmc_qsfp_1_rx_n), - // Serial data - .xcvr_txp(fmc_qsfp_1_tx_p[0]), - .xcvr_txn(fmc_qsfp_1_tx_n[0]), - .xcvr_rxp(fmc_qsfp_1_rx_p[0]), - .xcvr_rxn(fmc_qsfp_1_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmc_qsfp_1_tx_clk_1_int), + .phy_1_tx_rst(fmc_qsfp_1_tx_rst_1_int), + .phy_1_xgmii_txd(fmc_qsfp_1_txd_1_int), + .phy_1_xgmii_txc(fmc_qsfp_1_txc_1_int), + .phy_1_rx_clk(fmc_qsfp_1_rx_clk_1_int), + .phy_1_rx_rst(fmc_qsfp_1_rx_rst_1_int), + .phy_1_xgmii_rxd(fmc_qsfp_1_rxd_1_int), + .phy_1_xgmii_rxc(fmc_qsfp_1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmc_qsfp_1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmc_qsfp_1_tx_clk_1_int), - .phy_tx_rst(fmc_qsfp_1_tx_rst_1_int), - .phy_xgmii_txd(fmc_qsfp_1_txd_1_int), - .phy_xgmii_txc(fmc_qsfp_1_txc_1_int), - .phy_rx_clk(fmc_qsfp_1_rx_clk_1_int), - .phy_rx_rst(fmc_qsfp_1_rx_rst_1_int), - .phy_xgmii_rxd(fmc_qsfp_1_rxd_1_int), - .phy_xgmii_rxc(fmc_qsfp_1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmc_qsfp_1_tx_clk_2_int), + .phy_2_tx_rst(fmc_qsfp_1_tx_rst_2_int), + .phy_2_xgmii_txd(fmc_qsfp_1_txd_2_int), + .phy_2_xgmii_txc(fmc_qsfp_1_txc_2_int), + .phy_2_rx_clk(fmc_qsfp_1_rx_clk_2_int), + .phy_2_rx_rst(fmc_qsfp_1_rx_rst_2_int), + .phy_2_xgmii_rxd(fmc_qsfp_1_rxd_2_int), + .phy_2_xgmii_rxc(fmc_qsfp_1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmc_qsfp_1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), + .phy_3_tx_clk(fmc_qsfp_1_tx_clk_3_int), + .phy_3_tx_rst(fmc_qsfp_1_tx_rst_3_int), + .phy_3_xgmii_txd(fmc_qsfp_1_txd_3_int), + .phy_3_xgmii_txc(fmc_qsfp_1_txc_3_int), + .phy_3_rx_clk(fmc_qsfp_1_rx_clk_3_int), + .phy_3_rx_rst(fmc_qsfp_1_rx_rst_3_int), + .phy_3_xgmii_rxd(fmc_qsfp_1_rxd_3_int), + .phy_3_xgmii_rxc(fmc_qsfp_1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmc_qsfp_1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_1_tx_p[1]), - .xcvr_txn(fmc_qsfp_1_tx_n[1]), - .xcvr_rxp(fmc_qsfp_1_rx_p[1]), - .xcvr_rxn(fmc_qsfp_1_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_1_tx_clk_2_int), - .phy_tx_rst(fmc_qsfp_1_tx_rst_2_int), - .phy_xgmii_txd(fmc_qsfp_1_txd_2_int), - .phy_xgmii_txc(fmc_qsfp_1_txc_2_int), - .phy_rx_clk(fmc_qsfp_1_rx_clk_2_int), - .phy_rx_rst(fmc_qsfp_1_rx_rst_2_int), - .phy_xgmii_rxd(fmc_qsfp_1_rxd_2_int), - .phy_xgmii_rxc(fmc_qsfp_1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_1_tx_p[2]), - .xcvr_txn(fmc_qsfp_1_tx_n[2]), - .xcvr_rxp(fmc_qsfp_1_rx_p[2]), - .xcvr_rxn(fmc_qsfp_1_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_1_tx_clk_3_int), - .phy_tx_rst(fmc_qsfp_1_tx_rst_3_int), - .phy_xgmii_txd(fmc_qsfp_1_txd_3_int), - .phy_xgmii_txc(fmc_qsfp_1_txc_3_int), - .phy_rx_clk(fmc_qsfp_1_rx_clk_3_int), - .phy_rx_rst(fmc_qsfp_1_rx_rst_3_int), - .phy_xgmii_rxd(fmc_qsfp_1_rxd_3_int), - .phy_xgmii_rxc(fmc_qsfp_1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_1_tx_p[3]), - .xcvr_txn(fmc_qsfp_1_tx_n[3]), - .xcvr_rxp(fmc_qsfp_1_rx_p[3]), - .xcvr_rxn(fmc_qsfp_1_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_1_tx_clk_4_int), - .phy_tx_rst(fmc_qsfp_1_tx_rst_4_int), - .phy_xgmii_txd(fmc_qsfp_1_txd_4_int), - .phy_xgmii_txc(fmc_qsfp_1_txc_4_int), - .phy_rx_clk(fmc_qsfp_1_rx_clk_4_int), - .phy_rx_rst(fmc_qsfp_1_rx_rst_4_int), - .phy_xgmii_rxd(fmc_qsfp_1_rxd_4_int), - .phy_xgmii_rxc(fmc_qsfp_1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmc_qsfp_1_tx_clk_4_int), + .phy_4_tx_rst(fmc_qsfp_1_tx_rst_4_int), + .phy_4_xgmii_txd(fmc_qsfp_1_txd_4_int), + .phy_4_xgmii_txc(fmc_qsfp_1_txc_4_int), + .phy_4_rx_clk(fmc_qsfp_1_rx_clk_4_int), + .phy_4_rx_rst(fmc_qsfp_1_rx_rst_4_int), + .phy_4_xgmii_rxd(fmc_qsfp_1_rxd_4_int), + .phy_4_xgmii_rxc(fmc_qsfp_1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmc_qsfp_1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP 2 @@ -2988,196 +2018,99 @@ IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_2_mgt_refclk_inst ( .ODIV2 () ); -wire fmc_qsfp_2_qpll0lock; -wire fmc_qsfp_2_qpll0outclk; -wire fmc_qsfp_2_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmc_qsfp_2_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmc_qsfp_2_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmc_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmc_qsfp_2_mgt_refclk), - .xcvr_qpll0lock_out(fmc_qsfp_2_qpll0lock), - .xcvr_qpll0outclk_out(fmc_qsfp_2_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmc_qsfp_2_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmc_qsfp_2_tx_p), + .xcvr_txn(fmc_qsfp_2_tx_n), + .xcvr_rxp(fmc_qsfp_2_rx_p), + .xcvr_rxn(fmc_qsfp_2_rx_n), - // Serial data - .xcvr_txp(fmc_qsfp_2_tx_p[0]), - .xcvr_txn(fmc_qsfp_2_tx_n[0]), - .xcvr_rxp(fmc_qsfp_2_rx_p[0]), - .xcvr_rxn(fmc_qsfp_2_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmc_qsfp_2_tx_clk_1_int), + .phy_1_tx_rst(fmc_qsfp_2_tx_rst_1_int), + .phy_1_xgmii_txd(fmc_qsfp_2_txd_1_int), + .phy_1_xgmii_txc(fmc_qsfp_2_txc_1_int), + .phy_1_rx_clk(fmc_qsfp_2_rx_clk_1_int), + .phy_1_rx_rst(fmc_qsfp_2_rx_rst_1_int), + .phy_1_xgmii_rxd(fmc_qsfp_2_rxd_1_int), + .phy_1_xgmii_rxc(fmc_qsfp_2_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmc_qsfp_2_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmc_qsfp_2_tx_clk_1_int), - .phy_tx_rst(fmc_qsfp_2_tx_rst_1_int), - .phy_xgmii_txd(fmc_qsfp_2_txd_1_int), - .phy_xgmii_txc(fmc_qsfp_2_txc_1_int), - .phy_rx_clk(fmc_qsfp_2_rx_clk_1_int), - .phy_rx_rst(fmc_qsfp_2_rx_rst_1_int), - .phy_xgmii_rxd(fmc_qsfp_2_rxd_1_int), - .phy_xgmii_rxc(fmc_qsfp_2_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmc_qsfp_2_tx_clk_2_int), + .phy_2_tx_rst(fmc_qsfp_2_tx_rst_2_int), + .phy_2_xgmii_txd(fmc_qsfp_2_txd_2_int), + .phy_2_xgmii_txc(fmc_qsfp_2_txc_2_int), + .phy_2_rx_clk(fmc_qsfp_2_rx_clk_2_int), + .phy_2_rx_rst(fmc_qsfp_2_rx_rst_2_int), + .phy_2_xgmii_rxd(fmc_qsfp_2_rxd_2_int), + .phy_2_xgmii_rxc(fmc_qsfp_2_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmc_qsfp_2_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_2_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), + .phy_3_tx_clk(fmc_qsfp_2_tx_clk_3_int), + .phy_3_tx_rst(fmc_qsfp_2_tx_rst_3_int), + .phy_3_xgmii_txd(fmc_qsfp_2_txd_3_int), + .phy_3_xgmii_txc(fmc_qsfp_2_txc_3_int), + .phy_3_rx_clk(fmc_qsfp_2_rx_clk_3_int), + .phy_3_rx_rst(fmc_qsfp_2_rx_rst_3_int), + .phy_3_xgmii_rxd(fmc_qsfp_2_rxd_3_int), + .phy_3_xgmii_rxc(fmc_qsfp_2_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmc_qsfp_2_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_2_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_2_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_2_tx_p[1]), - .xcvr_txn(fmc_qsfp_2_tx_n[1]), - .xcvr_rxp(fmc_qsfp_2_rx_p[1]), - .xcvr_rxn(fmc_qsfp_2_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_2_tx_clk_2_int), - .phy_tx_rst(fmc_qsfp_2_tx_rst_2_int), - .phy_xgmii_txd(fmc_qsfp_2_txd_2_int), - .phy_xgmii_txc(fmc_qsfp_2_txc_2_int), - .phy_rx_clk(fmc_qsfp_2_rx_clk_2_int), - .phy_rx_rst(fmc_qsfp_2_rx_rst_2_int), - .phy_xgmii_rxd(fmc_qsfp_2_rxd_2_int), - .phy_xgmii_rxc(fmc_qsfp_2_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_2_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_2_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_2_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_2_tx_p[2]), - .xcvr_txn(fmc_qsfp_2_tx_n[2]), - .xcvr_rxp(fmc_qsfp_2_rx_p[2]), - .xcvr_rxn(fmc_qsfp_2_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_2_tx_clk_3_int), - .phy_tx_rst(fmc_qsfp_2_tx_rst_3_int), - .phy_xgmii_txd(fmc_qsfp_2_txd_3_int), - .phy_xgmii_txc(fmc_qsfp_2_txc_3_int), - .phy_rx_clk(fmc_qsfp_2_rx_clk_3_int), - .phy_rx_rst(fmc_qsfp_2_rx_rst_3_int), - .phy_xgmii_rxd(fmc_qsfp_2_rxd_3_int), - .phy_xgmii_rxc(fmc_qsfp_2_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_2_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_2_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_2_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_2_tx_p[3]), - .xcvr_txn(fmc_qsfp_2_tx_n[3]), - .xcvr_rxp(fmc_qsfp_2_rx_p[3]), - .xcvr_rxn(fmc_qsfp_2_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_2_tx_clk_4_int), - .phy_tx_rst(fmc_qsfp_2_tx_rst_4_int), - .phy_xgmii_txd(fmc_qsfp_2_txd_4_int), - .phy_xgmii_txc(fmc_qsfp_2_txc_4_int), - .phy_rx_clk(fmc_qsfp_2_rx_clk_4_int), - .phy_rx_rst(fmc_qsfp_2_rx_rst_4_int), - .phy_xgmii_rxd(fmc_qsfp_2_rxd_4_int), - .phy_xgmii_rxc(fmc_qsfp_2_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmc_qsfp_2_tx_clk_4_int), + .phy_4_tx_rst(fmc_qsfp_2_tx_rst_4_int), + .phy_4_xgmii_txd(fmc_qsfp_2_txd_4_int), + .phy_4_xgmii_txc(fmc_qsfp_2_txc_4_int), + .phy_4_rx_clk(fmc_qsfp_2_rx_clk_4_int), + .phy_4_rx_rst(fmc_qsfp_2_rx_rst_4_int), + .phy_4_xgmii_rxd(fmc_qsfp_2_rxd_4_int), + .phy_4_xgmii_rxc(fmc_qsfp_2_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmc_qsfp_2_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP 3 @@ -3233,196 +2166,99 @@ IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_3_mgt_refclk_inst ( .ODIV2 () ); -wire fmc_qsfp_3_qpll0lock; -wire fmc_qsfp_3_qpll0outclk; -wire fmc_qsfp_3_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmc_qsfp_3_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmc_qsfp_3_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmc_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmc_qsfp_3_mgt_refclk), - .xcvr_qpll0lock_out(fmc_qsfp_3_qpll0lock), - .xcvr_qpll0outclk_out(fmc_qsfp_3_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmc_qsfp_3_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmc_qsfp_3_tx_p), + .xcvr_txn(fmc_qsfp_3_tx_n), + .xcvr_rxp(fmc_qsfp_3_rx_p), + .xcvr_rxn(fmc_qsfp_3_rx_n), - // Serial data - .xcvr_txp(fmc_qsfp_3_tx_p[0]), - .xcvr_txn(fmc_qsfp_3_tx_n[0]), - .xcvr_rxp(fmc_qsfp_3_rx_p[0]), - .xcvr_rxn(fmc_qsfp_3_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmc_qsfp_3_tx_clk_1_int), + .phy_1_tx_rst(fmc_qsfp_3_tx_rst_1_int), + .phy_1_xgmii_txd(fmc_qsfp_3_txd_1_int), + .phy_1_xgmii_txc(fmc_qsfp_3_txc_1_int), + .phy_1_rx_clk(fmc_qsfp_3_rx_clk_1_int), + .phy_1_rx_rst(fmc_qsfp_3_rx_rst_1_int), + .phy_1_xgmii_rxd(fmc_qsfp_3_rxd_1_int), + .phy_1_xgmii_rxc(fmc_qsfp_3_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmc_qsfp_3_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmc_qsfp_3_tx_clk_1_int), - .phy_tx_rst(fmc_qsfp_3_tx_rst_1_int), - .phy_xgmii_txd(fmc_qsfp_3_txd_1_int), - .phy_xgmii_txc(fmc_qsfp_3_txc_1_int), - .phy_rx_clk(fmc_qsfp_3_rx_clk_1_int), - .phy_rx_rst(fmc_qsfp_3_rx_rst_1_int), - .phy_xgmii_rxd(fmc_qsfp_3_rxd_1_int), - .phy_xgmii_rxc(fmc_qsfp_3_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmc_qsfp_3_tx_clk_2_int), + .phy_2_tx_rst(fmc_qsfp_3_tx_rst_2_int), + .phy_2_xgmii_txd(fmc_qsfp_3_txd_2_int), + .phy_2_xgmii_txc(fmc_qsfp_3_txc_2_int), + .phy_2_rx_clk(fmc_qsfp_3_rx_clk_2_int), + .phy_2_rx_rst(fmc_qsfp_3_rx_rst_2_int), + .phy_2_xgmii_rxd(fmc_qsfp_3_rxd_2_int), + .phy_2_xgmii_rxc(fmc_qsfp_3_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmc_qsfp_3_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_3_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), + .phy_3_tx_clk(fmc_qsfp_3_tx_clk_3_int), + .phy_3_tx_rst(fmc_qsfp_3_tx_rst_3_int), + .phy_3_xgmii_txd(fmc_qsfp_3_txd_3_int), + .phy_3_xgmii_txc(fmc_qsfp_3_txc_3_int), + .phy_3_rx_clk(fmc_qsfp_3_rx_clk_3_int), + .phy_3_rx_rst(fmc_qsfp_3_rx_rst_3_int), + .phy_3_xgmii_rxd(fmc_qsfp_3_rxd_3_int), + .phy_3_xgmii_rxc(fmc_qsfp_3_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmc_qsfp_3_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_3_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_3_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_3_tx_p[1]), - .xcvr_txn(fmc_qsfp_3_tx_n[1]), - .xcvr_rxp(fmc_qsfp_3_rx_p[1]), - .xcvr_rxn(fmc_qsfp_3_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_3_tx_clk_2_int), - .phy_tx_rst(fmc_qsfp_3_tx_rst_2_int), - .phy_xgmii_txd(fmc_qsfp_3_txd_2_int), - .phy_xgmii_txc(fmc_qsfp_3_txc_2_int), - .phy_rx_clk(fmc_qsfp_3_rx_clk_2_int), - .phy_rx_rst(fmc_qsfp_3_rx_rst_2_int), - .phy_xgmii_rxd(fmc_qsfp_3_rxd_2_int), - .phy_xgmii_rxc(fmc_qsfp_3_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_3_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_3_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_3_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_3_tx_p[2]), - .xcvr_txn(fmc_qsfp_3_tx_n[2]), - .xcvr_rxp(fmc_qsfp_3_rx_p[2]), - .xcvr_rxn(fmc_qsfp_3_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_3_tx_clk_3_int), - .phy_tx_rst(fmc_qsfp_3_tx_rst_3_int), - .phy_xgmii_txd(fmc_qsfp_3_txd_3_int), - .phy_xgmii_txc(fmc_qsfp_3_txc_3_int), - .phy_rx_clk(fmc_qsfp_3_rx_clk_3_int), - .phy_rx_rst(fmc_qsfp_3_rx_rst_3_int), - .phy_xgmii_rxd(fmc_qsfp_3_rxd_3_int), - .phy_xgmii_rxc(fmc_qsfp_3_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_3_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_3_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_3_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_3_tx_p[3]), - .xcvr_txn(fmc_qsfp_3_tx_n[3]), - .xcvr_rxp(fmc_qsfp_3_rx_p[3]), - .xcvr_rxn(fmc_qsfp_3_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_3_tx_clk_4_int), - .phy_tx_rst(fmc_qsfp_3_tx_rst_4_int), - .phy_xgmii_txd(fmc_qsfp_3_txd_4_int), - .phy_xgmii_txc(fmc_qsfp_3_txc_4_int), - .phy_rx_clk(fmc_qsfp_3_rx_clk_4_int), - .phy_rx_rst(fmc_qsfp_3_rx_rst_4_int), - .phy_xgmii_rxd(fmc_qsfp_3_rxd_4_int), - .phy_xgmii_rxc(fmc_qsfp_3_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmc_qsfp_3_tx_clk_4_int), + .phy_4_tx_rst(fmc_qsfp_3_tx_rst_4_int), + .phy_4_xgmii_txd(fmc_qsfp_3_txd_4_int), + .phy_4_xgmii_txc(fmc_qsfp_3_txc_4_int), + .phy_4_rx_clk(fmc_qsfp_3_rx_clk_4_int), + .phy_4_rx_rst(fmc_qsfp_3_rx_rst_4_int), + .phy_4_xgmii_rxd(fmc_qsfp_3_rxd_4_int), + .phy_4_xgmii_rxc(fmc_qsfp_3_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmc_qsfp_3_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP 4 @@ -3478,196 +2314,99 @@ IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_4_mgt_refclk_inst ( .ODIV2 () ); -wire fmc_qsfp_4_qpll0lock; -wire fmc_qsfp_4_qpll0outclk; -wire fmc_qsfp_4_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmc_qsfp_4_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmc_qsfp_4_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmc_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmc_qsfp_4_mgt_refclk), - .xcvr_qpll0lock_out(fmc_qsfp_4_qpll0lock), - .xcvr_qpll0outclk_out(fmc_qsfp_4_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmc_qsfp_4_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmc_qsfp_4_tx_p), + .xcvr_txn(fmc_qsfp_4_tx_n), + .xcvr_rxp(fmc_qsfp_4_rx_p), + .xcvr_rxn(fmc_qsfp_4_rx_n), - // Serial data - .xcvr_txp(fmc_qsfp_4_tx_p[0]), - .xcvr_txn(fmc_qsfp_4_tx_n[0]), - .xcvr_rxp(fmc_qsfp_4_rx_p[0]), - .xcvr_rxn(fmc_qsfp_4_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmc_qsfp_4_tx_clk_1_int), + .phy_1_tx_rst(fmc_qsfp_4_tx_rst_1_int), + .phy_1_xgmii_txd(fmc_qsfp_4_txd_1_int), + .phy_1_xgmii_txc(fmc_qsfp_4_txc_1_int), + .phy_1_rx_clk(fmc_qsfp_4_rx_clk_1_int), + .phy_1_rx_rst(fmc_qsfp_4_rx_rst_1_int), + .phy_1_xgmii_rxd(fmc_qsfp_4_rxd_1_int), + .phy_1_xgmii_rxc(fmc_qsfp_4_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmc_qsfp_4_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmc_qsfp_4_tx_clk_1_int), - .phy_tx_rst(fmc_qsfp_4_tx_rst_1_int), - .phy_xgmii_txd(fmc_qsfp_4_txd_1_int), - .phy_xgmii_txc(fmc_qsfp_4_txc_1_int), - .phy_rx_clk(fmc_qsfp_4_rx_clk_1_int), - .phy_rx_rst(fmc_qsfp_4_rx_rst_1_int), - .phy_xgmii_rxd(fmc_qsfp_4_rxd_1_int), - .phy_xgmii_rxc(fmc_qsfp_4_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmc_qsfp_4_tx_clk_2_int), + .phy_2_tx_rst(fmc_qsfp_4_tx_rst_2_int), + .phy_2_xgmii_txd(fmc_qsfp_4_txd_2_int), + .phy_2_xgmii_txc(fmc_qsfp_4_txc_2_int), + .phy_2_rx_clk(fmc_qsfp_4_rx_clk_2_int), + .phy_2_rx_rst(fmc_qsfp_4_rx_rst_2_int), + .phy_2_xgmii_rxd(fmc_qsfp_4_rxd_2_int), + .phy_2_xgmii_rxc(fmc_qsfp_4_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmc_qsfp_4_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_4_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), + .phy_3_tx_clk(fmc_qsfp_4_tx_clk_3_int), + .phy_3_tx_rst(fmc_qsfp_4_tx_rst_3_int), + .phy_3_xgmii_txd(fmc_qsfp_4_txd_3_int), + .phy_3_xgmii_txc(fmc_qsfp_4_txc_3_int), + .phy_3_rx_clk(fmc_qsfp_4_rx_clk_3_int), + .phy_3_rx_rst(fmc_qsfp_4_rx_rst_3_int), + .phy_3_xgmii_rxd(fmc_qsfp_4_rxd_3_int), + .phy_3_xgmii_rxc(fmc_qsfp_4_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmc_qsfp_4_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_4_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_4_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_4_tx_p[1]), - .xcvr_txn(fmc_qsfp_4_tx_n[1]), - .xcvr_rxp(fmc_qsfp_4_rx_p[1]), - .xcvr_rxn(fmc_qsfp_4_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_4_tx_clk_2_int), - .phy_tx_rst(fmc_qsfp_4_tx_rst_2_int), - .phy_xgmii_txd(fmc_qsfp_4_txd_2_int), - .phy_xgmii_txc(fmc_qsfp_4_txc_2_int), - .phy_rx_clk(fmc_qsfp_4_rx_clk_2_int), - .phy_rx_rst(fmc_qsfp_4_rx_rst_2_int), - .phy_xgmii_rxd(fmc_qsfp_4_rxd_2_int), - .phy_xgmii_rxc(fmc_qsfp_4_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_4_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_4_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_4_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_4_tx_p[2]), - .xcvr_txn(fmc_qsfp_4_tx_n[2]), - .xcvr_rxp(fmc_qsfp_4_rx_p[2]), - .xcvr_rxn(fmc_qsfp_4_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_4_tx_clk_3_int), - .phy_tx_rst(fmc_qsfp_4_tx_rst_3_int), - .phy_xgmii_txd(fmc_qsfp_4_txd_3_int), - .phy_xgmii_txc(fmc_qsfp_4_txc_3_int), - .phy_rx_clk(fmc_qsfp_4_rx_clk_3_int), - .phy_rx_rst(fmc_qsfp_4_rx_rst_3_int), - .phy_xgmii_rxd(fmc_qsfp_4_rxd_3_int), - .phy_xgmii_rxc(fmc_qsfp_4_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_4_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_4_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_4_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_4_tx_p[3]), - .xcvr_txn(fmc_qsfp_4_tx_n[3]), - .xcvr_rxp(fmc_qsfp_4_rx_p[3]), - .xcvr_rxn(fmc_qsfp_4_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_4_tx_clk_4_int), - .phy_tx_rst(fmc_qsfp_4_tx_rst_4_int), - .phy_xgmii_txd(fmc_qsfp_4_txd_4_int), - .phy_xgmii_txc(fmc_qsfp_4_txc_4_int), - .phy_rx_clk(fmc_qsfp_4_rx_clk_4_int), - .phy_rx_rst(fmc_qsfp_4_rx_rst_4_int), - .phy_xgmii_rxd(fmc_qsfp_4_rxd_4_int), - .phy_xgmii_rxc(fmc_qsfp_4_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmc_qsfp_4_tx_clk_4_int), + .phy_4_tx_rst(fmc_qsfp_4_tx_rst_4_int), + .phy_4_xgmii_txd(fmc_qsfp_4_txd_4_int), + .phy_4_xgmii_txc(fmc_qsfp_4_txc_4_int), + .phy_4_rx_clk(fmc_qsfp_4_rx_clk_4_int), + .phy_4_rx_rst(fmc_qsfp_4_rx_rst_4_int), + .phy_4_xgmii_rxd(fmc_qsfp_4_rxd_4_int), + .phy_4_xgmii_rxc(fmc_qsfp_4_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmc_qsfp_4_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP 5 @@ -3723,196 +2462,99 @@ IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_5_mgt_refclk_inst ( .ODIV2 () ); -wire fmc_qsfp_5_qpll0lock; -wire fmc_qsfp_5_qpll0outclk; -wire fmc_qsfp_5_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmc_qsfp_5_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmc_qsfp_5_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmc_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmc_qsfp_5_mgt_refclk), - .xcvr_qpll0lock_out(fmc_qsfp_5_qpll0lock), - .xcvr_qpll0outclk_out(fmc_qsfp_5_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmc_qsfp_5_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmc_qsfp_5_tx_p), + .xcvr_txn(fmc_qsfp_5_tx_n), + .xcvr_rxp(fmc_qsfp_5_rx_p), + .xcvr_rxn(fmc_qsfp_5_rx_n), - // Serial data - .xcvr_txp(fmc_qsfp_5_tx_p[0]), - .xcvr_txn(fmc_qsfp_5_tx_n[0]), - .xcvr_rxp(fmc_qsfp_5_rx_p[0]), - .xcvr_rxn(fmc_qsfp_5_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmc_qsfp_5_tx_clk_1_int), + .phy_1_tx_rst(fmc_qsfp_5_tx_rst_1_int), + .phy_1_xgmii_txd(fmc_qsfp_5_txd_1_int), + .phy_1_xgmii_txc(fmc_qsfp_5_txc_1_int), + .phy_1_rx_clk(fmc_qsfp_5_rx_clk_1_int), + .phy_1_rx_rst(fmc_qsfp_5_rx_rst_1_int), + .phy_1_xgmii_rxd(fmc_qsfp_5_rxd_1_int), + .phy_1_xgmii_rxc(fmc_qsfp_5_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmc_qsfp_5_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmc_qsfp_5_tx_clk_1_int), - .phy_tx_rst(fmc_qsfp_5_tx_rst_1_int), - .phy_xgmii_txd(fmc_qsfp_5_txd_1_int), - .phy_xgmii_txc(fmc_qsfp_5_txc_1_int), - .phy_rx_clk(fmc_qsfp_5_rx_clk_1_int), - .phy_rx_rst(fmc_qsfp_5_rx_rst_1_int), - .phy_xgmii_rxd(fmc_qsfp_5_rxd_1_int), - .phy_xgmii_rxc(fmc_qsfp_5_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmc_qsfp_5_tx_clk_2_int), + .phy_2_tx_rst(fmc_qsfp_5_tx_rst_2_int), + .phy_2_xgmii_txd(fmc_qsfp_5_txd_2_int), + .phy_2_xgmii_txc(fmc_qsfp_5_txc_2_int), + .phy_2_rx_clk(fmc_qsfp_5_rx_clk_2_int), + .phy_2_rx_rst(fmc_qsfp_5_rx_rst_2_int), + .phy_2_xgmii_rxd(fmc_qsfp_5_rxd_2_int), + .phy_2_xgmii_rxc(fmc_qsfp_5_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmc_qsfp_5_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_5_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), + .phy_3_tx_clk(fmc_qsfp_5_tx_clk_3_int), + .phy_3_tx_rst(fmc_qsfp_5_tx_rst_3_int), + .phy_3_xgmii_txd(fmc_qsfp_5_txd_3_int), + .phy_3_xgmii_txc(fmc_qsfp_5_txc_3_int), + .phy_3_rx_clk(fmc_qsfp_5_rx_clk_3_int), + .phy_3_rx_rst(fmc_qsfp_5_rx_rst_3_int), + .phy_3_xgmii_rxd(fmc_qsfp_5_rxd_3_int), + .phy_3_xgmii_rxc(fmc_qsfp_5_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmc_qsfp_5_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_5_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_5_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_5_tx_p[1]), - .xcvr_txn(fmc_qsfp_5_tx_n[1]), - .xcvr_rxp(fmc_qsfp_5_rx_p[1]), - .xcvr_rxn(fmc_qsfp_5_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_5_tx_clk_2_int), - .phy_tx_rst(fmc_qsfp_5_tx_rst_2_int), - .phy_xgmii_txd(fmc_qsfp_5_txd_2_int), - .phy_xgmii_txc(fmc_qsfp_5_txc_2_int), - .phy_rx_clk(fmc_qsfp_5_rx_clk_2_int), - .phy_rx_rst(fmc_qsfp_5_rx_rst_2_int), - .phy_xgmii_rxd(fmc_qsfp_5_rxd_2_int), - .phy_xgmii_rxc(fmc_qsfp_5_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_5_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_5_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_5_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_5_tx_p[2]), - .xcvr_txn(fmc_qsfp_5_tx_n[2]), - .xcvr_rxp(fmc_qsfp_5_rx_p[2]), - .xcvr_rxn(fmc_qsfp_5_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_5_tx_clk_3_int), - .phy_tx_rst(fmc_qsfp_5_tx_rst_3_int), - .phy_xgmii_txd(fmc_qsfp_5_txd_3_int), - .phy_xgmii_txc(fmc_qsfp_5_txc_3_int), - .phy_rx_clk(fmc_qsfp_5_rx_clk_3_int), - .phy_rx_rst(fmc_qsfp_5_rx_rst_3_int), - .phy_xgmii_rxd(fmc_qsfp_5_rxd_3_int), - .phy_xgmii_rxc(fmc_qsfp_5_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_5_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_5_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_5_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_5_tx_p[3]), - .xcvr_txn(fmc_qsfp_5_tx_n[3]), - .xcvr_rxp(fmc_qsfp_5_rx_p[3]), - .xcvr_rxn(fmc_qsfp_5_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_5_tx_clk_4_int), - .phy_tx_rst(fmc_qsfp_5_tx_rst_4_int), - .phy_xgmii_txd(fmc_qsfp_5_txd_4_int), - .phy_xgmii_txc(fmc_qsfp_5_txc_4_int), - .phy_rx_clk(fmc_qsfp_5_rx_clk_4_int), - .phy_rx_rst(fmc_qsfp_5_rx_rst_4_int), - .phy_xgmii_rxd(fmc_qsfp_5_rxd_4_int), - .phy_xgmii_rxc(fmc_qsfp_5_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmc_qsfp_5_tx_clk_4_int), + .phy_4_tx_rst(fmc_qsfp_5_tx_rst_4_int), + .phy_4_xgmii_txd(fmc_qsfp_5_txd_4_int), + .phy_4_xgmii_txc(fmc_qsfp_5_txc_4_int), + .phy_4_rx_clk(fmc_qsfp_5_rx_clk_4_int), + .phy_4_rx_rst(fmc_qsfp_5_rx_rst_4_int), + .phy_4_xgmii_rxd(fmc_qsfp_5_rxd_4_int), + .phy_4_xgmii_rxc(fmc_qsfp_5_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmc_qsfp_5_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP 6 @@ -3968,196 +2610,99 @@ IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_6_mgt_refclk_inst ( .ODIV2 () ); -wire fmc_qsfp_6_qpll0lock; -wire fmc_qsfp_6_qpll0outclk; -wire fmc_qsfp_6_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmc_qsfp_6_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmc_qsfp_6_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmc_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmc_qsfp_6_mgt_refclk), - .xcvr_qpll0lock_out(fmc_qsfp_6_qpll0lock), - .xcvr_qpll0outclk_out(fmc_qsfp_6_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmc_qsfp_6_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmc_qsfp_6_tx_p), + .xcvr_txn(fmc_qsfp_6_tx_n), + .xcvr_rxp(fmc_qsfp_6_rx_p), + .xcvr_rxn(fmc_qsfp_6_rx_n), - // Serial data - .xcvr_txp(fmc_qsfp_6_tx_p[0]), - .xcvr_txn(fmc_qsfp_6_tx_n[0]), - .xcvr_rxp(fmc_qsfp_6_rx_p[0]), - .xcvr_rxn(fmc_qsfp_6_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmc_qsfp_6_tx_clk_1_int), + .phy_1_tx_rst(fmc_qsfp_6_tx_rst_1_int), + .phy_1_xgmii_txd(fmc_qsfp_6_txd_1_int), + .phy_1_xgmii_txc(fmc_qsfp_6_txc_1_int), + .phy_1_rx_clk(fmc_qsfp_6_rx_clk_1_int), + .phy_1_rx_rst(fmc_qsfp_6_rx_rst_1_int), + .phy_1_xgmii_rxd(fmc_qsfp_6_rxd_1_int), + .phy_1_xgmii_rxc(fmc_qsfp_6_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmc_qsfp_6_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmc_qsfp_6_tx_clk_1_int), - .phy_tx_rst(fmc_qsfp_6_tx_rst_1_int), - .phy_xgmii_txd(fmc_qsfp_6_txd_1_int), - .phy_xgmii_txc(fmc_qsfp_6_txc_1_int), - .phy_rx_clk(fmc_qsfp_6_rx_clk_1_int), - .phy_rx_rst(fmc_qsfp_6_rx_rst_1_int), - .phy_xgmii_rxd(fmc_qsfp_6_rxd_1_int), - .phy_xgmii_rxc(fmc_qsfp_6_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmc_qsfp_6_tx_clk_2_int), + .phy_2_tx_rst(fmc_qsfp_6_tx_rst_2_int), + .phy_2_xgmii_txd(fmc_qsfp_6_txd_2_int), + .phy_2_xgmii_txc(fmc_qsfp_6_txc_2_int), + .phy_2_rx_clk(fmc_qsfp_6_rx_clk_2_int), + .phy_2_rx_rst(fmc_qsfp_6_rx_rst_2_int), + .phy_2_xgmii_rxd(fmc_qsfp_6_rxd_2_int), + .phy_2_xgmii_rxc(fmc_qsfp_6_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmc_qsfp_6_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_6_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), + .phy_3_tx_clk(fmc_qsfp_6_tx_clk_3_int), + .phy_3_tx_rst(fmc_qsfp_6_tx_rst_3_int), + .phy_3_xgmii_txd(fmc_qsfp_6_txd_3_int), + .phy_3_xgmii_txc(fmc_qsfp_6_txc_3_int), + .phy_3_rx_clk(fmc_qsfp_6_rx_clk_3_int), + .phy_3_rx_rst(fmc_qsfp_6_rx_rst_3_int), + .phy_3_xgmii_rxd(fmc_qsfp_6_rxd_3_int), + .phy_3_xgmii_rxc(fmc_qsfp_6_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmc_qsfp_6_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_6_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_6_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_6_tx_p[1]), - .xcvr_txn(fmc_qsfp_6_tx_n[1]), - .xcvr_rxp(fmc_qsfp_6_rx_p[1]), - .xcvr_rxn(fmc_qsfp_6_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_6_tx_clk_2_int), - .phy_tx_rst(fmc_qsfp_6_tx_rst_2_int), - .phy_xgmii_txd(fmc_qsfp_6_txd_2_int), - .phy_xgmii_txc(fmc_qsfp_6_txc_2_int), - .phy_rx_clk(fmc_qsfp_6_rx_clk_2_int), - .phy_rx_rst(fmc_qsfp_6_rx_rst_2_int), - .phy_xgmii_rxd(fmc_qsfp_6_rxd_2_int), - .phy_xgmii_rxc(fmc_qsfp_6_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_6_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_6_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_6_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_6_tx_p[2]), - .xcvr_txn(fmc_qsfp_6_tx_n[2]), - .xcvr_rxp(fmc_qsfp_6_rx_p[2]), - .xcvr_rxn(fmc_qsfp_6_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_6_tx_clk_3_int), - .phy_tx_rst(fmc_qsfp_6_tx_rst_3_int), - .phy_xgmii_txd(fmc_qsfp_6_txd_3_int), - .phy_xgmii_txc(fmc_qsfp_6_txc_3_int), - .phy_rx_clk(fmc_qsfp_6_rx_clk_3_int), - .phy_rx_rst(fmc_qsfp_6_rx_rst_3_int), - .phy_xgmii_rxd(fmc_qsfp_6_rxd_3_int), - .phy_xgmii_rxc(fmc_qsfp_6_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmc_qsfp_6_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmc_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmc_qsfp_6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmc_qsfp_6_qpll0outclk), - .xcvr_qpll0refclk_in(fmc_qsfp_6_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmc_qsfp_6_tx_p[3]), - .xcvr_txn(fmc_qsfp_6_tx_n[3]), - .xcvr_rxp(fmc_qsfp_6_rx_p[3]), - .xcvr_rxn(fmc_qsfp_6_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmc_qsfp_6_tx_clk_4_int), - .phy_tx_rst(fmc_qsfp_6_tx_rst_4_int), - .phy_xgmii_txd(fmc_qsfp_6_txd_4_int), - .phy_xgmii_txc(fmc_qsfp_6_txc_4_int), - .phy_rx_clk(fmc_qsfp_6_rx_clk_4_int), - .phy_rx_rst(fmc_qsfp_6_rx_rst_4_int), - .phy_xgmii_rxd(fmc_qsfp_6_rxd_4_int), - .phy_xgmii_rxc(fmc_qsfp_6_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmc_qsfp_6_tx_clk_4_int), + .phy_4_tx_rst(fmc_qsfp_6_tx_rst_4_int), + .phy_4_xgmii_txd(fmc_qsfp_6_txd_4_int), + .phy_4_xgmii_txc(fmc_qsfp_6_txc_4_int), + .phy_4_rx_clk(fmc_qsfp_6_rx_clk_4_int), + .phy_4_rx_rst(fmc_qsfp_6_rx_rst_4_int), + .phy_4_xgmii_rxd(fmc_qsfp_6_rxd_4_int), + .phy_4_xgmii_rxc(fmc_qsfp_6_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmc_qsfp_6_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); fpga_core From 351ec79fef5899efba5598cd30b745594fcfd00d Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 25 Aug 2023 01:27:53 -0700 Subject: [PATCH 05/19] Use quad wrappers in VCU118 example designs Signed-off-by: Alex Forencich --- example/VCU118/fpga_1g/fpga.xdc | 64 +- example/VCU118/fpga_25g/fpga.xdc | 64 +- example/VCU118/fpga_25g/fpga/Makefile | 1 + example/VCU118/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 +++ .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/VCU118/fpga_25g/rtl/fpga.v | 594 ++--- .../VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc | 64 +- .../fpga_fmc_htg_6qsfp_25g/fpga/Makefile | 1 + .../fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile | 1 + .../rtl/eth_xcvr_phy_quad_wrapper.v | 395 +++ .../rtl/eth_xcvr_phy_wrapper.v | 18 +- .../VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v | 2152 +++++------------ 13 files changed, 1756 insertions(+), 2012 deletions(-) create mode 100644 example/VCU118/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v create mode 100644 example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/VCU118/fpga_1g/fpga.xdc b/example/VCU118/fpga_1g/fpga.xdc index 3b1fd2272..a7aa10bb1 100644 --- a/example/VCU118/fpga_1g/fpga.xdc +++ b/example/VCU118/fpga_1g/fpga.xdc @@ -131,22 +131,22 @@ set_false_path -from [get_ports {phy_int_n phy_mdio}] set_input_delay 0 [get_ports {phy_int_n phy_mdio}] # QSFP28 Interfaces -#set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC Y2 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC Y1 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC V7 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC V6 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC W4 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC W3 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC V2 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC V1 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC M7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC M6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 #set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4 #set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5 #set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28 @@ -167,22 +167,22 @@ set_input_delay 0 [get_ports {phy_int_n phy_mdio}] #set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] #set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] -#set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC T2 } [get_ports {qsfp2_rx_p[0]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC T1 } [get_ports {qsfp2_rx_n[0]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC L5 } [get_ports {qsfp2_tx_p[0]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC L4 } [get_ports {qsfp2_tx_n[0]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC R4 } [get_ports {qsfp2_rx_p[1]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC R3 } [get_ports {qsfp2_rx_n[1]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC K7 } [get_ports {qsfp2_tx_p[1]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC K6 } [get_ports {qsfp2_tx_n[1]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC P2 } [get_ports {qsfp2_rx_p[2]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC P1 } [get_ports {qsfp2_rx_n[2]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC J5 } [get_ports {qsfp2_tx_p[2]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC J4 } [get_ports {qsfp2_tx_n[2]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC M2 } [get_ports {qsfp2_rx_p[3]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC M1 } [get_ports {qsfp2_rx_n[3]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC H7 } [get_ports {qsfp2_tx_p[3]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC H6 } [get_ports {qsfp2_tx_n[3]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 #set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 #set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 #set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35 diff --git a/example/VCU118/fpga_25g/fpga.xdc b/example/VCU118/fpga_25g/fpga.xdc index c2fda604f..df08d8be8 100644 --- a/example/VCU118/fpga_25g/fpga.xdc +++ b/example/VCU118/fpga_25g/fpga.xdc @@ -131,22 +131,22 @@ set_false_path -from [get_ports {phy_int_n phy_mdio}] set_input_delay 0 [get_ports {phy_int_n phy_mdio}] # QSFP28 Interfaces -set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC Y2 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC Y1 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V7 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V6 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC W4 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC W3 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V2 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V1 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4 set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5 #set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28 @@ -167,22 +167,22 @@ set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] -set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC T2 } [get_ports {qsfp2_rx_p[0]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC T1 } [get_ports {qsfp2_rx_n[0]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC L5 } [get_ports {qsfp2_tx_p[0]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC L4 } [get_ports {qsfp2_tx_n[0]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC R4 } [get_ports {qsfp2_rx_p[1]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC R3 } [get_ports {qsfp2_rx_n[1]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC K7 } [get_ports {qsfp2_tx_p[1]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC K6 } [get_ports {qsfp2_tx_n[1]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC P2 } [get_ports {qsfp2_rx_p[2]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC P1 } [get_ports {qsfp2_rx_n[2]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J5 } [get_ports {qsfp2_tx_p[2]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J4 } [get_ports {qsfp2_tx_n[2]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC M2 } [get_ports {qsfp2_rx_p[3]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC M1 } [get_ports {qsfp2_rx_n[3]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H7 } [get_ports {qsfp2_tx_p[3]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H6 } [get_ports {qsfp2_tx_n[3]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 #set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 #set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 #set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35 diff --git a/example/VCU118/fpga_25g/fpga/Makefile b/example/VCU118/fpga_25g/fpga/Makefile index 81d9f3750..91326ee2d 100644 --- a/example/VCU118/fpga_25g/fpga/Makefile +++ b/example/VCU118/fpga_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/mdio_master.v diff --git a/example/VCU118/fpga_25g/fpga_10g/Makefile b/example/VCU118/fpga_25g/fpga_10g/Makefile index 81d9f3750..91326ee2d 100644 --- a/example/VCU118/fpga_25g/fpga_10g/Makefile +++ b/example/VCU118/fpga_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/mdio_master.v diff --git a/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/VCU118/fpga_25g/rtl/fpga.v b/example/VCU118/fpga_25g/rtl/fpga.v index 30b580ab2..5f091a973 100644 --- a/example/VCU118/fpga_25g/rtl/fpga.v +++ b/example/VCU118/fpga_25g/rtl/fpga.v @@ -60,22 +60,10 @@ module fpga ( /* * Ethernet: QSFP28 */ - output wire qsfp1_tx1_p, - output wire qsfp1_tx1_n, - input wire qsfp1_rx1_p, - input wire qsfp1_rx1_n, - output wire qsfp1_tx2_p, - output wire qsfp1_tx2_n, - input wire qsfp1_rx2_p, - input wire qsfp1_rx2_n, - output wire qsfp1_tx3_p, - output wire qsfp1_tx3_n, - input wire qsfp1_rx3_p, - input wire qsfp1_rx3_n, - output wire qsfp1_tx4_p, - output wire qsfp1_tx4_n, - input wire qsfp1_rx4_p, - input wire qsfp1_rx4_n, + output wire [3:0] qsfp1_tx_p, + output wire [3:0] qsfp1_tx_n, + input wire [3:0] qsfp1_rx_p, + input wire [3:0] qsfp1_rx_n, input wire qsfp1_mgt_refclk_0_p, input wire qsfp1_mgt_refclk_0_n, // input wire qsfp1_mgt_refclk_1_p, @@ -88,22 +76,10 @@ module fpga ( input wire qsfp1_intl, output wire qsfp1_lpmode, - output wire qsfp2_tx1_p, - output wire qsfp2_tx1_n, - input wire qsfp2_rx1_p, - input wire qsfp2_rx1_n, - output wire qsfp2_tx2_p, - output wire qsfp2_tx2_n, - input wire qsfp2_rx2_p, - input wire qsfp2_rx2_n, - output wire qsfp2_tx3_p, - output wire qsfp2_tx3_n, - input wire qsfp2_rx3_p, - input wire qsfp2_rx3_n, - output wire qsfp2_tx4_p, - output wire qsfp2_tx4_n, - input wire qsfp2_rx4_p, - input wire qsfp2_rx4_n, + output wire [3:0] qsfp2_tx_p, + output wire [3:0] qsfp2_tx_n, + input wire [3:0] qsfp2_rx_p, + input wire [3:0] qsfp2_rx_n, // input wire qsfp2_mgt_refclk_0_p, // input wire qsfp2_mgt_refclk_0_n, // input wire qsfp2_mgt_refclk_1_p, @@ -343,218 +319,109 @@ wire qsfp1_rx_block_lock_2; wire qsfp1_rx_block_lock_3; wire qsfp1_rx_block_lock_4; -wire qsfp1_mgt_refclk_0; +wire qsfp1_mgt_refclk; IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_0_inst ( .I (qsfp1_mgt_refclk_0_p), .IB (qsfp1_mgt_refclk_0_n), .CEB (1'b0), - .O (qsfp1_mgt_refclk_0), + .O (qsfp1_mgt_refclk), .ODIV2 () ); -wire qsfp1_qpll0lock; -wire qsfp1_qpll0outclk; -wire qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out - .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0), - .xcvr_qpll0lock_out(qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), + /* + * PLL + */ + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp1_tx_p), + .xcvr_txn(qsfp1_tx_n), + .xcvr_rxp(qsfp1_rx_p), + .xcvr_rxn(qsfp1_rx_n), - // Serial data - .xcvr_txp(qsfp1_tx1_p), - .xcvr_txn(qsfp1_tx1_n), - .xcvr_rxp(qsfp1_rx1_p), - .xcvr_rxn(qsfp1_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp1_tx_clk_1_int), + .phy_1_tx_rst(qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp1_txd_1_int), + .phy_1_xgmii_txc(qsfp1_txc_1_int), + .phy_1_rx_clk(qsfp1_rx_clk_1_int), + .phy_1_rx_rst(qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_1_int), - .phy_tx_rst(qsfp1_tx_rst_1_int), - .phy_xgmii_txd(qsfp1_txd_1_int), - .phy_xgmii_txc(qsfp1_txc_1_int), - .phy_rx_clk(qsfp1_rx_clk_1_int), - .phy_rx_rst(qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp1_rxd_1_int), - .phy_xgmii_rxc(qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp1_tx_clk_2_int), + .phy_2_tx_rst(qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp1_txd_2_int), + .phy_2_xgmii_txc(qsfp1_txc_2_int), + .phy_2_rx_clk(qsfp1_rx_clk_2_int), + .phy_2_rx_rst(qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp1_tx_clk_3_int), + .phy_3_tx_rst(qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp1_txd_3_int), + .phy_3_xgmii_txc(qsfp1_txc_3_int), + .phy_3_rx_clk(qsfp1_rx_clk_3_int), + .phy_3_rx_rst(qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx2_p), - .xcvr_txn(qsfp1_tx2_n), - .xcvr_rxp(qsfp1_rx2_p), - .xcvr_rxn(qsfp1_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_2_int), - .phy_tx_rst(qsfp1_tx_rst_2_int), - .phy_xgmii_txd(qsfp1_txd_2_int), - .phy_xgmii_txc(qsfp1_txc_2_int), - .phy_rx_clk(qsfp1_rx_clk_2_int), - .phy_rx_rst(qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp1_rxd_2_int), - .phy_xgmii_rxc(qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx3_p), - .xcvr_txn(qsfp1_tx3_n), - .xcvr_rxp(qsfp1_rx3_p), - .xcvr_rxn(qsfp1_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_3_int), - .phy_tx_rst(qsfp1_tx_rst_3_int), - .phy_xgmii_txd(qsfp1_txd_3_int), - .phy_xgmii_txc(qsfp1_txc_3_int), - .phy_rx_clk(qsfp1_rx_clk_3_int), - .phy_rx_rst(qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp1_rxd_3_int), - .phy_xgmii_rxc(qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx4_p), - .xcvr_txn(qsfp1_tx4_n), - .xcvr_rxp(qsfp1_rx4_p), - .xcvr_rxn(qsfp1_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_4_int), - .phy_tx_rst(qsfp1_tx_rst_4_int), - .phy_xgmii_txd(qsfp1_txd_4_int), - .phy_xgmii_txc(qsfp1_txc_4_int), - .phy_rx_clk(qsfp1_rx_clk_4_int), - .phy_rx_rst(qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp1_rxd_4_int), - .phy_xgmii_rxc(qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp1_tx_clk_4_int), + .phy_4_tx_rst(qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp1_txd_4_int), + .phy_4_xgmii_txc(qsfp1_txc_4_int), + .phy_4_rx_clk(qsfp1_rx_clk_4_int), + .phy_4_rx_rst(qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP2 @@ -600,208 +467,99 @@ wire qsfp2_rx_block_lock_2; wire qsfp2_rx_block_lock_3; wire qsfp2_rx_block_lock_4; -wire qsfp2_qpll0lock; -wire qsfp2_qpll0outclk; -wire qsfp2_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp2_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out - .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0), - .xcvr_qpll0lock_out(qsfp2_qpll0lock), - .xcvr_qpll0outclk_out(qsfp2_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp2_qpll0outrefclk), + /* + * PLL + */ + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp2_tx_p), + .xcvr_txn(qsfp2_tx_n), + .xcvr_rxp(qsfp2_rx_p), + .xcvr_rxn(qsfp2_rx_n), - // Serial data - .xcvr_txp(qsfp2_tx1_p), - .xcvr_txn(qsfp2_tx1_n), - .xcvr_rxp(qsfp2_rx1_p), - .xcvr_rxn(qsfp2_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp2_tx_clk_1_int), + .phy_1_tx_rst(qsfp2_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp2_txd_1_int), + .phy_1_xgmii_txc(qsfp2_txc_1_int), + .phy_1_rx_clk(qsfp2_rx_clk_1_int), + .phy_1_rx_rst(qsfp2_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp2_rxd_1_int), + .phy_1_xgmii_rxc(qsfp2_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp2_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_1_int), - .phy_tx_rst(qsfp2_tx_rst_1_int), - .phy_xgmii_txd(qsfp2_txd_1_int), - .phy_xgmii_txc(qsfp2_txc_1_int), - .phy_rx_clk(qsfp2_rx_clk_1_int), - .phy_rx_rst(qsfp2_rx_rst_1_int), - .phy_xgmii_rxd(qsfp2_rxd_1_int), - .phy_xgmii_rxc(qsfp2_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp2_tx_clk_2_int), + .phy_2_tx_rst(qsfp2_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp2_txd_2_int), + .phy_2_xgmii_txc(qsfp2_txc_2_int), + .phy_2_rx_clk(qsfp2_rx_clk_2_int), + .phy_2_rx_rst(qsfp2_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp2_rxd_2_int), + .phy_2_xgmii_rxc(qsfp2_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp2_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp2_tx_clk_3_int), + .phy_3_tx_rst(qsfp2_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp2_txd_3_int), + .phy_3_xgmii_txc(qsfp2_txc_3_int), + .phy_3_rx_clk(qsfp2_rx_clk_3_int), + .phy_3_rx_rst(qsfp2_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp2_rxd_3_int), + .phy_3_xgmii_rxc(qsfp2_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp2_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx2_p), - .xcvr_txn(qsfp2_tx2_n), - .xcvr_rxp(qsfp2_rx2_p), - .xcvr_rxn(qsfp2_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_2_int), - .phy_tx_rst(qsfp2_tx_rst_2_int), - .phy_xgmii_txd(qsfp2_txd_2_int), - .phy_xgmii_txc(qsfp2_txc_2_int), - .phy_rx_clk(qsfp2_rx_clk_2_int), - .phy_rx_rst(qsfp2_rx_rst_2_int), - .phy_xgmii_rxd(qsfp2_rxd_2_int), - .phy_xgmii_rxc(qsfp2_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx3_p), - .xcvr_txn(qsfp2_tx3_n), - .xcvr_rxp(qsfp2_rx3_p), - .xcvr_rxn(qsfp2_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_3_int), - .phy_tx_rst(qsfp2_tx_rst_3_int), - .phy_xgmii_txd(qsfp2_txd_3_int), - .phy_xgmii_txc(qsfp2_txc_3_int), - .phy_rx_clk(qsfp2_rx_clk_3_int), - .phy_rx_rst(qsfp2_rx_rst_3_int), - .phy_xgmii_rxd(qsfp2_rxd_3_int), - .phy_xgmii_rxc(qsfp2_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx4_p), - .xcvr_txn(qsfp2_tx4_n), - .xcvr_rxp(qsfp2_rx4_p), - .xcvr_rxn(qsfp2_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_4_int), - .phy_tx_rst(qsfp2_tx_rst_4_int), - .phy_xgmii_txd(qsfp2_txd_4_int), - .phy_xgmii_txc(qsfp2_txc_4_int), - .phy_rx_clk(qsfp2_rx_clk_4_int), - .phy_rx_rst(qsfp2_rx_rst_4_int), - .phy_xgmii_rxd(qsfp2_rxd_4_int), - .phy_xgmii_rxc(qsfp2_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp2_tx_clk_4_int), + .phy_4_tx_rst(qsfp2_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp2_txd_4_int), + .phy_4_xgmii_txc(qsfp2_txc_4_int), + .phy_4_rx_clk(qsfp2_rx_clk_4_int), + .phy_4_rx_rst(qsfp2_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp2_rxd_4_int), + .phy_4_xgmii_rxc(qsfp2_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp2_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // SGMII interface to PHY diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc index fb3596a51..8d5fb3f8f 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc @@ -131,22 +131,22 @@ set_false_path -from [get_ports {phy_int_n phy_mdio}] set_input_delay 0 [get_ports {phy_int_n phy_mdio}] # QSFP28 Interfaces -set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC Y2 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC Y1 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V7 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V6 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC W4 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC W3 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V2 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V1 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4 set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5 #set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28 @@ -167,22 +167,22 @@ set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] -set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC T2 } [get_ports {qsfp2_rx_p[0]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC T1 } [get_ports {qsfp2_rx_n[0]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC L5 } [get_ports {qsfp2_tx_p[0]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC L4 } [get_ports {qsfp2_tx_n[0]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC R4 } [get_ports {qsfp2_rx_p[1]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC R3 } [get_ports {qsfp2_rx_n[1]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC K7 } [get_ports {qsfp2_tx_p[1]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC K6 } [get_ports {qsfp2_tx_n[1]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC P2 } [get_ports {qsfp2_rx_p[2]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC P1 } [get_ports {qsfp2_rx_n[2]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J5 } [get_ports {qsfp2_tx_p[2]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J4 } [get_ports {qsfp2_tx_n[2]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC M2 } [get_ports {qsfp2_rx_p[3]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC M1 } [get_ports {qsfp2_rx_n[3]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H7 } [get_ports {qsfp2_tx_p[3]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H6 } [get_ports {qsfp2_tx_n[3]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 #set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 #set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 #set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35 diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile index 42996a88f..1f4bdd60d 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/mdio_master.v diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile index 42996a88f..1f4bdd60d 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/mdio_master.v diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v index 7e8b9d95e..fbfa089b2 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v @@ -60,22 +60,10 @@ module fpga ( /* * Ethernet: QSFP28 */ - output wire qsfp1_tx1_p, - output wire qsfp1_tx1_n, - input wire qsfp1_rx1_p, - input wire qsfp1_rx1_n, - output wire qsfp1_tx2_p, - output wire qsfp1_tx2_n, - input wire qsfp1_rx2_p, - input wire qsfp1_rx2_n, - output wire qsfp1_tx3_p, - output wire qsfp1_tx3_n, - input wire qsfp1_rx3_p, - input wire qsfp1_rx3_n, - output wire qsfp1_tx4_p, - output wire qsfp1_tx4_n, - input wire qsfp1_rx4_p, - input wire qsfp1_rx4_n, + output wire [3:0] qsfp1_tx_p, + output wire [3:0] qsfp1_tx_n, + input wire [3:0] qsfp1_rx_p, + input wire [3:0] qsfp1_rx_n, input wire qsfp1_mgt_refclk_0_p, input wire qsfp1_mgt_refclk_0_n, // input wire qsfp1_mgt_refclk_1_p, @@ -88,22 +76,10 @@ module fpga ( input wire qsfp1_intl, output wire qsfp1_lpmode, - output wire qsfp2_tx1_p, - output wire qsfp2_tx1_n, - input wire qsfp2_rx1_p, - input wire qsfp2_rx1_n, - output wire qsfp2_tx2_p, - output wire qsfp2_tx2_n, - input wire qsfp2_rx2_p, - input wire qsfp2_rx2_n, - output wire qsfp2_tx3_p, - output wire qsfp2_tx3_n, - input wire qsfp2_rx3_p, - input wire qsfp2_rx3_n, - output wire qsfp2_tx4_p, - output wire qsfp2_tx4_n, - input wire qsfp2_rx4_p, - input wire qsfp2_rx4_n, + output wire [3:0] qsfp2_tx_p, + output wire [3:0] qsfp2_tx_n, + input wire [3:0] qsfp2_rx_p, + input wire [3:0] qsfp2_rx_n, // input wire qsfp2_mgt_refclk_0_p, // input wire qsfp2_mgt_refclk_0_n, // input wire qsfp2_mgt_refclk_1_p, @@ -535,208 +511,99 @@ OBUFDS obufds_fmc_refclk_inst ( .OB(fmcp_hspc_sync_c2m_n) ); -wire qsfp1_qpll0lock; -wire qsfp1_qpll0outclk; -wire qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(qsfp1_gtpowergood), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), - .xcvr_qpll0lock_out(qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp1_tx_p), + .xcvr_txn(qsfp1_tx_n), + .xcvr_rxp(qsfp1_rx_p), + .xcvr_rxn(qsfp1_rx_n), - // Serial data - .xcvr_txp(qsfp1_tx1_p), - .xcvr_txn(qsfp1_tx1_n), - .xcvr_rxp(qsfp1_rx1_p), - .xcvr_rxn(qsfp1_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp1_tx_clk_1_int), + .phy_1_tx_rst(qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp1_txd_1_int), + .phy_1_xgmii_txc(qsfp1_txc_1_int), + .phy_1_rx_clk(qsfp1_rx_clk_1_int), + .phy_1_rx_rst(qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_1_int), - .phy_tx_rst(qsfp1_tx_rst_1_int), - .phy_xgmii_txd(qsfp1_txd_1_int), - .phy_xgmii_txc(qsfp1_txc_1_int), - .phy_rx_clk(qsfp1_rx_clk_1_int), - .phy_rx_rst(qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp1_rxd_1_int), - .phy_xgmii_rxc(qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp1_tx_clk_2_int), + .phy_2_tx_rst(qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp1_txd_2_int), + .phy_2_xgmii_txc(qsfp1_txc_2_int), + .phy_2_rx_clk(qsfp1_rx_clk_2_int), + .phy_2_rx_rst(qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp1_tx_clk_3_int), + .phy_3_tx_rst(qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp1_txd_3_int), + .phy_3_xgmii_txc(qsfp1_txc_3_int), + .phy_3_rx_clk(qsfp1_rx_clk_3_int), + .phy_3_rx_rst(qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx2_p), - .xcvr_txn(qsfp1_tx2_n), - .xcvr_rxp(qsfp1_rx2_p), - .xcvr_rxn(qsfp1_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_2_int), - .phy_tx_rst(qsfp1_tx_rst_2_int), - .phy_xgmii_txd(qsfp1_txd_2_int), - .phy_xgmii_txc(qsfp1_txc_2_int), - .phy_rx_clk(qsfp1_rx_clk_2_int), - .phy_rx_rst(qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp1_rxd_2_int), - .phy_xgmii_rxc(qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx3_p), - .xcvr_txn(qsfp1_tx3_n), - .xcvr_rxp(qsfp1_rx3_p), - .xcvr_rxn(qsfp1_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_3_int), - .phy_tx_rst(qsfp1_tx_rst_3_int), - .phy_xgmii_txd(qsfp1_txd_3_int), - .phy_xgmii_txc(qsfp1_txc_3_int), - .phy_rx_clk(qsfp1_rx_clk_3_int), - .phy_rx_rst(qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp1_rxd_3_int), - .phy_xgmii_rxc(qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx4_p), - .xcvr_txn(qsfp1_tx4_n), - .xcvr_rxp(qsfp1_rx4_p), - .xcvr_rxn(qsfp1_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_4_int), - .phy_tx_rst(qsfp1_tx_rst_4_int), - .phy_xgmii_txd(qsfp1_txd_4_int), - .phy_xgmii_txc(qsfp1_txc_4_int), - .phy_rx_clk(qsfp1_rx_clk_4_int), - .phy_rx_rst(qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp1_rxd_4_int), - .phy_xgmii_rxc(qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp1_tx_clk_4_int), + .phy_4_tx_rst(qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp1_txd_4_int), + .phy_4_xgmii_txc(qsfp1_txc_4_int), + .phy_4_rx_clk(qsfp1_rx_clk_4_int), + .phy_4_rx_rst(qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP2 @@ -782,208 +649,99 @@ wire qsfp2_rx_block_lock_2; wire qsfp2_rx_block_lock_3; wire qsfp2_rx_block_lock_4; -wire qsfp2_qpll0lock; -wire qsfp2_qpll0outclk; -wire qsfp2_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp2_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), - .xcvr_qpll0lock_out(qsfp2_qpll0lock), - .xcvr_qpll0outclk_out(qsfp2_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp2_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp2_tx_p), + .xcvr_txn(qsfp2_tx_n), + .xcvr_rxp(qsfp2_rx_p), + .xcvr_rxn(qsfp2_rx_n), - // Serial data - .xcvr_txp(qsfp2_tx1_p), - .xcvr_txn(qsfp2_tx1_n), - .xcvr_rxp(qsfp2_rx1_p), - .xcvr_rxn(qsfp2_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp2_tx_clk_1_int), + .phy_1_tx_rst(qsfp2_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp2_txd_1_int), + .phy_1_xgmii_txc(qsfp2_txc_1_int), + .phy_1_rx_clk(qsfp2_rx_clk_1_int), + .phy_1_rx_rst(qsfp2_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp2_rxd_1_int), + .phy_1_xgmii_rxc(qsfp2_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp2_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_1_int), - .phy_tx_rst(qsfp2_tx_rst_1_int), - .phy_xgmii_txd(qsfp2_txd_1_int), - .phy_xgmii_txc(qsfp2_txc_1_int), - .phy_rx_clk(qsfp2_rx_clk_1_int), - .phy_rx_rst(qsfp2_rx_rst_1_int), - .phy_xgmii_rxd(qsfp2_rxd_1_int), - .phy_xgmii_rxc(qsfp2_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp2_tx_clk_2_int), + .phy_2_tx_rst(qsfp2_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp2_txd_2_int), + .phy_2_xgmii_txc(qsfp2_txc_2_int), + .phy_2_rx_clk(qsfp2_rx_clk_2_int), + .phy_2_rx_rst(qsfp2_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp2_rxd_2_int), + .phy_2_xgmii_rxc(qsfp2_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp2_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp2_tx_clk_3_int), + .phy_3_tx_rst(qsfp2_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp2_txd_3_int), + .phy_3_xgmii_txc(qsfp2_txc_3_int), + .phy_3_rx_clk(qsfp2_rx_clk_3_int), + .phy_3_rx_rst(qsfp2_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp2_rxd_3_int), + .phy_3_xgmii_rxc(qsfp2_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp2_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx2_p), - .xcvr_txn(qsfp2_tx2_n), - .xcvr_rxp(qsfp2_rx2_p), - .xcvr_rxn(qsfp2_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_2_int), - .phy_tx_rst(qsfp2_tx_rst_2_int), - .phy_xgmii_txd(qsfp2_txd_2_int), - .phy_xgmii_txc(qsfp2_txc_2_int), - .phy_rx_clk(qsfp2_rx_clk_2_int), - .phy_rx_rst(qsfp2_rx_rst_2_int), - .phy_xgmii_rxd(qsfp2_rxd_2_int), - .phy_xgmii_rxc(qsfp2_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx3_p), - .xcvr_txn(qsfp2_tx3_n), - .xcvr_rxp(qsfp2_rx3_p), - .xcvr_rxn(qsfp2_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_3_int), - .phy_tx_rst(qsfp2_tx_rst_3_int), - .phy_xgmii_txd(qsfp2_txd_3_int), - .phy_xgmii_txc(qsfp2_txc_3_int), - .phy_rx_clk(qsfp2_rx_clk_3_int), - .phy_rx_rst(qsfp2_rx_rst_3_int), - .phy_xgmii_rxd(qsfp2_rxd_3_int), - .phy_xgmii_rxc(qsfp2_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx4_p), - .xcvr_txn(qsfp2_tx4_n), - .xcvr_rxp(qsfp2_rx4_p), - .xcvr_rxn(qsfp2_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_4_int), - .phy_tx_rst(qsfp2_tx_rst_4_int), - .phy_xgmii_txd(qsfp2_txd_4_int), - .phy_xgmii_txc(qsfp2_txc_4_int), - .phy_rx_clk(qsfp2_rx_clk_4_int), - .phy_rx_rst(qsfp2_rx_rst_4_int), - .phy_xgmii_rxd(qsfp2_rxd_4_int), - .phy_xgmii_rxc(qsfp2_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp2_tx_clk_4_int), + .phy_4_tx_rst(qsfp2_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp2_txd_4_int), + .phy_4_xgmii_txc(qsfp2_txc_4_int), + .phy_4_rx_clk(qsfp2_rx_clk_4_int), + .phy_4_rx_rst(qsfp2_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp2_rxd_4_int), + .phy_4_xgmii_rxc(qsfp2_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp2_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP1 @@ -1039,196 +797,99 @@ IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp1_mgt_refclk_inst ( .ODIV2 () ); -wire fmcp_qsfp1_qpll0lock; -wire fmcp_qsfp1_qpll0outclk; -wire fmcp_qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmcp_qsfp1_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmcp_qsfp1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmcp_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmcp_qsfp1_mgt_refclk), - .xcvr_qpll0lock_out(fmcp_qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(fmcp_qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmcp_qsfp1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmcp_qsfp1_tx_p), + .xcvr_txn(fmcp_qsfp1_tx_n), + .xcvr_rxp(fmcp_qsfp1_rx_p), + .xcvr_rxn(fmcp_qsfp1_rx_n), - // Serial data - .xcvr_txp(fmcp_qsfp1_tx_p[0]), - .xcvr_txn(fmcp_qsfp1_tx_n[0]), - .xcvr_rxp(fmcp_qsfp1_rx_p[0]), - .xcvr_rxn(fmcp_qsfp1_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmcp_qsfp1_tx_clk_1_int), + .phy_1_tx_rst(fmcp_qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(fmcp_qsfp1_txd_1_int), + .phy_1_xgmii_txc(fmcp_qsfp1_txc_1_int), + .phy_1_rx_clk(fmcp_qsfp1_rx_clk_1_int), + .phy_1_rx_rst(fmcp_qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(fmcp_qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(fmcp_qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmcp_qsfp1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmcp_qsfp1_tx_clk_1_int), - .phy_tx_rst(fmcp_qsfp1_tx_rst_1_int), - .phy_xgmii_txd(fmcp_qsfp1_txd_1_int), - .phy_xgmii_txc(fmcp_qsfp1_txc_1_int), - .phy_rx_clk(fmcp_qsfp1_rx_clk_1_int), - .phy_rx_rst(fmcp_qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(fmcp_qsfp1_rxd_1_int), - .phy_xgmii_rxc(fmcp_qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmcp_qsfp1_tx_clk_2_int), + .phy_2_tx_rst(fmcp_qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(fmcp_qsfp1_txd_2_int), + .phy_2_xgmii_txc(fmcp_qsfp1_txc_2_int), + .phy_2_rx_clk(fmcp_qsfp1_rx_clk_2_int), + .phy_2_rx_rst(fmcp_qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(fmcp_qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(fmcp_qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmcp_qsfp1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), + .phy_3_tx_clk(fmcp_qsfp1_tx_clk_3_int), + .phy_3_tx_rst(fmcp_qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(fmcp_qsfp1_txd_3_int), + .phy_3_xgmii_txc(fmcp_qsfp1_txc_3_int), + .phy_3_rx_clk(fmcp_qsfp1_rx_clk_3_int), + .phy_3_rx_rst(fmcp_qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(fmcp_qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(fmcp_qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmcp_qsfp1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp1_tx_p[1]), - .xcvr_txn(fmcp_qsfp1_tx_n[1]), - .xcvr_rxp(fmcp_qsfp1_rx_p[1]), - .xcvr_rxn(fmcp_qsfp1_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp1_tx_clk_2_int), - .phy_tx_rst(fmcp_qsfp1_tx_rst_2_int), - .phy_xgmii_txd(fmcp_qsfp1_txd_2_int), - .phy_xgmii_txc(fmcp_qsfp1_txc_2_int), - .phy_rx_clk(fmcp_qsfp1_rx_clk_2_int), - .phy_rx_rst(fmcp_qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(fmcp_qsfp1_rxd_2_int), - .phy_xgmii_rxc(fmcp_qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp1_tx_p[2]), - .xcvr_txn(fmcp_qsfp1_tx_n[2]), - .xcvr_rxp(fmcp_qsfp1_rx_p[2]), - .xcvr_rxn(fmcp_qsfp1_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp1_tx_clk_3_int), - .phy_tx_rst(fmcp_qsfp1_tx_rst_3_int), - .phy_xgmii_txd(fmcp_qsfp1_txd_3_int), - .phy_xgmii_txc(fmcp_qsfp1_txc_3_int), - .phy_rx_clk(fmcp_qsfp1_rx_clk_3_int), - .phy_rx_rst(fmcp_qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(fmcp_qsfp1_rxd_3_int), - .phy_xgmii_rxc(fmcp_qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp1_tx_p[3]), - .xcvr_txn(fmcp_qsfp1_tx_n[3]), - .xcvr_rxp(fmcp_qsfp1_rx_p[3]), - .xcvr_rxn(fmcp_qsfp1_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp1_tx_clk_4_int), - .phy_tx_rst(fmcp_qsfp1_tx_rst_4_int), - .phy_xgmii_txd(fmcp_qsfp1_txd_4_int), - .phy_xgmii_txc(fmcp_qsfp1_txc_4_int), - .phy_rx_clk(fmcp_qsfp1_rx_clk_4_int), - .phy_rx_rst(fmcp_qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(fmcp_qsfp1_rxd_4_int), - .phy_xgmii_rxc(fmcp_qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmcp_qsfp1_tx_clk_4_int), + .phy_4_tx_rst(fmcp_qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(fmcp_qsfp1_txd_4_int), + .phy_4_xgmii_txc(fmcp_qsfp1_txc_4_int), + .phy_4_rx_clk(fmcp_qsfp1_rx_clk_4_int), + .phy_4_rx_rst(fmcp_qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(fmcp_qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(fmcp_qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmcp_qsfp1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP2 @@ -1284,196 +945,99 @@ IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp2_mgt_refclk_inst ( .ODIV2 () ); -wire fmcp_qsfp2_qpll0lock; -wire fmcp_qsfp2_qpll0outclk; -wire fmcp_qsfp2_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmcp_qsfp2_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmcp_qsfp2_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmcp_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmcp_qsfp2_mgt_refclk), - .xcvr_qpll0lock_out(fmcp_qsfp2_qpll0lock), - .xcvr_qpll0outclk_out(fmcp_qsfp2_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmcp_qsfp2_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmcp_qsfp2_tx_p), + .xcvr_txn(fmcp_qsfp2_tx_n), + .xcvr_rxp(fmcp_qsfp2_rx_p), + .xcvr_rxn(fmcp_qsfp2_rx_n), - // Serial data - .xcvr_txp(fmcp_qsfp2_tx_p[0]), - .xcvr_txn(fmcp_qsfp2_tx_n[0]), - .xcvr_rxp(fmcp_qsfp2_rx_p[0]), - .xcvr_rxn(fmcp_qsfp2_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmcp_qsfp2_tx_clk_1_int), + .phy_1_tx_rst(fmcp_qsfp2_tx_rst_1_int), + .phy_1_xgmii_txd(fmcp_qsfp2_txd_1_int), + .phy_1_xgmii_txc(fmcp_qsfp2_txc_1_int), + .phy_1_rx_clk(fmcp_qsfp2_rx_clk_1_int), + .phy_1_rx_rst(fmcp_qsfp2_rx_rst_1_int), + .phy_1_xgmii_rxd(fmcp_qsfp2_rxd_1_int), + .phy_1_xgmii_rxc(fmcp_qsfp2_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmcp_qsfp2_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmcp_qsfp2_tx_clk_1_int), - .phy_tx_rst(fmcp_qsfp2_tx_rst_1_int), - .phy_xgmii_txd(fmcp_qsfp2_txd_1_int), - .phy_xgmii_txc(fmcp_qsfp2_txc_1_int), - .phy_rx_clk(fmcp_qsfp2_rx_clk_1_int), - .phy_rx_rst(fmcp_qsfp2_rx_rst_1_int), - .phy_xgmii_rxd(fmcp_qsfp2_rxd_1_int), - .phy_xgmii_rxc(fmcp_qsfp2_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmcp_qsfp2_tx_clk_2_int), + .phy_2_tx_rst(fmcp_qsfp2_tx_rst_2_int), + .phy_2_xgmii_txd(fmcp_qsfp2_txd_2_int), + .phy_2_xgmii_txc(fmcp_qsfp2_txc_2_int), + .phy_2_rx_clk(fmcp_qsfp2_rx_clk_2_int), + .phy_2_rx_rst(fmcp_qsfp2_rx_rst_2_int), + .phy_2_xgmii_rxd(fmcp_qsfp2_rxd_2_int), + .phy_2_xgmii_rxc(fmcp_qsfp2_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmcp_qsfp2_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp2_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), + .phy_3_tx_clk(fmcp_qsfp2_tx_clk_3_int), + .phy_3_tx_rst(fmcp_qsfp2_tx_rst_3_int), + .phy_3_xgmii_txd(fmcp_qsfp2_txd_3_int), + .phy_3_xgmii_txc(fmcp_qsfp2_txc_3_int), + .phy_3_rx_clk(fmcp_qsfp2_rx_clk_3_int), + .phy_3_rx_rst(fmcp_qsfp2_rx_rst_3_int), + .phy_3_xgmii_rxd(fmcp_qsfp2_rxd_3_int), + .phy_3_xgmii_rxc(fmcp_qsfp2_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmcp_qsfp2_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp2_tx_p[1]), - .xcvr_txn(fmcp_qsfp2_tx_n[1]), - .xcvr_rxp(fmcp_qsfp2_rx_p[1]), - .xcvr_rxn(fmcp_qsfp2_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp2_tx_clk_2_int), - .phy_tx_rst(fmcp_qsfp2_tx_rst_2_int), - .phy_xgmii_txd(fmcp_qsfp2_txd_2_int), - .phy_xgmii_txc(fmcp_qsfp2_txc_2_int), - .phy_rx_clk(fmcp_qsfp2_rx_clk_2_int), - .phy_rx_rst(fmcp_qsfp2_rx_rst_2_int), - .phy_xgmii_rxd(fmcp_qsfp2_rxd_2_int), - .phy_xgmii_rxc(fmcp_qsfp2_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp2_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp2_tx_p[2]), - .xcvr_txn(fmcp_qsfp2_tx_n[2]), - .xcvr_rxp(fmcp_qsfp2_rx_p[2]), - .xcvr_rxn(fmcp_qsfp2_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp2_tx_clk_3_int), - .phy_tx_rst(fmcp_qsfp2_tx_rst_3_int), - .phy_xgmii_txd(fmcp_qsfp2_txd_3_int), - .phy_xgmii_txc(fmcp_qsfp2_txc_3_int), - .phy_rx_clk(fmcp_qsfp2_rx_clk_3_int), - .phy_rx_rst(fmcp_qsfp2_rx_rst_3_int), - .phy_xgmii_rxd(fmcp_qsfp2_rxd_3_int), - .phy_xgmii_rxc(fmcp_qsfp2_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp2_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp2_tx_p[3]), - .xcvr_txn(fmcp_qsfp2_tx_n[3]), - .xcvr_rxp(fmcp_qsfp2_rx_p[3]), - .xcvr_rxn(fmcp_qsfp2_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp2_tx_clk_4_int), - .phy_tx_rst(fmcp_qsfp2_tx_rst_4_int), - .phy_xgmii_txd(fmcp_qsfp2_txd_4_int), - .phy_xgmii_txc(fmcp_qsfp2_txc_4_int), - .phy_rx_clk(fmcp_qsfp2_rx_clk_4_int), - .phy_rx_rst(fmcp_qsfp2_rx_rst_4_int), - .phy_xgmii_rxd(fmcp_qsfp2_rxd_4_int), - .phy_xgmii_rxc(fmcp_qsfp2_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmcp_qsfp2_tx_clk_4_int), + .phy_4_tx_rst(fmcp_qsfp2_tx_rst_4_int), + .phy_4_xgmii_txd(fmcp_qsfp2_txd_4_int), + .phy_4_xgmii_txc(fmcp_qsfp2_txc_4_int), + .phy_4_rx_clk(fmcp_qsfp2_rx_clk_4_int), + .phy_4_rx_rst(fmcp_qsfp2_rx_rst_4_int), + .phy_4_xgmii_rxd(fmcp_qsfp2_rxd_4_int), + .phy_4_xgmii_rxc(fmcp_qsfp2_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmcp_qsfp2_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP3 @@ -1529,196 +1093,99 @@ IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp3_mgt_refclk_inst ( .ODIV2 () ); -wire fmcp_qsfp3_qpll0lock; -wire fmcp_qsfp3_qpll0outclk; -wire fmcp_qsfp3_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmcp_qsfp3_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmcp_qsfp3_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmcp_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmcp_qsfp3_mgt_refclk), - .xcvr_qpll0lock_out(fmcp_qsfp3_qpll0lock), - .xcvr_qpll0outclk_out(fmcp_qsfp3_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmcp_qsfp3_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmcp_qsfp3_tx_p), + .xcvr_txn(fmcp_qsfp3_tx_n), + .xcvr_rxp(fmcp_qsfp3_rx_p), + .xcvr_rxn(fmcp_qsfp3_rx_n), - // Serial data - .xcvr_txp(fmcp_qsfp3_tx_p[0]), - .xcvr_txn(fmcp_qsfp3_tx_n[0]), - .xcvr_rxp(fmcp_qsfp3_rx_p[0]), - .xcvr_rxn(fmcp_qsfp3_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmcp_qsfp3_tx_clk_1_int), + .phy_1_tx_rst(fmcp_qsfp3_tx_rst_1_int), + .phy_1_xgmii_txd(fmcp_qsfp3_txd_1_int), + .phy_1_xgmii_txc(fmcp_qsfp3_txc_1_int), + .phy_1_rx_clk(fmcp_qsfp3_rx_clk_1_int), + .phy_1_rx_rst(fmcp_qsfp3_rx_rst_1_int), + .phy_1_xgmii_rxd(fmcp_qsfp3_rxd_1_int), + .phy_1_xgmii_rxc(fmcp_qsfp3_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmcp_qsfp3_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmcp_qsfp3_tx_clk_1_int), - .phy_tx_rst(fmcp_qsfp3_tx_rst_1_int), - .phy_xgmii_txd(fmcp_qsfp3_txd_1_int), - .phy_xgmii_txc(fmcp_qsfp3_txc_1_int), - .phy_rx_clk(fmcp_qsfp3_rx_clk_1_int), - .phy_rx_rst(fmcp_qsfp3_rx_rst_1_int), - .phy_xgmii_rxd(fmcp_qsfp3_rxd_1_int), - .phy_xgmii_rxc(fmcp_qsfp3_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmcp_qsfp3_tx_clk_2_int), + .phy_2_tx_rst(fmcp_qsfp3_tx_rst_2_int), + .phy_2_xgmii_txd(fmcp_qsfp3_txd_2_int), + .phy_2_xgmii_txc(fmcp_qsfp3_txc_2_int), + .phy_2_rx_clk(fmcp_qsfp3_rx_clk_2_int), + .phy_2_rx_rst(fmcp_qsfp3_rx_rst_2_int), + .phy_2_xgmii_rxd(fmcp_qsfp3_rxd_2_int), + .phy_2_xgmii_rxc(fmcp_qsfp3_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmcp_qsfp3_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp3_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), + .phy_3_tx_clk(fmcp_qsfp3_tx_clk_3_int), + .phy_3_tx_rst(fmcp_qsfp3_tx_rst_3_int), + .phy_3_xgmii_txd(fmcp_qsfp3_txd_3_int), + .phy_3_xgmii_txc(fmcp_qsfp3_txc_3_int), + .phy_3_rx_clk(fmcp_qsfp3_rx_clk_3_int), + .phy_3_rx_rst(fmcp_qsfp3_rx_rst_3_int), + .phy_3_xgmii_rxd(fmcp_qsfp3_rxd_3_int), + .phy_3_xgmii_rxc(fmcp_qsfp3_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmcp_qsfp3_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp3_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp3_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp3_tx_p[1]), - .xcvr_txn(fmcp_qsfp3_tx_n[1]), - .xcvr_rxp(fmcp_qsfp3_rx_p[1]), - .xcvr_rxn(fmcp_qsfp3_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp3_tx_clk_2_int), - .phy_tx_rst(fmcp_qsfp3_tx_rst_2_int), - .phy_xgmii_txd(fmcp_qsfp3_txd_2_int), - .phy_xgmii_txc(fmcp_qsfp3_txc_2_int), - .phy_rx_clk(fmcp_qsfp3_rx_clk_2_int), - .phy_rx_rst(fmcp_qsfp3_rx_rst_2_int), - .phy_xgmii_rxd(fmcp_qsfp3_rxd_2_int), - .phy_xgmii_rxc(fmcp_qsfp3_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp3_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp3_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp3_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp3_tx_p[2]), - .xcvr_txn(fmcp_qsfp3_tx_n[2]), - .xcvr_rxp(fmcp_qsfp3_rx_p[2]), - .xcvr_rxn(fmcp_qsfp3_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp3_tx_clk_3_int), - .phy_tx_rst(fmcp_qsfp3_tx_rst_3_int), - .phy_xgmii_txd(fmcp_qsfp3_txd_3_int), - .phy_xgmii_txc(fmcp_qsfp3_txc_3_int), - .phy_rx_clk(fmcp_qsfp3_rx_clk_3_int), - .phy_rx_rst(fmcp_qsfp3_rx_rst_3_int), - .phy_xgmii_rxd(fmcp_qsfp3_rxd_3_int), - .phy_xgmii_rxc(fmcp_qsfp3_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp3_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp3_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp3_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp3_tx_p[3]), - .xcvr_txn(fmcp_qsfp3_tx_n[3]), - .xcvr_rxp(fmcp_qsfp3_rx_p[3]), - .xcvr_rxn(fmcp_qsfp3_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp3_tx_clk_4_int), - .phy_tx_rst(fmcp_qsfp3_tx_rst_4_int), - .phy_xgmii_txd(fmcp_qsfp3_txd_4_int), - .phy_xgmii_txc(fmcp_qsfp3_txc_4_int), - .phy_rx_clk(fmcp_qsfp3_rx_clk_4_int), - .phy_rx_rst(fmcp_qsfp3_rx_rst_4_int), - .phy_xgmii_rxd(fmcp_qsfp3_rxd_4_int), - .phy_xgmii_rxc(fmcp_qsfp3_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmcp_qsfp3_tx_clk_4_int), + .phy_4_tx_rst(fmcp_qsfp3_tx_rst_4_int), + .phy_4_xgmii_txd(fmcp_qsfp3_txd_4_int), + .phy_4_xgmii_txc(fmcp_qsfp3_txc_4_int), + .phy_4_rx_clk(fmcp_qsfp3_rx_clk_4_int), + .phy_4_rx_rst(fmcp_qsfp3_rx_rst_4_int), + .phy_4_xgmii_rxd(fmcp_qsfp3_rxd_4_int), + .phy_4_xgmii_rxc(fmcp_qsfp3_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmcp_qsfp3_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP4 @@ -1774,196 +1241,99 @@ IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp4_mgt_refclk_inst ( .ODIV2 () ); -wire fmcp_qsfp4_qpll0lock; -wire fmcp_qsfp4_qpll0outclk; -wire fmcp_qsfp4_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmcp_qsfp4_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmcp_qsfp4_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmcp_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmcp_qsfp4_mgt_refclk), - .xcvr_qpll0lock_out(fmcp_qsfp4_qpll0lock), - .xcvr_qpll0outclk_out(fmcp_qsfp4_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmcp_qsfp4_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmcp_qsfp4_tx_p), + .xcvr_txn(fmcp_qsfp4_tx_n), + .xcvr_rxp(fmcp_qsfp4_rx_p), + .xcvr_rxn(fmcp_qsfp4_rx_n), - // Serial data - .xcvr_txp(fmcp_qsfp4_tx_p[0]), - .xcvr_txn(fmcp_qsfp4_tx_n[0]), - .xcvr_rxp(fmcp_qsfp4_rx_p[0]), - .xcvr_rxn(fmcp_qsfp4_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmcp_qsfp4_tx_clk_1_int), + .phy_1_tx_rst(fmcp_qsfp4_tx_rst_1_int), + .phy_1_xgmii_txd(fmcp_qsfp4_txd_1_int), + .phy_1_xgmii_txc(fmcp_qsfp4_txc_1_int), + .phy_1_rx_clk(fmcp_qsfp4_rx_clk_1_int), + .phy_1_rx_rst(fmcp_qsfp4_rx_rst_1_int), + .phy_1_xgmii_rxd(fmcp_qsfp4_rxd_1_int), + .phy_1_xgmii_rxc(fmcp_qsfp4_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmcp_qsfp4_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmcp_qsfp4_tx_clk_1_int), - .phy_tx_rst(fmcp_qsfp4_tx_rst_1_int), - .phy_xgmii_txd(fmcp_qsfp4_txd_1_int), - .phy_xgmii_txc(fmcp_qsfp4_txc_1_int), - .phy_rx_clk(fmcp_qsfp4_rx_clk_1_int), - .phy_rx_rst(fmcp_qsfp4_rx_rst_1_int), - .phy_xgmii_rxd(fmcp_qsfp4_rxd_1_int), - .phy_xgmii_rxc(fmcp_qsfp4_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmcp_qsfp4_tx_clk_2_int), + .phy_2_tx_rst(fmcp_qsfp4_tx_rst_2_int), + .phy_2_xgmii_txd(fmcp_qsfp4_txd_2_int), + .phy_2_xgmii_txc(fmcp_qsfp4_txc_2_int), + .phy_2_rx_clk(fmcp_qsfp4_rx_clk_2_int), + .phy_2_rx_rst(fmcp_qsfp4_rx_rst_2_int), + .phy_2_xgmii_rxd(fmcp_qsfp4_rxd_2_int), + .phy_2_xgmii_rxc(fmcp_qsfp4_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmcp_qsfp4_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp4_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), + .phy_3_tx_clk(fmcp_qsfp4_tx_clk_3_int), + .phy_3_tx_rst(fmcp_qsfp4_tx_rst_3_int), + .phy_3_xgmii_txd(fmcp_qsfp4_txd_3_int), + .phy_3_xgmii_txc(fmcp_qsfp4_txc_3_int), + .phy_3_rx_clk(fmcp_qsfp4_rx_clk_3_int), + .phy_3_rx_rst(fmcp_qsfp4_rx_rst_3_int), + .phy_3_xgmii_rxd(fmcp_qsfp4_rxd_3_int), + .phy_3_xgmii_rxc(fmcp_qsfp4_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmcp_qsfp4_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp4_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp4_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp4_tx_p[1]), - .xcvr_txn(fmcp_qsfp4_tx_n[1]), - .xcvr_rxp(fmcp_qsfp4_rx_p[1]), - .xcvr_rxn(fmcp_qsfp4_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp4_tx_clk_2_int), - .phy_tx_rst(fmcp_qsfp4_tx_rst_2_int), - .phy_xgmii_txd(fmcp_qsfp4_txd_2_int), - .phy_xgmii_txc(fmcp_qsfp4_txc_2_int), - .phy_rx_clk(fmcp_qsfp4_rx_clk_2_int), - .phy_rx_rst(fmcp_qsfp4_rx_rst_2_int), - .phy_xgmii_rxd(fmcp_qsfp4_rxd_2_int), - .phy_xgmii_rxc(fmcp_qsfp4_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp4_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp4_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp4_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp4_tx_p[2]), - .xcvr_txn(fmcp_qsfp4_tx_n[2]), - .xcvr_rxp(fmcp_qsfp4_rx_p[2]), - .xcvr_rxn(fmcp_qsfp4_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp4_tx_clk_3_int), - .phy_tx_rst(fmcp_qsfp4_tx_rst_3_int), - .phy_xgmii_txd(fmcp_qsfp4_txd_3_int), - .phy_xgmii_txc(fmcp_qsfp4_txc_3_int), - .phy_rx_clk(fmcp_qsfp4_rx_clk_3_int), - .phy_rx_rst(fmcp_qsfp4_rx_rst_3_int), - .phy_xgmii_rxd(fmcp_qsfp4_rxd_3_int), - .phy_xgmii_rxc(fmcp_qsfp4_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp4_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp4_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp4_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp4_tx_p[3]), - .xcvr_txn(fmcp_qsfp4_tx_n[3]), - .xcvr_rxp(fmcp_qsfp4_rx_p[3]), - .xcvr_rxn(fmcp_qsfp4_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp4_tx_clk_4_int), - .phy_tx_rst(fmcp_qsfp4_tx_rst_4_int), - .phy_xgmii_txd(fmcp_qsfp4_txd_4_int), - .phy_xgmii_txc(fmcp_qsfp4_txc_4_int), - .phy_rx_clk(fmcp_qsfp4_rx_clk_4_int), - .phy_rx_rst(fmcp_qsfp4_rx_rst_4_int), - .phy_xgmii_rxd(fmcp_qsfp4_rxd_4_int), - .phy_xgmii_rxc(fmcp_qsfp4_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmcp_qsfp4_tx_clk_4_int), + .phy_4_tx_rst(fmcp_qsfp4_tx_rst_4_int), + .phy_4_xgmii_txd(fmcp_qsfp4_txd_4_int), + .phy_4_xgmii_txc(fmcp_qsfp4_txc_4_int), + .phy_4_rx_clk(fmcp_qsfp4_rx_clk_4_int), + .phy_4_rx_rst(fmcp_qsfp4_rx_rst_4_int), + .phy_4_xgmii_rxd(fmcp_qsfp4_rxd_4_int), + .phy_4_xgmii_rxc(fmcp_qsfp4_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmcp_qsfp4_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP5 @@ -2019,196 +1389,99 @@ IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp5_mgt_refclk_inst ( .ODIV2 () ); -wire fmcp_qsfp5_qpll0lock; -wire fmcp_qsfp5_qpll0outclk; -wire fmcp_qsfp5_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmcp_qsfp5_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmcp_qsfp5_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmcp_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmcp_qsfp5_mgt_refclk), - .xcvr_qpll0lock_out(fmcp_qsfp5_qpll0lock), - .xcvr_qpll0outclk_out(fmcp_qsfp5_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmcp_qsfp5_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmcp_qsfp5_tx_p), + .xcvr_txn(fmcp_qsfp5_tx_n), + .xcvr_rxp(fmcp_qsfp5_rx_p), + .xcvr_rxn(fmcp_qsfp5_rx_n), - // Serial data - .xcvr_txp(fmcp_qsfp5_tx_p[0]), - .xcvr_txn(fmcp_qsfp5_tx_n[0]), - .xcvr_rxp(fmcp_qsfp5_rx_p[0]), - .xcvr_rxn(fmcp_qsfp5_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmcp_qsfp5_tx_clk_1_int), + .phy_1_tx_rst(fmcp_qsfp5_tx_rst_1_int), + .phy_1_xgmii_txd(fmcp_qsfp5_txd_1_int), + .phy_1_xgmii_txc(fmcp_qsfp5_txc_1_int), + .phy_1_rx_clk(fmcp_qsfp5_rx_clk_1_int), + .phy_1_rx_rst(fmcp_qsfp5_rx_rst_1_int), + .phy_1_xgmii_rxd(fmcp_qsfp5_rxd_1_int), + .phy_1_xgmii_rxc(fmcp_qsfp5_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmcp_qsfp5_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmcp_qsfp5_tx_clk_1_int), - .phy_tx_rst(fmcp_qsfp5_tx_rst_1_int), - .phy_xgmii_txd(fmcp_qsfp5_txd_1_int), - .phy_xgmii_txc(fmcp_qsfp5_txc_1_int), - .phy_rx_clk(fmcp_qsfp5_rx_clk_1_int), - .phy_rx_rst(fmcp_qsfp5_rx_rst_1_int), - .phy_xgmii_rxd(fmcp_qsfp5_rxd_1_int), - .phy_xgmii_rxc(fmcp_qsfp5_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmcp_qsfp5_tx_clk_2_int), + .phy_2_tx_rst(fmcp_qsfp5_tx_rst_2_int), + .phy_2_xgmii_txd(fmcp_qsfp5_txd_2_int), + .phy_2_xgmii_txc(fmcp_qsfp5_txc_2_int), + .phy_2_rx_clk(fmcp_qsfp5_rx_clk_2_int), + .phy_2_rx_rst(fmcp_qsfp5_rx_rst_2_int), + .phy_2_xgmii_rxd(fmcp_qsfp5_rxd_2_int), + .phy_2_xgmii_rxc(fmcp_qsfp5_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmcp_qsfp5_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp5_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), + .phy_3_tx_clk(fmcp_qsfp5_tx_clk_3_int), + .phy_3_tx_rst(fmcp_qsfp5_tx_rst_3_int), + .phy_3_xgmii_txd(fmcp_qsfp5_txd_3_int), + .phy_3_xgmii_txc(fmcp_qsfp5_txc_3_int), + .phy_3_rx_clk(fmcp_qsfp5_rx_clk_3_int), + .phy_3_rx_rst(fmcp_qsfp5_rx_rst_3_int), + .phy_3_xgmii_rxd(fmcp_qsfp5_rxd_3_int), + .phy_3_xgmii_rxc(fmcp_qsfp5_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmcp_qsfp5_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp5_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp5_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp5_tx_p[1]), - .xcvr_txn(fmcp_qsfp5_tx_n[1]), - .xcvr_rxp(fmcp_qsfp5_rx_p[1]), - .xcvr_rxn(fmcp_qsfp5_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp5_tx_clk_2_int), - .phy_tx_rst(fmcp_qsfp5_tx_rst_2_int), - .phy_xgmii_txd(fmcp_qsfp5_txd_2_int), - .phy_xgmii_txc(fmcp_qsfp5_txc_2_int), - .phy_rx_clk(fmcp_qsfp5_rx_clk_2_int), - .phy_rx_rst(fmcp_qsfp5_rx_rst_2_int), - .phy_xgmii_rxd(fmcp_qsfp5_rxd_2_int), - .phy_xgmii_rxc(fmcp_qsfp5_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp5_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp5_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp5_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp5_tx_p[2]), - .xcvr_txn(fmcp_qsfp5_tx_n[2]), - .xcvr_rxp(fmcp_qsfp5_rx_p[2]), - .xcvr_rxn(fmcp_qsfp5_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp5_tx_clk_3_int), - .phy_tx_rst(fmcp_qsfp5_tx_rst_3_int), - .phy_xgmii_txd(fmcp_qsfp5_txd_3_int), - .phy_xgmii_txc(fmcp_qsfp5_txc_3_int), - .phy_rx_clk(fmcp_qsfp5_rx_clk_3_int), - .phy_rx_rst(fmcp_qsfp5_rx_rst_3_int), - .phy_xgmii_rxd(fmcp_qsfp5_rxd_3_int), - .phy_xgmii_rxc(fmcp_qsfp5_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp5_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp5_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp5_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp5_tx_p[3]), - .xcvr_txn(fmcp_qsfp5_tx_n[3]), - .xcvr_rxp(fmcp_qsfp5_rx_p[3]), - .xcvr_rxn(fmcp_qsfp5_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp5_tx_clk_4_int), - .phy_tx_rst(fmcp_qsfp5_tx_rst_4_int), - .phy_xgmii_txd(fmcp_qsfp5_txd_4_int), - .phy_xgmii_txc(fmcp_qsfp5_txc_4_int), - .phy_rx_clk(fmcp_qsfp5_rx_clk_4_int), - .phy_rx_rst(fmcp_qsfp5_rx_rst_4_int), - .phy_xgmii_rxd(fmcp_qsfp5_rxd_4_int), - .phy_xgmii_rxc(fmcp_qsfp5_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmcp_qsfp5_tx_clk_4_int), + .phy_4_tx_rst(fmcp_qsfp5_tx_rst_4_int), + .phy_4_xgmii_txd(fmcp_qsfp5_txd_4_int), + .phy_4_xgmii_txc(fmcp_qsfp5_txc_4_int), + .phy_4_rx_clk(fmcp_qsfp5_rx_clk_4_int), + .phy_4_rx_rst(fmcp_qsfp5_rx_rst_4_int), + .phy_4_xgmii_rxd(fmcp_qsfp5_rxd_4_int), + .phy_4_xgmii_rxc(fmcp_qsfp5_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmcp_qsfp5_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP6 @@ -2264,196 +1537,99 @@ IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp6_mgt_refclk_inst ( .ODIV2 () ); -wire fmcp_qsfp6_qpll0lock; -wire fmcp_qsfp6_qpll0outclk; -wire fmcp_qsfp6_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmcp_qsfp6_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmcp_qsfp6_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmcp_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmcp_qsfp6_mgt_refclk), - .xcvr_qpll0lock_out(fmcp_qsfp6_qpll0lock), - .xcvr_qpll0outclk_out(fmcp_qsfp6_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmcp_qsfp6_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmcp_qsfp6_tx_p), + .xcvr_txn(fmcp_qsfp6_tx_n), + .xcvr_rxp(fmcp_qsfp6_rx_p), + .xcvr_rxn(fmcp_qsfp6_rx_n), - // Serial data - .xcvr_txp(fmcp_qsfp6_tx_p[0]), - .xcvr_txn(fmcp_qsfp6_tx_n[0]), - .xcvr_rxp(fmcp_qsfp6_rx_p[0]), - .xcvr_rxn(fmcp_qsfp6_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmcp_qsfp6_tx_clk_1_int), + .phy_1_tx_rst(fmcp_qsfp6_tx_rst_1_int), + .phy_1_xgmii_txd(fmcp_qsfp6_txd_1_int), + .phy_1_xgmii_txc(fmcp_qsfp6_txc_1_int), + .phy_1_rx_clk(fmcp_qsfp6_rx_clk_1_int), + .phy_1_rx_rst(fmcp_qsfp6_rx_rst_1_int), + .phy_1_xgmii_rxd(fmcp_qsfp6_rxd_1_int), + .phy_1_xgmii_rxc(fmcp_qsfp6_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmcp_qsfp6_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmcp_qsfp6_tx_clk_1_int), - .phy_tx_rst(fmcp_qsfp6_tx_rst_1_int), - .phy_xgmii_txd(fmcp_qsfp6_txd_1_int), - .phy_xgmii_txc(fmcp_qsfp6_txc_1_int), - .phy_rx_clk(fmcp_qsfp6_rx_clk_1_int), - .phy_rx_rst(fmcp_qsfp6_rx_rst_1_int), - .phy_xgmii_rxd(fmcp_qsfp6_rxd_1_int), - .phy_xgmii_rxc(fmcp_qsfp6_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmcp_qsfp6_tx_clk_2_int), + .phy_2_tx_rst(fmcp_qsfp6_tx_rst_2_int), + .phy_2_xgmii_txd(fmcp_qsfp6_txd_2_int), + .phy_2_xgmii_txc(fmcp_qsfp6_txc_2_int), + .phy_2_rx_clk(fmcp_qsfp6_rx_clk_2_int), + .phy_2_rx_rst(fmcp_qsfp6_rx_rst_2_int), + .phy_2_xgmii_rxd(fmcp_qsfp6_rxd_2_int), + .phy_2_xgmii_rxc(fmcp_qsfp6_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmcp_qsfp6_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp6_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), + .phy_3_tx_clk(fmcp_qsfp6_tx_clk_3_int), + .phy_3_tx_rst(fmcp_qsfp6_tx_rst_3_int), + .phy_3_xgmii_txd(fmcp_qsfp6_txd_3_int), + .phy_3_xgmii_txc(fmcp_qsfp6_txc_3_int), + .phy_3_rx_clk(fmcp_qsfp6_rx_clk_3_int), + .phy_3_rx_rst(fmcp_qsfp6_rx_rst_3_int), + .phy_3_xgmii_rxd(fmcp_qsfp6_rxd_3_int), + .phy_3_xgmii_rxc(fmcp_qsfp6_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmcp_qsfp6_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp6_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp6_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp6_tx_p[1]), - .xcvr_txn(fmcp_qsfp6_tx_n[1]), - .xcvr_rxp(fmcp_qsfp6_rx_p[1]), - .xcvr_rxn(fmcp_qsfp6_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp6_tx_clk_2_int), - .phy_tx_rst(fmcp_qsfp6_tx_rst_2_int), - .phy_xgmii_txd(fmcp_qsfp6_txd_2_int), - .phy_xgmii_txc(fmcp_qsfp6_txc_2_int), - .phy_rx_clk(fmcp_qsfp6_rx_clk_2_int), - .phy_rx_rst(fmcp_qsfp6_rx_rst_2_int), - .phy_xgmii_rxd(fmcp_qsfp6_rxd_2_int), - .phy_xgmii_rxc(fmcp_qsfp6_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp6_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp6_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp6_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp6_tx_p[2]), - .xcvr_txn(fmcp_qsfp6_tx_n[2]), - .xcvr_rxp(fmcp_qsfp6_rx_p[2]), - .xcvr_rxn(fmcp_qsfp6_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp6_tx_clk_3_int), - .phy_tx_rst(fmcp_qsfp6_tx_rst_3_int), - .phy_xgmii_txd(fmcp_qsfp6_txd_3_int), - .phy_xgmii_txc(fmcp_qsfp6_txc_3_int), - .phy_rx_clk(fmcp_qsfp6_rx_clk_3_int), - .phy_rx_rst(fmcp_qsfp6_rx_rst_3_int), - .phy_xgmii_rxd(fmcp_qsfp6_rxd_3_int), - .phy_xgmii_rxc(fmcp_qsfp6_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp6_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp6_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp6_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp6_tx_p[3]), - .xcvr_txn(fmcp_qsfp6_tx_n[3]), - .xcvr_rxp(fmcp_qsfp6_rx_p[3]), - .xcvr_rxn(fmcp_qsfp6_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp6_tx_clk_4_int), - .phy_tx_rst(fmcp_qsfp6_tx_rst_4_int), - .phy_xgmii_txd(fmcp_qsfp6_txd_4_int), - .phy_xgmii_txc(fmcp_qsfp6_txc_4_int), - .phy_rx_clk(fmcp_qsfp6_rx_clk_4_int), - .phy_rx_rst(fmcp_qsfp6_rx_rst_4_int), - .phy_xgmii_rxd(fmcp_qsfp6_rxd_4_int), - .phy_xgmii_rxc(fmcp_qsfp6_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmcp_qsfp6_tx_clk_4_int), + .phy_4_tx_rst(fmcp_qsfp6_tx_rst_4_int), + .phy_4_xgmii_txd(fmcp_qsfp6_txd_4_int), + .phy_4_xgmii_txc(fmcp_qsfp6_txc_4_int), + .phy_4_rx_clk(fmcp_qsfp6_rx_clk_4_int), + .phy_4_rx_rst(fmcp_qsfp6_rx_rst_4_int), + .phy_4_xgmii_rxd(fmcp_qsfp6_rxd_4_int), + .phy_4_xgmii_rxc(fmcp_qsfp6_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmcp_qsfp6_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // SGMII interface to PHY From 68736d02ae541b7f0d9cee89e03ddc9917965450 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 25 Aug 2023 23:06:49 -0700 Subject: [PATCH 06/19] Add 10G/25G design for Arista 7132LB-48Y4C switch Signed-off-by: Alex Forencich --- example/Arista_7132LB/fpga_25g/README.md | 40 + .../Arista_7132LB/fpga_25g/common/vivado.mk | 137 ++++ example/Arista_7132LB/fpga_25g/fpga.xdc | 533 +++++++++++++ example/Arista_7132LB/fpga_25g/fpga/Makefile | 75 ++ .../Arista_7132LB/fpga_25g/fpga/config.tcl | 51 ++ .../Arista_7132LB/fpga_25g/fpga_10g/Makefile | 75 ++ .../fpga_25g/fpga_10g/config.tcl | 51 ++ .../Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl | 76 ++ example/Arista_7132LB/fpga_25g/lib/eth | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++ .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 307 ++++++++ example/Arista_7132LB/fpga_25g/rtl/fpga.v | 323 ++++++++ .../Arista_7132LB/fpga_25g/rtl/fpga_core.v | 738 ++++++++++++++++++ .../Arista_7132LB/fpga_25g/rtl/sync_signal.v | 62 ++ .../fpga_25g/tb/fpga_core/Makefile | 96 +++ .../fpga_25g/tb/fpga_core/test_fpga_core.py | 220 ++++++ .../fpga_25g/tb/fpga_core/test_fpga_core.v | 104 +++ 17 files changed, 3284 insertions(+) create mode 100644 example/Arista_7132LB/fpga_25g/README.md create mode 100644 example/Arista_7132LB/fpga_25g/common/vivado.mk create mode 100644 example/Arista_7132LB/fpga_25g/fpga.xdc create mode 100644 example/Arista_7132LB/fpga_25g/fpga/Makefile create mode 100644 example/Arista_7132LB/fpga_25g/fpga/config.tcl create mode 100644 example/Arista_7132LB/fpga_25g/fpga_10g/Makefile create mode 100644 example/Arista_7132LB/fpga_25g/fpga_10g/config.tcl create mode 100644 example/Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl create mode 120000 example/Arista_7132LB/fpga_25g/lib/eth create mode 100644 example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v create mode 100644 example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v create mode 100644 example/Arista_7132LB/fpga_25g/rtl/fpga.v create mode 100644 example/Arista_7132LB/fpga_25g/rtl/fpga_core.v create mode 100644 example/Arista_7132LB/fpga_25g/rtl/sync_signal.v create mode 100644 example/Arista_7132LB/fpga_25g/tb/fpga_core/Makefile create mode 100644 example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py create mode 100644 example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v diff --git a/example/Arista_7132LB/fpga_25g/README.md b/example/Arista_7132LB/fpga_25g/README.md new file mode 100644 index 000000000..35164be49 --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/README.md @@ -0,0 +1,40 @@ +# Verilog Ethernet Arista 7132LB Example Design + +## Introduction + +This example design targets the Arista 7132LB-48Y4C switch. + +The design by default listens to UDP port 1234 at IP address 192.168.1.128 and +will echo back any packets received. The design will also respond correctly +to ARP requests. + +* FPGA: xcvu9p-flgb2104-3-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver + +## How to build + +Run make to build. Ensure that the Xilinx Vivado toolchain components are +in PATH. + +## How to test + +Load the design onto the FPGA in the 7132LB switch either by using the hardware manager on the switch, or by copying the bit file to the switch with scp and then loading it onto the FPGA with xc3sprog. + +To load the design with xc3sprog, run the following commands on the switch: + + switch>en + switch#conf t + switch(config)#bash sudo bash + bash-4.2# user@host:/path/to/fpga.bit . + bash-4.2# xc3sprog -c metamako -J 10000000 fpga.bit + +Once the design is running on the FPGA, run + + netcat -u 192.168.1.128 1234 + +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/Arista_7132LB/fpga_25g/common/vivado.mk b/example/Arista_7132LB/fpga_25g/common/vivado.mk new file mode 100644 index 000000000..1402e2382 --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/common/vivado.mk @@ -0,0 +1,137 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) + +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +ifdef XDC_FILES + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +else + XDC_FILES_REL = $(PROJECT).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/example/Arista_7132LB/fpga_25g/fpga.xdc b/example/Arista_7132LB/fpga_25g/fpga.xdc new file mode 100644 index 000000000..edad2baaa --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/fpga.xdc @@ -0,0 +1,533 @@ +# XDC constraints for the Arista 7132LB +# part: xcvu9p-flgb2104-3-e + +# General configuration +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# System clocks +# User refclk 0 156.26 MHz +set_property -dict {LOC AY13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_NONE} [get_ports {refclk_user_p[0]}] +set_property -dict {LOC BA13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_NONE} [get_ports {refclk_user_n[0]}] +create_clock -period 6.400 -name refclk_user_0 [get_ports {refclk_user_p[0]}] + +# User refclk 1 156.26 MHz +set_property -dict {LOC AW28 IOSTANDARD DIFF_SSTL12} [get_ports {refclk_user_p[1]}] +set_property -dict {LOC AY28 IOSTANDARD DIFF_SSTL12} [get_ports {refclk_user_n[1]}] +create_clock -period 6.400 -name refclk_user_1 [get_ports {refclk_user_p[1]}] + +# DDR4 DIMM 0 refclk +#set_property -dict {LOC N32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_dimm0_refclk_p] +#set_property -dict {LOC N33 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_dimm0_refclk_n] +#create_clock -period 3.333 -name clk_ddr4_dimm0_refclk [get_ports clk_ddr4_dimm0_refclk_p] + +# DDR4 DIMM 1 refclk +#set_property -dict {LOC BA35 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_dimm1_refclk_p] +#set_property -dict {LOC BB35 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_dimm1_refclk_n] +#create_clock -period 3.333 -name clk_ddr4_dimm1_refclk [get_ports clk_ddr4_dimm1_refclk_p] + +# DDR4 DIMM 2 refclk +#set_property -dict {LOC AV19 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_dimm2_refclk_p] +#set_property -dict {LOC AW19 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_dimm2_refclk_n] +#create_clock -period 3.333 -name clk_ddr4_dimm2_refclk [get_ports clk_ddr4_dimm2_refclk_p] + +# DDR4 DIMM 3 refclk +#set_property -dict {LOC J16 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_dimm3_refclk_p] +#set_property -dict {LOC J15 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_dimm3_refclk_n] +#create_clock -period 3.333 -name clk_ddr4_dimm3_refclk [get_ports clk_ddr4_dimm3_refclk_p] + +# Ethernet interfaces + +# GTY quad 122 +# 7132LB-48Y4C: SFP 1, 2, 3, 4 +set_property -dict {LOC AN45} [get_ports {eth_gt_ch_rx_p[0]}] ;# MGTYRXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN46} [get_ports {eth_gt_ch_rx_n[0]}] ;# MGTYRXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN40} [get_ports {eth_gt_ch_tx_p[0]}] ;# MGTYTXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN41} [get_ports {eth_gt_ch_tx_n[0]}] ;# MGTYTXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM43} [get_ports {eth_gt_ch_rx_p[1]}] ;# MGTYRXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM44} [get_ports {eth_gt_ch_rx_n[1]}] ;# MGTYRXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM38} [get_ports {eth_gt_ch_tx_p[1]}] ;# MGTYTXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM39} [get_ports {eth_gt_ch_tx_n[1]}] ;# MGTYTXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL45} [get_ports {eth_gt_ch_rx_p[2]}] ;# MGTYRXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL46} [get_ports {eth_gt_ch_rx_n[2]}] ;# MGTYRXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL40} [get_ports {eth_gt_ch_tx_p[2]}] ;# MGTYTXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL41} [get_ports {eth_gt_ch_tx_n[2]}] ;# MGTYTXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK43} [get_ports {eth_gt_ch_rx_p[3]}] ;# MGTYRXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK44} [get_ports {eth_gt_ch_rx_n[3]}] ;# MGTYRXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK38} [get_ports {eth_gt_ch_tx_p[3]}] ;# MGTYTXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK39} [get_ports {eth_gt_ch_tx_n[3]}] ;# MGTYTXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AR36} [get_ports {eth_gt_pri_refclk_p[0]}] ;# MGTREFCLK0P_122 +set_property -dict {LOC AR37} [get_ports {eth_gt_pri_refclk_n[0]}] ;# MGTREFCLK0N_122 +#set_property -dict {LOC AN36} [get_ports {eth_gt_sec_refclk_p[4]}] ;# MGTREFCLK1P_122 +#set_property -dict {LOC AN37} [get_ports {eth_gt_sec_refclk_n[4]}] ;# MGTREFCLK1N_122 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_0 [get_ports {eth_gt_pri_refclk_p[0]}] + +# 125 MHz MGT secondary reference clock +#create_clock -period 8.000 -name eth_gt_sec_refclk_4 [get_ports {eth_gt_sec_refclk_p[4]}] + +# GTY quad 123 +# 7132LB-48Y4C: SFP 5, 6, 7, 8 +set_property -dict {LOC AJ45} [get_ports {eth_gt_ch_rx_p[4]}] ;# MGTYRXP0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ46} [get_ports {eth_gt_ch_rx_n[4]}] ;# MGTYRXN0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ40} [get_ports {eth_gt_ch_tx_p[4]}] ;# MGTYTXP0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ41} [get_ports {eth_gt_ch_tx_n[4]}] ;# MGTYTXN0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH43} [get_ports {eth_gt_ch_rx_p[5]}] ;# MGTYRXP1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH44} [get_ports {eth_gt_ch_rx_n[5]}] ;# MGTYRXN1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH38} [get_ports {eth_gt_ch_tx_p[5]}] ;# MGTYTXP1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH39} [get_ports {eth_gt_ch_tx_n[5]}] ;# MGTYTXN1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG45} [get_ports {eth_gt_ch_rx_p[6]}] ;# MGTYRXP2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG46} [get_ports {eth_gt_ch_rx_n[6]}] ;# MGTYRXN2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG40} [get_ports {eth_gt_ch_tx_p[6]}] ;# MGTYTXP2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG41} [get_ports {eth_gt_ch_tx_n[6]}] ;# MGTYTXN2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF43} [get_ports {eth_gt_ch_rx_p[7]}] ;# MGTYRXP3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF44} [get_ports {eth_gt_ch_rx_n[7]}] ;# MGTYRXN3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF38} [get_ports {eth_gt_ch_tx_p[7]}] ;# MGTYTXP3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF39} [get_ports {eth_gt_ch_tx_n[7]}] ;# MGTYTXN3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AL36} [get_ports {eth_gt_pri_refclk_p[1]}] ;# MGTREFCLK0P_123 +set_property -dict {LOC AL37} [get_ports {eth_gt_pri_refclk_n[1]}] ;# MGTREFCLK0N_123 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_1 [get_ports {eth_gt_pri_refclk_p[1]}] + +# GTY quad 124 +# 7132LB-48Y4C: SFP 9, 10, 11, 12 +set_property -dict {LOC AE45} [get_ports {eth_gt_ch_rx_p[8]}] ;# MGTYRXP0_124 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AE46} [get_ports {eth_gt_ch_rx_n[8]}] ;# MGTYRXN0_124 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AE40} [get_ports {eth_gt_ch_tx_p[8]}] ;# MGTYTXP0_124 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AE41} [get_ports {eth_gt_ch_tx_n[8]}] ;# MGTYTXN0_124 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD43} [get_ports {eth_gt_ch_rx_p[9]}] ;# MGTYRXP1_124 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD44} [get_ports {eth_gt_ch_rx_n[9]}] ;# MGTYRXN1_124 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD38} [get_ports {eth_gt_ch_tx_p[9]}] ;# MGTYTXP1_124 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD39} [get_ports {eth_gt_ch_tx_n[9]}] ;# MGTYTXN1_124 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC45} [get_ports {eth_gt_ch_rx_p[10]}] ;# MGTYRXP2_124 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC46} [get_ports {eth_gt_ch_rx_n[10]}] ;# MGTYRXN2_124 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC40} [get_ports {eth_gt_ch_tx_p[10]}] ;# MGTYTXP2_124 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC41} [get_ports {eth_gt_ch_tx_n[10]}] ;# MGTYTXN2_124 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB43} [get_ports {eth_gt_ch_rx_p[11]}] ;# MGTYRXP3_124 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB44} [get_ports {eth_gt_ch_rx_n[11]}] ;# MGTYRXN3_124 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB38} [get_ports {eth_gt_ch_tx_p[11]}] ;# MGTYTXP3_124 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB39} [get_ports {eth_gt_ch_tx_n[11]}] ;# MGTYTXN3_124 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AG36} [get_ports {eth_gt_pri_refclk_p[2]}] ;# MGTREFCLK0P_124 +set_property -dict {LOC AG37} [get_ports {eth_gt_pri_refclk_n[2]}] ;# MGTREFCLK0N_124 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_2 [get_ports {eth_gt_pri_refclk_p[2]}] + +# GTY quad 125 +# 7132LB-48Y4C: SFP 13, 14, 15, 16 +set_property -dict {LOC AA45} [get_ports {eth_gt_ch_rx_p[12]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA46} [get_ports {eth_gt_ch_rx_n[12]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA40} [get_ports {eth_gt_ch_tx_p[12]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA41} [get_ports {eth_gt_ch_tx_n[12]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y43 } [get_ports {eth_gt_ch_rx_p[13]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y44 } [get_ports {eth_gt_ch_rx_n[13]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y38 } [get_ports {eth_gt_ch_tx_p[13]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y39 } [get_ports {eth_gt_ch_tx_n[13]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W45 } [get_ports {eth_gt_ch_rx_p[14]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W46 } [get_ports {eth_gt_ch_rx_n[14]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W40 } [get_ports {eth_gt_ch_tx_p[14]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W41 } [get_ports {eth_gt_ch_tx_n[14]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V43 } [get_ports {eth_gt_ch_rx_p[15]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V44 } [get_ports {eth_gt_ch_rx_n[15]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V38 } [get_ports {eth_gt_ch_tx_p[15]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V39 } [get_ports {eth_gt_ch_tx_n[15]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AC36} [get_ports {eth_gt_pri_refclk_p[3]}] ;# MGTREFCLK0P_125 +set_property -dict {LOC AC37} [get_ports {eth_gt_pri_refclk_n[3]}] ;# MGTREFCLK0N_125 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_3 [get_ports {eth_gt_pri_refclk_p[3]}] + +# GTY quad 126 +# 7132LB-48Y4C: SFP 17, 18, 19, 20 +set_property -dict {LOC U45 } [get_ports {eth_gt_ch_rx_p[16]}] ;# MGTYRXP0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC U46 } [get_ports {eth_gt_ch_rx_n[16]}] ;# MGTYRXN0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC U40 } [get_ports {eth_gt_ch_tx_p[16]}] ;# MGTYTXP0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC U41 } [get_ports {eth_gt_ch_tx_n[16]}] ;# MGTYTXN0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T43 } [get_ports {eth_gt_ch_rx_p[17]}] ;# MGTYRXP1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T44 } [get_ports {eth_gt_ch_rx_n[17]}] ;# MGTYRXN1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T38 } [get_ports {eth_gt_ch_tx_p[17]}] ;# MGTYTXP1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T39 } [get_ports {eth_gt_ch_tx_n[17]}] ;# MGTYTXN1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R45 } [get_ports {eth_gt_ch_rx_p[18]}] ;# MGTYRXP2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R46 } [get_ports {eth_gt_ch_rx_n[18]}] ;# MGTYRXN2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R40 } [get_ports {eth_gt_ch_tx_p[18]}] ;# MGTYTXP2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R41 } [get_ports {eth_gt_ch_tx_n[18]}] ;# MGTYTXN2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P43 } [get_ports {eth_gt_ch_rx_p[19]}] ;# MGTYRXP3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P44 } [get_ports {eth_gt_ch_rx_n[19]}] ;# MGTYRXN3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P38 } [get_ports {eth_gt_ch_tx_p[19]}] ;# MGTYTXP3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P39 } [get_ports {eth_gt_ch_tx_n[19]}] ;# MGTYTXN3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC W36 } [get_ports {eth_gt_pri_refclk_p[4]}] ;# MGTREFCLK0P_126 +set_property -dict {LOC W37 } [get_ports {eth_gt_pri_refclk_n[4]}] ;# MGTREFCLK0N_126 +#set_property -dict {LOC U36 } [get_ports {eth_gt_sec_refclk_p[5]}] ;# MGTREFCLK1P_126 +#set_property -dict {LOC U37 } [get_ports {eth_gt_sec_refclk_n[5]}] ;# MGTREFCLK1N_126 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_4 [get_ports {eth_gt_pri_refclk_p[4]}] + +# 125 MHz MGT secondary reference clock +#create_clock -period 8.000 -name eth_gt_sec_refclk_5 [get_ports {eth_gt_sec_refclk_p[5]}] + +# GTY quad 127 +# 7132LB-48Y4C: SFP 21, 22, 23, 24 +set_property -dict {LOC N45 } [get_ports {eth_gt_ch_rx_p[20]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N46 } [get_ports {eth_gt_ch_rx_n[20]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N40 } [get_ports {eth_gt_ch_tx_p[20]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N41 } [get_ports {eth_gt_ch_tx_n[20]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M43 } [get_ports {eth_gt_ch_rx_p[21]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M44 } [get_ports {eth_gt_ch_rx_n[21]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M38 } [get_ports {eth_gt_ch_tx_p[21]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M39 } [get_ports {eth_gt_ch_tx_n[21]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L45 } [get_ports {eth_gt_ch_rx_p[22]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L46 } [get_ports {eth_gt_ch_rx_n[22]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L40 } [get_ports {eth_gt_ch_tx_p[22]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L41 } [get_ports {eth_gt_ch_tx_n[22]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC K43 } [get_ports {eth_gt_ch_rx_p[23]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC K44 } [get_ports {eth_gt_ch_rx_n[23]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC J40 } [get_ports {eth_gt_ch_tx_p[23]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC J41 } [get_ports {eth_gt_ch_tx_n[23]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC R36 } [get_ports {eth_gt_pri_refclk_p[5]}] ;# MGTREFCLK0P_127 +set_property -dict {LOC R37 } [get_ports {eth_gt_pri_refclk_n[5]}] ;# MGTREFCLK0N_127 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_5 [get_ports {eth_gt_pri_refclk_p[5]}] + +# GTY quad 232 +# 7132LB-48Y4C: SFP 28, 27, 26, 25 +set_property -dict {LOC F2 } [get_ports {eth_gt_ch_rx_p[24]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC F1 } [get_ports {eth_gt_ch_rx_n[24]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC F7 } [get_ports {eth_gt_ch_tx_p[24]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC F6 } [get_ports {eth_gt_ch_tx_n[24]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC G4 } [get_ports {eth_gt_ch_rx_p[25]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC G3 } [get_ports {eth_gt_ch_rx_n[25]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC G9 } [get_ports {eth_gt_ch_tx_p[25]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC G8 } [get_ports {eth_gt_ch_tx_n[25]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H2 } [get_ports {eth_gt_ch_rx_p[26]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H1 } [get_ports {eth_gt_ch_rx_n[26]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H7 } [get_ports {eth_gt_ch_tx_p[26]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H6 } [get_ports {eth_gt_ch_tx_n[26]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J4 } [get_ports {eth_gt_ch_rx_p[27]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J3 } [get_ports {eth_gt_ch_rx_n[27]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J9 } [get_ports {eth_gt_ch_tx_p[27]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J8 } [get_ports {eth_gt_ch_tx_n[27]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H11 } [get_ports {eth_gt_pri_refclk_p[6]}] ;# MGTREFCLK0P_232 +set_property -dict {LOC H10 } [get_ports {eth_gt_pri_refclk_n[6]}] ;# MGTREFCLK0N_232 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_6 [get_ports {eth_gt_pri_refclk_p[6]}] + +# GTY quad 231 +# 7132LB-48Y4C: SFP 32, 31, 30, 29 +set_property -dict {LOC K2 } [get_ports {eth_gt_ch_rx_p[28]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K1 } [get_ports {eth_gt_ch_rx_n[28]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K7 } [get_ports {eth_gt_ch_tx_p[28]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K6 } [get_ports {eth_gt_ch_tx_n[28]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L4 } [get_ports {eth_gt_ch_rx_p[29]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L3 } [get_ports {eth_gt_ch_rx_n[29]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L9 } [get_ports {eth_gt_ch_tx_p[29]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L8 } [get_ports {eth_gt_ch_tx_n[29]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M2 } [get_ports {eth_gt_ch_rx_p[30]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M1 } [get_ports {eth_gt_ch_rx_n[30]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M7 } [get_ports {eth_gt_ch_tx_p[30]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M6 } [get_ports {eth_gt_ch_tx_n[30]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N4 } [get_ports {eth_gt_ch_rx_p[31]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N3 } [get_ports {eth_gt_ch_rx_n[31]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N9 } [get_ports {eth_gt_ch_tx_p[31]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N8 } [get_ports {eth_gt_ch_tx_n[31]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M11 } [get_ports {eth_gt_pri_refclk_p[7]}] ;# MGTREFCLK0P_231 +set_property -dict {LOC M10 } [get_ports {eth_gt_pri_refclk_n[7]}] ;# MGTREFCLK0N_231 +#set_property -dict {LOC K11 } [get_ports {eth_gt_sec_refclk_p[2]}] ;# MGTREFCLK1P_231 +#set_property -dict {LOC K10 } [get_ports {eth_gt_sec_refclk_n[2]}] ;# MGTREFCLK1N_231 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_7 [get_ports {eth_gt_pri_refclk_p[7]}] + +# 125 MHz MGT secondary reference clock +#create_clock -period 8.000 -name eth_gt_sec_refclk_2 [get_ports {eth_gt_sec_refclk_p[2]}] + +# GTY quad 230 +# 7132LB-48Y4C: SFP 36, 35, 34, 33 +set_property -dict {LOC P2 } [get_ports {eth_gt_ch_rx_p[32]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P1 } [get_ports {eth_gt_ch_rx_n[32]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P7 } [get_ports {eth_gt_ch_tx_p[32]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P6 } [get_ports {eth_gt_ch_tx_n[32]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R4 } [get_ports {eth_gt_ch_rx_p[33]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R3 } [get_ports {eth_gt_ch_rx_n[33]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R9 } [get_ports {eth_gt_ch_tx_p[33]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R8 } [get_ports {eth_gt_ch_tx_n[33]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T2 } [get_ports {eth_gt_ch_rx_p[34]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T1 } [get_ports {eth_gt_ch_rx_n[34]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T7 } [get_ports {eth_gt_ch_tx_p[34]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T6 } [get_ports {eth_gt_ch_tx_n[34]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U4 } [get_ports {eth_gt_ch_rx_p[35]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U3 } [get_ports {eth_gt_ch_rx_n[35]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U9 } [get_ports {eth_gt_ch_tx_p[35]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U8 } [get_ports {eth_gt_ch_tx_n[35]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T11 } [get_ports {eth_gt_pri_refclk_p[8]}] ;# MGTREFCLK0P_230 +set_property -dict {LOC T10 } [get_ports {eth_gt_pri_refclk_n[8]}] ;# MGTREFCLK0N_230 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_8 [get_ports {eth_gt_pri_refclk_p[8]}] + +# GTY quad 229 +# 7132LB-48Y4C: SFP 40, 39, 38, 37 +set_property -dict {LOC V2 } [get_ports {eth_gt_ch_rx_p[36]}] ;# MGTYRXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC V1 } [get_ports {eth_gt_ch_rx_n[36]}] ;# MGTYRXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC V7 } [get_ports {eth_gt_ch_tx_p[36]}] ;# MGTYTXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC V6 } [get_ports {eth_gt_ch_tx_n[36]}] ;# MGTYTXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC W4 } [get_ports {eth_gt_ch_rx_p[37]}] ;# MGTYRXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC W3 } [get_ports {eth_gt_ch_rx_n[37]}] ;# MGTYRXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC W9 } [get_ports {eth_gt_ch_tx_p[37]}] ;# MGTYTXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC W8 } [get_ports {eth_gt_ch_tx_n[37]}] ;# MGTYTXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC Y2 } [get_ports {eth_gt_ch_rx_p[38]}] ;# MGTYRXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC Y1 } [get_ports {eth_gt_ch_rx_n[38]}] ;# MGTYRXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC Y7 } [get_ports {eth_gt_ch_tx_p[38]}] ;# MGTYTXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC Y6 } [get_ports {eth_gt_ch_tx_n[38]}] ;# MGTYTXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC AA4 } [get_ports {eth_gt_ch_rx_p[39]}] ;# MGTYRXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC AA3 } [get_ports {eth_gt_ch_rx_n[39]}] ;# MGTYRXNN_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC AA9 } [get_ports {eth_gt_ch_tx_p[39]}] ;# MGTYTXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC AA8 } [get_ports {eth_gt_ch_tx_n[39]}] ;# MGTYTXNN_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC Y11 } [get_ports {eth_gt_pri_refclk_p[9]}] ;# MGTREFCLK0P_229 +set_property -dict {LOC Y10 } [get_ports {eth_gt_pri_refclk_n[9]}] ;# MGTREFCLK0N_229 +#set_property -dict {LOC V11 } [get_ports {eth_gt_sec_refclk_p[1]}] ;# MGTREFCLK1P_229 +#set_property -dict {LOC V10 } [get_ports {eth_gt_sec_refclk_n[1]}] ;# MGTREFCLK1N_229 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_9 [get_ports {eth_gt_pri_refclk_p[9]}] + +# 125 MHz MGT secondary reference clock +#create_clock -period 8.000 -name eth_gt_sec_refclk_1 [get_ports {eth_gt_sec_refclk_p[1]}] + +# GTY quad 228 +# 7132LB-48Y4C: SFP 44, 43, 42, 41 +set_property -dict {LOC AB2 } [get_ports {eth_gt_ch_rx_p[40]}] ;# MGTYRXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AB1 } [get_ports {eth_gt_ch_rx_n[40]}] ;# MGTYRXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AB7 } [get_ports {eth_gt_ch_tx_p[40]}] ;# MGTYTXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AB6 } [get_ports {eth_gt_ch_tx_n[40]}] ;# MGTYTXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AC4 } [get_ports {eth_gt_ch_rx_p[41]}] ;# MGTYRXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AC3 } [get_ports {eth_gt_ch_rx_n[41]}] ;# MGTYRXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AC9 } [get_ports {eth_gt_ch_tx_p[41]}] ;# MGTYTXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AC8 } [get_ports {eth_gt_ch_tx_n[41]}] ;# MGTYTXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AD2 } [get_ports {eth_gt_ch_rx_p[42]}] ;# MGTYRXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AD1 } [get_ports {eth_gt_ch_rx_n[42]}] ;# MGTYRXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AD7 } [get_ports {eth_gt_ch_tx_p[42]}] ;# MGTYTXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AD6 } [get_ports {eth_gt_ch_tx_n[42]}] ;# MGTYTXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AE4 } [get_ports {eth_gt_ch_rx_p[43]}] ;# MGTYRXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AE3 } [get_ports {eth_gt_ch_rx_n[43]}] ;# MGTYRXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AE9 } [get_ports {eth_gt_ch_tx_p[43]}] ;# MGTYTXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AE8 } [get_ports {eth_gt_ch_tx_n[43]}] ;# MGTYTXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 +set_property -dict {LOC AD11} [get_ports {eth_gt_pri_refclk_p[10]}] ;# MGTREFCLK0P_228 +set_property -dict {LOC AD10} [get_ports {eth_gt_pri_refclk_n[10]}] ;# MGTREFCLK0N_228 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_10 [get_ports {eth_gt_pri_refclk_p[10]}] + +# GTY quad 227 +# 7132LB-48Y4C: SFP 48, 47, 46, 45 +set_property -dict {LOC AF2 } [get_ports {eth_gt_ch_rx_p[44]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AF1 } [get_ports {eth_gt_ch_rx_n[44]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AF7 } [get_ports {eth_gt_ch_tx_p[44]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AF6 } [get_ports {eth_gt_ch_tx_n[44]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG4 } [get_ports {eth_gt_ch_rx_p[45]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG3 } [get_ports {eth_gt_ch_rx_n[45]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG9 } [get_ports {eth_gt_ch_tx_p[45]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG8 } [get_ports {eth_gt_ch_tx_n[45]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH2 } [get_ports {eth_gt_ch_rx_p[46]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH1 } [get_ports {eth_gt_ch_rx_n[46]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH7 } [get_ports {eth_gt_ch_tx_p[46]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH6 } [get_ports {eth_gt_ch_tx_n[46]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ4 } [get_ports {eth_gt_ch_rx_p[47]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ3 } [get_ports {eth_gt_ch_rx_n[47]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ9 } [get_ports {eth_gt_ch_tx_p[47]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ8 } [get_ports {eth_gt_ch_tx_n[47]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH11} [get_ports {eth_gt_pri_refclk_p[11]}] ;# MGTREFCLK0P_227 +set_property -dict {LOC AH10} [get_ports {eth_gt_pri_refclk_n[11]}] ;# MGTREFCLK0N_227 +#set_property -dict {LOC AF11} [get_ports {eth_gt_sec_refclk_p[0]}] ;# MGTREFCLK1P_227 +#set_property -dict {LOC AF10} [get_ports {eth_gt_sec_refclk_n[0]}] ;# MGTREFCLK1N_227 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_11 [get_ports {eth_gt_pri_refclk_p[11]}] + +# 125 MHz MGT secondary reference clock +#create_clock -period 8.000 -name eth_gt_sec_refclk_0 [get_ports {eth_gt_sec_refclk_p[0]}] + +# GTY quad 120 +# 7132LB-48Y4C: QSFP 49 lanes 1, 2, 3, 4 +set_property -dict {LOC BC45} [get_ports {eth_gt_ch_rx_p[48]}] ;# MGTYRXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BC46} [get_ports {eth_gt_ch_rx_n[48]}] ;# MGTYRXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BF42} [get_ports {eth_gt_ch_tx_p[48]}] ;# MGTYTXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BF43} [get_ports {eth_gt_ch_tx_n[48]}] ;# MGTYTXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA45} [get_ports {eth_gt_ch_rx_p[49]}] ;# MGTYRXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA46} [get_ports {eth_gt_ch_rx_n[49]}] ;# MGTYRXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BD42} [get_ports {eth_gt_ch_tx_p[49]}] ;# MGTYTXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BD43} [get_ports {eth_gt_ch_tx_n[49]}] ;# MGTYTXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW45} [get_ports {eth_gt_ch_rx_p[50]}] ;# MGTYRXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW46} [get_ports {eth_gt_ch_rx_n[50]}] ;# MGTYRXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BB42} [get_ports {eth_gt_ch_tx_p[50]}] ;# MGTYTXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BB43} [get_ports {eth_gt_ch_tx_n[50]}] ;# MGTYTXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AV43} [get_ports {eth_gt_ch_rx_p[51]}] ;# MGTYRXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AV44} [get_ports {eth_gt_ch_rx_n[51]}] ;# MGTYRXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW40} [get_ports {eth_gt_ch_tx_p[51]}] ;# MGTYTXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW41} [get_ports {eth_gt_ch_tx_n[51]}] ;# MGTYTXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA40} [get_ports {eth_gt_pri_refclk_p[12]}] ;# MGTREFCLK0P_120 +set_property -dict {LOC BA41} [get_ports {eth_gt_pri_refclk_n[12]}] ;# MGTREFCLK0N_120 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_12 [get_ports {eth_gt_pri_refclk_p[12]}] + +# GTY quad 128 +# 7132LB-48Y4C: QSFP 50 lanes 1, 2, 3, 4 +set_property -dict {LOC J45 } [get_ports {eth_gt_ch_rx_p[52]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC J46 } [get_ports {eth_gt_ch_rx_n[52]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC G40 } [get_ports {eth_gt_ch_tx_p[52]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC G41 } [get_ports {eth_gt_ch_tx_n[52]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC H43 } [get_ports {eth_gt_ch_rx_p[53]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC H44 } [get_ports {eth_gt_ch_rx_n[53]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC E42 } [get_ports {eth_gt_ch_tx_p[53]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC E43 } [get_ports {eth_gt_ch_tx_n[53]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC F45 } [get_ports {eth_gt_ch_rx_p[54]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC F46 } [get_ports {eth_gt_ch_rx_n[54]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC C42 } [get_ports {eth_gt_ch_tx_p[54]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC C43 } [get_ports {eth_gt_ch_tx_n[54]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC D45 } [get_ports {eth_gt_ch_rx_p[55]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC D46 } [get_ports {eth_gt_ch_rx_n[55]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC A42 } [get_ports {eth_gt_ch_tx_p[55]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC A43 } [get_ports {eth_gt_ch_tx_n[55]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC L36 } [get_ports {eth_gt_pri_refclk_p[13]}] ;# MGTREFCLK0P_128 +set_property -dict {LOC L37 } [get_ports {eth_gt_pri_refclk_n[13]}] ;# MGTREFCLK0N_128 +#set_property -dict {LOC K38 } [get_ports {eth_gt_sec_refclk_p[6]}] ;# MGTREFCLK1P_128 +#set_property -dict {LOC K39 } [get_ports {eth_gt_sec_refclk_n[6]}] ;# MGTREFCLK1N_128 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_13 [get_ports {eth_gt_pri_refclk_p[13]}] + +# 125 MHz MGT secondary reference clock +#create_clock -period 8.000 -name eth_gt_sec_refclk_6 [get_ports {eth_gt_sec_refclk_p[6]}] + +# GTY quad 233 +# 7132LB-48Y4C: QSFP 51 lanes 1, 2, 3, 4 +set_property -dict {LOC E4 } [get_ports {eth_gt_ch_rx_p[56]}] ;# MGTYRXP0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC E3 } [get_ports {eth_gt_ch_rx_n[56]}] ;# MGTYRXN0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC E9 } [get_ports {eth_gt_ch_tx_p[56]}] ;# MGTYTXP0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC E8 } [get_ports {eth_gt_ch_tx_n[56]}] ;# MGTYTXN0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC D2 } [get_ports {eth_gt_ch_rx_p[57]}] ;# MGTYRXP1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC D1 } [get_ports {eth_gt_ch_rx_n[57]}] ;# MGTYRXN1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC D7 } [get_ports {eth_gt_ch_tx_p[57]}] ;# MGTYTXP1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC D6 } [get_ports {eth_gt_ch_tx_n[57]}] ;# MGTYTXN1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC C4 } [get_ports {eth_gt_ch_rx_p[58]}] ;# MGTYRXP2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC C3 } [get_ports {eth_gt_ch_rx_n[58]}] ;# MGTYRXN2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC C9 } [get_ports {eth_gt_ch_tx_p[58]}] ;# MGTYTXP2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC C8 } [get_ports {eth_gt_ch_tx_n[58]}] ;# MGTYTXN2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC A5 } [get_ports {eth_gt_ch_rx_p[59]}] ;# MGTYRXP3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC A4 } [get_ports {eth_gt_ch_rx_n[59]}] ;# MGTYRXN3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC A9 } [get_ports {eth_gt_ch_tx_p[59]}] ;# MGTYTXP3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC A8 } [get_ports {eth_gt_ch_tx_n[59]}] ;# MGTYTXN3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +set_property -dict {LOC D11 } [get_ports {eth_gt_pri_refclk_p[14]}] ;# MGTREFCLK0P_233 +set_property -dict {LOC D10 } [get_ports {eth_gt_pri_refclk_n[14]}] ;# MGTREFCLK0N_233 +#set_property -dict {LOC B11 } [get_ports {eth_gt_sec_refclk_p[3]}] ;# MGTREFCLK1P_233 +#set_property -dict {LOC B10 } [get_ports {eth_gt_sec_refclk_n[3]}] ;# MGTREFCLK1N_233 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_14 [get_ports {eth_gt_pri_refclk_p[14]}] + +# 125 MHz MGT secondary reference clock +#create_clock -period 8.000 -name eth_gt_sec_refclk_3 [get_ports {eth_gt_sec_refclk_p[3]}] + +# GTY quad 226 +# 7132LB-48Y4C: QSFP 52 lanes 1, 2, 3, 4 +set_property -dict {LOC AN4 } [get_ports {eth_gt_ch_rx_p[60]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN3 } [get_ports {eth_gt_ch_rx_n[60]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN9 } [get_ports {eth_gt_ch_tx_p[60]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN8 } [get_ports {eth_gt_ch_tx_n[60]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM2 } [get_ports {eth_gt_ch_rx_p[61]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM1 } [get_ports {eth_gt_ch_rx_n[61]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM7 } [get_ports {eth_gt_ch_tx_p[61]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM6 } [get_ports {eth_gt_ch_tx_n[61]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL4 } [get_ports {eth_gt_ch_rx_p[62]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL3 } [get_ports {eth_gt_ch_rx_n[62]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL9 } [get_ports {eth_gt_ch_tx_p[62]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL8 } [get_ports {eth_gt_ch_tx_n[62]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK2 } [get_ports {eth_gt_ch_rx_p[63]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK1 } [get_ports {eth_gt_ch_rx_n[63]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK7 } [get_ports {eth_gt_ch_tx_p[63]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK6 } [get_ports {eth_gt_ch_tx_n[63]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM11} [get_ports {eth_gt_pri_refclk_p[15]}] ;# MGTREFCLK0P_226 +set_property -dict {LOC AM10} [get_ports {eth_gt_pri_refclk_n[15]}] ;# MGTREFCLK0N_226 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_15 [get_ports {eth_gt_pri_refclk_p[15]}] + +# GTY quad 121 +# 7132LB-48Y4C: CPU ports +set_property -dict {LOC AU45} [get_ports {eth_gt_ch_rx_p[64]}] ;# MGTYRXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU46} [get_ports {eth_gt_ch_rx_n[64]}] ;# MGTYRXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU40} [get_ports {eth_gt_ch_tx_p[64]}] ;# MGTYTXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU41} [get_ports {eth_gt_ch_tx_n[64]}] ;# MGTYTXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT43} [get_ports {eth_gt_ch_rx_p[65]}] ;# MGTYRXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT44} [get_ports {eth_gt_ch_rx_n[65]}] ;# MGTYRXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT38} [get_ports {eth_gt_ch_tx_p[65]}] ;# MGTYTXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT39} [get_ports {eth_gt_ch_tx_n[65]}] ;# MGTYTXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR45} [get_ports {eth_gt_ch_rx_p[66]}] ;# MGTYRXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR46} [get_ports {eth_gt_ch_rx_n[66]}] ;# MGTYRXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR40} [get_ports {eth_gt_ch_tx_p[66]}] ;# MGTYTXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR41} [get_ports {eth_gt_ch_tx_n[66]}] ;# MGTYTXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP43} [get_ports {eth_gt_ch_rx_p[67]}] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP44} [get_ports {eth_gt_ch_rx_n[67]}] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP38} [get_ports {eth_gt_ch_tx_p[67]}] ;# MGTYTXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP39} [get_ports {eth_gt_ch_tx_n[67]}] ;# MGTYTXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AV38} [get_ports {eth_gt_pri_refclk_p[16]}] ;# MGTREFCLK0P_121 +set_property -dict {LOC AV39} [get_ports {eth_gt_pri_refclk_n[16]}] ;# MGTREFCLK0N_121 + +# 156.25 MHz MGT primary reference clock +create_clock -period 6.400 -name eth_gt_pri_refclk_16 [get_ports {eth_gt_pri_refclk_p[16]}] + +# PCIe Interface +#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AT11} [get_ports pcie_refclk_p] ;# MGTREFCLK0P_225 +#set_property -dict {LOC AT10} [get_ports pcie_refclk_n] ;# MGTREFCLK0P_225 +#set_property -dict {LOC AR26 IOSTANDARD LVCMOS12} [get_ports pcie_rst_n] +#set_property -dict {LOC BF8 IOSTANDARD LVCMOS18} [get_ports pcie_wake_n] + +# 100 MHz MGT reference clock +#create_clock -period 10.000 -name pcie_mgt_refclk [get_ports pcie_refclk_p] + +#set_false_path -from [get_ports {pcie_rst_n pcie_wake_n}] +#set_input_delay 0 [get_ports {pcie_rst_n pcie_wake_n}] diff --git a/example/Arista_7132LB/fpga_25g/fpga/Makefile b/example/Arista_7132LB/fpga_25g/fpga/Makefile new file mode 100644 index 000000000..eb4db586a --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/fpga/Makefile @@ -0,0 +1,75 @@ + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-3-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES = ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + diff --git a/example/Arista_7132LB/fpga_25g/fpga/config.tcl b/example/Arista_7132LB/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..9e49ced3e --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/fpga/config.tcl @@ -0,0 +1,51 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +# set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/example/Arista_7132LB/fpga_25g/fpga_10g/Makefile b/example/Arista_7132LB/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..eb4db586a --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,75 @@ + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-3-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES = ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + diff --git a/example/Arista_7132LB/fpga_25g/fpga_10g/config.tcl b/example/Arista_7132LB/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..7ba6faf0b --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,51 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +# set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/example/Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl b/example/Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl new file mode 100644 index 000000000..cecca12f7 --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl @@ -0,0 +1,76 @@ +# Copyright (c) 2021 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +set base_name {eth_xcvr_gt} + +set preset {GTY-10GBASE-R} + +set freerun_freq {125} +set line_rate {10.3125} +set refclk_freq {161.1328125} +set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set user_data_width {64} +set int_data_width $user_data_width +set extra_ports [list] +set extra_pll_ports [list {qpll0lock_out}] + +set config [dict create] + +dict set config TX_LINE_RATE $line_rate +dict set config TX_REFCLK_FREQUENCY $refclk_freq +dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn +dict set config TX_USER_DATA_WIDTH $user_data_width +dict set config TX_INT_DATA_WIDTH $int_data_width +dict set config RX_LINE_RATE $line_rate +dict set config RX_REFCLK_FREQUENCY $refclk_freq +dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn +dict set config RX_USER_DATA_WIDTH $user_data_width +dict set config RX_INT_DATA_WIDTH $int_data_width +dict set config ENABLE_OPTIONAL_PORTS $extra_ports +dict set config LOCATE_COMMON {CORE} +dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_TX_USER_CLOCKING {CORE} +dict set config LOCATE_RX_USER_CLOCKING {CORE} +dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} +dict set config FREERUN_FREQUENCY $freerun_freq +dict set config DISABLE_LOC_XDC {1} + +proc create_gtwizard_ip {name preset config} { + create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name + set ip [get_ips $name] + set_property CONFIG.preset $preset $ip + set config_list {} + dict for {name value} $config { + lappend config_list "CONFIG.${name}" $value + } + set_property -dict $config_list $ip +} + +# variant with channel and common +dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] +dict set config LOCATE_COMMON {CORE} + +create_gtwizard_ip "${base_name}_full" $preset $config + +# variant with channel only +dict set config ENABLE_OPTIONAL_PORTS $extra_ports +dict set config LOCATE_COMMON {EXAMPLE_DESIGN} + +create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/example/Arista_7132LB/fpga_25g/lib/eth b/example/Arista_7132LB/fpga_25g/lib/eth new file mode 120000 index 000000000..11a54ed36 --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/lib/eth @@ -0,0 +1 @@ +../../../../ \ No newline at end of file diff --git a/example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v new file mode 100644 index 000000000..0d1142eb6 --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -0,0 +1,307 @@ +/* + +Copyright (c) 2021-2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY wrapper + */ +module eth_xcvr_phy_wrapper # +( + parameter HAS_COMMON = 1, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL out + */ + input wire xcvr_gtrefclk00_in, + output wire xcvr_qpll0lock_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, + + /* + * PLL in + */ + input wire xcvr_qpll0lock_in, + output wire xcvr_qpll0reset_out, + input wire xcvr_qpll0clk_in, + input wire xcvr_qpll0refclk_in, + + /* + * Serial data + */ + output wire xcvr_txp, + output wire xcvr_txn, + input wire xcvr_rxp, + input wire xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_tx_clk, + output wire phy_tx_rst, + input wire [DATA_WIDTH-1:0] phy_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_xgmii_txc, + output wire phy_rx_clk, + output wire phy_rx_rst, + output wire [DATA_WIDTH-1:0] phy_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc, + output wire phy_tx_bad_block, + output wire [6:0] phy_rx_error_count, + output wire phy_rx_bad_block, + output wire phy_rx_sequence_error, + output wire phy_rx_block_lock, + output wire phy_rx_high_ber, + output wire phy_rx_status, + input wire phy_cfg_tx_prbs31_enable, + input wire phy_cfg_rx_prbs31_enable +); + +wire phy_rx_reset_req; + +wire gt_reset_tx_datapath = 1'b0; +wire gt_reset_rx_datapath = phy_rx_reset_req; + +wire gt_reset_tx_done; +wire gt_reset_rx_done; + +wire [5:0] gt_txheader; +wire [63:0] gt_txdata; +wire gt_rxgearboxslip; +wire [5:0] gt_rxheader; +wire [1:0] gt_rxheadervalid; +wire [63:0] gt_rxdata; +wire [1:0] gt_rxdatavalid; + +generate + +if (HAS_COMMON) begin : xcvr + + eth_xcvr_gt_full + eth_xcvr_gt_full_inst ( + // Common + .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), + .gtwiz_reset_all_in(xcvr_ctrl_rst), + .gtpowergood_out(xcvr_gtpowergood_out), + + // PLL + .gtrefclk00_in(xcvr_gtrefclk00_in), + .qpll0lock_out(xcvr_qpll0lock_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), + + // Serial data + .gtytxp_out(xcvr_txp), + .gtytxn_out(xcvr_txn), + .gtyrxp_in(xcvr_rxp), + .gtyrxn_in(xcvr_rxn), + + // Transmit + .gtwiz_userclk_tx_reset_in(1'b0), + .gtwiz_userclk_tx_srcclk_out(), + .gtwiz_userclk_tx_usrclk_out(), + .gtwiz_userclk_tx_usrclk2_out(phy_tx_clk), + .gtwiz_userclk_tx_active_out(), + .gtwiz_reset_tx_pll_and_datapath_in(1'b0), + .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), + .gtwiz_reset_tx_done_out(gt_reset_tx_done), + .txpmaresetdone_out(), + .txprgdivresetdone_out(), + + .gtwiz_userdata_tx_in(gt_txdata), + .txheader_in(gt_txheader), + .txsequence_in(7'b0), + + // Receive + .gtwiz_userclk_rx_reset_in(1'b0), + .gtwiz_userclk_rx_srcclk_out(), + .gtwiz_userclk_rx_usrclk_out(), + .gtwiz_userclk_rx_usrclk2_out(phy_rx_clk), + .gtwiz_userclk_rx_active_out(), + .gtwiz_reset_rx_pll_and_datapath_in(1'b0), + .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), + .gtwiz_reset_rx_cdr_stable_out(), + .gtwiz_reset_rx_done_out(gt_reset_rx_done), + .rxpmaresetdone_out(), + .rxprgdivresetdone_out(), + + .rxgearboxslip_in(gt_rxgearboxslip), + .gtwiz_userdata_rx_out(gt_rxdata), + .rxdatavalid_out(gt_rxdatavalid), + .rxheader_out(gt_rxheader), + .rxheadervalid_out(gt_rxheadervalid), + .rxstartofseq_out() + ); + + assign xcvr_qpll0reset_out = 1'b0; + +end else begin : xcvr + + eth_xcvr_gt_channel + eth_xcvr_gt_channel_inst ( + // Common + .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), + .gtwiz_reset_all_in(xcvr_ctrl_rst), + .gtpowergood_out(xcvr_gtpowergood_out), + + // PLL + .gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in), + .gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out), + .qpll0clk_in(xcvr_qpll0clk_in), + .qpll0refclk_in(xcvr_qpll0refclk_in), + .qpll1clk_in(1'b0), + .qpll1refclk_in(1'b0), + + // Serial data + .gtytxp_out(xcvr_txp), + .gtytxn_out(xcvr_txn), + .gtyrxp_in(xcvr_rxp), + .gtyrxn_in(xcvr_rxn), + + // Transmit + .gtwiz_userclk_tx_reset_in(1'b0), + .gtwiz_userclk_tx_srcclk_out(), + .gtwiz_userclk_tx_usrclk_out(), + .gtwiz_userclk_tx_usrclk2_out(phy_tx_clk), + .gtwiz_userclk_tx_active_out(), + .gtwiz_reset_tx_pll_and_datapath_in(1'b0), + .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), + .gtwiz_reset_tx_done_out(gt_reset_tx_done), + .txpmaresetdone_out(), + .txprgdivresetdone_out(), + + .gtwiz_userdata_tx_in(gt_txdata), + .txheader_in(gt_txheader), + .txsequence_in(7'b0), + + // Receive + .gtwiz_userclk_rx_reset_in(1'b0), + .gtwiz_userclk_rx_srcclk_out(), + .gtwiz_userclk_rx_usrclk_out(), + .gtwiz_userclk_rx_usrclk2_out(phy_rx_clk), + .gtwiz_userclk_rx_active_out(), + .gtwiz_reset_rx_pll_and_datapath_in(1'b0), + .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), + .gtwiz_reset_rx_cdr_stable_out(), + .gtwiz_reset_rx_done_out(gt_reset_rx_done), + .rxpmaresetdone_out(), + .rxprgdivresetdone_out(), + + .rxgearboxslip_in(gt_rxgearboxslip), + .gtwiz_userdata_rx_out(gt_rxdata), + .rxdatavalid_out(gt_rxdatavalid), + .rxheader_out(gt_rxheader), + .rxheadervalid_out(gt_rxheadervalid), + .rxstartofseq_out() + ); + + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + +end + +endgenerate + +sync_reset #( + .N(4) +) +tx_reset_sync_inst ( + .clk(phy_tx_clk), + .rst(!gt_reset_tx_done), + .out(phy_tx_rst) +); + +sync_reset #( + .N(4) +) +rx_reset_sync_inst ( + .clk(phy_rx_clk), + .rst(!gt_reset_rx_done), + .out(phy_rx_rst) +); + +eth_phy_10g #( + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .BIT_REVERSE(1), + .SCRAMBLER_DISABLE(0), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) +) +phy_inst ( + .tx_clk(phy_tx_clk), + .tx_rst(phy_tx_rst), + .rx_clk(phy_rx_clk), + .rx_rst(phy_rx_rst), + .xgmii_txd(phy_xgmii_txd), + .xgmii_txc(phy_xgmii_txc), + .xgmii_rxd(phy_xgmii_rxd), + .xgmii_rxc(phy_xgmii_rxc), + .serdes_tx_data(gt_txdata), + .serdes_tx_hdr(gt_txheader), + .serdes_rx_data(gt_rxdata), + .serdes_rx_hdr(gt_rxheader), + .serdes_rx_bitslip(gt_rxgearboxslip), + .serdes_rx_reset_req(phy_rx_reset_req), + .tx_bad_block(phy_tx_bad_block), + .rx_error_count(phy_rx_error_count), + .rx_bad_block(phy_rx_bad_block), + .rx_sequence_error(phy_rx_sequence_error), + .rx_block_lock(phy_rx_block_lock), + .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), + .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) +); + +endmodule + +`resetall diff --git a/example/Arista_7132LB/fpga_25g/rtl/fpga.v b/example/Arista_7132LB/fpga_25g/rtl/fpga.v new file mode 100644 index 000000000..1129b6f53 --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/rtl/fpga.v @@ -0,0 +1,323 @@ +/* + +Copyright (c) 2014-2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga ( + /* + * Clock: 156.25MHz + */ + input wire [1:0] refclk_user_p, + input wire [1:0] refclk_user_n, + + /* + * Ethernet: QSFP28 + */ + input wire [67:0] eth_gt_ch_rx_p, + input wire [67:0] eth_gt_ch_rx_n, + output wire [67:0] eth_gt_ch_tx_p, + output wire [67:0] eth_gt_ch_tx_n, + input wire [16:0] eth_gt_pri_refclk_p, + input wire [16:0] eth_gt_pri_refclk_n +); + +genvar n; + +// Clock and reset + +// Buffers +wire [1:0] refclk_user; + +generate + +for (n = 0; n < 2; n = n + 1) begin : refclk_buf + + IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") + ) + refclk_ibufg_inst ( + .O (refclk_user[n]), + .I (refclk_user_p[n]), + .IB (refclk_user_n[n]) + ); + +end + +endgenerate + +// Internal 125 MHz clock +wire clk_125mhz_mmcm_out; +wire clk_125mhz_int; +wire rst_125mhz_int; + +// Internal 156.25 MHz clock +wire clk_156mhz_int; +wire rst_156mhz_int; + +wire mmcm_rst = 1'b0; +wire mmcm_locked; +wire mmcm_clkfb; + +// MMCM instance +// 156.25 MHz in, 125 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 8, D = 1 sets Fvco = 1250 MHz +// Divide by 10 to get output frequency of 125 MHz +MMCME3_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(10), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(8), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(6.400), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +clk_mmcm_inst ( + .CLKIN1(refclk_user[0]), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// XGMII 10G PHY +parameter QUAD_CNT = 17; +parameter CH_CNT = QUAD_CNT*4; + +wire [CH_CNT-1:0] eth_tx_clk; +wire [CH_CNT-1:0] eth_tx_rst; +wire [CH_CNT*64-1:0] eth_txd; +wire [CH_CNT*8-1:0] eth_txc; +wire [CH_CNT-1:0] eth_rx_clk; +wire [CH_CNT-1:0] eth_rx_rst; +wire [CH_CNT*64-1:0] eth_rxd; +wire [CH_CNT*8-1:0] eth_rxc; + + +assign clk_156mhz_int = eth_tx_clk[0]; +assign rst_156mhz_int = eth_tx_rst[0]; + +generate + +for (n = 0; n < QUAD_CNT; n = n + 1) begin : eth_quad + + wire quad_mgt_refclk; + + IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst ( + .I (eth_gt_pri_refclk_p[n]), + .IB (eth_gt_pri_refclk_n[n]), + .CEB (1'b0), + .O (quad_mgt_refclk), + .ODIV2 () + ); + + eth_xcvr_phy_quad_wrapper + quad_phy_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + /* + * Common + */ + .xcvr_gtpowergood_out(), + + /* + * PLL + */ + .xcvr_gtrefclk00_in(quad_mgt_refclk), + + /* + * Serial data + */ + .xcvr_txp(eth_gt_ch_tx_p[n*4 +: 4]), + .xcvr_txn(eth_gt_ch_tx_n[n*4 +: 4]), + .xcvr_rxp(eth_gt_ch_rx_p[n*4 +: 4]), + .xcvr_rxn(eth_gt_ch_rx_n[n*4 +: 4]), + + /* + * PHY connections + */ + .phy_1_tx_clk(eth_tx_clk[n*4+0 +: 1]), + .phy_1_tx_rst(eth_tx_rst[n*4+0 +: 1]), + .phy_1_xgmii_txd(eth_txd[(n*4+0)*64 +: 64]), + .phy_1_xgmii_txc(eth_txc[(n*4+0)*8 +: 8]), + .phy_1_rx_clk(eth_rx_clk[n*4+0 +: 1]), + .phy_1_rx_rst(eth_rx_rst[n*4+0 +: 1]), + .phy_1_xgmii_rxd(eth_rxd[(n*4+0)*64 +: 64]), + .phy_1_xgmii_rxc(eth_rxc[(n*4+0)*8 +: 8]), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(), + .phy_1_rx_high_ber(), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), + + .phy_2_tx_clk(eth_tx_clk[n*4+1 +: 1]), + .phy_2_tx_rst(eth_tx_rst[n*4+1 +: 1]), + .phy_2_xgmii_txd(eth_txd[(n*4+1)*64 +: 64]), + .phy_2_xgmii_txc(eth_txc[(n*4+1)*8 +: 8]), + .phy_2_rx_clk(eth_rx_clk[n*4+1 +: 1]), + .phy_2_rx_rst(eth_rx_rst[n*4+1 +: 1]), + .phy_2_xgmii_rxd(eth_rxd[(n*4+1)*64 +: 64]), + .phy_2_xgmii_rxc(eth_rxc[(n*4+1)*8 +: 8]), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(), + .phy_2_rx_high_ber(), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), + + .phy_3_tx_clk(eth_tx_clk[n*4+2 +: 1]), + .phy_3_tx_rst(eth_tx_rst[n*4+2 +: 1]), + .phy_3_xgmii_txd(eth_txd[(n*4+2)*64 +: 64]), + .phy_3_xgmii_txc(eth_txc[(n*4+2)*8 +: 8]), + .phy_3_rx_clk(eth_rx_clk[n*4+2 +: 1]), + .phy_3_rx_rst(eth_rx_rst[n*4+2 +: 1]), + .phy_3_xgmii_rxd(eth_rxd[(n*4+2)*64 +: 64]), + .phy_3_xgmii_rxc(eth_rxc[(n*4+2)*8 +: 8]), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(), + .phy_3_rx_high_ber(), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), + + .phy_4_tx_clk(eth_tx_clk[n*4+3 +: 1]), + .phy_4_tx_rst(eth_tx_rst[n*4+3 +: 1]), + .phy_4_xgmii_txd(eth_txd[(n*4+3)*64 +: 64]), + .phy_4_xgmii_txc(eth_txc[(n*4+3)*8 +: 8]), + .phy_4_rx_clk(eth_rx_clk[n*4+3 +: 1]), + .phy_4_rx_rst(eth_rx_rst[n*4+3 +: 1]), + .phy_4_xgmii_rxd(eth_rxd[(n*4+3)*64 +: 64]), + .phy_4_xgmii_rxc(eth_rxc[(n*4+3)*8 +: 8]), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(), + .phy_4_rx_high_ber(), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) + ); + +end + +endgenerate + +fpga_core #( + .CH_CNT(CH_CNT) +) +core_inst ( + /* + * Clock: 156.25 MHz + * Synchronous reset + */ + .clk(clk_156mhz_int), + .rst(rst_156mhz_int), + + /* + * Ethernet: QSFP28 + */ + .eth_tx_clk(eth_tx_clk), + .eth_tx_rst(eth_tx_rst), + .eth_txd(eth_txd), + .eth_txc(eth_txc), + .eth_rx_clk(eth_rx_clk), + .eth_rx_rst(eth_rx_rst), + .eth_rxd(eth_rxd), + .eth_rxc(eth_rxc) +); + +endmodule + +`resetall diff --git a/example/Arista_7132LB/fpga_25g/rtl/fpga_core.v b/example/Arista_7132LB/fpga_25g/rtl/fpga_core.v new file mode 100644 index 000000000..56ceaf79a --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/rtl/fpga_core.v @@ -0,0 +1,738 @@ +/* + +Copyright (c) 2014-2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core # +( + parameter CH_CNT = 68 +) +( + /* + * Clock: 156.25MHz + * Synchronous reset + */ + input wire clk, + input wire rst, + + /* + * Ethernet + */ + input wire [CH_CNT-1:0] eth_tx_clk, + input wire [CH_CNT-1:0] eth_tx_rst, + output wire [CH_CNT*64-1:0] eth_txd, + output wire [CH_CNT*8-1:0] eth_txc, + input wire [CH_CNT-1:0] eth_rx_clk, + input wire [CH_CNT-1:0] eth_rx_rst, + input wire [CH_CNT*64-1:0] eth_rxd, + input wire [CH_CNT*8-1:0] eth_rxc +); + +// AXI between MAC and Ethernet modules +wire [63:0] rx_axis_tdata; +wire [7:0] rx_axis_tkeep; +wire rx_axis_tvalid; +wire rx_axis_tready; +wire rx_axis_tlast; +wire rx_axis_tuser; + +wire [63:0] tx_axis_tdata; +wire [7:0] tx_axis_tkeep; +wire tx_axis_tvalid; +wire tx_axis_tready; +wire tx_axis_tlast; +wire tx_axis_tuser; + +// Ethernet frame between Ethernet modules and UDP stack +wire rx_eth_hdr_ready; +wire rx_eth_hdr_valid; +wire [47:0] rx_eth_dest_mac; +wire [47:0] rx_eth_src_mac; +wire [15:0] rx_eth_type; +wire [63:0] rx_eth_payload_axis_tdata; +wire [7:0] rx_eth_payload_axis_tkeep; +wire rx_eth_payload_axis_tvalid; +wire rx_eth_payload_axis_tready; +wire rx_eth_payload_axis_tlast; +wire rx_eth_payload_axis_tuser; + +wire tx_eth_hdr_ready; +wire tx_eth_hdr_valid; +wire [47:0] tx_eth_dest_mac; +wire [47:0] tx_eth_src_mac; +wire [15:0] tx_eth_type; +wire [63:0] tx_eth_payload_axis_tdata; +wire [7:0] tx_eth_payload_axis_tkeep; +wire tx_eth_payload_axis_tvalid; +wire tx_eth_payload_axis_tready; +wire tx_eth_payload_axis_tlast; +wire tx_eth_payload_axis_tuser; + +// IP frame connections +wire rx_ip_hdr_valid; +wire rx_ip_hdr_ready; +wire [47:0] rx_ip_eth_dest_mac; +wire [47:0] rx_ip_eth_src_mac; +wire [15:0] rx_ip_eth_type; +wire [3:0] rx_ip_version; +wire [3:0] rx_ip_ihl; +wire [5:0] rx_ip_dscp; +wire [1:0] rx_ip_ecn; +wire [15:0] rx_ip_length; +wire [15:0] rx_ip_identification; +wire [2:0] rx_ip_flags; +wire [12:0] rx_ip_fragment_offset; +wire [7:0] rx_ip_ttl; +wire [7:0] rx_ip_protocol; +wire [15:0] rx_ip_header_checksum; +wire [31:0] rx_ip_source_ip; +wire [31:0] rx_ip_dest_ip; +wire [63:0] rx_ip_payload_axis_tdata; +wire [7:0] rx_ip_payload_axis_tkeep; +wire rx_ip_payload_axis_tvalid; +wire rx_ip_payload_axis_tready; +wire rx_ip_payload_axis_tlast; +wire rx_ip_payload_axis_tuser; + +wire tx_ip_hdr_valid; +wire tx_ip_hdr_ready; +wire [5:0] tx_ip_dscp; +wire [1:0] tx_ip_ecn; +wire [15:0] tx_ip_length; +wire [7:0] tx_ip_ttl; +wire [7:0] tx_ip_protocol; +wire [31:0] tx_ip_source_ip; +wire [31:0] tx_ip_dest_ip; +wire [63:0] tx_ip_payload_axis_tdata; +wire [7:0] tx_ip_payload_axis_tkeep; +wire tx_ip_payload_axis_tvalid; +wire tx_ip_payload_axis_tready; +wire tx_ip_payload_axis_tlast; +wire tx_ip_payload_axis_tuser; + +// UDP frame connections +wire rx_udp_hdr_valid; +wire rx_udp_hdr_ready; +wire [47:0] rx_udp_eth_dest_mac; +wire [47:0] rx_udp_eth_src_mac; +wire [15:0] rx_udp_eth_type; +wire [3:0] rx_udp_ip_version; +wire [3:0] rx_udp_ip_ihl; +wire [5:0] rx_udp_ip_dscp; +wire [1:0] rx_udp_ip_ecn; +wire [15:0] rx_udp_ip_length; +wire [15:0] rx_udp_ip_identification; +wire [2:0] rx_udp_ip_flags; +wire [12:0] rx_udp_ip_fragment_offset; +wire [7:0] rx_udp_ip_ttl; +wire [7:0] rx_udp_ip_protocol; +wire [15:0] rx_udp_ip_header_checksum; +wire [31:0] rx_udp_ip_source_ip; +wire [31:0] rx_udp_ip_dest_ip; +wire [15:0] rx_udp_source_port; +wire [15:0] rx_udp_dest_port; +wire [15:0] rx_udp_length; +wire [15:0] rx_udp_checksum; +wire [63:0] rx_udp_payload_axis_tdata; +wire [7:0] rx_udp_payload_axis_tkeep; +wire rx_udp_payload_axis_tvalid; +wire rx_udp_payload_axis_tready; +wire rx_udp_payload_axis_tlast; +wire rx_udp_payload_axis_tuser; + +wire tx_udp_hdr_valid; +wire tx_udp_hdr_ready; +wire [5:0] tx_udp_ip_dscp; +wire [1:0] tx_udp_ip_ecn; +wire [7:0] tx_udp_ip_ttl; +wire [31:0] tx_udp_ip_source_ip; +wire [31:0] tx_udp_ip_dest_ip; +wire [15:0] tx_udp_source_port; +wire [15:0] tx_udp_dest_port; +wire [15:0] tx_udp_length; +wire [15:0] tx_udp_checksum; +wire [63:0] tx_udp_payload_axis_tdata; +wire [7:0] tx_udp_payload_axis_tkeep; +wire tx_udp_payload_axis_tvalid; +wire tx_udp_payload_axis_tready; +wire tx_udp_payload_axis_tlast; +wire tx_udp_payload_axis_tuser; + +wire [63:0] rx_fifo_udp_payload_axis_tdata; +wire [7:0] rx_fifo_udp_payload_axis_tkeep; +wire rx_fifo_udp_payload_axis_tvalid; +wire rx_fifo_udp_payload_axis_tready; +wire rx_fifo_udp_payload_axis_tlast; +wire rx_fifo_udp_payload_axis_tuser; + +wire [63:0] tx_fifo_udp_payload_axis_tdata; +wire [7:0] tx_fifo_udp_payload_axis_tkeep; +wire tx_fifo_udp_payload_axis_tvalid; +wire tx_fifo_udp_payload_axis_tready; +wire tx_fifo_udp_payload_axis_tlast; +wire tx_fifo_udp_payload_axis_tuser; + +// Configuration +wire [47:0] local_mac = 48'h02_00_00_00_00_00; +wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128}; +wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1}; +wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0}; + +// IP ports not used +assign rx_ip_hdr_ready = 1; +assign rx_ip_payload_axis_tready = 1; + +assign tx_ip_hdr_valid = 0; +assign tx_ip_dscp = 0; +assign tx_ip_ecn = 0; +assign tx_ip_length = 0; +assign tx_ip_ttl = 0; +assign tx_ip_protocol = 0; +assign tx_ip_source_ip = 0; +assign tx_ip_dest_ip = 0; +assign tx_ip_payload_axis_tdata = 0; +assign tx_ip_payload_axis_tkeep = 0; +assign tx_ip_payload_axis_tvalid = 0; +assign tx_ip_payload_axis_tlast = 0; +assign tx_ip_payload_axis_tuser = 0; + +// Loop back UDP +wire match_cond = rx_udp_dest_port == 1234; +wire no_match = !match_cond; + +reg match_cond_reg = 0; +reg no_match_reg = 0; + +always @(posedge clk) begin + if (rst) begin + match_cond_reg <= 0; + no_match_reg <= 0; + end else begin + if (rx_udp_payload_axis_tvalid) begin + if ((!match_cond_reg && !no_match_reg) || + (rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin + match_cond_reg <= match_cond; + no_match_reg <= no_match; + end + end else begin + match_cond_reg <= 0; + no_match_reg <= 0; + end + end +end + +assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond; +assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match; +assign tx_udp_ip_dscp = 0; +assign tx_udp_ip_ecn = 0; +assign tx_udp_ip_ttl = 64; +assign tx_udp_ip_source_ip = local_ip; +assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip; +assign tx_udp_source_port = rx_udp_dest_port; +assign tx_udp_dest_port = rx_udp_source_port; +assign tx_udp_length = rx_udp_length; +assign tx_udp_checksum = 0; + +assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata; +assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep; +assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid; +assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready; +assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast; +assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser; + +assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata; +assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep; +assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg; +assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg; +assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast; +assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser; + +// Place first payload byte onto LEDs +reg valid_last = 0; +reg [7:0] led_reg = 0; + +always @(posedge clk) begin + if (rst) begin + led_reg <= 0; + end else begin + valid_last <= tx_udp_payload_axis_tvalid; + if (tx_udp_payload_axis_tvalid && !valid_last) begin + led_reg <= tx_udp_payload_axis_tdata; + end + end +end + +assign eth_txd[1*64 +: 64] = 64'h0707070707070707; +assign eth_txc[1*8 +: 8] = 8'hff; +assign eth_txd[2*64 +: 64] = 64'h0707070707070707; +assign eth_txc[2*8 +: 8] = 8'hff; +assign eth_txd[3*64 +: 64] = 64'h0707070707070707; +assign eth_txc[3*8 +: 8] = 8'hff; +assign eth_txd[4*64 +: 64] = 64'h0707070707070707; +assign eth_txc[4*8 +: 8] = 8'hff; +assign eth_txd[5*64 +: 64] = 64'h0707070707070707; +assign eth_txc[5*8 +: 8] = 8'hff; +assign eth_txd[6*64 +: 64] = 64'h0707070707070707; +assign eth_txc[6*8 +: 8] = 8'hff; +assign eth_txd[7*64 +: 64] = 64'h0707070707070707; +assign eth_txc[7*8 +: 8] = 8'hff; +assign eth_txd[8*64 +: 64] = 64'h0707070707070707; +assign eth_txc[8*8 +: 8] = 8'hff; +assign eth_txd[9*64 +: 64] = 64'h0707070707070707; +assign eth_txc[9*8 +: 8] = 8'hff; +assign eth_txd[10*64 +: 64] = 64'h0707070707070707; +assign eth_txc[10*8 +: 8] = 8'hff; +assign eth_txd[11*64 +: 64] = 64'h0707070707070707; +assign eth_txc[11*8 +: 8] = 8'hff; +assign eth_txd[12*64 +: 64] = 64'h0707070707070707; +assign eth_txc[12*8 +: 8] = 8'hff; +assign eth_txd[13*64 +: 64] = 64'h0707070707070707; +assign eth_txc[13*8 +: 8] = 8'hff; +assign eth_txd[14*64 +: 64] = 64'h0707070707070707; +assign eth_txc[14*8 +: 8] = 8'hff; +assign eth_txd[15*64 +: 64] = 64'h0707070707070707; +assign eth_txc[15*8 +: 8] = 8'hff; +assign eth_txd[16*64 +: 64] = 64'h0707070707070707; +assign eth_txc[16*8 +: 8] = 8'hff; +assign eth_txd[17*64 +: 64] = 64'h0707070707070707; +assign eth_txc[17*8 +: 8] = 8'hff; +assign eth_txd[18*64 +: 64] = 64'h0707070707070707; +assign eth_txc[18*8 +: 8] = 8'hff; +assign eth_txd[19*64 +: 64] = 64'h0707070707070707; +assign eth_txc[19*8 +: 8] = 8'hff; +assign eth_txd[10*64 +: 64] = 64'h0707070707070707; +assign eth_txc[10*8 +: 8] = 8'hff; +assign eth_txd[11*64 +: 64] = 64'h0707070707070707; +assign eth_txc[11*8 +: 8] = 8'hff; +assign eth_txd[12*64 +: 64] = 64'h0707070707070707; +assign eth_txc[12*8 +: 8] = 8'hff; +assign eth_txd[13*64 +: 64] = 64'h0707070707070707; +assign eth_txc[13*8 +: 8] = 8'hff; +assign eth_txd[14*64 +: 64] = 64'h0707070707070707; +assign eth_txc[14*8 +: 8] = 8'hff; +assign eth_txd[15*64 +: 64] = 64'h0707070707070707; +assign eth_txc[15*8 +: 8] = 8'hff; +assign eth_txd[16*64 +: 64] = 64'h0707070707070707; +assign eth_txc[16*8 +: 8] = 8'hff; +assign eth_txd[17*64 +: 64] = 64'h0707070707070707; +assign eth_txc[17*8 +: 8] = 8'hff; +assign eth_txd[18*64 +: 64] = 64'h0707070707070707; +assign eth_txc[18*8 +: 8] = 8'hff; +assign eth_txd[19*64 +: 64] = 64'h0707070707070707; +assign eth_txc[19*8 +: 8] = 8'hff; +assign eth_txd[20*64 +: 64] = 64'h0707070707070707; +assign eth_txc[20*8 +: 8] = 8'hff; +assign eth_txd[21*64 +: 64] = 64'h0707070707070707; +assign eth_txc[21*8 +: 8] = 8'hff; +assign eth_txd[22*64 +: 64] = 64'h0707070707070707; +assign eth_txc[22*8 +: 8] = 8'hff; +assign eth_txd[23*64 +: 64] = 64'h0707070707070707; +assign eth_txc[23*8 +: 8] = 8'hff; +assign eth_txd[24*64 +: 64] = 64'h0707070707070707; +assign eth_txc[24*8 +: 8] = 8'hff; +assign eth_txd[25*64 +: 64] = 64'h0707070707070707; +assign eth_txc[25*8 +: 8] = 8'hff; +assign eth_txd[26*64 +: 64] = 64'h0707070707070707; +assign eth_txc[26*8 +: 8] = 8'hff; +assign eth_txd[27*64 +: 64] = 64'h0707070707070707; +assign eth_txc[27*8 +: 8] = 8'hff; +assign eth_txd[28*64 +: 64] = 64'h0707070707070707; +assign eth_txc[28*8 +: 8] = 8'hff; +assign eth_txd[29*64 +: 64] = 64'h0707070707070707; +assign eth_txc[29*8 +: 8] = 8'hff; +assign eth_txd[30*64 +: 64] = 64'h0707070707070707; +assign eth_txc[30*8 +: 8] = 8'hff; +assign eth_txd[31*64 +: 64] = 64'h0707070707070707; +assign eth_txc[31*8 +: 8] = 8'hff; +assign eth_txd[32*64 +: 64] = 64'h0707070707070707; +assign eth_txc[32*8 +: 8] = 8'hff; +assign eth_txd[33*64 +: 64] = 64'h0707070707070707; +assign eth_txc[33*8 +: 8] = 8'hff; +assign eth_txd[34*64 +: 64] = 64'h0707070707070707; +assign eth_txc[34*8 +: 8] = 8'hff; +assign eth_txd[35*64 +: 64] = 64'h0707070707070707; +assign eth_txc[35*8 +: 8] = 8'hff; +assign eth_txd[36*64 +: 64] = 64'h0707070707070707; +assign eth_txc[36*8 +: 8] = 8'hff; +assign eth_txd[37*64 +: 64] = 64'h0707070707070707; +assign eth_txc[37*8 +: 8] = 8'hff; +assign eth_txd[38*64 +: 64] = 64'h0707070707070707; +assign eth_txc[38*8 +: 8] = 8'hff; +assign eth_txd[39*64 +: 64] = 64'h0707070707070707; +assign eth_txc[39*8 +: 8] = 8'hff; +assign eth_txd[40*64 +: 64] = 64'h0707070707070707; +assign eth_txc[40*8 +: 8] = 8'hff; +assign eth_txd[41*64 +: 64] = 64'h0707070707070707; +assign eth_txc[41*8 +: 8] = 8'hff; +assign eth_txd[42*64 +: 64] = 64'h0707070707070707; +assign eth_txc[42*8 +: 8] = 8'hff; +assign eth_txd[43*64 +: 64] = 64'h0707070707070707; +assign eth_txc[43*8 +: 8] = 8'hff; +assign eth_txd[44*64 +: 64] = 64'h0707070707070707; +assign eth_txc[44*8 +: 8] = 8'hff; +assign eth_txd[45*64 +: 64] = 64'h0707070707070707; +assign eth_txc[45*8 +: 8] = 8'hff; +assign eth_txd[46*64 +: 64] = 64'h0707070707070707; +assign eth_txc[46*8 +: 8] = 8'hff; +assign eth_txd[47*64 +: 64] = 64'h0707070707070707; +assign eth_txc[47*8 +: 8] = 8'hff; +assign eth_txd[48*64 +: 64] = 64'h0707070707070707; +assign eth_txc[48*8 +: 8] = 8'hff; +assign eth_txd[49*64 +: 64] = 64'h0707070707070707; +assign eth_txc[49*8 +: 8] = 8'hff; +assign eth_txd[50*64 +: 64] = 64'h0707070707070707; +assign eth_txc[50*8 +: 8] = 8'hff; +assign eth_txd[51*64 +: 64] = 64'h0707070707070707; +assign eth_txc[51*8 +: 8] = 8'hff; +assign eth_txd[52*64 +: 64] = 64'h0707070707070707; +assign eth_txc[52*8 +: 8] = 8'hff; +assign eth_txd[53*64 +: 64] = 64'h0707070707070707; +assign eth_txc[53*8 +: 8] = 8'hff; +assign eth_txd[54*64 +: 64] = 64'h0707070707070707; +assign eth_txc[54*8 +: 8] = 8'hff; +assign eth_txd[55*64 +: 64] = 64'h0707070707070707; +assign eth_txc[55*8 +: 8] = 8'hff; +assign eth_txd[56*64 +: 64] = 64'h0707070707070707; +assign eth_txc[56*8 +: 8] = 8'hff; +assign eth_txd[57*64 +: 64] = 64'h0707070707070707; +assign eth_txc[57*8 +: 8] = 8'hff; +assign eth_txd[58*64 +: 64] = 64'h0707070707070707; +assign eth_txc[58*8 +: 8] = 8'hff; +assign eth_txd[59*64 +: 64] = 64'h0707070707070707; +assign eth_txc[59*8 +: 8] = 8'hff; +assign eth_txd[60*64 +: 64] = 64'h0707070707070707; +assign eth_txc[60*8 +: 8] = 8'hff; +assign eth_txd[61*64 +: 64] = 64'h0707070707070707; +assign eth_txc[61*8 +: 8] = 8'hff; +assign eth_txd[62*64 +: 64] = 64'h0707070707070707; +assign eth_txc[62*8 +: 8] = 8'hff; +assign eth_txd[63*64 +: 64] = 64'h0707070707070707; +assign eth_txc[63*8 +: 8] = 8'hff; +assign eth_txd[64*64 +: 64] = 64'h0707070707070707; +assign eth_txc[64*8 +: 8] = 8'hff; +assign eth_txd[65*64 +: 64] = 64'h0707070707070707; +assign eth_txc[65*8 +: 8] = 8'hff; +assign eth_txd[66*64 +: 64] = 64'h0707070707070707; +assign eth_txc[66*8 +: 8] = 8'hff; +assign eth_txd[67*64 +: 64] = 64'h0707070707070707; +assign eth_txc[67*8 +: 8] = 8'hff; + +eth_mac_10g_fifo #( + .ENABLE_PADDING(1), + .ENABLE_DIC(1), + .MIN_FRAME_LENGTH(64), + .TX_FIFO_DEPTH(4096), + .TX_FRAME_FIFO(1), + .RX_FIFO_DEPTH(4096), + .RX_FRAME_FIFO(1) +) +eth_mac_10g_fifo_inst ( + .rx_clk(eth_rx_clk[0 +: 1]), + .rx_rst(eth_rx_rst[0 +: 1]), + .tx_clk(eth_tx_clk[0 +: 1]), + .tx_rst(eth_tx_rst[0 +: 1]), + .logic_clk(clk), + .logic_rst(rst), + + .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tkeep(tx_axis_tkeep), + .tx_axis_tvalid(tx_axis_tvalid), + .tx_axis_tready(tx_axis_tready), + .tx_axis_tlast(tx_axis_tlast), + .tx_axis_tuser(tx_axis_tuser), + + .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tkeep(rx_axis_tkeep), + .rx_axis_tvalid(rx_axis_tvalid), + .rx_axis_tready(rx_axis_tready), + .rx_axis_tlast(rx_axis_tlast), + .rx_axis_tuser(rx_axis_tuser), + + .xgmii_rxd(eth_rxd[0*64 +: 64]), + .xgmii_rxc(eth_rxc[0*8 +: 8]), + .xgmii_txd(eth_txd[0*64 +: 64]), + .xgmii_txc(eth_txc[0*8 +: 8]), + + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), + + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) +); + +eth_axis_rx #( + .DATA_WIDTH(64) +) +eth_axis_rx_inst ( + .clk(clk), + .rst(rst), + // AXI input + .s_axis_tdata(rx_axis_tdata), + .s_axis_tkeep(rx_axis_tkeep), + .s_axis_tvalid(rx_axis_tvalid), + .s_axis_tready(rx_axis_tready), + .s_axis_tlast(rx_axis_tlast), + .s_axis_tuser(rx_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(rx_eth_hdr_valid), + .m_eth_hdr_ready(rx_eth_hdr_ready), + .m_eth_dest_mac(rx_eth_dest_mac), + .m_eth_src_mac(rx_eth_src_mac), + .m_eth_type(rx_eth_type), + .m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), + .m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), + .m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(rx_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), + .m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), + // Status signals + .busy(), + .error_header_early_termination() +); + +eth_axis_tx #( + .DATA_WIDTH(64) +) +eth_axis_tx_inst ( + .clk(clk), + .rst(rst), + // Ethernet frame input + .s_eth_hdr_valid(tx_eth_hdr_valid), + .s_eth_hdr_ready(tx_eth_hdr_ready), + .s_eth_dest_mac(tx_eth_dest_mac), + .s_eth_src_mac(tx_eth_src_mac), + .s_eth_type(tx_eth_type), + .s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), + .s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), + .s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(tx_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), + .s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), + // AXI output + .m_axis_tdata(tx_axis_tdata), + .m_axis_tkeep(tx_axis_tkeep), + .m_axis_tvalid(tx_axis_tvalid), + .m_axis_tready(tx_axis_tready), + .m_axis_tlast(tx_axis_tlast), + .m_axis_tuser(tx_axis_tuser), + // Status signals + .busy() +); + +udp_complete_64 +udp_complete_inst ( + .clk(clk), + .rst(rst), + // Ethernet frame input + .s_eth_hdr_valid(rx_eth_hdr_valid), + .s_eth_hdr_ready(rx_eth_hdr_ready), + .s_eth_dest_mac(rx_eth_dest_mac), + .s_eth_src_mac(rx_eth_src_mac), + .s_eth_type(rx_eth_type), + .s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), + .s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), + .s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(rx_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), + .s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(tx_eth_hdr_valid), + .m_eth_hdr_ready(tx_eth_hdr_ready), + .m_eth_dest_mac(tx_eth_dest_mac), + .m_eth_src_mac(tx_eth_src_mac), + .m_eth_type(tx_eth_type), + .m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), + .m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), + .m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(tx_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), + .m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), + // IP frame input + .s_ip_hdr_valid(tx_ip_hdr_valid), + .s_ip_hdr_ready(tx_ip_hdr_ready), + .s_ip_dscp(tx_ip_dscp), + .s_ip_ecn(tx_ip_ecn), + .s_ip_length(tx_ip_length), + .s_ip_ttl(tx_ip_ttl), + .s_ip_protocol(tx_ip_protocol), + .s_ip_source_ip(tx_ip_source_ip), + .s_ip_dest_ip(tx_ip_dest_ip), + .s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata), + .s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep), + .s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid), + .s_ip_payload_axis_tready(tx_ip_payload_axis_tready), + .s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast), + .s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser), + // IP frame output + .m_ip_hdr_valid(rx_ip_hdr_valid), + .m_ip_hdr_ready(rx_ip_hdr_ready), + .m_ip_eth_dest_mac(rx_ip_eth_dest_mac), + .m_ip_eth_src_mac(rx_ip_eth_src_mac), + .m_ip_eth_type(rx_ip_eth_type), + .m_ip_version(rx_ip_version), + .m_ip_ihl(rx_ip_ihl), + .m_ip_dscp(rx_ip_dscp), + .m_ip_ecn(rx_ip_ecn), + .m_ip_length(rx_ip_length), + .m_ip_identification(rx_ip_identification), + .m_ip_flags(rx_ip_flags), + .m_ip_fragment_offset(rx_ip_fragment_offset), + .m_ip_ttl(rx_ip_ttl), + .m_ip_protocol(rx_ip_protocol), + .m_ip_header_checksum(rx_ip_header_checksum), + .m_ip_source_ip(rx_ip_source_ip), + .m_ip_dest_ip(rx_ip_dest_ip), + .m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata), + .m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep), + .m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid), + .m_ip_payload_axis_tready(rx_ip_payload_axis_tready), + .m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast), + .m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser), + // UDP frame input + .s_udp_hdr_valid(tx_udp_hdr_valid), + .s_udp_hdr_ready(tx_udp_hdr_ready), + .s_udp_ip_dscp(tx_udp_ip_dscp), + .s_udp_ip_ecn(tx_udp_ip_ecn), + .s_udp_ip_ttl(tx_udp_ip_ttl), + .s_udp_ip_source_ip(tx_udp_ip_source_ip), + .s_udp_ip_dest_ip(tx_udp_ip_dest_ip), + .s_udp_source_port(tx_udp_source_port), + .s_udp_dest_port(tx_udp_dest_port), + .s_udp_length(tx_udp_length), + .s_udp_checksum(tx_udp_checksum), + .s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata), + .s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep), + .s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid), + .s_udp_payload_axis_tready(tx_udp_payload_axis_tready), + .s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast), + .s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser), + // UDP frame output + .m_udp_hdr_valid(rx_udp_hdr_valid), + .m_udp_hdr_ready(rx_udp_hdr_ready), + .m_udp_eth_dest_mac(rx_udp_eth_dest_mac), + .m_udp_eth_src_mac(rx_udp_eth_src_mac), + .m_udp_eth_type(rx_udp_eth_type), + .m_udp_ip_version(rx_udp_ip_version), + .m_udp_ip_ihl(rx_udp_ip_ihl), + .m_udp_ip_dscp(rx_udp_ip_dscp), + .m_udp_ip_ecn(rx_udp_ip_ecn), + .m_udp_ip_length(rx_udp_ip_length), + .m_udp_ip_identification(rx_udp_ip_identification), + .m_udp_ip_flags(rx_udp_ip_flags), + .m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset), + .m_udp_ip_ttl(rx_udp_ip_ttl), + .m_udp_ip_protocol(rx_udp_ip_protocol), + .m_udp_ip_header_checksum(rx_udp_ip_header_checksum), + .m_udp_ip_source_ip(rx_udp_ip_source_ip), + .m_udp_ip_dest_ip(rx_udp_ip_dest_ip), + .m_udp_source_port(rx_udp_source_port), + .m_udp_dest_port(rx_udp_dest_port), + .m_udp_length(rx_udp_length), + .m_udp_checksum(rx_udp_checksum), + .m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata), + .m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep), + .m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid), + .m_udp_payload_axis_tready(rx_udp_payload_axis_tready), + .m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast), + .m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser), + // Status signals + .ip_rx_busy(), + .ip_tx_busy(), + .udp_rx_busy(), + .udp_tx_busy(), + .ip_rx_error_header_early_termination(), + .ip_rx_error_payload_early_termination(), + .ip_rx_error_invalid_header(), + .ip_rx_error_invalid_checksum(), + .ip_tx_error_payload_early_termination(), + .ip_tx_error_arp_failed(), + .udp_rx_error_header_early_termination(), + .udp_rx_error_payload_early_termination(), + .udp_tx_error_payload_early_termination(), + // Configuration + .local_mac(local_mac), + .local_ip(local_ip), + .gateway_ip(gateway_ip), + .subnet_mask(subnet_mask), + .clear_arp_cache(1'b0) +); + +axis_fifo #( + .DEPTH(8192), + .DATA_WIDTH(64), + .KEEP_ENABLE(1), + .KEEP_WIDTH(8), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(1), + .FRAME_FIFO(0) +) +udp_payload_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(rx_fifo_udp_payload_axis_tdata), + .s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep), + .s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid), + .s_axis_tready(rx_fifo_udp_payload_axis_tready), + .s_axis_tlast(rx_fifo_udp_payload_axis_tlast), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(rx_fifo_udp_payload_axis_tuser), + + // AXI output + .m_axis_tdata(tx_fifo_udp_payload_axis_tdata), + .m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep), + .m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid), + .m_axis_tready(tx_fifo_udp_payload_axis_tready), + .m_axis_tlast(tx_fifo_udp_payload_axis_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(tx_fifo_udp_payload_axis_tuser), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() +); + +endmodule + +`resetall diff --git a/example/Arista_7132LB/fpga_25g/rtl/sync_signal.v b/example/Arista_7132LB/fpga_25g/rtl/sync_signal.v new file mode 100644 index 000000000..74b855fa1 --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/rtl/sync_signal.v @@ -0,0 +1,62 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`resetall +`timescale 1 ns / 1 ps +`default_nettype none + +/* + * Synchronizes an asyncronous signal to a given clock by using a pipeline of + * two registers. + */ +module sync_signal #( + parameter WIDTH=1, // width of the input and output signals + parameter N=2 // depth of synchronizer +)( + input wire clk, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [WIDTH-1:0] sync_reg[N-1:0]; + +/* + * The synchronized output is the last register in the pipeline. + */ +assign out = sync_reg[N-1]; + +integer k; + +always @(posedge clk) begin + sync_reg[0] <= in; + for (k = 1; k < N; k = k + 1) begin + sync_reg[k] <= sync_reg[k-1]; + end +end + +endmodule + +`resetall diff --git a/example/Arista_7132LB/fpga_25g/tb/fpga_core/Makefile b/example/Arista_7132LB/fpga_25g/tb/fpga_core/Makefile new file mode 100644 index 000000000..7f0403cef --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/tb/fpga_core/Makefile @@ -0,0 +1,96 @@ +# Copyright (c) 2020 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +TOPLEVEL_LANG = verilog + +SIM ?= icarus +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = fpga_core +TOPLEVEL = test_$(DUT) +MODULE = test_$(DUT) +VERILOG_SOURCES += $(TOPLEVEL).v +VERILOG_SOURCES += ../../rtl/$(DUT).v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g_fifo.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_rx.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_tx.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_complete_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_checksum_gen_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_complete_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_arb_mux.v +VERILOG_SOURCES += ../../lib/eth/rtl/arp.v +VERILOG_SOURCES += ../../lib/eth/rtl/arp_cache.v +VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_rx.v +VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_tx.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_arb_mux.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/arbiter.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/priority_encoder.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v + +# module parameters +#export PARAM_A := value + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + +# COMPILE_ARGS += -P $(TOPLEVEL).A=$(PARAM_A) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH + +# COMPILE_ARGS += -GA=$(PARAM_A) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py b/example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py new file mode 100644 index 000000000..69a83b273 --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,220 @@ +""" + +Copyright (c) 2020 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +import logging +import os + +from scapy.layers.l2 import Ether, ARP +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) + + # Ethernet + self.ch_source = [] + self.ch_sink = [] + + for ch in self.dut.ch: + cocotb.start_soon(Clock(ch.ch_rx_clk, 2.56, units="ns").start()) + source = XgmiiSource(ch.ch_rxd, ch.ch_rxc, ch.ch_rx_clk, ch.ch_rx_rst) + self.ch_source.append(source) + cocotb.start_soon(Clock(ch.ch_tx_clk, 2.56, units="ns").start()) + sink = XgmiiSink(ch.ch_txd, ch.ch_txc, ch.ch_tx_clk, ch.ch_tx_rst) + self.ch_sink.append(sink) + + async def init(self): + + self.dut.rst.setimmediatevalue(0) + for ch in self.dut.ch: + ch.ch_rx_rst.setimmediatevalue(0) + ch.ch_tx_rst.setimmediatevalue(0) + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 1 + for ch in self.dut.ch: + ch.ch_rx_rst.value = 1 + ch.ch_tx_rst.value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 0 + for ch in self.dut.ch: + ch.ch_rx_rst.value = 0 + ch.ch_tx_rst.value = 0 + + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("test UDP RX packet") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') + ip = IP(src='192.168.1.100', dst='192.168.1.128') + udp = UDP(sport=5678, dport=1234) + test_pkt = eth / ip / udp / payload + + test_frame = XgmiiFrame.from_payload(test_pkt.build()) + + await tb.ch_source[0].send(test_frame) + + tb.log.info("receive ARP request") + + rx_frame = await tb.ch_sink[0].recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[ARP].hwtype == 1 + assert rx_pkt[ARP].ptype == 0x0800 + assert rx_pkt[ARP].hwlen == 6 + assert rx_pkt[ARP].plen == 4 + assert rx_pkt[ARP].op == 1 + assert rx_pkt[ARP].hwsrc == test_pkt.dst + assert rx_pkt[ARP].psrc == test_pkt[IP].dst + assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' + assert rx_pkt[ARP].pdst == test_pkt[IP].src + + tb.log.info("send ARP response") + + eth = Ether(src=test_pkt.src, dst=test_pkt.dst) + arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, + hwsrc=test_pkt.src, psrc=test_pkt[IP].src, + hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) + resp_pkt = eth / arp + + resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) + + await tb.ch_source[0].send(resp_frame) + + tb.log.info("receive UDP packet") + + rx_frame = await tb.ch_sink[0].recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == test_pkt.src + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[IP].dst == test_pkt[IP].src + assert rx_pkt[IP].src == test_pkt[IP].dst + assert rx_pkt[UDP].dport == test_pkt[UDP].sport + assert rx_pkt[UDP].sport == test_pkt[UDP].dport + assert rx_pkt[UDP].payload == test_pkt[UDP].payload + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = "test_fpga_core" + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.v"), + os.path.join(rtl_dir, f"{dut}.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(eth_rtl_dir, "lfsr.v"), + os.path.join(eth_rtl_dir, "eth_axis_rx.v"), + os.path.join(eth_rtl_dir, "eth_axis_tx.v"), + os.path.join(eth_rtl_dir, "udp_complete_64.v"), + os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), + os.path.join(eth_rtl_dir, "udp_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_complete_64.v"), + os.path.join(eth_rtl_dir, "ip_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_arb_mux.v"), + os.path.join(eth_rtl_dir, "arp.v"), + os.path.join(eth_rtl_dir, "arp_cache.v"), + os.path.join(eth_rtl_dir, "arp_eth_rx.v"), + os.path.join(eth_rtl_dir, "arp_eth_tx.v"), + os.path.join(eth_rtl_dir, "eth_arb_mux.v"), + os.path.join(axis_rtl_dir, "arbiter.v"), + os.path.join(axis_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + ] + + parameters = {} + + # parameters['A'] = val + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v b/example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v new file mode 100644 index 000000000..bbcf4ae3d --- /dev/null +++ b/example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v @@ -0,0 +1,104 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Testbench top-level module + */ +module test_fpga_core (); + +genvar n; + +wire clk; +wire rst; + +// XGMII 10G PHY +parameter QUAD_CNT = 17; +parameter CH_CNT = QUAD_CNT*4; + +wire [CH_CNT-1:0] eth_tx_clk; +wire [CH_CNT-1:0] eth_tx_rst; +wire [CH_CNT*64-1:0] eth_txd; +wire [CH_CNT*8-1:0] eth_txc; +wire [CH_CNT-1:0] eth_rx_clk; +wire [CH_CNT-1:0] eth_rx_rst; +wire [CH_CNT*64-1:0] eth_rxd; +wire [CH_CNT*8-1:0] eth_rxc; + +generate + +for (n = 0; n < CH_CNT; n = n + 1) begin : ch + + wire ch_tx_clk; + wire ch_tx_rst; + wire [63:0] ch_txd; + wire [7:0] ch_txc; + wire ch_rx_clk; + wire ch_rx_rst; + wire [63:0] ch_rxd; + wire [7:0] ch_rxc; + + assign eth_tx_clk[n +: 1] = ch_tx_clk; + assign eth_tx_rst[n +: 1] = ch_tx_rst; + assign ch_txd = eth_txd[n*64 +: 64]; + assign ch_txc = eth_txc[n*8 +: 8]; + assign eth_rx_clk[n +: 1] = ch_rx_clk; + assign eth_rx_rst[n +: 1] = ch_rx_rst; + assign eth_rxd[n*64 +: 64] = ch_rxd; + assign eth_rxc[n*8 +: 8] = ch_rxc; + +end + +endgenerate + +fpga_core +core_inst ( + /* + * Clock: 156.25 MHz + * Synchronous reset + */ + .clk(clk), + .rst(rst), + + /* + * Ethernet: QSFP28 + */ + .eth_tx_clk(eth_tx_clk), + .eth_tx_rst(eth_tx_rst), + .eth_txd(eth_txd), + .eth_txc(eth_txc), + .eth_rx_clk(eth_rx_clk), + .eth_rx_rst(eth_rx_rst), + .eth_rxd(eth_rxd), + .eth_rxc(eth_rxc) +); + +endmodule + +`resetall From 1e88ed3d2e8a473c2eafb2003a56f2691688ebcc Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 25 Aug 2023 23:12:59 -0700 Subject: [PATCH 07/19] Update readme Signed-off-by: Alex Forencich --- README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 0ade5cedf..c22744ee9 100644 --- a/README.md +++ b/README.md @@ -45,7 +45,7 @@ following boards: * Terasic DE5-Net (Intel Stratix V 5SGXEA7N2F45C2) * Exablaze ExaNIC X10 (Xilinx Kintex UltraScale XCKU035) * Exablaze ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P) -* HiTech Global HTG-9200 (Xilinx UltraScale+ XCVU9P) +* HiTech Global HTG-9200 (Xilinx Virtex UltraScale+ XCVU9P) * HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) (Xilinx Virtex 6 XC6VHX565T) * Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P) * Xilinx KC705 (Xilinx Kintex 7 XC7K325T) @@ -63,6 +63,7 @@ following boards: * Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P) * Xilinx ZCU102 (Xilinx Zynq UltraScale+ XCZU9EG) * Xilinx ZCU106 (Xilinx Zynq UltraScale+ XCZU7EV) +* Arista 7132LB-48Y4C (Xilinx Virtex UltraScale+ XCVU9P) ## Documentation From 5d610594888e1758206dccb4d181cb288968665e Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 00:36:39 -0700 Subject: [PATCH 08/19] Use quad wrappers in ADM-PCIE-9V3 example design Signed-off-by: Alex Forencich --- example/ADM_PCIE_9V3/fpga_25g/fpga.xdc | 64 +- example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile | 1 + .../ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++ .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 578 ++++++------------ 6 files changed, 614 insertions(+), 443 deletions(-) create mode 100644 example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/ADM_PCIE_9V3/fpga_25g/fpga.xdc b/example/ADM_PCIE_9V3/fpga_25g/fpga.xdc index 526ed4a88..f5c9996e0 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/fpga.xdc +++ b/example/ADM_PCIE_9V3/fpga_25g/fpga.xdc @@ -41,22 +41,22 @@ set_input_delay 0 [get_ports {user_sw[*]}] #set_property -dict {LOC H31 IOSTANDARD LVCMOS18} [get_ports gpio_n[1]] # QSFP28 Interfaces -set_property -dict {LOC G38 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC G39 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC F35 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC F36 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC E38 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC E39 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC D35 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC D36 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC C38 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC C39 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC C33 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC C34 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC B36 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC B37 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC A33 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC A34 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC G38 } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC G39 } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC F35 } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC F36 } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC E38 } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC E39 } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC D35 } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC D36 } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC C38 } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC C39 } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC C33 } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC C34 } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC B36 } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC B37 } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC A33 } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC A34 } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 set_property -dict {LOC N33 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_128 from ? set_property -dict {LOC N34 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_128 from ? set_property -dict {LOC F29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_modprs_l] @@ -65,22 +65,22 @@ set_property -dict {LOC D31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports # 161.1328125 MHz MGT reference clock create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p] -set_property -dict {LOC R38 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC R39 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC P35 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC P36 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC N38 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC N39 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC M35 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC M36 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC L38 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC L39 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC K35 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC K36 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC J38 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC J39 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC H35 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC H36 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC R38 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC R39 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC P35 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC P36 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC N38 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC N39 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC M35 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC M36 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC L38 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC L39 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC K35 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC K36 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC J38 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC J39 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC H35 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC H36 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 set_property -dict {LOC U33 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_127 from ? set_property -dict {LOC U34 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_127 from ? set_property -dict {LOC F33 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_modprs_l] diff --git a/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index 54d446b2e..e1edb3035 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v diff --git a/example/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile b/example/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile index 54d446b2e..e1edb3035 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile +++ b/example/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index 9e6aacf4c..23f78e6bb 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -49,43 +49,19 @@ module fpga ( /* * Ethernet: QSFP28 */ - output wire qsfp_0_tx_0_p, - output wire qsfp_0_tx_0_n, - input wire qsfp_0_rx_0_p, - input wire qsfp_0_rx_0_n, - output wire qsfp_0_tx_1_p, - output wire qsfp_0_tx_1_n, - input wire qsfp_0_rx_1_p, - input wire qsfp_0_rx_1_n, - output wire qsfp_0_tx_2_p, - output wire qsfp_0_tx_2_n, - input wire qsfp_0_rx_2_p, - input wire qsfp_0_rx_2_n, - output wire qsfp_0_tx_3_p, - output wire qsfp_0_tx_3_n, - input wire qsfp_0_rx_3_p, - input wire qsfp_0_rx_3_n, + output wire [3:0] qsfp_0_tx_p, + output wire [3:0] qsfp_0_tx_n, + input wire [3:0] qsfp_0_rx_p, + input wire [3:0] qsfp_0_rx_n, input wire qsfp_0_mgt_refclk_p, input wire qsfp_0_mgt_refclk_n, input wire qsfp_0_modprs_l, output wire qsfp_0_sel_l, - output wire qsfp_1_tx_0_p, - output wire qsfp_1_tx_0_n, - input wire qsfp_1_rx_0_p, - input wire qsfp_1_rx_0_n, - output wire qsfp_1_tx_1_p, - output wire qsfp_1_tx_1_n, - input wire qsfp_1_rx_1_p, - input wire qsfp_1_rx_1_n, - output wire qsfp_1_tx_2_p, - output wire qsfp_1_tx_2_n, - input wire qsfp_1_rx_2_p, - input wire qsfp_1_rx_2_n, - output wire qsfp_1_tx_3_p, - output wire qsfp_1_tx_3_n, - input wire qsfp_1_rx_3_p, - input wire qsfp_1_rx_3_n, + output wire [3:0] qsfp_1_tx_p, + output wire [3:0] qsfp_1_tx_n, + input wire [3:0] qsfp_1_rx_p, + input wire [3:0] qsfp_1_rx_n, input wire qsfp_1_mgt_refclk_p, input wire qsfp_1_mgt_refclk_n, input wire qsfp_1_modprs_l, @@ -268,208 +244,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_0_qpll0lock; -wire qsfp_0_qpll0outclk; -wire qsfp_0_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1), +eth_xcvr_phy_quad_wrapper #( .TX_SERDES_PIPELINE(2), .RX_SERDES_PIPELINE(2), .COUNT_125US(125000/2.56) ) -qsfp_0_phy_0_inst ( +qsfp_0_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_0_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_0_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_0_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_0_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_0_tx_p), + .xcvr_txn(qsfp_0_tx_n), + .xcvr_rxp(qsfp_0_rx_p), + .xcvr_rxn(qsfp_0_rx_n), - // Serial data - .xcvr_txp(qsfp_0_tx_0_p), - .xcvr_txn(qsfp_0_tx_0_n), - .xcvr_rxp(qsfp_0_rx_0_p), - .xcvr_rxn(qsfp_0_rx_0_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_0_tx_clk_0_int), + .phy_1_tx_rst(qsfp_0_tx_rst_0_int), + .phy_1_xgmii_txd(qsfp_0_txd_0_int), + .phy_1_xgmii_txc(qsfp_0_txc_0_int), + .phy_1_rx_clk(qsfp_0_rx_clk_0_int), + .phy_1_rx_rst(qsfp_0_rx_rst_0_int), + .phy_1_xgmii_rxd(qsfp_0_rxd_0_int), + .phy_1_xgmii_rxc(qsfp_0_rxc_0_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_0_rx_block_lock_0), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_0_tx_clk_0_int), - .phy_tx_rst(qsfp_0_tx_rst_0_int), - .phy_xgmii_txd(qsfp_0_txd_0_int), - .phy_xgmii_txc(qsfp_0_txc_0_int), - .phy_rx_clk(qsfp_0_rx_clk_0_int), - .phy_rx_rst(qsfp_0_rx_rst_0_int), - .phy_xgmii_rxd(qsfp_0_rxd_0_int), - .phy_xgmii_rxc(qsfp_0_rxc_0_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_0_rx_block_lock_0), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_0_tx_clk_1_int), + .phy_2_tx_rst(qsfp_0_tx_rst_1_int), + .phy_2_xgmii_txd(qsfp_0_txd_1_int), + .phy_2_xgmii_txc(qsfp_0_txc_1_int), + .phy_2_rx_clk(qsfp_0_rx_clk_1_int), + .phy_2_rx_rst(qsfp_0_rx_rst_1_int), + .phy_2_xgmii_rxd(qsfp_0_rxd_1_int), + .phy_2_xgmii_rxc(qsfp_0_rxc_1_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_0_rx_block_lock_1), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp_0_phy_1_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp_0_tx_clk_2_int), + .phy_3_tx_rst(qsfp_0_tx_rst_2_int), + .phy_3_xgmii_txd(qsfp_0_txd_2_int), + .phy_3_xgmii_txc(qsfp_0_txc_2_int), + .phy_3_rx_clk(qsfp_0_rx_clk_2_int), + .phy_3_rx_rst(qsfp_0_rx_rst_2_int), + .phy_3_xgmii_rxd(qsfp_0_rxd_2_int), + .phy_3_xgmii_rxc(qsfp_0_rxc_2_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_0_rx_block_lock_2), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_0_tx_1_p), - .xcvr_txn(qsfp_0_tx_1_n), - .xcvr_rxp(qsfp_0_rx_1_p), - .xcvr_rxn(qsfp_0_rx_1_n), - - // PHY connections - .phy_tx_clk(qsfp_0_tx_clk_1_int), - .phy_tx_rst(qsfp_0_tx_rst_1_int), - .phy_xgmii_txd(qsfp_0_txd_1_int), - .phy_xgmii_txc(qsfp_0_txc_1_int), - .phy_rx_clk(qsfp_0_rx_clk_1_int), - .phy_rx_rst(qsfp_0_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_0_rxd_1_int), - .phy_xgmii_rxc(qsfp_0_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_0_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp_0_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_0_tx_2_p), - .xcvr_txn(qsfp_0_tx_2_n), - .xcvr_rxp(qsfp_0_rx_2_p), - .xcvr_rxn(qsfp_0_rx_2_n), - - // PHY connections - .phy_tx_clk(qsfp_0_tx_clk_2_int), - .phy_tx_rst(qsfp_0_tx_rst_2_int), - .phy_xgmii_txd(qsfp_0_txd_2_int), - .phy_xgmii_txc(qsfp_0_txc_2_int), - .phy_rx_clk(qsfp_0_rx_clk_2_int), - .phy_rx_rst(qsfp_0_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_0_rxd_2_int), - .phy_xgmii_rxc(qsfp_0_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_0_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp_0_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_0_tx_3_p), - .xcvr_txn(qsfp_0_tx_3_n), - .xcvr_rxp(qsfp_0_rx_3_p), - .xcvr_rxn(qsfp_0_rx_3_n), - - // PHY connections - .phy_tx_clk(qsfp_0_tx_clk_3_int), - .phy_tx_rst(qsfp_0_tx_rst_3_int), - .phy_xgmii_txd(qsfp_0_txd_3_int), - .phy_xgmii_txc(qsfp_0_txc_3_int), - .phy_rx_clk(qsfp_0_rx_clk_3_int), - .phy_rx_rst(qsfp_0_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_0_rxd_3_int), - .phy_xgmii_rxc(qsfp_0_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_0_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_0_tx_clk_3_int), + .phy_4_tx_rst(qsfp_0_tx_rst_3_int), + .phy_4_xgmii_txd(qsfp_0_txd_3_int), + .phy_4_xgmii_txc(qsfp_0_txc_3_int), + .phy_4_rx_clk(qsfp_0_rx_clk_3_int), + .phy_4_rx_rst(qsfp_0_rx_rst_3_int), + .phy_4_xgmii_rxd(qsfp_0_rxd_3_int), + .phy_4_xgmii_rxc(qsfp_0_rxc_3_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_0_rx_block_lock_3), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP 1 @@ -523,208 +394,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst ( .ODIV2 () ); -wire qsfp_1_qpll0lock; -wire qsfp_1_qpll0outclk; -wire qsfp_1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1), +eth_xcvr_phy_quad_wrapper #( .TX_SERDES_PIPELINE(2), .RX_SERDES_PIPELINE(2), .COUNT_125US(125000/2.56) ) -qsfp_1_phy_0_inst ( +qsfp_1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_1_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_1_tx_p), + .xcvr_txn(qsfp_1_tx_n), + .xcvr_rxp(qsfp_1_rx_p), + .xcvr_rxn(qsfp_1_rx_n), - // Serial data - .xcvr_txp(qsfp_1_tx_0_p), - .xcvr_txn(qsfp_1_tx_0_n), - .xcvr_rxp(qsfp_1_rx_0_p), - .xcvr_rxn(qsfp_1_rx_0_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_1_tx_clk_0_int), + .phy_1_tx_rst(qsfp_1_tx_rst_0_int), + .phy_1_xgmii_txd(qsfp_1_txd_0_int), + .phy_1_xgmii_txc(qsfp_1_txc_0_int), + .phy_1_rx_clk(qsfp_1_rx_clk_0_int), + .phy_1_rx_rst(qsfp_1_rx_rst_0_int), + .phy_1_xgmii_rxd(qsfp_1_rxd_0_int), + .phy_1_xgmii_rxc(qsfp_1_rxc_0_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_1_rx_block_lock_0), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_0_int), - .phy_tx_rst(qsfp_1_tx_rst_0_int), - .phy_xgmii_txd(qsfp_1_txd_0_int), - .phy_xgmii_txc(qsfp_1_txc_0_int), - .phy_rx_clk(qsfp_1_rx_clk_0_int), - .phy_rx_rst(qsfp_1_rx_rst_0_int), - .phy_xgmii_rxd(qsfp_1_rxd_0_int), - .phy_xgmii_rxc(qsfp_1_rxc_0_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_0), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_1_tx_clk_1_int), + .phy_2_tx_rst(qsfp_1_tx_rst_1_int), + .phy_2_xgmii_txd(qsfp_1_txd_1_int), + .phy_2_xgmii_txc(qsfp_1_txc_1_int), + .phy_2_rx_clk(qsfp_1_rx_clk_1_int), + .phy_2_rx_rst(qsfp_1_rx_rst_1_int), + .phy_2_xgmii_rxd(qsfp_1_rxd_1_int), + .phy_2_xgmii_rxc(qsfp_1_rxc_1_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_1_rx_block_lock_1), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp_1_phy_1_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp_1_tx_clk_2_int), + .phy_3_tx_rst(qsfp_1_tx_rst_2_int), + .phy_3_xgmii_txd(qsfp_1_txd_2_int), + .phy_3_xgmii_txc(qsfp_1_txc_2_int), + .phy_3_rx_clk(qsfp_1_rx_clk_2_int), + .phy_3_rx_rst(qsfp_1_rx_rst_2_int), + .phy_3_xgmii_rxd(qsfp_1_rxd_2_int), + .phy_3_xgmii_rxc(qsfp_1_rxc_2_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_1_rx_block_lock_2), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_1_p), - .xcvr_txn(qsfp_1_tx_1_n), - .xcvr_rxp(qsfp_1_rx_1_p), - .xcvr_rxn(qsfp_1_rx_1_n), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_1_int), - .phy_tx_rst(qsfp_1_tx_rst_1_int), - .phy_xgmii_txd(qsfp_1_txd_1_int), - .phy_xgmii_txc(qsfp_1_txc_1_int), - .phy_rx_clk(qsfp_1_rx_clk_1_int), - .phy_rx_rst(qsfp_1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_1_rxd_1_int), - .phy_xgmii_rxc(qsfp_1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp_1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_2_p), - .xcvr_txn(qsfp_1_tx_2_n), - .xcvr_rxp(qsfp_1_rx_2_p), - .xcvr_rxn(qsfp_1_rx_2_n), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_2_int), - .phy_tx_rst(qsfp_1_tx_rst_2_int), - .phy_xgmii_txd(qsfp_1_txd_2_int), - .phy_xgmii_txc(qsfp_1_txc_2_int), - .phy_rx_clk(qsfp_1_rx_clk_2_int), - .phy_rx_rst(qsfp_1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_1_rxd_2_int), - .phy_xgmii_rxc(qsfp_1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp_1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_3_p), - .xcvr_txn(qsfp_1_tx_3_n), - .xcvr_rxp(qsfp_1_rx_3_p), - .xcvr_rxn(qsfp_1_rx_3_n), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_3_int), - .phy_tx_rst(qsfp_1_tx_rst_3_int), - .phy_xgmii_txd(qsfp_1_txd_3_int), - .phy_xgmii_txc(qsfp_1_txc_3_int), - .phy_rx_clk(qsfp_1_rx_clk_3_int), - .phy_rx_rst(qsfp_1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_1_rxd_3_int), - .phy_xgmii_rxc(qsfp_1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_1_tx_clk_3_int), + .phy_4_tx_rst(qsfp_1_tx_rst_3_int), + .phy_4_xgmii_txd(qsfp_1_txd_3_int), + .phy_4_xgmii_txc(qsfp_1_txc_3_int), + .phy_4_rx_clk(qsfp_1_rx_clk_3_int), + .phy_4_rx_rst(qsfp_1_rx_rst_3_int), + .phy_4_xgmii_rxd(qsfp_1_rxd_3_int), + .phy_4_xgmii_rxc(qsfp_1_rxc_3_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_1_rx_block_lock_3), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); assign front_led[0] = qsfp_0_rx_block_lock_0; From c673ddbc144fd9e9f9b9afe173179608b2016981 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 00:37:44 -0700 Subject: [PATCH 09/19] Use quad wrappers in fb2CG@KU15P example design Signed-off-by: Alex Forencich --- example/fb2CG/fpga_25g/fpga.xdc | 64 +- example/fb2CG/fpga_25g/fpga/Makefile | 1 + example/fb2CG/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++ .../fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/fb2CG/fpga_25g/rtl/fpga.v | 566 ++++++------------ 6 files changed, 620 insertions(+), 425 deletions(-) create mode 100644 example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/fb2CG/fpga_25g/fpga.xdc b/example/fb2CG/fpga_25g/fpga.xdc index 13f9b1390..7c2b5e0c2 100644 --- a/example/fb2CG/fpga_25g/fpga.xdc +++ b/example/fb2CG/fpga_25g/fpga.xdc @@ -78,22 +78,22 @@ set_false_path -from [get_ports {pg[*]}] set_input_delay 0 [get_ports {pg[*]}] # QSFP28 Interfaces -set_property -dict {LOC Y39 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC Y40 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC Y34 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC Y35 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC W41 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC W42 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC W36 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC W37 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC V39 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC V40 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC V34 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC V35 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC U41 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC U42 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC U36 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC U37 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC Y39 } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC Y40 } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC Y34 } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC Y35 } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC W41 } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC W42 } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC W36 } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC W37 } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC V39 } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC V40 } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC V34 } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC V35 } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC U41 } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC U42 } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC U36 } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC U37 } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 set_property -dict {LOC W32 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_130 from U28 set_property -dict {LOC W33 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_130 from U28 set_property -dict {LOC B9 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_0_mod_prsnt_n] @@ -116,22 +116,22 @@ set_input_delay 0 [get_ports {qsfp_0_mod_prsnt_n qsfp_0_intr_n}] #set_false_path -from [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] #set_input_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] -set_property -dict {LOC M39 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC M40 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC M34 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC M35 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC L41 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC L42 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC L36 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC L37 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC K39 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC K40 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC K34 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC K35 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC J41 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC J42 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC J36 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC J37 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC M39 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC M40 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC M34 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC M35 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC L41 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC L42 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC L36 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC L37 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC K39 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC K40 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC K34 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC K35 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC J41 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC J42 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC J36 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC J37 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 set_property -dict {LOC P30 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_132 from U28 set_property -dict {LOC P31 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_132 from U28 set_property -dict {LOC E10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_1_mod_prsnt_n] diff --git a/example/fb2CG/fpga_25g/fpga/Makefile b/example/fb2CG/fpga_25g/fpga/Makefile index 4efc48e93..f3f5055ac 100644 --- a/example/fb2CG/fpga_25g/fpga/Makefile +++ b/example/fb2CG/fpga_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = kintexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/led_sreg_driver.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v diff --git a/example/fb2CG/fpga_25g/fpga_10g/Makefile b/example/fb2CG/fpga_25g/fpga_10g/Makefile index 4efc48e93..f3f5055ac 100644 --- a/example/fb2CG/fpga_25g/fpga_10g/Makefile +++ b/example/fb2CG/fpga_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = kintexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/led_sreg_driver.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v diff --git a/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/fb2CG/fpga_25g/rtl/fpga.v b/example/fb2CG/fpga_25g/rtl/fpga.v index b34def624..60552d946 100644 --- a/example/fb2CG/fpga_25g/rtl/fpga.v +++ b/example/fb2CG/fpga_25g/rtl/fpga.v @@ -54,22 +54,10 @@ module fpga ( /* * Ethernet: QSFP28 */ - output wire qsfp_0_tx_0_p, - output wire qsfp_0_tx_0_n, - input wire qsfp_0_rx_0_p, - input wire qsfp_0_rx_0_n, - output wire qsfp_0_tx_1_p, - output wire qsfp_0_tx_1_n, - input wire qsfp_0_rx_1_p, - input wire qsfp_0_rx_1_n, - output wire qsfp_0_tx_2_p, - output wire qsfp_0_tx_2_n, - input wire qsfp_0_rx_2_p, - input wire qsfp_0_rx_2_n, - output wire qsfp_0_tx_3_p, - output wire qsfp_0_tx_3_n, - input wire qsfp_0_rx_3_p, - input wire qsfp_0_rx_3_n, + output wire [3:0] qsfp_0_tx_p, + output wire [3:0] qsfp_0_tx_n, + input wire [3:0] qsfp_0_rx_p, + input wire [3:0] qsfp_0_rx_n, input wire qsfp_0_mgt_refclk_p, input wire qsfp_0_mgt_refclk_n, input wire qsfp_0_mod_prsnt_n, @@ -77,22 +65,10 @@ module fpga ( output wire qsfp_0_lp_mode, input wire qsfp_0_intr_n, - output wire qsfp_1_tx_0_p, - output wire qsfp_1_tx_0_n, - input wire qsfp_1_rx_0_p, - input wire qsfp_1_rx_0_n, - output wire qsfp_1_tx_1_p, - output wire qsfp_1_tx_1_n, - input wire qsfp_1_rx_1_p, - input wire qsfp_1_rx_1_n, - output wire qsfp_1_tx_2_p, - output wire qsfp_1_tx_2_n, - input wire qsfp_1_rx_2_p, - input wire qsfp_1_rx_2_n, - output wire qsfp_1_tx_3_p, - output wire qsfp_1_tx_3_n, - input wire qsfp_1_rx_3_p, - input wire qsfp_1_rx_3_n, + output wire [3:0] qsfp_1_tx_p, + output wire [3:0] qsfp_1_tx_n, + input wire [3:0] qsfp_1_rx_p, + input wire [3:0] qsfp_1_rx_n, input wire qsfp_1_mgt_refclk_p, input wire qsfp_1_mgt_refclk_n, input wire qsfp_1_mod_prsnt_n, @@ -317,196 +293,103 @@ qsfp_0_sync_reset_inst ( .out(qsfp_0_rst) ); -wire qsfp_0_qpll0lock; -wire qsfp_0_qpll0outclk; -wire qsfp_0_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp_0_phy_0_inst ( +qsfp_0_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_0_rst), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(qsfp_0_gtpowergood), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_0_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_0_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_0_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_0_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_0_tx_p), + .xcvr_txn(qsfp_0_tx_n), + .xcvr_rxp(qsfp_0_rx_p), + .xcvr_rxn(qsfp_0_rx_n), - // Serial data - .xcvr_txp(qsfp_0_tx_0_p), - .xcvr_txn(qsfp_0_tx_0_n), - .xcvr_rxp(qsfp_0_rx_0_p), - .xcvr_rxn(qsfp_0_rx_0_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_0_tx_clk_0_int), + .phy_1_tx_rst(qsfp_0_tx_rst_0_int), + .phy_1_xgmii_txd(qsfp_0_txd_0_int), + .phy_1_xgmii_txc(qsfp_0_txc_0_int), + .phy_1_rx_clk(qsfp_0_rx_clk_0_int), + .phy_1_rx_rst(qsfp_0_rx_rst_0_int), + .phy_1_xgmii_rxd(qsfp_0_rxd_0_int), + .phy_1_xgmii_rxc(qsfp_0_rxc_0_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_0_rx_block_lock_0), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_0_tx_clk_0_int), - .phy_tx_rst(qsfp_0_tx_rst_0_int), - .phy_xgmii_txd(qsfp_0_txd_0_int), - .phy_xgmii_txc(qsfp_0_txc_0_int), - .phy_rx_clk(qsfp_0_rx_clk_0_int), - .phy_rx_rst(qsfp_0_rx_rst_0_int), - .phy_xgmii_rxd(qsfp_0_rxd_0_int), - .phy_xgmii_rxc(qsfp_0_rxc_0_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_0_rx_block_lock_0), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_0_tx_clk_1_int), + .phy_2_tx_rst(qsfp_0_tx_rst_1_int), + .phy_2_xgmii_txd(qsfp_0_txd_1_int), + .phy_2_xgmii_txc(qsfp_0_txc_1_int), + .phy_2_rx_clk(qsfp_0_rx_clk_1_int), + .phy_2_rx_rst(qsfp_0_rx_rst_1_int), + .phy_2_xgmii_rxd(qsfp_0_rxd_1_int), + .phy_2_xgmii_rxc(qsfp_0_rxc_1_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_0_rx_block_lock_1), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_0_phy_1_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_0_rst), + .phy_3_tx_clk(qsfp_0_tx_clk_2_int), + .phy_3_tx_rst(qsfp_0_tx_rst_2_int), + .phy_3_xgmii_txd(qsfp_0_txd_2_int), + .phy_3_xgmii_txc(qsfp_0_txc_2_int), + .phy_3_rx_clk(qsfp_0_rx_clk_2_int), + .phy_3_rx_rst(qsfp_0_rx_rst_2_int), + .phy_3_xgmii_rxd(qsfp_0_rxd_2_int), + .phy_3_xgmii_rxc(qsfp_0_rxc_2_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_0_rx_block_lock_2), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_0_tx_1_p), - .xcvr_txn(qsfp_0_tx_1_n), - .xcvr_rxp(qsfp_0_rx_1_p), - .xcvr_rxn(qsfp_0_rx_1_n), - - // PHY connections - .phy_tx_clk(qsfp_0_tx_clk_1_int), - .phy_tx_rst(qsfp_0_tx_rst_1_int), - .phy_xgmii_txd(qsfp_0_txd_1_int), - .phy_xgmii_txc(qsfp_0_txc_1_int), - .phy_rx_clk(qsfp_0_rx_clk_1_int), - .phy_rx_rst(qsfp_0_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_0_rxd_1_int), - .phy_xgmii_rxc(qsfp_0_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_0_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_0_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_0_rst), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_0_tx_2_p), - .xcvr_txn(qsfp_0_tx_2_n), - .xcvr_rxp(qsfp_0_rx_2_p), - .xcvr_rxn(qsfp_0_rx_2_n), - - // PHY connections - .phy_tx_clk(qsfp_0_tx_clk_2_int), - .phy_tx_rst(qsfp_0_tx_rst_2_int), - .phy_xgmii_txd(qsfp_0_txd_2_int), - .phy_xgmii_txc(qsfp_0_txc_2_int), - .phy_rx_clk(qsfp_0_rx_clk_2_int), - .phy_rx_rst(qsfp_0_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_0_rxd_2_int), - .phy_xgmii_rxc(qsfp_0_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_0_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_0_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_0_rst), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_0_tx_3_p), - .xcvr_txn(qsfp_0_tx_3_n), - .xcvr_rxp(qsfp_0_rx_3_p), - .xcvr_rxn(qsfp_0_rx_3_n), - - // PHY connections - .phy_tx_clk(qsfp_0_tx_clk_3_int), - .phy_tx_rst(qsfp_0_tx_rst_3_int), - .phy_xgmii_txd(qsfp_0_txd_3_int), - .phy_xgmii_txc(qsfp_0_txc_3_int), - .phy_rx_clk(qsfp_0_rx_clk_3_int), - .phy_rx_rst(qsfp_0_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_0_rxd_3_int), - .phy_xgmii_rxc(qsfp_0_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_0_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_0_tx_clk_3_int), + .phy_4_tx_rst(qsfp_0_tx_rst_3_int), + .phy_4_xgmii_txd(qsfp_0_txd_3_int), + .phy_4_xgmii_txc(qsfp_0_txc_3_int), + .phy_4_rx_clk(qsfp_0_rx_clk_3_int), + .phy_4_rx_rst(qsfp_0_rx_rst_3_int), + .phy_4_xgmii_rxd(qsfp_0_rxd_3_int), + .phy_4_xgmii_rxc(qsfp_0_rxc_3_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_0_rx_block_lock_3), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP1 @@ -586,196 +469,103 @@ qsfp_1_sync_reset_inst ( .out(qsfp_1_rst) ); -wire qsfp_1_qpll0lock; -wire qsfp_1_qpll0outclk; -wire qsfp_1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp_1_phy_0_inst ( +qsfp_1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(qsfp_1_rst), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(qsfp_1_gtpowergood), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_1_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_1_tx_p), + .xcvr_txn(qsfp_1_tx_n), + .xcvr_rxp(qsfp_1_rx_p), + .xcvr_rxn(qsfp_1_rx_n), - // Serial data - .xcvr_txp(qsfp_1_tx_0_p), - .xcvr_txn(qsfp_1_tx_0_n), - .xcvr_rxp(qsfp_1_rx_0_p), - .xcvr_rxn(qsfp_1_rx_0_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_1_tx_clk_0_int), + .phy_1_tx_rst(qsfp_1_tx_rst_0_int), + .phy_1_xgmii_txd(qsfp_1_txd_0_int), + .phy_1_xgmii_txc(qsfp_1_txc_0_int), + .phy_1_rx_clk(qsfp_1_rx_clk_0_int), + .phy_1_rx_rst(qsfp_1_rx_rst_0_int), + .phy_1_xgmii_rxd(qsfp_1_rxd_0_int), + .phy_1_xgmii_rxc(qsfp_1_rxc_0_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_1_rx_block_lock_0), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_0_int), - .phy_tx_rst(qsfp_1_tx_rst_0_int), - .phy_xgmii_txd(qsfp_1_txd_0_int), - .phy_xgmii_txc(qsfp_1_txc_0_int), - .phy_rx_clk(qsfp_1_rx_clk_0_int), - .phy_rx_rst(qsfp_1_rx_rst_0_int), - .phy_xgmii_rxd(qsfp_1_rxd_0_int), - .phy_xgmii_rxc(qsfp_1_rxc_0_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_0), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_1_tx_clk_1_int), + .phy_2_tx_rst(qsfp_1_tx_rst_1_int), + .phy_2_xgmii_txd(qsfp_1_txd_1_int), + .phy_2_xgmii_txc(qsfp_1_txc_1_int), + .phy_2_rx_clk(qsfp_1_rx_clk_1_int), + .phy_2_rx_rst(qsfp_1_rx_rst_1_int), + .phy_2_xgmii_rxd(qsfp_1_rxd_1_int), + .phy_2_xgmii_rxc(qsfp_1_rxc_1_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_1_rx_block_lock_1), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_1_phy_1_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_1_rst), + .phy_3_tx_clk(qsfp_1_tx_clk_2_int), + .phy_3_tx_rst(qsfp_1_tx_rst_2_int), + .phy_3_xgmii_txd(qsfp_1_txd_2_int), + .phy_3_xgmii_txc(qsfp_1_txc_2_int), + .phy_3_rx_clk(qsfp_1_rx_clk_2_int), + .phy_3_rx_rst(qsfp_1_rx_rst_2_int), + .phy_3_xgmii_rxd(qsfp_1_rxd_2_int), + .phy_3_xgmii_rxc(qsfp_1_rxc_2_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_1_rx_block_lock_2), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_1_p), - .xcvr_txn(qsfp_1_tx_1_n), - .xcvr_rxp(qsfp_1_rx_1_p), - .xcvr_rxn(qsfp_1_rx_1_n), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_1_int), - .phy_tx_rst(qsfp_1_tx_rst_1_int), - .phy_xgmii_txd(qsfp_1_txd_1_int), - .phy_xgmii_txc(qsfp_1_txc_1_int), - .phy_rx_clk(qsfp_1_rx_clk_1_int), - .phy_rx_rst(qsfp_1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_1_rxd_1_int), - .phy_xgmii_rxc(qsfp_1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_1_rst), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_2_p), - .xcvr_txn(qsfp_1_tx_2_n), - .xcvr_rxp(qsfp_1_rx_2_p), - .xcvr_rxn(qsfp_1_rx_2_n), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_2_int), - .phy_tx_rst(qsfp_1_tx_rst_2_int), - .phy_xgmii_txd(qsfp_1_txd_2_int), - .phy_xgmii_txc(qsfp_1_txc_2_int), - .phy_rx_clk(qsfp_1_rx_clk_2_int), - .phy_rx_rst(qsfp_1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_1_rxd_2_int), - .phy_xgmii_rxc(qsfp_1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_1_rst), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_3_p), - .xcvr_txn(qsfp_1_tx_3_n), - .xcvr_rxp(qsfp_1_rx_3_p), - .xcvr_rxn(qsfp_1_rx_3_n), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_3_int), - .phy_tx_rst(qsfp_1_tx_rst_3_int), - .phy_xgmii_txd(qsfp_1_txd_3_int), - .phy_xgmii_txc(qsfp_1_txc_3_int), - .phy_rx_clk(qsfp_1_rx_clk_3_int), - .phy_rx_rst(qsfp_1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_1_rxd_3_int), - .phy_xgmii_rxc(qsfp_1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_1_tx_clk_3_int), + .phy_4_tx_rst(qsfp_1_tx_rst_3_int), + .phy_4_xgmii_txd(qsfp_1_txd_3_int), + .phy_4_xgmii_txc(qsfp_1_txc_3_int), + .phy_4_rx_clk(qsfp_1_rx_clk_3_int), + .phy_4_rx_rst(qsfp_1_rx_rst_3_int), + .phy_4_xgmii_rxd(qsfp_1_rxd_3_int), + .phy_4_xgmii_rxc(qsfp_1_rxc_3_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_1_rx_block_lock_3), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); assign led_green[0] = qsfp_0_rx_block_lock_0; From bd06e577643b6682d7900ff9560db341d2ec83c5 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 01:05:23 -0700 Subject: [PATCH 10/19] Use quad wrappers in VCU1525 example design Signed-off-by: Alex Forencich --- example/VCU1525/fpga_25g/fpga.xdc | 64 +- example/VCU1525/fpga_25g/fpga/Makefile | 1 + example/VCU1525/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++ .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/VCU1525/fpga_25g/rtl/fpga.v | 566 ++++++------------ 6 files changed, 620 insertions(+), 425 deletions(-) create mode 100644 example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/VCU1525/fpga_25g/fpga.xdc b/example/VCU1525/fpga_25g/fpga.xdc index d78cb3ec2..d91d10266 100644 --- a/example/VCU1525/fpga_25g/fpga.xdc +++ b/example/VCU1525/fpga_25g/fpga.xdc @@ -73,22 +73,22 @@ set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] #set_input_delay 0 [get_ports {uart_rxd}] # QSFP28 Interfaces -set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 #set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 #set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 @@ -116,22 +116,22 @@ set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_ref set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] -set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 #set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 #set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 diff --git a/example/VCU1525/fpga_25g/fpga/Makefile b/example/VCU1525/fpga_25g/fpga/Makefile index 16f015da3..ce7660017 100644 --- a/example/VCU1525/fpga_25g/fpga/Makefile +++ b/example/VCU1525/fpga_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v diff --git a/example/VCU1525/fpga_25g/fpga_10g/Makefile b/example/VCU1525/fpga_25g/fpga_10g/Makefile index 16f015da3..ce7660017 100644 --- a/example/VCU1525/fpga_25g/fpga_10g/Makefile +++ b/example/VCU1525/fpga_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v diff --git a/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/VCU1525/fpga_25g/rtl/fpga.v b/example/VCU1525/fpga_25g/rtl/fpga.v index fa17cb4cc..929d9324c 100644 --- a/example/VCU1525/fpga_25g/rtl/fpga.v +++ b/example/VCU1525/fpga_25g/rtl/fpga.v @@ -52,22 +52,10 @@ module fpga ( /* * Ethernet: QSFP28 */ - output wire qsfp0_tx1_p, - output wire qsfp0_tx1_n, - input wire qsfp0_rx1_p, - input wire qsfp0_rx1_n, - output wire qsfp0_tx2_p, - output wire qsfp0_tx2_n, - input wire qsfp0_rx2_p, - input wire qsfp0_rx2_n, - output wire qsfp0_tx3_p, - output wire qsfp0_tx3_n, - input wire qsfp0_rx3_p, - input wire qsfp0_rx3_n, - output wire qsfp0_tx4_p, - output wire qsfp0_tx4_n, - input wire qsfp0_rx4_p, - input wire qsfp0_rx4_n, + output wire [3:0] qsfp0_tx_p, + output wire [3:0] qsfp0_tx_n, + input wire [3:0] qsfp0_rx_p, + input wire [3:0] qsfp0_rx_n, // input wire qsfp0_mgt_refclk_0_p, // input wire qsfp0_mgt_refclk_0_n, input wire qsfp0_mgt_refclk_1_p, @@ -80,22 +68,10 @@ module fpga ( output wire qsfp0_refclk_reset, output wire [1:0] qsfp0_fs, - output wire qsfp1_tx1_p, - output wire qsfp1_tx1_n, - input wire qsfp1_rx1_p, - input wire qsfp1_rx1_n, - output wire qsfp1_tx2_p, - output wire qsfp1_tx2_n, - input wire qsfp1_rx2_p, - input wire qsfp1_rx2_n, - output wire qsfp1_tx3_p, - output wire qsfp1_tx3_n, - input wire qsfp1_rx3_p, - input wire qsfp1_rx3_n, - output wire qsfp1_tx4_p, - output wire qsfp1_tx4_n, - input wire qsfp1_rx4_p, - input wire qsfp1_rx4_n, + output wire [3:0] qsfp1_tx_p, + output wire [3:0] qsfp1_tx_n, + input wire [3:0] qsfp1_rx_p, + input wire [3:0] qsfp1_rx_n, // input wire qsfp1_mgt_refclk_0_p, // input wire qsfp1_mgt_refclk_0_n, input wire qsfp1_mgt_refclk_1_p, @@ -381,196 +357,103 @@ BUFG_GT bufg_gt_refclk_inst ( .O (qsfp0_mgt_refclk_1_bufg) ); -wire qsfp0_qpll0lock; -wire qsfp0_qpll0outclk; -wire qsfp0_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp0_phy_1_inst ( +qsfp0_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(qsfp0_gtpowergood), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1), - .xcvr_qpll0lock_out(qsfp0_qpll0lock), - .xcvr_qpll0outclk_out(qsfp0_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp0_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp0_tx_p), + .xcvr_txn(qsfp0_tx_n), + .xcvr_rxp(qsfp0_rx_p), + .xcvr_rxn(qsfp0_rx_n), - // Serial data - .xcvr_txp(qsfp0_tx1_p), - .xcvr_txn(qsfp0_tx1_n), - .xcvr_rxp(qsfp0_rx1_p), - .xcvr_rxn(qsfp0_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp0_tx_clk_1_int), + .phy_1_tx_rst(qsfp0_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp0_txd_1_int), + .phy_1_xgmii_txc(qsfp0_txc_1_int), + .phy_1_rx_clk(qsfp0_rx_clk_1_int), + .phy_1_rx_rst(qsfp0_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp0_rxd_1_int), + .phy_1_xgmii_rxc(qsfp0_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp0_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_1_int), - .phy_tx_rst(qsfp0_tx_rst_1_int), - .phy_xgmii_txd(qsfp0_txd_1_int), - .phy_xgmii_txc(qsfp0_txc_1_int), - .phy_rx_clk(qsfp0_rx_clk_1_int), - .phy_rx_rst(qsfp0_rx_rst_1_int), - .phy_xgmii_rxd(qsfp0_rxd_1_int), - .phy_xgmii_rxc(qsfp0_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp0_tx_clk_2_int), + .phy_2_tx_rst(qsfp0_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp0_txd_2_int), + .phy_2_xgmii_txc(qsfp0_txc_2_int), + .phy_2_rx_clk(qsfp0_rx_clk_2_int), + .phy_2_rx_rst(qsfp0_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp0_rxd_2_int), + .phy_2_xgmii_rxc(qsfp0_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp0_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp0_tx_clk_3_int), + .phy_3_tx_rst(qsfp0_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp0_txd_3_int), + .phy_3_xgmii_txc(qsfp0_txc_3_int), + .phy_3_rx_clk(qsfp0_rx_clk_3_int), + .phy_3_rx_rst(qsfp0_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp0_rxd_3_int), + .phy_3_xgmii_rxc(qsfp0_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp0_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx2_p), - .xcvr_txn(qsfp0_tx2_n), - .xcvr_rxp(qsfp0_rx2_p), - .xcvr_rxn(qsfp0_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_2_int), - .phy_tx_rst(qsfp0_tx_rst_2_int), - .phy_xgmii_txd(qsfp0_txd_2_int), - .phy_xgmii_txc(qsfp0_txc_2_int), - .phy_rx_clk(qsfp0_rx_clk_2_int), - .phy_rx_rst(qsfp0_rx_rst_2_int), - .phy_xgmii_rxd(qsfp0_rxd_2_int), - .phy_xgmii_rxc(qsfp0_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx3_p), - .xcvr_txn(qsfp0_tx3_n), - .xcvr_rxp(qsfp0_rx3_p), - .xcvr_rxn(qsfp0_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_3_int), - .phy_tx_rst(qsfp0_tx_rst_3_int), - .phy_xgmii_txd(qsfp0_txd_3_int), - .phy_xgmii_txc(qsfp0_txc_3_int), - .phy_rx_clk(qsfp0_rx_clk_3_int), - .phy_rx_rst(qsfp0_rx_rst_3_int), - .phy_xgmii_rxd(qsfp0_rxd_3_int), - .phy_xgmii_rxc(qsfp0_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx4_p), - .xcvr_txn(qsfp0_tx4_n), - .xcvr_rxp(qsfp0_rx4_p), - .xcvr_rxn(qsfp0_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_4_int), - .phy_tx_rst(qsfp0_tx_rst_4_int), - .phy_xgmii_txd(qsfp0_txd_4_int), - .phy_xgmii_txc(qsfp0_txc_4_int), - .phy_rx_clk(qsfp0_rx_clk_4_int), - .phy_rx_rst(qsfp0_rx_rst_4_int), - .phy_xgmii_rxd(qsfp0_rxd_4_int), - .phy_xgmii_rxc(qsfp0_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp0_tx_clk_4_int), + .phy_4_tx_rst(qsfp0_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp0_txd_4_int), + .phy_4_xgmii_txc(qsfp0_txc_4_int), + .phy_4_rx_clk(qsfp0_rx_clk_4_int), + .phy_4_rx_rst(qsfp0_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp0_rxd_4_int), + .phy_4_xgmii_rxc(qsfp0_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp0_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP1 @@ -628,196 +511,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst ( .ODIV2 () ); -wire qsfp1_qpll0lock; -wire qsfp1_qpll0outclk; -wire qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp1_phy_1_inst ( +qsfp1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1), - .xcvr_qpll0lock_out(qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp1_tx_p), + .xcvr_txn(qsfp1_tx_n), + .xcvr_rxp(qsfp1_rx_p), + .xcvr_rxn(qsfp1_rx_n), - // Serial data - .xcvr_txp(qsfp1_tx1_p), - .xcvr_txn(qsfp1_tx1_n), - .xcvr_rxp(qsfp1_rx1_p), - .xcvr_rxn(qsfp1_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp1_tx_clk_1_int), + .phy_1_tx_rst(qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp1_txd_1_int), + .phy_1_xgmii_txc(qsfp1_txc_1_int), + .phy_1_rx_clk(qsfp1_rx_clk_1_int), + .phy_1_rx_rst(qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_1_int), - .phy_tx_rst(qsfp1_tx_rst_1_int), - .phy_xgmii_txd(qsfp1_txd_1_int), - .phy_xgmii_txc(qsfp1_txc_1_int), - .phy_rx_clk(qsfp1_rx_clk_1_int), - .phy_rx_rst(qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp1_rxd_1_int), - .phy_xgmii_rxc(qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp1_tx_clk_2_int), + .phy_2_tx_rst(qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp1_txd_2_int), + .phy_2_xgmii_txc(qsfp1_txc_2_int), + .phy_2_rx_clk(qsfp1_rx_clk_2_int), + .phy_2_rx_rst(qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp1_tx_clk_3_int), + .phy_3_tx_rst(qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp1_txd_3_int), + .phy_3_xgmii_txc(qsfp1_txc_3_int), + .phy_3_rx_clk(qsfp1_rx_clk_3_int), + .phy_3_rx_rst(qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx2_p), - .xcvr_txn(qsfp1_tx2_n), - .xcvr_rxp(qsfp1_rx2_p), - .xcvr_rxn(qsfp1_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_2_int), - .phy_tx_rst(qsfp1_tx_rst_2_int), - .phy_xgmii_txd(qsfp1_txd_2_int), - .phy_xgmii_txc(qsfp1_txc_2_int), - .phy_rx_clk(qsfp1_rx_clk_2_int), - .phy_rx_rst(qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp1_rxd_2_int), - .phy_xgmii_rxc(qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx3_p), - .xcvr_txn(qsfp1_tx3_n), - .xcvr_rxp(qsfp1_rx3_p), - .xcvr_rxn(qsfp1_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_3_int), - .phy_tx_rst(qsfp1_tx_rst_3_int), - .phy_xgmii_txd(qsfp1_txd_3_int), - .phy_xgmii_txc(qsfp1_txc_3_int), - .phy_rx_clk(qsfp1_rx_clk_3_int), - .phy_rx_rst(qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp1_rxd_3_int), - .phy_xgmii_rxc(qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx4_p), - .xcvr_txn(qsfp1_tx4_n), - .xcvr_rxp(qsfp1_rx4_p), - .xcvr_rxn(qsfp1_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_4_int), - .phy_tx_rst(qsfp1_tx_rst_4_int), - .phy_xgmii_txd(qsfp1_txd_4_int), - .phy_xgmii_txc(qsfp1_txc_4_int), - .phy_rx_clk(qsfp1_rx_clk_4_int), - .phy_rx_rst(qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp1_rxd_4_int), - .phy_xgmii_rxc(qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp1_tx_clk_4_int), + .phy_4_tx_rst(qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp1_txd_4_int), + .phy_4_xgmii_txc(qsfp1_txc_4_int), + .phy_4_rx_clk(qsfp1_rx_clk_4_int), + .phy_4_rx_rst(qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); fpga_core From 65361d157b793646b3331ed750bb7060843a8167 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 01:06:28 -0700 Subject: [PATCH 11/19] Use quad wrappers in AU200 example design Signed-off-by: Alex Forencich --- example/AU200/fpga_25g/fpga.xdc | 64 +- example/AU200/fpga_25g/fpga/Makefile | 1 + example/AU200/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++ .../AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/AU200/fpga_25g/rtl/fpga.v | 566 ++++++------------ 6 files changed, 620 insertions(+), 425 deletions(-) create mode 100644 example/AU200/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/AU200/fpga_25g/fpga.xdc b/example/AU200/fpga_25g/fpga.xdc index 53665ef34..b83e8c59c 100644 --- a/example/AU200/fpga_25g/fpga.xdc +++ b/example/AU200/fpga_25g/fpga.xdc @@ -88,22 +88,22 @@ set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] #set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}] # QSFP28 Interfaces -set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 #set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 #set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 @@ -131,22 +131,22 @@ set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_ref set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] -set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 #set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 #set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 diff --git a/example/AU200/fpga_25g/fpga/Makefile b/example/AU200/fpga_25g/fpga/Makefile index 632b41026..d8670336b 100644 --- a/example/AU200/fpga_25g/fpga/Makefile +++ b/example/AU200/fpga_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v diff --git a/example/AU200/fpga_25g/fpga_10g/Makefile b/example/AU200/fpga_25g/fpga_10g/Makefile index 632b41026..d8670336b 100644 --- a/example/AU200/fpga_25g/fpga_10g/Makefile +++ b/example/AU200/fpga_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v diff --git a/example/AU200/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/AU200/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/AU200/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/AU200/fpga_25g/rtl/fpga.v b/example/AU200/fpga_25g/rtl/fpga.v index fa17cb4cc..929d9324c 100644 --- a/example/AU200/fpga_25g/rtl/fpga.v +++ b/example/AU200/fpga_25g/rtl/fpga.v @@ -52,22 +52,10 @@ module fpga ( /* * Ethernet: QSFP28 */ - output wire qsfp0_tx1_p, - output wire qsfp0_tx1_n, - input wire qsfp0_rx1_p, - input wire qsfp0_rx1_n, - output wire qsfp0_tx2_p, - output wire qsfp0_tx2_n, - input wire qsfp0_rx2_p, - input wire qsfp0_rx2_n, - output wire qsfp0_tx3_p, - output wire qsfp0_tx3_n, - input wire qsfp0_rx3_p, - input wire qsfp0_rx3_n, - output wire qsfp0_tx4_p, - output wire qsfp0_tx4_n, - input wire qsfp0_rx4_p, - input wire qsfp0_rx4_n, + output wire [3:0] qsfp0_tx_p, + output wire [3:0] qsfp0_tx_n, + input wire [3:0] qsfp0_rx_p, + input wire [3:0] qsfp0_rx_n, // input wire qsfp0_mgt_refclk_0_p, // input wire qsfp0_mgt_refclk_0_n, input wire qsfp0_mgt_refclk_1_p, @@ -80,22 +68,10 @@ module fpga ( output wire qsfp0_refclk_reset, output wire [1:0] qsfp0_fs, - output wire qsfp1_tx1_p, - output wire qsfp1_tx1_n, - input wire qsfp1_rx1_p, - input wire qsfp1_rx1_n, - output wire qsfp1_tx2_p, - output wire qsfp1_tx2_n, - input wire qsfp1_rx2_p, - input wire qsfp1_rx2_n, - output wire qsfp1_tx3_p, - output wire qsfp1_tx3_n, - input wire qsfp1_rx3_p, - input wire qsfp1_rx3_n, - output wire qsfp1_tx4_p, - output wire qsfp1_tx4_n, - input wire qsfp1_rx4_p, - input wire qsfp1_rx4_n, + output wire [3:0] qsfp1_tx_p, + output wire [3:0] qsfp1_tx_n, + input wire [3:0] qsfp1_rx_p, + input wire [3:0] qsfp1_rx_n, // input wire qsfp1_mgt_refclk_0_p, // input wire qsfp1_mgt_refclk_0_n, input wire qsfp1_mgt_refclk_1_p, @@ -381,196 +357,103 @@ BUFG_GT bufg_gt_refclk_inst ( .O (qsfp0_mgt_refclk_1_bufg) ); -wire qsfp0_qpll0lock; -wire qsfp0_qpll0outclk; -wire qsfp0_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp0_phy_1_inst ( +qsfp0_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(qsfp0_gtpowergood), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1), - .xcvr_qpll0lock_out(qsfp0_qpll0lock), - .xcvr_qpll0outclk_out(qsfp0_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp0_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp0_tx_p), + .xcvr_txn(qsfp0_tx_n), + .xcvr_rxp(qsfp0_rx_p), + .xcvr_rxn(qsfp0_rx_n), - // Serial data - .xcvr_txp(qsfp0_tx1_p), - .xcvr_txn(qsfp0_tx1_n), - .xcvr_rxp(qsfp0_rx1_p), - .xcvr_rxn(qsfp0_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp0_tx_clk_1_int), + .phy_1_tx_rst(qsfp0_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp0_txd_1_int), + .phy_1_xgmii_txc(qsfp0_txc_1_int), + .phy_1_rx_clk(qsfp0_rx_clk_1_int), + .phy_1_rx_rst(qsfp0_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp0_rxd_1_int), + .phy_1_xgmii_rxc(qsfp0_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp0_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_1_int), - .phy_tx_rst(qsfp0_tx_rst_1_int), - .phy_xgmii_txd(qsfp0_txd_1_int), - .phy_xgmii_txc(qsfp0_txc_1_int), - .phy_rx_clk(qsfp0_rx_clk_1_int), - .phy_rx_rst(qsfp0_rx_rst_1_int), - .phy_xgmii_rxd(qsfp0_rxd_1_int), - .phy_xgmii_rxc(qsfp0_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp0_tx_clk_2_int), + .phy_2_tx_rst(qsfp0_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp0_txd_2_int), + .phy_2_xgmii_txc(qsfp0_txc_2_int), + .phy_2_rx_clk(qsfp0_rx_clk_2_int), + .phy_2_rx_rst(qsfp0_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp0_rxd_2_int), + .phy_2_xgmii_rxc(qsfp0_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp0_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp0_tx_clk_3_int), + .phy_3_tx_rst(qsfp0_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp0_txd_3_int), + .phy_3_xgmii_txc(qsfp0_txc_3_int), + .phy_3_rx_clk(qsfp0_rx_clk_3_int), + .phy_3_rx_rst(qsfp0_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp0_rxd_3_int), + .phy_3_xgmii_rxc(qsfp0_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp0_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx2_p), - .xcvr_txn(qsfp0_tx2_n), - .xcvr_rxp(qsfp0_rx2_p), - .xcvr_rxn(qsfp0_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_2_int), - .phy_tx_rst(qsfp0_tx_rst_2_int), - .phy_xgmii_txd(qsfp0_txd_2_int), - .phy_xgmii_txc(qsfp0_txc_2_int), - .phy_rx_clk(qsfp0_rx_clk_2_int), - .phy_rx_rst(qsfp0_rx_rst_2_int), - .phy_xgmii_rxd(qsfp0_rxd_2_int), - .phy_xgmii_rxc(qsfp0_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx3_p), - .xcvr_txn(qsfp0_tx3_n), - .xcvr_rxp(qsfp0_rx3_p), - .xcvr_rxn(qsfp0_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_3_int), - .phy_tx_rst(qsfp0_tx_rst_3_int), - .phy_xgmii_txd(qsfp0_txd_3_int), - .phy_xgmii_txc(qsfp0_txc_3_int), - .phy_rx_clk(qsfp0_rx_clk_3_int), - .phy_rx_rst(qsfp0_rx_rst_3_int), - .phy_xgmii_rxd(qsfp0_rxd_3_int), - .phy_xgmii_rxc(qsfp0_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx4_p), - .xcvr_txn(qsfp0_tx4_n), - .xcvr_rxp(qsfp0_rx4_p), - .xcvr_rxn(qsfp0_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_4_int), - .phy_tx_rst(qsfp0_tx_rst_4_int), - .phy_xgmii_txd(qsfp0_txd_4_int), - .phy_xgmii_txc(qsfp0_txc_4_int), - .phy_rx_clk(qsfp0_rx_clk_4_int), - .phy_rx_rst(qsfp0_rx_rst_4_int), - .phy_xgmii_rxd(qsfp0_rxd_4_int), - .phy_xgmii_rxc(qsfp0_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp0_tx_clk_4_int), + .phy_4_tx_rst(qsfp0_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp0_txd_4_int), + .phy_4_xgmii_txc(qsfp0_txc_4_int), + .phy_4_rx_clk(qsfp0_rx_clk_4_int), + .phy_4_rx_rst(qsfp0_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp0_rxd_4_int), + .phy_4_xgmii_rxc(qsfp0_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp0_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP1 @@ -628,196 +511,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst ( .ODIV2 () ); -wire qsfp1_qpll0lock; -wire qsfp1_qpll0outclk; -wire qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp1_phy_1_inst ( +qsfp1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1), - .xcvr_qpll0lock_out(qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp1_tx_p), + .xcvr_txn(qsfp1_tx_n), + .xcvr_rxp(qsfp1_rx_p), + .xcvr_rxn(qsfp1_rx_n), - // Serial data - .xcvr_txp(qsfp1_tx1_p), - .xcvr_txn(qsfp1_tx1_n), - .xcvr_rxp(qsfp1_rx1_p), - .xcvr_rxn(qsfp1_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp1_tx_clk_1_int), + .phy_1_tx_rst(qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp1_txd_1_int), + .phy_1_xgmii_txc(qsfp1_txc_1_int), + .phy_1_rx_clk(qsfp1_rx_clk_1_int), + .phy_1_rx_rst(qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_1_int), - .phy_tx_rst(qsfp1_tx_rst_1_int), - .phy_xgmii_txd(qsfp1_txd_1_int), - .phy_xgmii_txc(qsfp1_txc_1_int), - .phy_rx_clk(qsfp1_rx_clk_1_int), - .phy_rx_rst(qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp1_rxd_1_int), - .phy_xgmii_rxc(qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp1_tx_clk_2_int), + .phy_2_tx_rst(qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp1_txd_2_int), + .phy_2_xgmii_txc(qsfp1_txc_2_int), + .phy_2_rx_clk(qsfp1_rx_clk_2_int), + .phy_2_rx_rst(qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp1_tx_clk_3_int), + .phy_3_tx_rst(qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp1_txd_3_int), + .phy_3_xgmii_txc(qsfp1_txc_3_int), + .phy_3_rx_clk(qsfp1_rx_clk_3_int), + .phy_3_rx_rst(qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx2_p), - .xcvr_txn(qsfp1_tx2_n), - .xcvr_rxp(qsfp1_rx2_p), - .xcvr_rxn(qsfp1_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_2_int), - .phy_tx_rst(qsfp1_tx_rst_2_int), - .phy_xgmii_txd(qsfp1_txd_2_int), - .phy_xgmii_txc(qsfp1_txc_2_int), - .phy_rx_clk(qsfp1_rx_clk_2_int), - .phy_rx_rst(qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp1_rxd_2_int), - .phy_xgmii_rxc(qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx3_p), - .xcvr_txn(qsfp1_tx3_n), - .xcvr_rxp(qsfp1_rx3_p), - .xcvr_rxn(qsfp1_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_3_int), - .phy_tx_rst(qsfp1_tx_rst_3_int), - .phy_xgmii_txd(qsfp1_txd_3_int), - .phy_xgmii_txc(qsfp1_txc_3_int), - .phy_rx_clk(qsfp1_rx_clk_3_int), - .phy_rx_rst(qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp1_rxd_3_int), - .phy_xgmii_rxc(qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx4_p), - .xcvr_txn(qsfp1_tx4_n), - .xcvr_rxp(qsfp1_rx4_p), - .xcvr_rxn(qsfp1_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_4_int), - .phy_tx_rst(qsfp1_tx_rst_4_int), - .phy_xgmii_txd(qsfp1_txd_4_int), - .phy_xgmii_txc(qsfp1_txc_4_int), - .phy_rx_clk(qsfp1_rx_clk_4_int), - .phy_rx_rst(qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp1_rxd_4_int), - .phy_xgmii_rxc(qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp1_tx_clk_4_int), + .phy_4_tx_rst(qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp1_txd_4_int), + .phy_4_xgmii_txc(qsfp1_txc_4_int), + .phy_4_rx_clk(qsfp1_rx_clk_4_int), + .phy_4_rx_rst(qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); fpga_core From 22f327b35ff7c16083edf916e32cdc52e68c35e3 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 01:07:30 -0700 Subject: [PATCH 12/19] Use quad wrappers in AU250 example design Signed-off-by: Alex Forencich --- example/AU250/fpga_25g/fpga.xdc | 64 +- example/AU250/fpga_25g/fpga/Makefile | 1 + example/AU250/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++ .../AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/AU250/fpga_25g/rtl/fpga.v | 566 ++++++------------ 6 files changed, 620 insertions(+), 425 deletions(-) create mode 100644 example/AU250/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/AU250/fpga_25g/fpga.xdc b/example/AU250/fpga_25g/fpga.xdc index 2d006125a..900df213f 100644 --- a/example/AU250/fpga_25g/fpga.xdc +++ b/example/AU250/fpga_25g/fpga.xdc @@ -88,22 +88,22 @@ set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] #set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}] # QSFP28 Interfaces -set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 #set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 #set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 @@ -131,22 +131,22 @@ set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_ref set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] -set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 #set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 #set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 diff --git a/example/AU250/fpga_25g/fpga/Makefile b/example/AU250/fpga_25g/fpga/Makefile index ae7c4ef1b..5e8aef004 100644 --- a/example/AU250/fpga_25g/fpga/Makefile +++ b/example/AU250/fpga_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v diff --git a/example/AU250/fpga_25g/fpga_10g/Makefile b/example/AU250/fpga_25g/fpga_10g/Makefile index ae7c4ef1b..5e8aef004 100644 --- a/example/AU250/fpga_25g/fpga_10g/Makefile +++ b/example/AU250/fpga_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v diff --git a/example/AU250/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/AU250/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/AU250/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/AU250/fpga_25g/rtl/fpga.v b/example/AU250/fpga_25g/rtl/fpga.v index fa17cb4cc..929d9324c 100644 --- a/example/AU250/fpga_25g/rtl/fpga.v +++ b/example/AU250/fpga_25g/rtl/fpga.v @@ -52,22 +52,10 @@ module fpga ( /* * Ethernet: QSFP28 */ - output wire qsfp0_tx1_p, - output wire qsfp0_tx1_n, - input wire qsfp0_rx1_p, - input wire qsfp0_rx1_n, - output wire qsfp0_tx2_p, - output wire qsfp0_tx2_n, - input wire qsfp0_rx2_p, - input wire qsfp0_rx2_n, - output wire qsfp0_tx3_p, - output wire qsfp0_tx3_n, - input wire qsfp0_rx3_p, - input wire qsfp0_rx3_n, - output wire qsfp0_tx4_p, - output wire qsfp0_tx4_n, - input wire qsfp0_rx4_p, - input wire qsfp0_rx4_n, + output wire [3:0] qsfp0_tx_p, + output wire [3:0] qsfp0_tx_n, + input wire [3:0] qsfp0_rx_p, + input wire [3:0] qsfp0_rx_n, // input wire qsfp0_mgt_refclk_0_p, // input wire qsfp0_mgt_refclk_0_n, input wire qsfp0_mgt_refclk_1_p, @@ -80,22 +68,10 @@ module fpga ( output wire qsfp0_refclk_reset, output wire [1:0] qsfp0_fs, - output wire qsfp1_tx1_p, - output wire qsfp1_tx1_n, - input wire qsfp1_rx1_p, - input wire qsfp1_rx1_n, - output wire qsfp1_tx2_p, - output wire qsfp1_tx2_n, - input wire qsfp1_rx2_p, - input wire qsfp1_rx2_n, - output wire qsfp1_tx3_p, - output wire qsfp1_tx3_n, - input wire qsfp1_rx3_p, - input wire qsfp1_rx3_n, - output wire qsfp1_tx4_p, - output wire qsfp1_tx4_n, - input wire qsfp1_rx4_p, - input wire qsfp1_rx4_n, + output wire [3:0] qsfp1_tx_p, + output wire [3:0] qsfp1_tx_n, + input wire [3:0] qsfp1_rx_p, + input wire [3:0] qsfp1_rx_n, // input wire qsfp1_mgt_refclk_0_p, // input wire qsfp1_mgt_refclk_0_n, input wire qsfp1_mgt_refclk_1_p, @@ -381,196 +357,103 @@ BUFG_GT bufg_gt_refclk_inst ( .O (qsfp0_mgt_refclk_1_bufg) ); -wire qsfp0_qpll0lock; -wire qsfp0_qpll0outclk; -wire qsfp0_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp0_phy_1_inst ( +qsfp0_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(qsfp0_gtpowergood), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1), - .xcvr_qpll0lock_out(qsfp0_qpll0lock), - .xcvr_qpll0outclk_out(qsfp0_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp0_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp0_tx_p), + .xcvr_txn(qsfp0_tx_n), + .xcvr_rxp(qsfp0_rx_p), + .xcvr_rxn(qsfp0_rx_n), - // Serial data - .xcvr_txp(qsfp0_tx1_p), - .xcvr_txn(qsfp0_tx1_n), - .xcvr_rxp(qsfp0_rx1_p), - .xcvr_rxn(qsfp0_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp0_tx_clk_1_int), + .phy_1_tx_rst(qsfp0_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp0_txd_1_int), + .phy_1_xgmii_txc(qsfp0_txc_1_int), + .phy_1_rx_clk(qsfp0_rx_clk_1_int), + .phy_1_rx_rst(qsfp0_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp0_rxd_1_int), + .phy_1_xgmii_rxc(qsfp0_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp0_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_1_int), - .phy_tx_rst(qsfp0_tx_rst_1_int), - .phy_xgmii_txd(qsfp0_txd_1_int), - .phy_xgmii_txc(qsfp0_txc_1_int), - .phy_rx_clk(qsfp0_rx_clk_1_int), - .phy_rx_rst(qsfp0_rx_rst_1_int), - .phy_xgmii_rxd(qsfp0_rxd_1_int), - .phy_xgmii_rxc(qsfp0_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp0_tx_clk_2_int), + .phy_2_tx_rst(qsfp0_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp0_txd_2_int), + .phy_2_xgmii_txc(qsfp0_txc_2_int), + .phy_2_rx_clk(qsfp0_rx_clk_2_int), + .phy_2_rx_rst(qsfp0_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp0_rxd_2_int), + .phy_2_xgmii_rxc(qsfp0_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp0_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp0_tx_clk_3_int), + .phy_3_tx_rst(qsfp0_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp0_txd_3_int), + .phy_3_xgmii_txc(qsfp0_txc_3_int), + .phy_3_rx_clk(qsfp0_rx_clk_3_int), + .phy_3_rx_rst(qsfp0_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp0_rxd_3_int), + .phy_3_xgmii_rxc(qsfp0_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp0_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx2_p), - .xcvr_txn(qsfp0_tx2_n), - .xcvr_rxp(qsfp0_rx2_p), - .xcvr_rxn(qsfp0_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_2_int), - .phy_tx_rst(qsfp0_tx_rst_2_int), - .phy_xgmii_txd(qsfp0_txd_2_int), - .phy_xgmii_txc(qsfp0_txc_2_int), - .phy_rx_clk(qsfp0_rx_clk_2_int), - .phy_rx_rst(qsfp0_rx_rst_2_int), - .phy_xgmii_rxd(qsfp0_rxd_2_int), - .phy_xgmii_rxc(qsfp0_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx3_p), - .xcvr_txn(qsfp0_tx3_n), - .xcvr_rxp(qsfp0_rx3_p), - .xcvr_rxn(qsfp0_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_3_int), - .phy_tx_rst(qsfp0_tx_rst_3_int), - .phy_xgmii_txd(qsfp0_txd_3_int), - .phy_xgmii_txc(qsfp0_txc_3_int), - .phy_rx_clk(qsfp0_rx_clk_3_int), - .phy_rx_rst(qsfp0_rx_rst_3_int), - .phy_xgmii_rxd(qsfp0_rxd_3_int), - .phy_xgmii_rxc(qsfp0_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx4_p), - .xcvr_txn(qsfp0_tx4_n), - .xcvr_rxp(qsfp0_rx4_p), - .xcvr_rxn(qsfp0_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_4_int), - .phy_tx_rst(qsfp0_tx_rst_4_int), - .phy_xgmii_txd(qsfp0_txd_4_int), - .phy_xgmii_txc(qsfp0_txc_4_int), - .phy_rx_clk(qsfp0_rx_clk_4_int), - .phy_rx_rst(qsfp0_rx_rst_4_int), - .phy_xgmii_rxd(qsfp0_rxd_4_int), - .phy_xgmii_rxc(qsfp0_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp0_tx_clk_4_int), + .phy_4_tx_rst(qsfp0_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp0_txd_4_int), + .phy_4_xgmii_txc(qsfp0_txc_4_int), + .phy_4_rx_clk(qsfp0_rx_clk_4_int), + .phy_4_rx_rst(qsfp0_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp0_rxd_4_int), + .phy_4_xgmii_rxc(qsfp0_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp0_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP1 @@ -628,196 +511,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst ( .ODIV2 () ); -wire qsfp1_qpll0lock; -wire qsfp1_qpll0outclk; -wire qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp1_phy_1_inst ( +qsfp1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1), - .xcvr_qpll0lock_out(qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp1_tx_p), + .xcvr_txn(qsfp1_tx_n), + .xcvr_rxp(qsfp1_rx_p), + .xcvr_rxn(qsfp1_rx_n), - // Serial data - .xcvr_txp(qsfp1_tx1_p), - .xcvr_txn(qsfp1_tx1_n), - .xcvr_rxp(qsfp1_rx1_p), - .xcvr_rxn(qsfp1_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp1_tx_clk_1_int), + .phy_1_tx_rst(qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp1_txd_1_int), + .phy_1_xgmii_txc(qsfp1_txc_1_int), + .phy_1_rx_clk(qsfp1_rx_clk_1_int), + .phy_1_rx_rst(qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_1_int), - .phy_tx_rst(qsfp1_tx_rst_1_int), - .phy_xgmii_txd(qsfp1_txd_1_int), - .phy_xgmii_txc(qsfp1_txc_1_int), - .phy_rx_clk(qsfp1_rx_clk_1_int), - .phy_rx_rst(qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp1_rxd_1_int), - .phy_xgmii_rxc(qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp1_tx_clk_2_int), + .phy_2_tx_rst(qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp1_txd_2_int), + .phy_2_xgmii_txc(qsfp1_txc_2_int), + .phy_2_rx_clk(qsfp1_rx_clk_2_int), + .phy_2_rx_rst(qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp1_tx_clk_3_int), + .phy_3_tx_rst(qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp1_txd_3_int), + .phy_3_xgmii_txc(qsfp1_txc_3_int), + .phy_3_rx_clk(qsfp1_rx_clk_3_int), + .phy_3_rx_rst(qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx2_p), - .xcvr_txn(qsfp1_tx2_n), - .xcvr_rxp(qsfp1_rx2_p), - .xcvr_rxn(qsfp1_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_2_int), - .phy_tx_rst(qsfp1_tx_rst_2_int), - .phy_xgmii_txd(qsfp1_txd_2_int), - .phy_xgmii_txc(qsfp1_txc_2_int), - .phy_rx_clk(qsfp1_rx_clk_2_int), - .phy_rx_rst(qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp1_rxd_2_int), - .phy_xgmii_rxc(qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx3_p), - .xcvr_txn(qsfp1_tx3_n), - .xcvr_rxp(qsfp1_rx3_p), - .xcvr_rxn(qsfp1_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_3_int), - .phy_tx_rst(qsfp1_tx_rst_3_int), - .phy_xgmii_txd(qsfp1_txd_3_int), - .phy_xgmii_txc(qsfp1_txc_3_int), - .phy_rx_clk(qsfp1_rx_clk_3_int), - .phy_rx_rst(qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp1_rxd_3_int), - .phy_xgmii_rxc(qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx4_p), - .xcvr_txn(qsfp1_tx4_n), - .xcvr_rxp(qsfp1_rx4_p), - .xcvr_rxn(qsfp1_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_4_int), - .phy_tx_rst(qsfp1_tx_rst_4_int), - .phy_xgmii_txd(qsfp1_txd_4_int), - .phy_xgmii_txc(qsfp1_txc_4_int), - .phy_rx_clk(qsfp1_rx_clk_4_int), - .phy_rx_rst(qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp1_rxd_4_int), - .phy_xgmii_rxc(qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp1_tx_clk_4_int), + .phy_4_tx_rst(qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp1_txd_4_int), + .phy_4_xgmii_txc(qsfp1_txc_4_int), + .phy_4_rx_clk(qsfp1_rx_clk_4_int), + .phy_4_rx_rst(qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); fpga_core From 66987c8f62de33401c7b84945a5814ddbf6f0948 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 01:08:32 -0700 Subject: [PATCH 13/19] Use quad wrappers in AU280 example design Signed-off-by: Alex Forencich --- example/AU280/fpga_25g/fpga.xdc | 64 +- example/AU280/fpga_25g/fpga/Makefile | 1 + example/AU280/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++ .../AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/AU280/fpga_25g/rtl/fpga.v | 566 ++++++------------ 6 files changed, 620 insertions(+), 425 deletions(-) create mode 100644 example/AU280/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/AU280/fpga_25g/fpga.xdc b/example/AU280/fpga_25g/fpga.xdc index ff6be120e..0c65a0b72 100644 --- a/example/AU280/fpga_25g/fpga.xdc +++ b/example/AU280/fpga_25g/fpga.xdc @@ -60,22 +60,22 @@ set_false_path -to [get_ports {hbm_cattrip}] set_output_delay 0 [get_ports {hbm_cattrip}] # QSFP28 Interfaces -set_property -dict {LOC L53 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L54 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L48 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L49 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC K51 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC K52 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L44 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L45 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC J53 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC J54 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC K46 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC K47 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC H51 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC H52 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC J48 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC J49 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L53 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L54 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L48 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L49 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC K51 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC K52 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L44 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L45 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC J53 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC J54 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC K46 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC K47 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC H51 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC H52 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC J48 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC J49 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 #set_property -dict {LOC T42 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_134 from SI570 #set_property -dict {LOC T43 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_134 from SI570 set_property -dict {LOC R40 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_134 from SI546 @@ -95,22 +95,22 @@ create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_ set_false_path -to [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}] set_output_delay 0 [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}] -set_property -dict {LOC G53 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC G54 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC G48 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC G49 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC F51 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC F52 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC E48 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC E49 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC E53 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC E54 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC C48 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC C49 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC D51 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC D52 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC A49 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC A50 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC G53 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC G54 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC G48 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC G49 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC F51 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC F52 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC E48 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC E49 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC E53 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC E54 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC C48 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC C49 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC D51 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC D52 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC A49 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC A50 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 #set_property -dict {LOC P42 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_135 from SI570 #set_property -dict {LOC P43 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_135 from SI570 set_property -dict {LOC M42 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_135 from SI546 diff --git a/example/AU280/fpga_25g/fpga/Makefile b/example/AU280/fpga_25g/fpga/Makefile index 158a27cd0..0cb457f14 100644 --- a/example/AU280/fpga_25g/fpga/Makefile +++ b/example/AU280/fpga_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v diff --git a/example/AU280/fpga_25g/fpga_10g/Makefile b/example/AU280/fpga_25g/fpga_10g/Makefile index 158a27cd0..0cb457f14 100644 --- a/example/AU280/fpga_25g/fpga_10g/Makefile +++ b/example/AU280/fpga_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v diff --git a/example/AU280/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/AU280/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/AU280/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/AU280/fpga_25g/rtl/fpga.v b/example/AU280/fpga_25g/rtl/fpga.v index e67a86339..634923269 100644 --- a/example/AU280/fpga_25g/rtl/fpga.v +++ b/example/AU280/fpga_25g/rtl/fpga.v @@ -45,22 +45,10 @@ module fpga ( /* * Ethernet: QSFP28 */ - output wire qsfp0_tx1_p, - output wire qsfp0_tx1_n, - input wire qsfp0_rx1_p, - input wire qsfp0_rx1_n, - output wire qsfp0_tx2_p, - output wire qsfp0_tx2_n, - input wire qsfp0_rx2_p, - input wire qsfp0_rx2_n, - output wire qsfp0_tx3_p, - output wire qsfp0_tx3_n, - input wire qsfp0_rx3_p, - input wire qsfp0_rx3_n, - output wire qsfp0_tx4_p, - output wire qsfp0_tx4_n, - input wire qsfp0_rx4_p, - input wire qsfp0_rx4_n, + output wire [3:0] qsfp0_tx_p, + output wire [3:0] qsfp0_tx_n, + input wire [3:0] qsfp0_rx_p, + input wire [3:0] qsfp0_rx_n, // input wire qsfp0_mgt_refclk_0_p, // input wire qsfp0_mgt_refclk_0_n, input wire qsfp0_mgt_refclk_1_p, @@ -68,22 +56,10 @@ module fpga ( output wire qsfp0_refclk_oe_b, output wire qsfp0_refclk_fs, - output wire qsfp1_tx1_p, - output wire qsfp1_tx1_n, - input wire qsfp1_rx1_p, - input wire qsfp1_rx1_n, - output wire qsfp1_tx2_p, - output wire qsfp1_tx2_n, - input wire qsfp1_rx2_p, - input wire qsfp1_rx2_n, - output wire qsfp1_tx3_p, - output wire qsfp1_tx3_n, - input wire qsfp1_rx3_p, - input wire qsfp1_rx3_n, - output wire qsfp1_tx4_p, - output wire qsfp1_tx4_n, - input wire qsfp1_rx4_p, - input wire qsfp1_rx4_n, + output wire [3:0] qsfp1_tx_p, + output wire [3:0] qsfp1_tx_n, + input wire [3:0] qsfp1_rx_p, + input wire [3:0] qsfp1_rx_n, // input wire qsfp1_mgt_refclk_0_p, // input wire qsfp1_mgt_refclk_0_n, input wire qsfp1_mgt_refclk_1_p, @@ -258,196 +234,103 @@ BUFG_GT bufg_gt_refclk_inst ( .O (qsfp0_mgt_refclk_1_bufg) ); -wire qsfp0_qpll0lock; -wire qsfp0_qpll0outclk; -wire qsfp0_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp0_phy_1_inst ( +qsfp0_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(qsfp0_gtpowergood), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1), - .xcvr_qpll0lock_out(qsfp0_qpll0lock), - .xcvr_qpll0outclk_out(qsfp0_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp0_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp0_tx_p), + .xcvr_txn(qsfp0_tx_n), + .xcvr_rxp(qsfp0_rx_p), + .xcvr_rxn(qsfp0_rx_n), - // Serial data - .xcvr_txp(qsfp0_tx1_p), - .xcvr_txn(qsfp0_tx1_n), - .xcvr_rxp(qsfp0_rx1_p), - .xcvr_rxn(qsfp0_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp0_tx_clk_1_int), + .phy_1_tx_rst(qsfp0_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp0_txd_1_int), + .phy_1_xgmii_txc(qsfp0_txc_1_int), + .phy_1_rx_clk(qsfp0_rx_clk_1_int), + .phy_1_rx_rst(qsfp0_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp0_rxd_1_int), + .phy_1_xgmii_rxc(qsfp0_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp0_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_1_int), - .phy_tx_rst(qsfp0_tx_rst_1_int), - .phy_xgmii_txd(qsfp0_txd_1_int), - .phy_xgmii_txc(qsfp0_txc_1_int), - .phy_rx_clk(qsfp0_rx_clk_1_int), - .phy_rx_rst(qsfp0_rx_rst_1_int), - .phy_xgmii_rxd(qsfp0_rxd_1_int), - .phy_xgmii_rxc(qsfp0_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp0_tx_clk_2_int), + .phy_2_tx_rst(qsfp0_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp0_txd_2_int), + .phy_2_xgmii_txc(qsfp0_txc_2_int), + .phy_2_rx_clk(qsfp0_rx_clk_2_int), + .phy_2_rx_rst(qsfp0_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp0_rxd_2_int), + .phy_2_xgmii_rxc(qsfp0_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp0_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp0_tx_clk_3_int), + .phy_3_tx_rst(qsfp0_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp0_txd_3_int), + .phy_3_xgmii_txc(qsfp0_txc_3_int), + .phy_3_rx_clk(qsfp0_rx_clk_3_int), + .phy_3_rx_rst(qsfp0_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp0_rxd_3_int), + .phy_3_xgmii_rxc(qsfp0_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp0_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx2_p), - .xcvr_txn(qsfp0_tx2_n), - .xcvr_rxp(qsfp0_rx2_p), - .xcvr_rxn(qsfp0_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_2_int), - .phy_tx_rst(qsfp0_tx_rst_2_int), - .phy_xgmii_txd(qsfp0_txd_2_int), - .phy_xgmii_txc(qsfp0_txc_2_int), - .phy_rx_clk(qsfp0_rx_clk_2_int), - .phy_rx_rst(qsfp0_rx_rst_2_int), - .phy_xgmii_rxd(qsfp0_rxd_2_int), - .phy_xgmii_rxc(qsfp0_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx3_p), - .xcvr_txn(qsfp0_tx3_n), - .xcvr_rxp(qsfp0_rx3_p), - .xcvr_rxn(qsfp0_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_3_int), - .phy_tx_rst(qsfp0_tx_rst_3_int), - .phy_xgmii_txd(qsfp0_txd_3_int), - .phy_xgmii_txc(qsfp0_txc_3_int), - .phy_rx_clk(qsfp0_rx_clk_3_int), - .phy_rx_rst(qsfp0_rx_rst_3_int), - .phy_xgmii_rxd(qsfp0_rxd_3_int), - .phy_xgmii_rxc(qsfp0_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx4_p), - .xcvr_txn(qsfp0_tx4_n), - .xcvr_rxp(qsfp0_rx4_p), - .xcvr_rxn(qsfp0_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_4_int), - .phy_tx_rst(qsfp0_tx_rst_4_int), - .phy_xgmii_txd(qsfp0_txd_4_int), - .phy_xgmii_txc(qsfp0_txc_4_int), - .phy_rx_clk(qsfp0_rx_clk_4_int), - .phy_rx_rst(qsfp0_rx_rst_4_int), - .phy_xgmii_rxd(qsfp0_rxd_4_int), - .phy_xgmii_rxc(qsfp0_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp0_tx_clk_4_int), + .phy_4_tx_rst(qsfp0_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp0_txd_4_int), + .phy_4_xgmii_txc(qsfp0_txc_4_int), + .phy_4_rx_clk(qsfp0_rx_clk_4_int), + .phy_4_rx_rst(qsfp0_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp0_rxd_4_int), + .phy_4_xgmii_rxc(qsfp0_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp0_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP1 @@ -502,196 +385,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst ( .ODIV2 () ); -wire qsfp1_qpll0lock; -wire qsfp1_qpll0outclk; -wire qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp1_phy_1_inst ( +qsfp1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1), - .xcvr_qpll0lock_out(qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp1_tx_p), + .xcvr_txn(qsfp1_tx_n), + .xcvr_rxp(qsfp1_rx_p), + .xcvr_rxn(qsfp1_rx_n), - // Serial data - .xcvr_txp(qsfp1_tx1_p), - .xcvr_txn(qsfp1_tx1_n), - .xcvr_rxp(qsfp1_rx1_p), - .xcvr_rxn(qsfp1_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp1_tx_clk_1_int), + .phy_1_tx_rst(qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp1_txd_1_int), + .phy_1_xgmii_txc(qsfp1_txc_1_int), + .phy_1_rx_clk(qsfp1_rx_clk_1_int), + .phy_1_rx_rst(qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_1_int), - .phy_tx_rst(qsfp1_tx_rst_1_int), - .phy_xgmii_txd(qsfp1_txd_1_int), - .phy_xgmii_txc(qsfp1_txc_1_int), - .phy_rx_clk(qsfp1_rx_clk_1_int), - .phy_rx_rst(qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp1_rxd_1_int), - .phy_xgmii_rxc(qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp1_tx_clk_2_int), + .phy_2_tx_rst(qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp1_txd_2_int), + .phy_2_xgmii_txc(qsfp1_txc_2_int), + .phy_2_rx_clk(qsfp1_rx_clk_2_int), + .phy_2_rx_rst(qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp1_tx_clk_3_int), + .phy_3_tx_rst(qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp1_txd_3_int), + .phy_3_xgmii_txc(qsfp1_txc_3_int), + .phy_3_rx_clk(qsfp1_rx_clk_3_int), + .phy_3_rx_rst(qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx2_p), - .xcvr_txn(qsfp1_tx2_n), - .xcvr_rxp(qsfp1_rx2_p), - .xcvr_rxn(qsfp1_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_2_int), - .phy_tx_rst(qsfp1_tx_rst_2_int), - .phy_xgmii_txd(qsfp1_txd_2_int), - .phy_xgmii_txc(qsfp1_txc_2_int), - .phy_rx_clk(qsfp1_rx_clk_2_int), - .phy_rx_rst(qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp1_rxd_2_int), - .phy_xgmii_rxc(qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx3_p), - .xcvr_txn(qsfp1_tx3_n), - .xcvr_rxp(qsfp1_rx3_p), - .xcvr_rxn(qsfp1_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_3_int), - .phy_tx_rst(qsfp1_tx_rst_3_int), - .phy_xgmii_txd(qsfp1_txd_3_int), - .phy_xgmii_txc(qsfp1_txc_3_int), - .phy_rx_clk(qsfp1_rx_clk_3_int), - .phy_rx_rst(qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp1_rxd_3_int), - .phy_xgmii_rxc(qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx4_p), - .xcvr_txn(qsfp1_tx4_n), - .xcvr_rxp(qsfp1_rx4_p), - .xcvr_rxn(qsfp1_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_4_int), - .phy_tx_rst(qsfp1_tx_rst_4_int), - .phy_xgmii_txd(qsfp1_txd_4_int), - .phy_xgmii_txc(qsfp1_txc_4_int), - .phy_rx_clk(qsfp1_rx_clk_4_int), - .phy_rx_rst(qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp1_rxd_4_int), - .phy_xgmii_rxc(qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp1_tx_clk_4_int), + .phy_4_tx_rst(qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp1_txd_4_int), + .phy_4_xgmii_txc(qsfp1_txc_4_int), + .phy_4_rx_clk(qsfp1_rx_clk_4_int), + .phy_4_rx_rst(qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); fpga_core From 72de6c653a01738a0e71b7f2fd8a1d64914e3dbb Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 01:09:00 -0700 Subject: [PATCH 14/19] Use quad wrappers in AU50 example design Signed-off-by: Alex Forencich --- example/AU50/fpga_25g/fpga.xdc | 32 +- example/AU50/fpga_25g/fpga/Makefile | 1 + example/AU50/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++++++++ .../AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/AU50/fpga_25g/rtl/fpga.v | 283 ++++--------- 6 files changed, 515 insertions(+), 215 deletions(-) create mode 100644 example/AU50/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/AU50/fpga_25g/fpga.xdc b/example/AU50/fpga_25g/fpga.xdc index 5d3515481..c07fdfa5a 100644 --- a/example/AU50/fpga_25g/fpga.xdc +++ b/example/AU50/fpga_25g/fpga.xdc @@ -90,22 +90,22 @@ set_output_delay 0 [get_ports {hbm_cattrip}] #set_input_delay 0 [get_ports {si5394_i2c_sda si5394_i2c_scl}] # QSFP28 Interfaces -set_property -dict {LOC J45 } [get_ports qsfp_rx1_p] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC J46 } [get_ports qsfp_rx1_n] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC D42 } [get_ports qsfp_tx1_p] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC D43 } [get_ports qsfp_tx1_n] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC G45 } [get_ports qsfp_rx2_p] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC G46 } [get_ports qsfp_rx2_n] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC C40 } [get_ports qsfp_tx2_p] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC C41 } [get_ports qsfp_tx2_n] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC F43 } [get_ports qsfp_rx3_p] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC F44 } [get_ports qsfp_rx3_n] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC B42 } [get_ports qsfp_tx3_p] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC B43 } [get_ports qsfp_tx3_n] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC E45 } [get_ports qsfp_rx4_p] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC E46 } [get_ports qsfp_rx4_n] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC A40 } [get_ports qsfp_tx4_p] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 -set_property -dict {LOC A41 } [get_ports qsfp_tx4_n] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC J45 } [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC J46 } [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC D42 } [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC D43 } [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC G45 } [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC G46 } [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC C40 } [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC C41 } [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC F43 } [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC F44 } [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC B42 } [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC B43 } [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC E45 } [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC E46 } [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC A40 } [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC A41 } [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 set_property -dict {LOC N36 } [get_ports qsfp_mgt_refclk_0_p] ;# MGTREFCLK0P_131 from SI5394 OUT0 set_property -dict {LOC N37 } [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_131 from SI5394 OUT0 #set_property -dict {LOC M38 } [get_ports qsfp_mgt_refclk_1_p] ;# MGTREFCLK1P_131 from SI5394 OUT2 diff --git a/example/AU50/fpga_25g/fpga/Makefile b/example/AU50/fpga_25g/fpga/Makefile index 0bf97979b..fde78da47 100644 --- a/example/AU50/fpga_25g/fpga/Makefile +++ b/example/AU50/fpga_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v diff --git a/example/AU50/fpga_25g/fpga_10g/Makefile b/example/AU50/fpga_25g/fpga_10g/Makefile index 0bf97979b..fde78da47 100644 --- a/example/AU50/fpga_25g/fpga_10g/Makefile +++ b/example/AU50/fpga_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v diff --git a/example/AU50/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/AU50/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/AU50/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/AU50/fpga_25g/rtl/fpga.v b/example/AU50/fpga_25g/rtl/fpga.v index d032b7332..82852287a 100644 --- a/example/AU50/fpga_25g/rtl/fpga.v +++ b/example/AU50/fpga_25g/rtl/fpga.v @@ -43,22 +43,10 @@ module fpga ( /* * Ethernet: QSFP28 */ - output wire qsfp_tx1_p, - output wire qsfp_tx1_n, - input wire qsfp_rx1_p, - input wire qsfp_rx1_n, - output wire qsfp_tx2_p, - output wire qsfp_tx2_n, - input wire qsfp_rx2_p, - input wire qsfp_rx2_n, - output wire qsfp_tx3_p, - output wire qsfp_tx3_n, - input wire qsfp_rx3_p, - input wire qsfp_rx3_n, - output wire qsfp_tx4_p, - output wire qsfp_tx4_n, - input wire qsfp_rx4_p, - input wire qsfp_rx4_n, + output wire [3:0] qsfp_tx_p, + output wire [3:0] qsfp_tx_n, + input wire [3:0] qsfp_rx_p, + input wire [3:0] qsfp_rx_n, input wire qsfp_mgt_refclk_0_p, input wire qsfp_mgt_refclk_0_n // input wire qsfp_mgt_refclk_1_p, @@ -226,196 +214,103 @@ BUFG_GT bufg_gt_refclk_inst ( .O (qsfp_mgt_refclk_0_bufg) ); -wire qsfp_qpll0lock; -wire qsfp_qpll0outclk; -wire qsfp_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp_phy_1_inst ( +qsfp_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(qsfp_gtpowergood), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_mgt_refclk_0), - .xcvr_qpll0lock_out(qsfp_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_tx_p), + .xcvr_txn(qsfp_tx_n), + .xcvr_rxp(qsfp_rx_p), + .xcvr_rxn(qsfp_rx_n), - // Serial data - .xcvr_txp(qsfp_tx1_p), - .xcvr_txn(qsfp_tx1_n), - .xcvr_rxp(qsfp_rx1_p), - .xcvr_rxn(qsfp_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_tx_clk_1_int), + .phy_1_tx_rst(qsfp_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_txd_1_int), + .phy_1_xgmii_txc(qsfp_txc_1_int), + .phy_1_rx_clk(qsfp_rx_clk_1_int), + .phy_1_rx_rst(qsfp_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_tx_clk_1_int), - .phy_tx_rst(qsfp_tx_rst_1_int), - .phy_xgmii_txd(qsfp_txd_1_int), - .phy_xgmii_txc(qsfp_txc_1_int), - .phy_rx_clk(qsfp_rx_clk_1_int), - .phy_rx_rst(qsfp_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_rxd_1_int), - .phy_xgmii_rxc(qsfp_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_tx_clk_2_int), + .phy_2_tx_rst(qsfp_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_txd_2_int), + .phy_2_xgmii_txc(qsfp_txc_2_int), + .phy_2_rx_clk(qsfp_rx_clk_2_int), + .phy_2_rx_rst(qsfp_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp_tx_clk_3_int), + .phy_3_tx_rst(qsfp_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_txd_3_int), + .phy_3_xgmii_txc(qsfp_txc_3_int), + .phy_3_rx_clk(qsfp_rx_clk_3_int), + .phy_3_rx_rst(qsfp_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_tx2_p), - .xcvr_txn(qsfp_tx2_n), - .xcvr_rxp(qsfp_rx2_p), - .xcvr_rxn(qsfp_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp_tx_clk_2_int), - .phy_tx_rst(qsfp_tx_rst_2_int), - .phy_xgmii_txd(qsfp_txd_2_int), - .phy_xgmii_txc(qsfp_txc_2_int), - .phy_rx_clk(qsfp_rx_clk_2_int), - .phy_rx_rst(qsfp_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_rxd_2_int), - .phy_xgmii_rxc(qsfp_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_tx3_p), - .xcvr_txn(qsfp_tx3_n), - .xcvr_rxp(qsfp_rx3_p), - .xcvr_rxn(qsfp_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp_tx_clk_3_int), - .phy_tx_rst(qsfp_tx_rst_3_int), - .phy_xgmii_txd(qsfp_txd_3_int), - .phy_xgmii_txc(qsfp_txc_3_int), - .phy_rx_clk(qsfp_rx_clk_3_int), - .phy_rx_rst(qsfp_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_rxd_3_int), - .phy_xgmii_rxc(qsfp_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_tx4_p), - .xcvr_txn(qsfp_tx4_n), - .xcvr_rxp(qsfp_rx4_p), - .xcvr_rxn(qsfp_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp_tx_clk_4_int), - .phy_tx_rst(qsfp_tx_rst_4_int), - .phy_xgmii_txd(qsfp_txd_4_int), - .phy_xgmii_txc(qsfp_txc_4_int), - .phy_rx_clk(qsfp_rx_clk_4_int), - .phy_rx_rst(qsfp_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_rxd_4_int), - .phy_xgmii_rxc(qsfp_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_tx_clk_4_int), + .phy_4_tx_rst(qsfp_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_txd_4_int), + .phy_4_xgmii_txc(qsfp_txc_4_int), + .phy_4_rx_clk(qsfp_rx_clk_4_int), + .phy_4_rx_rst(qsfp_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); fpga_core From 4618edcd8e628af433f495ee11fd5968d3275405 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 01:15:29 -0700 Subject: [PATCH 15/19] Use quad wrappers in VCU108 example design Signed-off-by: Alex Forencich --- example/VCU108/fpga_10g/fpga.xdc | 144 +++---- example/VCU108/fpga_10g/fpga/Makefile | 1 + .../fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++++++++ .../fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/VCU108/fpga_10g/rtl/fpga.v | 281 ++++--------- example/VCU108/fpga_1g/fpga.xdc | 144 +++---- 6 files changed, 639 insertions(+), 344 deletions(-) create mode 100644 example/VCU108/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/VCU108/fpga_10g/fpga.xdc b/example/VCU108/fpga_10g/fpga.xdc index 1187f1bd4..30d4f8db1 100644 --- a/example/VCU108/fpga_10g/fpga.xdc +++ b/example/VCU108/fpga_10g/fpga.xdc @@ -130,22 +130,22 @@ set_input_delay 0 [get_ports {phy_int_n}] #set_input_delay 0 [get_ports {phy_mdio}] # Bullseye GTY -#set_property -dict {LOC AR45} [get_ports bullseye_rx0_p] ;# MGTYRXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AR46} [get_ports bullseye_rx0_n] ;# MGTYRXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AT42} [get_ports bullseye_tx0_p] ;# MGTYTXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AT43} [get_ports bullseye_tx0_n] ;# MGTYTXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AN45} [get_ports bullseye_rx1_p] ;# MGTYRXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AN46} [get_ports bullseye_rx1_n] ;# MGTYRXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AP42} [get_ports bullseye_tx1_p] ;# MGTYTXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AP43} [get_ports bullseye_tx1_n] ;# MGTYTXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AL45} [get_ports bullseye_rx2_p] ;# MGTYRXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AL46} [get_ports bullseye_rx2_n] ;# MGTYRXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AM42} [get_ports bullseye_tx2_p] ;# MGTYTXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AM43} [get_ports bullseye_tx2_n] ;# MGTYTXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AJ45} [get_ports bullseye_rx3_p] ;# MGTYRXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AJ46} [get_ports bullseye_rx3_n] ;# MGTYRXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AL40} [get_ports bullseye_tx3_p] ;# MGTYTXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AL41} [get_ports bullseye_tx3_n] ;# MGTYTXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AR45} [get_ports {bullseye_rx_p[0]}] ;# MGTYRXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AR46} [get_ports {bullseye_rx_n[0]}] ;# MGTYRXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AT42} [get_ports {bullseye_tx_p[0]}] ;# MGTYTXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AT43} [get_ports {bullseye_tx_n[0]}] ;# MGTYTXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AN45} [get_ports {bullseye_rx_p[1]}] ;# MGTYRXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AN46} [get_ports {bullseye_rx_n[1]}] ;# MGTYRXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AP42} [get_ports {bullseye_tx_p[1]}] ;# MGTYTXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AP43} [get_ports {bullseye_tx_n[1]}] ;# MGTYTXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AL45} [get_ports {bullseye_rx_p[2]}] ;# MGTYRXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AL46} [get_ports {bullseye_rx_n[2]}] ;# MGTYRXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AM42} [get_ports {bullseye_tx_p[2]}] ;# MGTYTXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AM43} [get_ports {bullseye_tx_n[2]}] ;# MGTYTXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AJ45} [get_ports {bullseye_rx_p[3]}] ;# MGTYRXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AJ46} [get_ports {bullseye_rx_n[3]}] ;# MGTYRXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AL40} [get_ports {bullseye_tx_p[3]}] ;# MGTYTXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AL41} [get_ports {bullseye_tx_n[3]}] ;# MGTYTXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 #set_property -dict {LOC AK38} [get_ports bullseye_mgt_refclk_0_p] ;# MGTREFCLK0P_126 from J87 P19 #set_property -dict {LOC AK39} [get_ports bullseye_mgt_refclk_0_n] ;# MGTREFCLK0N_126 from J87 P20 #set_property -dict {LOC AH38} [get_ports bullseye_mgt_refclk_1_p] ;# MGTREFCLK1P_126 from U32 SI570 via U104 SI53340 @@ -155,22 +155,22 @@ set_input_delay 0 [get_ports {phy_int_n}] #create_clock -period 6.4 -name bullseye_mgt_refclk [get_ports bullseye_mgt_refclk_1_p] # QSFP28 Interface -set_property -dict {LOC AG45} [get_ports qsfp_rx1_p] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AG46} [get_ports qsfp_rx1_n] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AK42} [get_ports qsfp_tx1_p] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AK43} [get_ports qsfp_tx1_n] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AF43} [get_ports qsfp_rx2_p] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AF44} [get_ports qsfp_rx2_n] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AJ40} [get_ports qsfp_tx2_p] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AJ41} [get_ports qsfp_tx2_n] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AE45} [get_ports qsfp_rx3_p] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AE46} [get_ports qsfp_rx3_n] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AG40} [get_ports qsfp_tx3_p] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AG41} [get_ports qsfp_tx3_n] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AD43} [get_ports qsfp_rx4_p] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AD44} [get_ports qsfp_rx4_n] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AE40} [get_ports qsfp_tx4_p] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AE41} [get_ports qsfp_tx4_n] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AG45} [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AG46} [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AK42} [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AK43} [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AF43} [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AF44} [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AJ40} [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AJ41} [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AE45} [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AE46} [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AG40} [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AG41} [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AD43} [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AD44} [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AE40} [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AE41} [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 set_property -dict {LOC AF38} [get_ports qsfp_mgt_refclk_0_p] ;# MGTREFCLK0P_127 from U32 SI570 via U102 SI53340 set_property -dict {LOC AF39} [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_127 from U32 SI570 via U102 SI53340 #set_property -dict {LOC AD38} [get_ports qsfp_mgt_refclk_1_p] ;# MGTREFCLK1P_127 from U57 CKOUT2 SI5328 @@ -192,46 +192,46 @@ set_false_path -from [get_ports {qsfp_modprsl qsfp_intl}] set_input_delay 0 [get_ports {qsfp_modprsl qsfp_intl}] # CFP2 GTY -#set_property -dict {LOC J45 } [get_ports cfp2_rx0_p] ;# MGTYRXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC J46 } [get_ports cfp2_rx0_n] ;# MGTYRXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC F42 } [get_ports cfp2_tx0_p] ;# MGTYTXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC F43 } [get_ports cfp2_tx0_n] ;# MGTYTXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC N45 } [get_ports cfp2_rx1_p] ;# MGTYRXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC N46 } [get_ports cfp2_rx1_n] ;# MGTYRXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC K42 } [get_ports cfp2_tx1_p] ;# MGTYTXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC K43 } [get_ports cfp2_tx1_n] ;# MGTYTXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC R45 } [get_ports cfp2_rx2_p] ;# MGTYRXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC R46 } [get_ports cfp2_rx2_n] ;# MGTYRXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC M42 } [get_ports cfp2_tx2_p] ;# MGTYTXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC M43 } [get_ports cfp2_tx2_n] ;# MGTYTXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC L45 } [get_ports cfp2_rx3_p] ;# MGTYRXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC L46 } [get_ports cfp2_rx3_n] ;# MGTYRXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC H42 } [get_ports cfp2_tx3_p] ;# MGTYTXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC H43 } [get_ports cfp2_tx3_n] ;# MGTYTXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC Y43 } [get_ports cfp2_rx4_p] ;# MGTYRXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC Y44 } [get_ports cfp2_rx4_n] ;# MGTYRXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC U40 } [get_ports cfp2_tx4_p] ;# MGTYTXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC U41 } [get_ports cfp2_tx4_n] ;# MGTYTXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC U45 } [get_ports cfp2_rx5_p] ;# MGTYRXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC U46 } [get_ports cfp2_rx5_n] ;# MGTYRXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC P42 } [get_ports cfp2_tx5_p] ;# MGTYTXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC P43 } [get_ports cfp2_tx5_n] ;# MGTYTXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC W45 } [get_ports cfp2_rx6_p] ;# MGTYRXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC W46 } [get_ports cfp2_rx6_n] ;# MGTYRXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC T42 } [get_ports cfp2_tx6_p] ;# MGTYTXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC T43 } [get_ports cfp2_tx6_n] ;# MGTYTXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC AA45} [get_ports cfp2_rx7_p] ;# MGTYRXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AA46} [get_ports cfp2_rx7_n] ;# MGTYRXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC W40 } [get_ports cfp2_tx7_p] ;# MGTYTXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC W41 } [get_ports cfp2_tx7_n] ;# MGTYTXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AB43} [get_ports cfp2_rx8_p] ;# MGTYRXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AB44} [get_ports cfp2_rx8_n] ;# MGTYRXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AA40} [get_ports cfp2_tx8_p] ;# MGTYTXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AA41} [get_ports cfp2_tx8_n] ;# MGTYTXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AC45} [get_ports cfp2_rx9_p] ;# MGTYRXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AC46} [get_ports cfp2_rx9_n] ;# MGTYRXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AC40} [get_ports cfp2_tx9_p] ;# MGTYTXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AC41} [get_ports cfp2_tx9_n] ;# MGTYTXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC J45 } [get_ports {cfp2_rx_p[0]}] ;# MGTYRXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC J46 } [get_ports {cfp2_rx_n[0]}] ;# MGTYRXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC F42 } [get_ports {cfp2_tx_p[0]}] ;# MGTYTXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC F43 } [get_ports {cfp2_tx_n[0]}] ;# MGTYTXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC N45 } [get_ports {cfp2_rx_p[1]}] ;# MGTYRXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC N46 } [get_ports {cfp2_rx_n[1]}] ;# MGTYRXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC K42 } [get_ports {cfp2_tx_p[1]}] ;# MGTYTXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC K43 } [get_ports {cfp2_tx_n[1]}] ;# MGTYTXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC R45 } [get_ports {cfp2_rx_p[2]}] ;# MGTYRXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC R46 } [get_ports {cfp2_rx_n[2]}] ;# MGTYRXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC M42 } [get_ports {cfp2_tx_p[2]}] ;# MGTYTXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC M43 } [get_ports {cfp2_tx_n[2]}] ;# MGTYTXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC L45 } [get_ports {cfp2_rx_p[3]}] ;# MGTYRXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC L46 } [get_ports {cfp2_rx_n[3]}] ;# MGTYRXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC H42 } [get_ports {cfp2_tx_p[3]}] ;# MGTYTXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC H43 } [get_ports {cfp2_tx_n[3]}] ;# MGTYTXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC Y43 } [get_ports {cfp2_rx_p[4]}] ;# MGTYRXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC Y44 } [get_ports {cfp2_rx_n[4]}] ;# MGTYRXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC U40 } [get_ports {cfp2_tx_p[4]}] ;# MGTYTXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC U41 } [get_ports {cfp2_tx_n[4]}] ;# MGTYTXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC U45 } [get_ports {cfp2_rx_p[5]}] ;# MGTYRXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC U46 } [get_ports {cfp2_rx_n[5]}] ;# MGTYRXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC P42 } [get_ports {cfp2_tx_p[5]}] ;# MGTYTXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC P43 } [get_ports {cfp2_tx_n[5]}] ;# MGTYTXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC W45 } [get_ports {cfp2_rx_p[6]}] ;# MGTYRXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC W46 } [get_ports {cfp2_rx_n[6]}] ;# MGTYRXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC T42 } [get_ports {cfp2_tx_p[6]}] ;# MGTYTXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC T43 } [get_ports {cfp2_tx_n[6]}] ;# MGTYTXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC AA45} [get_ports {cfp2_rx_p[7]}] ;# MGTYRXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AA46} [get_ports {cfp2_rx_n[7]}] ;# MGTYRXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC W40 } [get_ports {cfp2_tx_p[7]}] ;# MGTYTXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC W41 } [get_ports {cfp2_tx_n[7]}] ;# MGTYTXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AB43} [get_ports {cfp2_rx_p[8]}] ;# MGTYRXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AB44} [get_ports {cfp2_rx_n[8]}] ;# MGTYRXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AA40} [get_ports {cfp2_tx_p[8]}] ;# MGTYTXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AA41} [get_ports {cfp2_tx_n[8]}] ;# MGTYTXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AC45} [get_ports {cfp2_rx_p[9]}] ;# MGTYRXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AC46} [get_ports {cfp2_rx_n[9]}] ;# MGTYRXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AC40} [get_ports {cfp2_tx_p[9]}] ;# MGTYTXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AC41} [get_ports {cfp2_tx_n[9]}] ;# MGTYTXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 #set_property -dict {LOC V38 } [get_ports cfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_129 from U32 SI570 via U104 SI53340 #set_property -dict {LOC V39 } [get_ports cfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_129 from U32 SI570 via U104 SI53340 #set_property -dict {LOC T38 } [get_ports cfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_129 from U57 CKOUT1 SI5328 diff --git a/example/VCU108/fpga_10g/fpga/Makefile b/example/VCU108/fpga_10g/fpga/Makefile index 1b2a4f0b3..849450bfb 100644 --- a/example/VCU108/fpga_10g/fpga/Makefile +++ b/example/VCU108/fpga_10g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = VirtexUltrascale SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v diff --git a/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/VCU108/fpga_10g/rtl/fpga.v b/example/VCU108/fpga_10g/rtl/fpga.v index 1d41c176c..7c8223ed2 100644 --- a/example/VCU108/fpga_10g/rtl/fpga.v +++ b/example/VCU108/fpga_10g/rtl/fpga.v @@ -60,22 +60,10 @@ module fpga ( /* * Ethernet: QSFP28 */ - input wire qsfp_rx1_p, - input wire qsfp_rx1_n, - input wire qsfp_rx2_p, - input wire qsfp_rx2_n, - input wire qsfp_rx3_p, - input wire qsfp_rx3_n, - input wire qsfp_rx4_p, - input wire qsfp_rx4_n, - output wire qsfp_tx1_p, - output wire qsfp_tx1_n, - output wire qsfp_tx2_p, - output wire qsfp_tx2_n, - output wire qsfp_tx3_p, - output wire qsfp_tx3_n, - output wire qsfp_tx4_p, - output wire qsfp_tx4_n, + input wire [3:0] qsfp_rx_p, + input wire [3:0] qsfp_rx_n, + output wire [3:0] qsfp_tx_p, + output wire [3:0] qsfp_tx_n, input wire qsfp_mgt_refclk_0_p, input wire qsfp_mgt_refclk_0_n, // input wire qsfp_mgt_refclk_1_p, @@ -321,196 +309,99 @@ IBUFDS_GTE3 ibufds_gte3_qsfp_mgt_refclk_0_inst ( .ODIV2 () ); -wire qsfp_qpll0lock; -wire qsfp_qpll0outclk; -wire qsfp_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp_mgt_refclk_0), - .xcvr_qpll0lock_out(qsfp_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp_tx_p), + .xcvr_txn(qsfp_tx_n), + .xcvr_rxp(qsfp_rx_p), + .xcvr_rxn(qsfp_rx_n), - // Serial data - .xcvr_txp(qsfp_tx1_p), - .xcvr_txn(qsfp_tx1_n), - .xcvr_rxp(qsfp_rx1_p), - .xcvr_rxn(qsfp_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_tx_clk_1_int), + .phy_1_tx_rst(qsfp_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp_txd_1_int), + .phy_1_xgmii_txc(qsfp_txc_1_int), + .phy_1_rx_clk(qsfp_rx_clk_1_int), + .phy_1_rx_rst(qsfp_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp_rxd_1_int), + .phy_1_xgmii_rxc(qsfp_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp_tx_clk_1_int), - .phy_tx_rst(qsfp_tx_rst_1_int), - .phy_xgmii_txd(qsfp_txd_1_int), - .phy_xgmii_txc(qsfp_txc_1_int), - .phy_rx_clk(qsfp_rx_clk_1_int), - .phy_rx_rst(qsfp_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_rxd_1_int), - .phy_xgmii_rxc(qsfp_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp_tx_clk_2_int), + .phy_2_tx_rst(qsfp_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp_txd_2_int), + .phy_2_xgmii_txc(qsfp_txc_2_int), + .phy_2_rx_clk(qsfp_rx_clk_2_int), + .phy_2_rx_rst(qsfp_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp_rxd_2_int), + .phy_2_xgmii_rxc(qsfp_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp_tx_clk_3_int), + .phy_3_tx_rst(qsfp_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp_txd_3_int), + .phy_3_xgmii_txc(qsfp_txc_3_int), + .phy_3_rx_clk(qsfp_rx_clk_3_int), + .phy_3_rx_rst(qsfp_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp_rxd_3_int), + .phy_3_xgmii_rxc(qsfp_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_tx2_p), - .xcvr_txn(qsfp_tx2_n), - .xcvr_rxp(qsfp_rx2_p), - .xcvr_rxn(qsfp_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp_tx_clk_2_int), - .phy_tx_rst(qsfp_tx_rst_2_int), - .phy_xgmii_txd(qsfp_txd_2_int), - .phy_xgmii_txc(qsfp_txc_2_int), - .phy_rx_clk(qsfp_rx_clk_2_int), - .phy_rx_rst(qsfp_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_rxd_2_int), - .phy_xgmii_rxc(qsfp_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_tx3_p), - .xcvr_txn(qsfp_tx3_n), - .xcvr_rxp(qsfp_rx3_p), - .xcvr_rxn(qsfp_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp_tx_clk_3_int), - .phy_tx_rst(qsfp_tx_rst_3_int), - .phy_xgmii_txd(qsfp_txd_3_int), - .phy_xgmii_txc(qsfp_txc_3_int), - .phy_rx_clk(qsfp_rx_clk_3_int), - .phy_rx_rst(qsfp_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_rxd_3_int), - .phy_xgmii_rxc(qsfp_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_tx4_p), - .xcvr_txn(qsfp_tx4_n), - .xcvr_rxp(qsfp_rx4_p), - .xcvr_rxn(qsfp_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp_tx_clk_4_int), - .phy_tx_rst(qsfp_tx_rst_4_int), - .phy_xgmii_txd(qsfp_txd_4_int), - .phy_xgmii_txc(qsfp_txc_4_int), - .phy_rx_clk(qsfp_rx_clk_4_int), - .phy_rx_rst(qsfp_rx_rst_4_int), - .phy_xgmii_rxd(qsfp_rxd_4_int), - .phy_xgmii_rxc(qsfp_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp_tx_clk_4_int), + .phy_4_tx_rst(qsfp_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp_txd_4_int), + .phy_4_xgmii_txc(qsfp_txc_4_int), + .phy_4_rx_clk(qsfp_rx_clk_4_int), + .phy_4_rx_rst(qsfp_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp_rxd_4_int), + .phy_4_xgmii_rxc(qsfp_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // SGMII interface to PHY diff --git a/example/VCU108/fpga_1g/fpga.xdc b/example/VCU108/fpga_1g/fpga.xdc index 275e1869c..4a56a8294 100644 --- a/example/VCU108/fpga_1g/fpga.xdc +++ b/example/VCU108/fpga_1g/fpga.xdc @@ -130,22 +130,22 @@ set_input_delay 0 [get_ports {phy_int_n}] #set_input_delay 0 [get_ports {phy_mdio}] # Bullseye GTY -#set_property -dict {LOC AR45} [get_ports bullseye_rx0_p] ;# MGTYRXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AR46} [get_ports bullseye_rx0_n] ;# MGTYRXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AT42} [get_ports bullseye_tx0_p] ;# MGTYTXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AT43} [get_ports bullseye_tx0_n] ;# MGTYTXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AN45} [get_ports bullseye_rx1_p] ;# MGTYRXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AN46} [get_ports bullseye_rx1_n] ;# MGTYRXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AP42} [get_ports bullseye_tx1_p] ;# MGTYTXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AP43} [get_ports bullseye_tx1_n] ;# MGTYTXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AL45} [get_ports bullseye_rx2_p] ;# MGTYRXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AL46} [get_ports bullseye_rx2_n] ;# MGTYRXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AM42} [get_ports bullseye_tx2_p] ;# MGTYTXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AM43} [get_ports bullseye_tx2_n] ;# MGTYTXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AJ45} [get_ports bullseye_rx3_p] ;# MGTYRXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AJ46} [get_ports bullseye_rx3_n] ;# MGTYRXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AL40} [get_ports bullseye_tx3_p] ;# MGTYTXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 -#set_property -dict {LOC AL41} [get_ports bullseye_tx3_n] ;# MGTYTXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AR45} [get_ports {bullseye_rx_p[0]}] ;# MGTYRXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AR46} [get_ports {bullseye_rx_n[0]}] ;# MGTYRXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AT42} [get_ports {bullseye_tx_p[0]}] ;# MGTYTXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AT43} [get_ports {bullseye_tx_n[0]}] ;# MGTYTXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AN45} [get_ports {bullseye_rx_p[1]}] ;# MGTYRXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AN46} [get_ports {bullseye_rx_n[1]}] ;# MGTYRXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AP42} [get_ports {bullseye_tx_p[1]}] ;# MGTYTXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AP43} [get_ports {bullseye_tx_n[1]}] ;# MGTYTXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AL45} [get_ports {bullseye_rx_p[2]}] ;# MGTYRXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AL46} [get_ports {bullseye_rx_n[2]}] ;# MGTYRXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AM42} [get_ports {bullseye_tx_p[2]}] ;# MGTYTXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AM43} [get_ports {bullseye_tx_n[2]}] ;# MGTYTXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AJ45} [get_ports {bullseye_rx_p[3]}] ;# MGTYRXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AJ46} [get_ports {bullseye_rx_n[3]}] ;# MGTYRXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AL40} [get_ports {bullseye_tx_p[3]}] ;# MGTYTXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC AL41} [get_ports {bullseye_tx_n[3]}] ;# MGTYTXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2 #set_property -dict {LOC AK38} [get_ports bullseye_mgt_refclk_0_p] ;# MGTREFCLK0P_126 from J87 P19 #set_property -dict {LOC AK39} [get_ports bullseye_mgt_refclk_0_n] ;# MGTREFCLK0N_126 from J87 P20 #set_property -dict {LOC AH38} [get_ports bullseye_mgt_refclk_1_p] ;# MGTREFCLK1P_126 from U32 SI570 via U104 SI53340 @@ -155,22 +155,22 @@ set_input_delay 0 [get_ports {phy_int_n}] #create_clock -period 6.4 -name bullseye_mgt_refclk [get_ports bullseye_mgt_refclk_1_p] # QSFP28 Interface -#set_property -dict {LOC AG45} [get_ports qsfp_rx1_p] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AG46} [get_ports qsfp_rx1_n] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AK42} [get_ports qsfp_tx1_p] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AK43} [get_ports qsfp_tx1_n] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AF43} [get_ports qsfp_rx2_p] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AF44} [get_ports qsfp_rx2_n] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AJ40} [get_ports qsfp_tx2_p] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AJ41} [get_ports qsfp_tx2_n] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AE45} [get_ports qsfp_rx3_p] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AE46} [get_ports qsfp_rx3_n] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AG40} [get_ports qsfp_tx3_p] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AG41} [get_ports qsfp_tx3_n] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AD43} [get_ports qsfp_rx4_p] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AD44} [get_ports qsfp_rx4_n] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AE40} [get_ports qsfp_tx4_p] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AE41} [get_ports qsfp_tx4_n] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AG45} [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AG46} [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AK42} [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AK43} [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AF43} [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AF44} [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AJ40} [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AJ41} [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AE45} [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AE46} [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AG40} [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AG41} [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AD43} [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AD44} [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AE40} [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AE41} [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 #set_property -dict {LOC AF38} [get_ports qsfp_mgt_refclk_0_p] ;# MGTREFCLK0P_127 from U32 SI570 via U102 SI53340 #set_property -dict {LOC AF39} [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_127 from U32 SI570 via U102 SI53340 #set_property -dict {LOC AD38} [get_ports qsfp_mgt_refclk_1_p] ;# MGTREFCLK1P_127 from U57 CKOUT2 SI5328 @@ -192,46 +192,46 @@ set_input_delay 0 [get_ports {phy_int_n}] #set_input_delay 0 [get_ports {qsfp_modprsl qsfp_intl}] # CFP2 GTY -#set_property -dict {LOC J45 } [get_ports cfp2_rx0_p] ;# MGTYRXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC J46 } [get_ports cfp2_rx0_n] ;# MGTYRXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC F42 } [get_ports cfp2_tx0_p] ;# MGTYTXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC F43 } [get_ports cfp2_tx0_n] ;# MGTYTXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC N45 } [get_ports cfp2_rx1_p] ;# MGTYRXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC N46 } [get_ports cfp2_rx1_n] ;# MGTYRXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC K42 } [get_ports cfp2_tx1_p] ;# MGTYTXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC K43 } [get_ports cfp2_tx1_n] ;# MGTYTXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC R45 } [get_ports cfp2_rx2_p] ;# MGTYRXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC R46 } [get_ports cfp2_rx2_n] ;# MGTYRXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC M42 } [get_ports cfp2_tx2_p] ;# MGTYTXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC M43 } [get_ports cfp2_tx2_n] ;# MGTYTXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC L45 } [get_ports cfp2_rx3_p] ;# MGTYRXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC L46 } [get_ports cfp2_rx3_n] ;# MGTYRXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC H42 } [get_ports cfp2_tx3_p] ;# MGTYTXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC H43 } [get_ports cfp2_tx3_n] ;# MGTYTXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 -#set_property -dict {LOC Y43 } [get_ports cfp2_rx4_p] ;# MGTYRXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC Y44 } [get_ports cfp2_rx4_n] ;# MGTYRXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC U40 } [get_ports cfp2_tx4_p] ;# MGTYTXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC U41 } [get_ports cfp2_tx4_n] ;# MGTYTXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC U45 } [get_ports cfp2_rx5_p] ;# MGTYRXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC U46 } [get_ports cfp2_rx5_n] ;# MGTYRXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC P42 } [get_ports cfp2_tx5_p] ;# MGTYTXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC P43 } [get_ports cfp2_tx5_n] ;# MGTYTXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC W45 } [get_ports cfp2_rx6_p] ;# MGTYRXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC W46 } [get_ports cfp2_rx6_n] ;# MGTYRXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC T42 } [get_ports cfp2_tx6_p] ;# MGTYTXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC T43 } [get_ports cfp2_tx6_n] ;# MGTYTXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 -#set_property -dict {LOC AA45} [get_ports cfp2_rx7_p] ;# MGTYRXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AA46} [get_ports cfp2_rx7_n] ;# MGTYRXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC W40 } [get_ports cfp2_tx7_p] ;# MGTYTXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC W41 } [get_ports cfp2_tx7_n] ;# MGTYTXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AB43} [get_ports cfp2_rx8_p] ;# MGTYRXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AB44} [get_ports cfp2_rx8_n] ;# MGTYRXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AA40} [get_ports cfp2_tx8_p] ;# MGTYTXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AA41} [get_ports cfp2_tx8_n] ;# MGTYTXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AC45} [get_ports cfp2_rx9_p] ;# MGTYRXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AC46} [get_ports cfp2_rx9_n] ;# MGTYRXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AC40} [get_ports cfp2_tx9_p] ;# MGTYTXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 -#set_property -dict {LOC AC41} [get_ports cfp2_tx9_n] ;# MGTYTXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC J45 } [get_ports {cfp2_rx_p[0]}] ;# MGTYRXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC J46 } [get_ports {cfp2_rx_n[0]}] ;# MGTYRXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC F42 } [get_ports {cfp2_tx_p[0]}] ;# MGTYTXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC F43 } [get_ports {cfp2_tx_n[0]}] ;# MGTYTXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC N45 } [get_ports {cfp2_rx_p[1]}] ;# MGTYRXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC N46 } [get_ports {cfp2_rx_n[1]}] ;# MGTYRXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC K42 } [get_ports {cfp2_tx_p[1]}] ;# MGTYTXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC K43 } [get_ports {cfp2_tx_n[1]}] ;# MGTYTXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC R45 } [get_ports {cfp2_rx_p[2]}] ;# MGTYRXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC R46 } [get_ports {cfp2_rx_n[2]}] ;# MGTYRXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC M42 } [get_ports {cfp2_tx_p[2]}] ;# MGTYTXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC M43 } [get_ports {cfp2_tx_n[2]}] ;# MGTYTXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC L45 } [get_ports {cfp2_rx_p[3]}] ;# MGTYRXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC L46 } [get_ports {cfp2_rx_n[3]}] ;# MGTYRXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC H42 } [get_ports {cfp2_tx_p[3]}] ;# MGTYTXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC H43 } [get_ports {cfp2_tx_n[3]}] ;# MGTYTXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6 +#set_property -dict {LOC Y43 } [get_ports {cfp2_rx_p[4]}] ;# MGTYRXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC Y44 } [get_ports {cfp2_rx_n[4]}] ;# MGTYRXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC U40 } [get_ports {cfp2_tx_p[4]}] ;# MGTYTXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC U41 } [get_ports {cfp2_tx_n[4]}] ;# MGTYTXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC U45 } [get_ports {cfp2_rx_p[5]}] ;# MGTYRXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC U46 } [get_ports {cfp2_rx_n[5]}] ;# MGTYRXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC P42 } [get_ports {cfp2_tx_p[5]}] ;# MGTYTXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC P43 } [get_ports {cfp2_tx_n[5]}] ;# MGTYTXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC W45 } [get_ports {cfp2_rx_p[6]}] ;# MGTYRXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC W46 } [get_ports {cfp2_rx_n[6]}] ;# MGTYRXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC T42 } [get_ports {cfp2_tx_p[6]}] ;# MGTYTXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC T43 } [get_ports {cfp2_tx_n[6]}] ;# MGTYTXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5 +#set_property -dict {LOC AA45} [get_ports {cfp2_rx_p[7]}] ;# MGTYRXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AA46} [get_ports {cfp2_rx_n[7]}] ;# MGTYRXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC W40 } [get_ports {cfp2_tx_p[7]}] ;# MGTYTXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC W41 } [get_ports {cfp2_tx_n[7]}] ;# MGTYTXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AB43} [get_ports {cfp2_rx_p[8]}] ;# MGTYRXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AB44} [get_ports {cfp2_rx_n[8]}] ;# MGTYRXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AA40} [get_ports {cfp2_tx_p[8]}] ;# MGTYTXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AA41} [get_ports {cfp2_tx_n[8]}] ;# MGTYTXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AC45} [get_ports {cfp2_rx_p[9]}] ;# MGTYRXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AC46} [get_ports {cfp2_rx_n[9]}] ;# MGTYRXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AC40} [get_ports {cfp2_tx_p[9]}] ;# MGTYTXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 +#set_property -dict {LOC AC41} [get_ports {cfp2_tx_n[9]}] ;# MGTYTXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4 #set_property -dict {LOC V38 } [get_ports cfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_129 from U32 SI570 via U104 SI53340 #set_property -dict {LOC V39 } [get_ports cfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_129 from U32 SI570 via U104 SI53340 #set_property -dict {LOC T38 } [get_ports cfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_129 from U57 CKOUT1 SI5328 From d5df47d8b0f9a052b3e264df9052c9f64634ad5f Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 12:42:04 -0700 Subject: [PATCH 16/19] Use quad wrappers in ZCU106 example design Signed-off-by: Alex Forencich --- example/ZCU106/fpga/fpga/Makefile | 1 + .../fpga/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++++++++ .../ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/ZCU106/fpga/rtl/fpga.v | 137 +++--- 4 files changed, 460 insertions(+), 91 deletions(-) create mode 100644 example/ZCU106/fpga/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/ZCU106/fpga/fpga/Makefile b/example/ZCU106/fpga/fpga/Makefile index 5c14941f5..02de90cdb 100644 --- a/example/ZCU106/fpga/fpga/Makefile +++ b/example/ZCU106/fpga/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = zynquplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v diff --git a/example/ZCU106/fpga/rtl/eth_xcvr_phy_quad_wrapper.v b/example/ZCU106/fpga/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/ZCU106/fpga/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v b/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v index 84908a1f2..d986312cd 100644 --- a/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gthtxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/ZCU106/fpga/rtl/fpga.v b/example/ZCU106/fpga/rtl/fpga.v index 4023fed12..df8cdb80a 100644 --- a/example/ZCU106/fpga/rtl/fpga.v +++ b/example/ZCU106/fpga/rtl/fpga.v @@ -257,102 +257,67 @@ IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_0_inst ( .ODIV2 () ); -wire sfp_qpll0lock; -wire sfp_qpll0outclk; -wire sfp_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .COUNT(2) ) -sfp0_phy_inst ( +sfp_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(sfp_mgt_refclk_0), - .xcvr_qpll0lock_out(sfp_qpll0lock), - .xcvr_qpll0outclk_out(sfp_qpll0outclk), - .xcvr_qpll0outrefclk_out(sfp_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp({sfp1_tx_p, sfp0_tx_p}), + .xcvr_txn({sfp1_tx_n, sfp0_tx_n}), + .xcvr_rxp({sfp1_rx_p, sfp0_rx_p}), + .xcvr_rxn({sfp1_rx_n, sfp0_rx_n}), - // Serial data - .xcvr_txp(sfp0_tx_p), - .xcvr_txn(sfp0_tx_n), - .xcvr_rxp(sfp0_rx_p), - .xcvr_rxn(sfp0_rx_n), + /* + * PHY connections + */ + .phy_1_tx_clk(sfp0_tx_clk_int), + .phy_1_tx_rst(sfp0_tx_rst_int), + .phy_1_xgmii_txd(sfp0_txd_int), + .phy_1_xgmii_txc(sfp0_txc_int), + .phy_1_rx_clk(sfp0_rx_clk_int), + .phy_1_rx_rst(sfp0_rx_rst_int), + .phy_1_xgmii_rxd(sfp0_rxd_int), + .phy_1_xgmii_rxc(sfp0_rxc_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(sfp0_rx_block_lock), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(sfp0_tx_clk_int), - .phy_tx_rst(sfp0_tx_rst_int), - .phy_xgmii_txd(sfp0_txd_int), - .phy_xgmii_txc(sfp0_txc_int), - .phy_rx_clk(sfp0_rx_clk_int), - .phy_rx_rst(sfp0_rx_rst_int), - .phy_xgmii_rxd(sfp0_rxd_int), - .phy_xgmii_rxc(sfp0_rxc_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(sfp0_rx_block_lock), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -sfp1_phy_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(sfp_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(sfp_qpll0outclk), - .xcvr_qpll0refclk_in(sfp_qpll0outrefclk), - - // Serial data - .xcvr_txp(sfp1_tx_p), - .xcvr_txn(sfp1_tx_n), - .xcvr_rxp(sfp1_rx_p), - .xcvr_rxn(sfp1_rx_n), - - // PHY connections - .phy_tx_clk(sfp1_tx_clk_int), - .phy_tx_rst(sfp1_tx_rst_int), - .phy_xgmii_txd(sfp1_txd_int), - .phy_xgmii_txc(sfp1_txc_int), - .phy_rx_clk(sfp1_rx_clk_int), - .phy_rx_rst(sfp1_rx_rst_int), - .phy_xgmii_rxd(sfp1_rxd_int), - .phy_xgmii_rxc(sfp1_rxc_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(sfp1_rx_block_lock), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_2_tx_clk(sfp1_tx_clk_int), + .phy_2_tx_rst(sfp1_tx_rst_int), + .phy_2_xgmii_txd(sfp1_txd_int), + .phy_2_xgmii_txc(sfp1_txc_int), + .phy_2_rx_clk(sfp1_rx_clk_int), + .phy_2_rx_rst(sfp1_rx_rst_int), + .phy_2_xgmii_rxd(sfp1_rxd_int), + .phy_2_xgmii_rxc(sfp1_rxc_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(sfp1_rx_block_lock), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0) ); fpga_core From dc58b2447f8f8382d189cc08c8414637839e9da3 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 12:42:39 -0700 Subject: [PATCH 17/19] Use quad wrappers in ZCU102 example design Signed-off-by: Alex Forencich --- example/ZCU102/fpga/fpga/Makefile | 1 + .../fpga/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++++++++ .../ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/ZCU102/fpga/rtl/fpga.v | 261 ++++-------- 4 files changed, 491 insertions(+), 184 deletions(-) create mode 100644 example/ZCU102/fpga/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/ZCU102/fpga/fpga/Makefile b/example/ZCU102/fpga/fpga/Makefile index b13a5c7f6..f575f2dfd 100644 --- a/example/ZCU102/fpga/fpga/Makefile +++ b/example/ZCU102/fpga/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = zynquplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v diff --git a/example/ZCU102/fpga/rtl/eth_xcvr_phy_quad_wrapper.v b/example/ZCU102/fpga/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/ZCU102/fpga/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v b/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v index 84908a1f2..d986312cd 100644 --- a/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gthtxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/ZCU102/fpga/rtl/fpga.v b/example/ZCU102/fpga/rtl/fpga.v index ddf539a18..25b9416cc 100644 --- a/example/ZCU102/fpga/rtl/fpga.v +++ b/example/ZCU102/fpga/rtl/fpga.v @@ -296,196 +296,99 @@ IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_0_inst ( .ODIV2 () ); -wire sfp_qpll0lock; -wire sfp_qpll0outclk; -wire sfp_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -sfp0_phy_inst ( +eth_xcvr_phy_quad_wrapper +sfp_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(sfp_mgt_refclk_0), - .xcvr_qpll0lock_out(sfp_qpll0lock), - .xcvr_qpll0outclk_out(sfp_qpll0outclk), - .xcvr_qpll0outrefclk_out(sfp_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp({sfp3_tx_p, sfp2_tx_p, sfp1_tx_p, sfp0_tx_p}), + .xcvr_txn({sfp3_tx_n, sfp2_tx_n, sfp1_tx_n, sfp0_tx_n}), + .xcvr_rxp({sfp3_rx_p, sfp2_rx_p, sfp1_rx_p, sfp0_rx_p}), + .xcvr_rxn({sfp3_rx_n, sfp2_rx_n, sfp1_rx_n, sfp0_rx_n}), - // Serial data - .xcvr_txp(sfp0_tx_p), - .xcvr_txn(sfp0_tx_n), - .xcvr_rxp(sfp0_rx_p), - .xcvr_rxn(sfp0_rx_n), + /* + * PHY connections + */ + .phy_1_tx_clk(sfp0_tx_clk_int), + .phy_1_tx_rst(sfp0_tx_rst_int), + .phy_1_xgmii_txd(sfp0_txd_int), + .phy_1_xgmii_txc(sfp0_txc_int), + .phy_1_rx_clk(sfp0_rx_clk_int), + .phy_1_rx_rst(sfp0_rx_rst_int), + .phy_1_xgmii_rxd(sfp0_rxd_int), + .phy_1_xgmii_rxc(sfp0_rxc_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(sfp0_rx_block_lock), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(sfp0_tx_clk_int), - .phy_tx_rst(sfp0_tx_rst_int), - .phy_xgmii_txd(sfp0_txd_int), - .phy_xgmii_txc(sfp0_txc_int), - .phy_rx_clk(sfp0_rx_clk_int), - .phy_rx_rst(sfp0_rx_rst_int), - .phy_xgmii_rxd(sfp0_rxd_int), - .phy_xgmii_rxc(sfp0_rxc_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(sfp0_rx_block_lock), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(sfp1_tx_clk_int), + .phy_2_tx_rst(sfp1_tx_rst_int), + .phy_2_xgmii_txd(sfp1_txd_int), + .phy_2_xgmii_txc(sfp1_txc_int), + .phy_2_rx_clk(sfp1_rx_clk_int), + .phy_2_rx_rst(sfp1_rx_rst_int), + .phy_2_xgmii_rxd(sfp1_rxd_int), + .phy_2_xgmii_rxc(sfp1_rxc_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(sfp1_rx_block_lock), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -sfp1_phy_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(sfp2_tx_clk_int), + .phy_3_tx_rst(sfp2_tx_rst_int), + .phy_3_xgmii_txd(sfp2_txd_int), + .phy_3_xgmii_txc(sfp2_txc_int), + .phy_3_rx_clk(sfp2_rx_clk_int), + .phy_3_rx_rst(sfp2_rx_rst_int), + .phy_3_xgmii_rxd(sfp2_rxd_int), + .phy_3_xgmii_rxc(sfp2_rxc_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(sfp2_rx_block_lock), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(sfp_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(sfp_qpll0outclk), - .xcvr_qpll0refclk_in(sfp_qpll0outrefclk), - - // Serial data - .xcvr_txp(sfp1_tx_p), - .xcvr_txn(sfp1_tx_n), - .xcvr_rxp(sfp1_rx_p), - .xcvr_rxn(sfp1_rx_n), - - // PHY connections - .phy_tx_clk(sfp1_tx_clk_int), - .phy_tx_rst(sfp1_tx_rst_int), - .phy_xgmii_txd(sfp1_txd_int), - .phy_xgmii_txc(sfp1_txc_int), - .phy_rx_clk(sfp1_rx_clk_int), - .phy_rx_rst(sfp1_rx_rst_int), - .phy_xgmii_rxd(sfp1_rxd_int), - .phy_xgmii_rxc(sfp1_rxc_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(sfp1_rx_block_lock), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -sfp2_phy_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(sfp_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(sfp_qpll0outclk), - .xcvr_qpll0refclk_in(sfp_qpll0outrefclk), - - // Serial data - .xcvr_txp(sfp2_tx_p), - .xcvr_txn(sfp2_tx_n), - .xcvr_rxp(sfp2_rx_p), - .xcvr_rxn(sfp2_rx_n), - - // PHY connections - .phy_tx_clk(sfp2_tx_clk_int), - .phy_tx_rst(sfp2_tx_rst_int), - .phy_xgmii_txd(sfp2_txd_int), - .phy_xgmii_txc(sfp2_txc_int), - .phy_rx_clk(sfp2_rx_clk_int), - .phy_rx_rst(sfp2_rx_rst_int), - .phy_xgmii_rxd(sfp2_rxd_int), - .phy_xgmii_rxc(sfp2_rxc_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(sfp2_rx_block_lock), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -sfp3_phy_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(sfp_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(sfp_qpll0outclk), - .xcvr_qpll0refclk_in(sfp_qpll0outrefclk), - - // Serial data - .xcvr_txp(sfp3_tx_p), - .xcvr_txn(sfp3_tx_n), - .xcvr_rxp(sfp3_rx_p), - .xcvr_rxn(sfp3_rx_n), - - // PHY connections - .phy_tx_clk(sfp3_tx_clk_int), - .phy_tx_rst(sfp3_tx_rst_int), - .phy_xgmii_txd(sfp3_txd_int), - .phy_xgmii_txc(sfp3_txc_int), - .phy_rx_clk(sfp3_rx_clk_int), - .phy_rx_rst(sfp3_rx_rst_int), - .phy_xgmii_rxd(sfp3_rxd_int), - .phy_xgmii_rxc(sfp3_rxc_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(sfp3_rx_block_lock), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(sfp3_tx_clk_int), + .phy_4_tx_rst(sfp3_tx_rst_int), + .phy_4_xgmii_txd(sfp3_txd_int), + .phy_4_xgmii_txc(sfp3_txc_int), + .phy_4_rx_clk(sfp3_rx_clk_int), + .phy_4_rx_rst(sfp3_rx_rst_int), + .phy_4_xgmii_rxd(sfp3_rxd_int), + .phy_4_xgmii_rxc(sfp3_rxc_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(sfp3_rx_block_lock), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); fpga_core From f9eda00d685ddb6aed08980f78fe2e267732ea18 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 12:43:29 -0700 Subject: [PATCH 18/19] Use quad wrappers in ExaNIC X10 example design Signed-off-by: Alex Forencich --- example/ExaNIC_X10/fpga/fpga/Makefile | 1 + .../fpga/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++++++++ .../fpga/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/ExaNIC_X10/fpga/rtl/fpga.v | 137 +++--- 4 files changed, 460 insertions(+), 91 deletions(-) create mode 100644 example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/ExaNIC_X10/fpga/fpga/Makefile b/example/ExaNIC_X10/fpga/fpga/Makefile index ea7982fd1..18c85aeb3 100644 --- a/example/ExaNIC_X10/fpga/fpga/Makefile +++ b/example/ExaNIC_X10/fpga/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = kintexu SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v diff --git a/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_quad_wrapper.v b/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v b/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v index d5109f8d6..e5fa51c40 100644 --- a/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gthtxp_out(xcvr_txp), @@ -178,6 +179,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -242,6 +245,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -298,6 +305,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/ExaNIC_X10/fpga/rtl/fpga.v b/example/ExaNIC_X10/fpga/rtl/fpga.v index 447a2d555..20e03c0ed 100644 --- a/example/ExaNIC_X10/fpga/rtl/fpga.v +++ b/example/ExaNIC_X10/fpga/rtl/fpga.v @@ -213,102 +213,67 @@ IBUFDS_GTE3 ibufds_gte3_sfp_mgt_refclk_inst ( .ODIV2 () ); -wire sfp_qpll0lock; -wire sfp_qpll0outclk; -wire sfp_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .COUNT(2) ) -sfp_1_phy_inst ( +sfp_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(sfp_mgt_refclk), - .xcvr_qpll0lock_out(sfp_qpll0lock), - .xcvr_qpll0outclk_out(sfp_qpll0outclk), - .xcvr_qpll0outrefclk_out(sfp_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp({sfp_2_tx_p, sfp_1_tx_p}), + .xcvr_txn({sfp_2_tx_n, sfp_1_tx_n}), + .xcvr_rxp({sfp_2_rx_p, sfp_1_rx_p}), + .xcvr_rxn({sfp_2_rx_n, sfp_1_rx_n}), - // Serial data - .xcvr_txp(sfp_1_tx_p), - .xcvr_txn(sfp_1_tx_n), - .xcvr_rxp(sfp_1_rx_p), - .xcvr_rxn(sfp_1_rx_n), + /* + * PHY connections + */ + .phy_1_tx_clk(sfp_1_tx_clk_int), + .phy_1_tx_rst(sfp_1_tx_rst_int), + .phy_1_xgmii_txd(sfp_1_txd_int), + .phy_1_xgmii_txc(sfp_1_txc_int), + .phy_1_rx_clk(sfp_1_rx_clk_int), + .phy_1_rx_rst(sfp_1_rx_rst_int), + .phy_1_xgmii_rxd(sfp_1_rxd_int), + .phy_1_xgmii_rxc(sfp_1_rxc_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(sfp_1_rx_block_lock), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(sfp_1_tx_clk_int), - .phy_tx_rst(sfp_1_tx_rst_int), - .phy_xgmii_txd(sfp_1_txd_int), - .phy_xgmii_txc(sfp_1_txc_int), - .phy_rx_clk(sfp_1_rx_clk_int), - .phy_rx_rst(sfp_1_rx_rst_int), - .phy_xgmii_rxd(sfp_1_rxd_int), - .phy_xgmii_rxc(sfp_1_rxc_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(sfp_1_rx_block_lock), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -sfp_2_phy_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(sfp_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(sfp_qpll0outclk), - .xcvr_qpll0refclk_in(sfp_qpll0outrefclk), - - // Serial data - .xcvr_txp(sfp_2_tx_p), - .xcvr_txn(sfp_2_tx_n), - .xcvr_rxp(sfp_2_rx_p), - .xcvr_rxn(sfp_2_rx_n), - - // PHY connections - .phy_tx_clk(sfp_2_tx_clk_int), - .phy_tx_rst(sfp_2_tx_rst_int), - .phy_xgmii_txd(sfp_2_txd_int), - .phy_xgmii_txc(sfp_2_txc_int), - .phy_rx_clk(sfp_2_rx_clk_int), - .phy_rx_rst(sfp_2_rx_rst_int), - .phy_xgmii_rxd(sfp_2_rxd_int), - .phy_xgmii_rxc(sfp_2_rxc_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(sfp_2_rx_block_lock), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_2_tx_clk(sfp_2_tx_clk_int), + .phy_2_tx_rst(sfp_2_tx_rst_int), + .phy_2_xgmii_txd(sfp_2_txd_int), + .phy_2_xgmii_txc(sfp_2_txc_int), + .phy_2_rx_clk(sfp_2_rx_clk_int), + .phy_2_rx_rst(sfp_2_rx_rst_int), + .phy_2_xgmii_rxd(sfp_2_rxd_int), + .phy_2_xgmii_rxc(sfp_2_rxc_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(sfp_2_rx_block_lock), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0) ); assign sfp_1_led[0] = sfp_1_rx_block_lock; From b316c6764e083823f95f52b3f324fccee4f12fa0 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 12:44:50 -0700 Subject: [PATCH 19/19] Use quad wrappers in ExaNIC X25 example design Signed-off-by: Alex Forencich --- example/ExaNIC_X25/fpga_25g/fpga/Makefile | 1 + example/ExaNIC_X25/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++++++++ .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/ExaNIC_X25/fpga_25g/rtl/fpga.v | 142 +++---- 5 files changed, 465 insertions(+), 92 deletions(-) create mode 100644 example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/ExaNIC_X25/fpga_25g/fpga/Makefile b/example/ExaNIC_X25/fpga_25g/fpga/Makefile index ccd409e06..d78f205a0 100644 --- a/example/ExaNIC_X25/fpga_25g/fpga/Makefile +++ b/example/ExaNIC_X25/fpga_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = kintexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v diff --git a/example/ExaNIC_X25/fpga_25g/fpga_10g/Makefile b/example/ExaNIC_X25/fpga_25g/fpga_10g/Makefile index ccd409e06..d78f205a0 100644 --- a/example/ExaNIC_X25/fpga_25g/fpga_10g/Makefile +++ b/example/ExaNIC_X25/fpga_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = kintexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v diff --git a/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index 6baa85e78..efefa8bd0 100644 --- a/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -178,6 +179,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -242,6 +245,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -298,6 +305,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/ExaNIC_X25/fpga_25g/rtl/fpga.v b/example/ExaNIC_X25/fpga_25g/rtl/fpga.v index ae3d0ec6b..f5accd5e9 100644 --- a/example/ExaNIC_X25/fpga_25g/rtl/fpga.v +++ b/example/ExaNIC_X25/fpga_25g/rtl/fpga.v @@ -213,102 +213,70 @@ BUFG_GT bufg_gt_refclk_inst ( .O (sfp_mgt_refclk_bufg) ); -wire sfp_qpll0lock; -wire sfp_qpll0outclk; -wire sfp_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .COUNT(2), + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -sfp_1_phy_inst ( +sfp_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common - .xcvr_gtpowergood_out(sfp_gtpowergood), - - // PLL out - .xcvr_gtrefclk00_in(sfp_mgt_refclk), - .xcvr_qpll0lock_out(sfp_qpll0lock), - .xcvr_qpll0outclk_out(sfp_qpll0outclk), - .xcvr_qpll0outrefclk_out(sfp_qpll0outrefclk), - - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), - - // Serial data - .xcvr_txp(sfp_1_tx_p), - .xcvr_txn(sfp_1_tx_n), - .xcvr_rxp(sfp_1_rx_p), - .xcvr_rxn(sfp_1_rx_n), - - // PHY connections - .phy_tx_clk(sfp_1_tx_clk_int), - .phy_tx_rst(sfp_1_tx_rst_int), - .phy_xgmii_txd(sfp_1_txd_int), - .phy_xgmii_txc(sfp_1_txc_int), - .phy_rx_clk(sfp_1_rx_clk_int), - .phy_rx_rst(sfp_1_rx_rst_int), - .phy_xgmii_rxd(sfp_1_rxd_int), - .phy_xgmii_rxc(sfp_1_rxc_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(sfp_1_rx_block_lock), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -sfp_2_phy_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), + /* + * PLL + */ + .xcvr_gtrefclk00_in(sfp_mgt_refclk), - // PLL in - .xcvr_qpll0lock_in(sfp_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(sfp_qpll0outclk), - .xcvr_qpll0refclk_in(sfp_qpll0outrefclk), + /* + * Serial data + */ + .xcvr_txp({sfp_2_tx_p, sfp_1_tx_p}), + .xcvr_txn({sfp_2_tx_n, sfp_1_tx_n}), + .xcvr_rxp({sfp_2_rx_p, sfp_1_rx_p}), + .xcvr_rxn({sfp_2_rx_n, sfp_1_rx_n}), - // Serial data - .xcvr_txp(sfp_2_tx_p), - .xcvr_txn(sfp_2_tx_n), - .xcvr_rxp(sfp_2_rx_p), - .xcvr_rxn(sfp_2_rx_n), + /* + * PHY connections + */ + .phy_1_tx_clk(sfp_1_tx_clk_int), + .phy_1_tx_rst(sfp_1_tx_rst_int), + .phy_1_xgmii_txd(sfp_1_txd_int), + .phy_1_xgmii_txc(sfp_1_txc_int), + .phy_1_rx_clk(sfp_1_rx_clk_int), + .phy_1_rx_rst(sfp_1_rx_rst_int), + .phy_1_xgmii_rxd(sfp_1_rxd_int), + .phy_1_xgmii_rxc(sfp_1_rxc_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(sfp_1_rx_block_lock), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(sfp_2_tx_clk_int), - .phy_tx_rst(sfp_2_tx_rst_int), - .phy_xgmii_txd(sfp_2_txd_int), - .phy_xgmii_txc(sfp_2_txc_int), - .phy_rx_clk(sfp_2_rx_clk_int), - .phy_rx_rst(sfp_2_rx_rst_int), - .phy_xgmii_rxd(sfp_2_rxd_int), - .phy_xgmii_rxc(sfp_2_rxc_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(sfp_2_rx_block_lock), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_2_tx_clk(sfp_2_tx_clk_int), + .phy_2_tx_rst(sfp_2_tx_rst_int), + .phy_2_xgmii_txd(sfp_2_txd_int), + .phy_2_xgmii_txc(sfp_2_txc_int), + .phy_2_rx_clk(sfp_2_rx_clk_int), + .phy_2_rx_rst(sfp_2_rx_rst_int), + .phy_2_xgmii_rxd(sfp_2_rxd_int), + .phy_2_xgmii_rxc(sfp_2_rxc_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(sfp_2_rx_block_lock), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0) ); assign sfp_1_led[0] = sfp_1_rx_block_lock;