Rename port and interface modules

README.md

@@ -94,11 +94,11 @@ from different sources to enable sharing a single desc_fetch module instance.
 
 Event mux module.  Enables multiple event sources to feed the same event queue.
 
-#### interface module
+#### mqnic_interface module
 
 Interface module.  Contains the event queues, interface queues, and ports.
 
-#### port module
+#### mqnic_port module
 
 Port module.  Contains the transmit and receive datapath components, including
 transmit and receive engines and checksum and hash offloading.
@@ -174,8 +174,8 @@ packets.
     desc_op_mux.v            : Descriptor operation mux
     event_mux.v              : Event mux
     event_queue.v            : Event queue
-    interface.v              : Interface
-    port.v                   : Port
+    mqnic_interface.v        : Interface
+    mqnic_port.v             : Port
     queue_manager.v          : Queue manager
     rx_checksum.v            : Receive checksum offload
     rx_engine.v              : Receive engine

fpga/common/rtl/mqnic_interface.v

@@ -38,7 +38,7 @@ either expressed or implied, of The Regents of the University of California.
 /*
  * NIC Interface
  */
-module interface #
+module mqnic_interface #
 (
     // Number of ports
     parameter PORTS = 1,
@@ -2019,7 +2019,7 @@ generate
 
         assign port_cpl_req_sel[n*2+1 +: 1] = 1'b0;
 
-        port #(
+        mqnic_port #(
             .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
             .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
             .DMA_TAG_WIDTH(DMA_TAG_WIDTH_INT),

fpga/common/rtl/mqnic_port.v

@@ -38,7 +38,7 @@ either expressed or implied, of The Regents of the University of California.
 /*
  * NIC Port
  */
-module port #
+module mqnic_port #
 (
     // DMA address width
     parameter DMA_ADDR_WIDTH = 64,

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v

@@ -2067,7 +2067,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/test_fpga_core.py

@@ -51,8 +51,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v

@@ -2279,7 +2279,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v

@@ -2279,7 +2279,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/AU200/fpga_100g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v

@@ -1982,7 +1982,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/AU200/fpga_100g/tb/test_fpga_core.py

@@ -51,8 +51,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/AU200/fpga_10g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v

@@ -2145,7 +2145,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/AU200/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/AU250/fpga_100g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v

@@ -1982,7 +1982,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/AU250/fpga_100g/tb/test_fpga_core.py

@@ -51,8 +51,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/AU250/fpga_10g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v

@@ -2145,7 +2145,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/AU250/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/AU280/fpga_100g/fpga/Makefile

@@ -8,8 +8,8 @@ FPGA_ARCH = virtexuplus
 SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v

@@ -1893,7 +1893,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py

@@ -51,8 +51,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/AU280/fpga_10g/fpga/Makefile

@@ -8,8 +8,8 @@ FPGA_ARCH = virtexuplus
 SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v

@@ -2056,7 +2056,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/AU50/fpga_100g/fpga/Makefile

@@ -8,8 +8,8 @@ FPGA_ARCH = virtexuplus
 SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v

@@ -1853,7 +1853,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/AU50/fpga_100g/tb/test_fpga_core.py

@@ -51,8 +51,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/AU50/fpga_10g/fpga/Makefile

@@ -8,8 +8,8 @@ FPGA_ARCH = virtexuplus
 SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v

@@ -1939,7 +1939,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v

@@ -2030,7 +2030,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v

@@ -2030,7 +2030,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile

@@ -11,8 +11,8 @@ SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
 SYN_FILES += rtl/i2c_master.v
 SYN_FILES += rtl/si5324_i2c_init.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v

@@ -1958,7 +1958,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/NetFPGA_SUME/fpga/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/VCU108/fpga_10g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v

@@ -2139,7 +2139,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/VCU118/fpga_100g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v

@@ -2077,7 +2077,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/VCU118/fpga_100g/tb/test_fpga_core.py

@@ -51,8 +51,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/VCU118/fpga_10g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v

@@ -2286,7 +2286,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v

@@ -1982,7 +1982,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/VCU1525/fpga_100g/tb/test_fpga_core.py

@@ -51,8 +51,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v

@@ -2145,7 +2145,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/VCU1525/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v

@@ -1810,7 +1810,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/ZCU106/fpga_pcie/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/led_sreg_driver.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v

@@ -2130,7 +2130,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/fb2CG/fpga_100g/tb/test_fpga_core.py

@@ -51,8 +51,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/led_sreg_driver.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v

@@ -2342,7 +2342,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/fb2CG/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/led_sreg_driver.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v

@@ -2342,7 +2342,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic/fb2CG/fpga_25g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v

@@ -2268,7 +2268,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v

@@ -2030,7 +2030,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic_tdma/VCU108/fpga_10g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v

@@ -2139,7 +2139,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")

fpga/mqnic_tdma/VCU118/fpga_10g/fpga/Makefile

@@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
-SYN_FILES += rtl/common/interface.v
-SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_port.v
 SYN_FILES += rtl/common/cpl_write.v
 SYN_FILES += rtl/common/cpl_op_mux.v
 SYN_FILES += rtl/common/desc_fetch.v

fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v

@@ -2286,7 +2286,7 @@ generate
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
         wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
 
-        interface #(
+        mqnic_interface #(
             .PORTS(PORTS_PER_IF),
             .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),

fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py

@@ -52,8 +52,8 @@ testbench = 'test_%s' % module
 srcs = []
 
 srcs.append("../rtl/%s.v" % module)
-srcs.append("../rtl/common/interface.v")
-srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/mqnic_interface.v")
+srcs.append("../rtl/common/mqnic_port.v")
 srcs.append("../rtl/common/cpl_write.v")
 srcs.append("../rtl/common/cpl_op_mux.v")
 srcs.append("../rtl/common/desc_fetch.v")