From 91edbbf3dc42dd2987cf6e6db1f98aa031d51b6c Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 26 Nov 2020 15:05:59 -0800 Subject: [PATCH] Rename port and interface modules --- README.md | 8 ++++---- fpga/common/rtl/{interface.v => mqnic_interface.v} | 4 ++-- fpga/common/rtl/{port.v => mqnic_port.v} | 2 +- fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile | 4 ++-- fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v | 2 +- fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile | 4 ++-- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 2 +- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/AU200/fpga_100g/fpga/Makefile | 4 ++-- fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v | 2 +- fpga/mqnic/AU200/fpga_100g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/AU200/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/AU200/fpga_10g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/AU250/fpga_100g/fpga/Makefile | 4 ++-- fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v | 2 +- fpga/mqnic/AU250/fpga_100g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/AU250/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/AU250/fpga_10g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/AU280/fpga_100g/fpga/Makefile | 4 ++-- fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v | 2 +- fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/AU280/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/AU50/fpga_100g/fpga/Makefile | 4 ++-- fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v | 2 +- fpga/mqnic/AU50/fpga_100g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/AU50/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile | 4 ++-- fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v | 2 +- fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile | 4 ++-- fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v | 2 +- fpga/mqnic/NetFPGA_SUME/fpga/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/VCU108/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/VCU118/fpga_100g/fpga/Makefile | 4 ++-- fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v | 2 +- fpga/mqnic/VCU118/fpga_100g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/VCU118/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile | 4 ++-- fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v | 2 +- fpga/mqnic/VCU1525/fpga_100g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/VCU1525/fpga_10g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile | 4 ++-- fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v | 2 +- fpga/mqnic/ZCU106/fpga_pcie/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile | 4 ++-- fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v | 2 +- fpga/mqnic/fb2CG/fpga_100g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/fb2CG/fpga_10g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile | 4 ++-- fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v | 2 +- fpga/mqnic/fb2CG/fpga_25g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v | 2 +- .../mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile | 4 ++-- fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v | 2 +- fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py | 4 ++-- fpga/mqnic_tdma/VCU108/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py | 4 ++-- fpga/mqnic_tdma/VCU118/fpga_10g/fpga/Makefile | 4 ++-- fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py | 4 ++-- 84 files changed, 142 insertions(+), 142 deletions(-) rename fpga/common/rtl/{interface.v => mqnic_interface.v} (99%) rename fpga/common/rtl/{port.v => mqnic_port.v} (99%) diff --git a/README.md b/README.md index 190659e54..9a27b8d05 100644 --- a/README.md +++ b/README.md @@ -94,11 +94,11 @@ from different sources to enable sharing a single desc_fetch module instance. Event mux module. Enables multiple event sources to feed the same event queue. -#### interface module +#### mqnic_interface module Interface module. Contains the event queues, interface queues, and ports. -#### port module +#### mqnic_port module Port module. Contains the transmit and receive datapath components, including transmit and receive engines and checksum and hash offloading. @@ -174,8 +174,8 @@ packets. desc_op_mux.v : Descriptor operation mux event_mux.v : Event mux event_queue.v : Event queue - interface.v : Interface - port.v : Port + mqnic_interface.v : Interface + mqnic_port.v : Port queue_manager.v : Queue manager rx_checksum.v : Receive checksum offload rx_engine.v : Receive engine diff --git a/fpga/common/rtl/interface.v b/fpga/common/rtl/mqnic_interface.v similarity index 99% rename from fpga/common/rtl/interface.v rename to fpga/common/rtl/mqnic_interface.v index 07accfc27..f0374dea5 100644 --- a/fpga/common/rtl/interface.v +++ b/fpga/common/rtl/mqnic_interface.v @@ -38,7 +38,7 @@ either expressed or implied, of The Regents of the University of California. /* * NIC Interface */ -module interface # +module mqnic_interface # ( // Number of ports parameter PORTS = 1, @@ -2019,7 +2019,7 @@ generate assign port_cpl_req_sel[n*2+1 +: 1] = 1'b0; - port #( + mqnic_port #( .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), .DMA_LEN_WIDTH(DMA_LEN_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH_INT), diff --git a/fpga/common/rtl/port.v b/fpga/common/rtl/mqnic_port.v similarity index 99% rename from fpga/common/rtl/port.v rename to fpga/common/rtl/mqnic_port.v index 6c0e2d607..ed1291c9c 100644 --- a/fpga/common/rtl/port.v +++ b/fpga/common/rtl/mqnic_port.v @@ -38,7 +38,7 @@ either expressed or implied, of The Regents of the University of California. /* * NIC Port */ -module port # +module mqnic_port # ( // DMA address width parameter DMA_ADDR_WIDTH = 64, diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile index 597f801e6..c8a62962c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index 1a7f01cc4..560877423 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -2067,7 +2067,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/test_fpga_core.py index 581aa8387..a9cb5ef45 100755 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/test_fpga_core.py @@ -51,8 +51,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile index 472613f9d..5811e21e7 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index 0973c36a3..5cd19dce2 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -2279,7 +2279,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py index a48510175..09e3c125b 100755 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index 472613f9d..5811e21e7 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 4490d966c..fcd07598b 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -2279,7 +2279,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py index b246376b6..57552f3e1 100755 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile index 400fffcd4..deca937d7 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index 7f27fa91d..0fec521d9 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -1982,7 +1982,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/AU200/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/test_fpga_core.py index 1b9bd3ba8..bd17d57c1 100755 --- a/fpga/mqnic/AU200/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_100g/tb/test_fpga_core.py @@ -51,8 +51,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/AU200/fpga_10g/fpga/Makefile b/fpga/mqnic/AU200/fpga_10g/fpga/Makefile index d0167cfd1..ef629cc8d 100644 --- a/fpga/mqnic/AU200/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_10g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v index 48843b084..9b42ab740 100644 --- a/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v @@ -2145,7 +2145,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/AU200/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/AU200/fpga_10g/tb/test_fpga_core.py index 2603cd519..3afc41b44 100755 --- a/fpga/mqnic/AU200/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile index 7b1e6cf38..cac8bc3d4 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v index 68efe88c8..24a2fcae8 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v @@ -1982,7 +1982,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/AU250/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/test_fpga_core.py index 1b9bd3ba8..bd17d57c1 100755 --- a/fpga/mqnic/AU250/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_100g/tb/test_fpga_core.py @@ -51,8 +51,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/AU250/fpga_10g/fpga/Makefile b/fpga/mqnic/AU250/fpga_10g/fpga/Makefile index c54a5fb05..2039920b1 100644 --- a/fpga/mqnic/AU250/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_10g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v index 893d356a8..aabd14450 100644 --- a/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v @@ -2145,7 +2145,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/AU250/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/AU250/fpga_10g/tb/test_fpga_core.py index 2603cd519..3afc41b44 100755 --- a/fpga/mqnic/AU250/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile index dacc9b66e..838265415 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile @@ -8,8 +8,8 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v index 3aba512fc..20dd58325 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -1893,7 +1893,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py index 52c82d338..0ac81f46b 100755 --- a/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py @@ -51,8 +51,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/AU280/fpga_10g/fpga/Makefile b/fpga/mqnic/AU280/fpga_10g/fpga/Makefile index 39f476914..f55ae8e4c 100644 --- a/fpga/mqnic/AU280/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_10g/fpga/Makefile @@ -8,8 +8,8 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v index 9807eb72f..225368b36 100644 --- a/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v @@ -2056,7 +2056,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py index e37b707e4..ee5246ac4 100755 --- a/fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile index e9f6dfc7b..9a7a8e1c0 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile @@ -8,8 +8,8 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v index e29978700..b5f5ba582 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v @@ -1853,7 +1853,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/AU50/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/test_fpga_core.py index 16c1d8b69..13f75cc6c 100755 --- a/fpga/mqnic/AU50/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/test_fpga_core.py @@ -51,8 +51,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/AU50/fpga_10g/fpga/Makefile b/fpga/mqnic/AU50/fpga_10g/fpga/Makefile index 7733195f3..f746d83f2 100644 --- a/fpga/mqnic/AU50/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_10g/fpga/Makefile @@ -8,8 +8,8 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v index 04d035096..9e06e8d25 100644 --- a/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v @@ -1939,7 +1939,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py index ac50af292..3f10cbb33 100755 --- a/fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile b/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile index 22d2ff09d..7e0338865 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile +++ b/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v index 021b13e58..4154d67bf 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -2030,7 +2030,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py b/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py index 72ee9df8c..bec15b957 100755 --- a/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py +++ b/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile index 9f874db8a..8c596a275 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v index d9762efea..f8dd285a5 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v @@ -2030,7 +2030,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py index aa203b679..1bc04d11c 100755 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile index 36370df64..d104a509a 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile @@ -11,8 +11,8 @@ SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/i2c_master.v SYN_FILES += rtl/si5324_i2c_init.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v index 0b708b6d3..cf6183dcb 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -1958,7 +1958,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/test_fpga_core.py index 43f531d43..da64963fe 100755 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/test_fpga_core.py +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile index a20540a90..1a3832686 100644 --- a/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v index 68c1d6c4d..2a90b2be9 100644 --- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v @@ -2139,7 +2139,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py index 1dcb186d0..85f65ed49 100755 --- a/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile index 0a311b136..936e91574 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v index c83e685d3..ee5808652 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v @@ -2077,7 +2077,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/test_fpga_core.py index edc43a2f9..315fb85dc 100755 --- a/fpga/mqnic/VCU118/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/test_fpga_core.py @@ -51,8 +51,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/VCU118/fpga_10g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_10g/fpga/Makefile index a8c53468d..01df00a48 100644 --- a/fpga/mqnic/VCU118/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_10g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v index 67555e22f..e7aa59275 100644 --- a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v @@ -2286,7 +2286,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py index b844e8d3a..5dfd0466e 100755 --- a/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile index 033f3ae51..6349045c7 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v index 90942c506..e7abc4118 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v @@ -1982,7 +1982,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/test_fpga_core.py index 1b9bd3ba8..bd17d57c1 100755 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/test_fpga_core.py @@ -51,8 +51,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile index 8dde75f69..b3b765ab5 100644 --- a/fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v index 9e10b9dbe..8ed626ee4 100644 --- a/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v @@ -2145,7 +2145,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/VCU1525/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_10g/tb/test_fpga_core.py index 2603cd519..3afc41b44 100755 --- a/fpga/mqnic/VCU1525/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile index 10a256851..cf2a76a43 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v index 47a0423b2..9b42033e9 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v @@ -1810,7 +1810,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/test_fpga_core.py index f34d35d7f..0d020c52b 100755 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile index ccaf7a15a..f097f7c90 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/led_sreg_driver.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index c082a5ca1..1e22907cf 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -2130,7 +2130,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/test_fpga_core.py index 71d935861..7b5dcaffb 100755 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/test_fpga_core.py @@ -51,8 +51,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile index 9eca58a1f..d3d69136d 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/led_sreg_driver.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v index c6b8dce30..8c6c3359d 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v @@ -2342,7 +2342,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/fb2CG/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_10g/tb/test_fpga_core.py index 2145d3e26..deaee3974 100755 --- a/fpga/mqnic/fb2CG/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile index 9eca58a1f..d3d69136d 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/led_sreg_driver.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index 98dd97bf0..6b4c4dea4 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -2342,7 +2342,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/test_fpga_core.py index ecde5e1ef..3ebddf276 100755 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile index eda9c0a8d..c674833bb 100644 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index eecf05a59..c432055be 100644 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -2268,7 +2268,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py index 0ac36813c..19258a6d6 100755 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile b/fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile index 0a9f7b3f8..b9e1c8455 100644 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v index b581532c7..e364eccaf 100644 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -2030,7 +2030,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py b/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py index 6a9ccc562..735a9540f 100755 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/fpga/Makefile b/fpga/mqnic_tdma/VCU108/fpga_10g/fpga/Makefile index e2913a832..76e2e36a0 100644 --- a/fpga/mqnic_tdma/VCU108/fpga_10g/fpga/Makefile +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v index 110e90bed..7a1f8d4b3 100644 --- a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v @@ -2139,7 +2139,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py index 6946a2012..e1a58a5a9 100755 --- a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v") diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/fpga/Makefile b/fpga/mqnic_tdma/VCU118/fpga_10g/fpga/Makefile index 758d339d3..8f7754ef2 100644 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/fpga/Makefile +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/fpga/Makefile @@ -9,8 +9,8 @@ SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/common/interface.v -SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_port.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v index 610fe5bf7..ef961d2d1 100644 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v @@ -2286,7 +2286,7 @@ generate wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; - interface #( + mqnic_interface #( .PORTS(PORTS_PER_IF), .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py index 32167f4ca..a0e061d1f 100755 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py @@ -52,8 +52,8 @@ testbench = 'test_%s' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/common/interface.v") -srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/mqnic_interface.v") +srcs.append("../rtl/common/mqnic_port.v") srcs.append("../rtl/common/cpl_write.v") srcs.append("../rtl/common/cpl_op_mux.v") srcs.append("../rtl/common/desc_fetch.v")