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fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
eb990643f2
commit
941288e926
@ -253,6 +253,174 @@ Parameters
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Receive scratchpad RAM size per interface, default ``32768``.
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.. object:: DDR_CH
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Number of DDR memory interfaces, default ``1``.
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.. object:: DDR_ENABLE
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Enable DDR memory interfaces, default ``0``.
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.. object:: DDR_GROUP_SIZE
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DDR channel group size, default ``1``. All channels in each group share the same address space.
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.. object:: AXI_DDR_DATA_WIDTH
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DDR memory interface AXI data width, default ``256``.
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.. object:: AXI_DDR_ADDR_WIDTH
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DDR memory interface AXI address width, default ``32``.
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.. object:: AXI_DDR_STRB_WIDTH
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DDR memory interface AXI strobe width, default ``(AXI_DDR_DATA_WIDTH/8)``.
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.. object:: AXI_DDR_ID_WIDTH
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DDR memory interface AXI ID width, default ``8``.
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.. object:: AXI_DDR_AWUSER_ENABLE
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DDR memory interface AXI AWUSER signal enable, default ``0``.
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.. object:: AXI_DDR_AWUSER_WIDTH
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DDR memory interface AXI AWUSER signal width, default ``1``.
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.. object:: AXI_DDR_WUSER_ENABLE
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DDR memory interface AXI WUSER signal enable, default ``0``.
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.. object:: AXI_DDR_WUSER_WIDTH
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DDR memory interface AXI WUSER signal width, default ``1``.
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.. object:: AXI_DDR_BUSER_ENABLE
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DDR memory interface AXI BUSER signal enable, default ``0``.
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.. object:: AXI_DDR_BUSER_WIDTH
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DDR memory interface AXI BUSER signal width, default ``1``.
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.. object:: AXI_DDR_ARUSER_ENABLE
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DDR memory interface AXI ARUSER signal enable, default ``0``.
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.. object:: AXI_DDR_ARUSER_WIDTH
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DDR memory interface AXI ARUSER signal width, default ``1``.
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.. object:: AXI_DDR_RUSER_ENABLE
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DDR memory interface AXI RUSER signal enable, default ``0``.
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.. object:: AXI_DDR_RUSER_WIDTH
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DDR memory interface AXI RUSER signal width, default ``1``.
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.. object:: AXI_DDR_MAX_BURST_LEN
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DDR memory interface max AXI burst length, default ``256``.
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.. object:: AXI_DDR_NARROW_BURST
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DDR memory interface AXI narrow burst support, default ``0``.
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.. object:: AXI_DDR_FIXED_BURST
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DDR memory interface AXI fixed burst support, default ``0``.
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.. object:: AXI_DDR_WRAP_BURST
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DDR memory interface AXI wrap burst support, default ``0``.
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.. object:: HBM_CH
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Number of HBM memory interfaces, default ``1``.
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.. object:: HBM_ENABLE
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Enable HBM memory interfaces, default ``0``.
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.. object:: HBM_GROUP_SIZE
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HBM channel group size, default ``1``. All channels in each group share the same address space.
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.. object:: AXI_HBM_DATA_WIDTH
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HBM memory interface AXI data width, default ``256``.
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.. object:: AXI_HBM_AHBM_WIDTH
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HBM memory interface AXI address width, default ``32``.
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.. object:: AXI_HBM_STRB_WIDTH
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HBM memory interface AXI strobe width, default ``(AXI_HBM_DATA_WIDTH/8)``.
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.. object:: AXI_HBM_ID_WIDTH
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HBM memory interface AXI ID width, default ``8``.
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.. object:: AXI_HBM_AWUSER_ENABLE
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HBM memory interface AXI AWUSER signal enable, default ``0``.
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.. object:: AXI_HBM_AWUSER_WIDTH
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HBM memory interface AXI AWUSER signal width, default ``1``.
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.. object:: AXI_HBM_WUSER_ENABLE
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HBM memory interface AXI WUSER signal enable, default ``0``.
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.. object:: AXI_HBM_WUSER_WIDTH
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HBM memory interface AXI WUSER signal width, default ``1``.
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.. object:: AXI_HBM_BUSER_ENABLE
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HBM memory interface AXI BUSER signal enable, default ``0``.
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.. object:: AXI_HBM_BUSER_WIDTH
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HBM memory interface AXI BUSER signal width, default ``1``.
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.. object:: AXI_HBM_ARUSER_ENABLE
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HBM memory interface AXI ARUSER signal enable, default ``0``.
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.. object:: AXI_HBM_ARUSER_WIDTH
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HBM memory interface AXI ARUSER signal width, default ``1``.
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.. object:: AXI_HBM_RUSER_ENABLE
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HBM memory interface AXI RUSER signal enable, default ``0``.
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.. object:: AXI_HBM_RUSER_WIDTH
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HBM memory interface AXI RUSER signal width, default ``1``.
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.. object:: AXI_HBM_MAX_BURST_LEN
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HBM memory interface max AXI burst length, default ``256``.
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.. object:: AXI_HBM_NARROW_BURST
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HBM memory interface AXI narrow burst support, default ``0``.
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.. object:: AXI_HBM_FIXED_BURST
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HBM memory interface AXI fixed burst support, default ``0``.
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.. object:: AXI_HBM_WRAP_BURST
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HBM memory interface AXI wrap burst support, default ``0``.
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.. object:: APP_ID
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Application ID, default ``0``.
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@ -68,6 +68,50 @@ module mqnic_app_block #
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parameter MAX_TX_SIZE = 9214,
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parameter MAX_RX_SIZE = 9214,
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// RAM configuration
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parameter DDR_CH = 1,
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parameter DDR_ENABLE = 0,
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parameter DDR_GROUP_SIZE = 1,
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parameter AXI_DDR_DATA_WIDTH = 256,
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parameter AXI_DDR_ADDR_WIDTH = 32,
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parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
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parameter AXI_DDR_ID_WIDTH = 8,
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parameter AXI_DDR_AWUSER_ENABLE = 0,
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parameter AXI_DDR_AWUSER_WIDTH = 1,
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parameter AXI_DDR_WUSER_ENABLE = 0,
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parameter AXI_DDR_WUSER_WIDTH = 1,
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parameter AXI_DDR_BUSER_ENABLE = 0,
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parameter AXI_DDR_BUSER_WIDTH = 1,
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parameter AXI_DDR_ARUSER_ENABLE = 0,
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parameter AXI_DDR_ARUSER_WIDTH = 1,
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parameter AXI_DDR_RUSER_ENABLE = 0,
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parameter AXI_DDR_RUSER_WIDTH = 1,
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parameter AXI_DDR_MAX_BURST_LEN = 256,
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parameter AXI_DDR_NARROW_BURST = 0,
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parameter AXI_DDR_FIXED_BURST = 0,
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parameter AXI_DDR_WRAP_BURST = 0,
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parameter HBM_CH = 1,
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parameter HBM_ENABLE = 0,
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parameter HBM_GROUP_SIZE = 1,
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parameter AXI_HBM_DATA_WIDTH = 256,
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parameter AXI_HBM_ADDR_WIDTH = 32,
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parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
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parameter AXI_HBM_ID_WIDTH = 8,
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parameter AXI_HBM_AWUSER_ENABLE = 0,
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parameter AXI_HBM_AWUSER_WIDTH = 1,
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parameter AXI_HBM_WUSER_ENABLE = 0,
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parameter AXI_HBM_WUSER_WIDTH = 1,
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parameter AXI_HBM_BUSER_ENABLE = 0,
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parameter AXI_HBM_BUSER_WIDTH = 1,
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parameter AXI_HBM_ARUSER_ENABLE = 0,
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parameter AXI_HBM_ARUSER_WIDTH = 1,
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parameter AXI_HBM_RUSER_ENABLE = 0,
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parameter AXI_HBM_RUSER_WIDTH = 1,
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parameter AXI_HBM_MAX_BURST_LEN = 256,
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parameter AXI_HBM_NARROW_BURST = 0,
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parameter AXI_HBM_FIXED_BURST = 0,
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parameter AXI_HBM_WRAP_BURST = 0,
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// Application configuration
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parameter APP_ID = 32'h12348001,
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parameter APP_CTRL_ENABLE = 1,
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@ -447,6 +491,108 @@ module mqnic_app_block #
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output wire [IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0] m_axis_if_rx_tdest,
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output wire [IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] m_axis_if_rx_tuser,
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/*
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* DDR
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*/
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input wire [DDR_CH-1:0] ddr_clk,
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input wire [DDR_CH-1:0] ddr_rst,
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output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
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output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
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output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
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output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
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output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
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output wire [DDR_CH-1:0] m_axi_ddr_awlock,
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output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
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output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
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output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
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output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser,
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output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
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input wire [DDR_CH-1:0] m_axi_ddr_awready,
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output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
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output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
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output wire [DDR_CH-1:0] m_axi_ddr_wlast,
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output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser,
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output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
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input wire [DDR_CH-1:0] m_axi_ddr_wready,
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input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
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input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
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input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser,
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input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
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output wire [DDR_CH-1:0] m_axi_ddr_bready,
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output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
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output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
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output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
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output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
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output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
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output wire [DDR_CH-1:0] m_axi_ddr_arlock,
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output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
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output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
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output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
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output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser,
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output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
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input wire [DDR_CH-1:0] m_axi_ddr_arready,
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input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
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input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
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input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
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input wire [DDR_CH-1:0] m_axi_ddr_rlast,
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input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser,
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input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
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output wire [DDR_CH-1:0] m_axi_ddr_rready,
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input wire [DDR_CH-1:0] ddr_status,
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/*
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* HBM
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*/
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input wire [HBM_CH-1:0] hbm_clk,
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input wire [HBM_CH-1:0] hbm_rst,
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output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
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output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
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output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
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output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
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output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
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output wire [HBM_CH-1:0] m_axi_hbm_awlock,
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output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
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output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
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output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
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output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser,
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output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
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input wire [HBM_CH-1:0] m_axi_hbm_awready,
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output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
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output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
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output wire [HBM_CH-1:0] m_axi_hbm_wlast,
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output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser,
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output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
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input wire [HBM_CH-1:0] m_axi_hbm_wready,
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input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
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input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
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input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser,
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input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
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output wire [HBM_CH-1:0] m_axi_hbm_bready,
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output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
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output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
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output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
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output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
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output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
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output wire [HBM_CH-1:0] m_axi_hbm_arlock,
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output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
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output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
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output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
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output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser,
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output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
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input wire [HBM_CH-1:0] m_axi_hbm_arready,
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input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
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input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
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input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
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input wire [HBM_CH-1:0] m_axi_hbm_rlast,
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input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser,
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input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
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output wire [HBM_CH-1:0] m_axi_hbm_rready,
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input wire [HBM_CH-1:0] hbm_status,
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/*
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* Statistics increment output
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*/
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@ -500,6 +646,30 @@ assign m_axil_ctrl_arprot = 0;
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assign m_axil_ctrl_arvalid = 1'b0;
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assign m_axil_ctrl_rready = 1'b1;
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/*
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* DMA interface (control)
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*/
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assign m_axis_ctrl_dma_read_desc_dma_addr = 0;
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assign m_axis_ctrl_dma_read_desc_ram_sel = 0;
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assign m_axis_ctrl_dma_read_desc_ram_addr = 0;
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assign m_axis_ctrl_dma_read_desc_len = 0;
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assign m_axis_ctrl_dma_read_desc_tag = 0;
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assign m_axis_ctrl_dma_read_desc_valid = 1'b0;
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assign m_axis_ctrl_dma_write_desc_dma_addr = 0;
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assign m_axis_ctrl_dma_write_desc_ram_sel = 0;
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assign m_axis_ctrl_dma_write_desc_ram_addr = 0;
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assign m_axis_ctrl_dma_write_desc_imm = 0;
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assign m_axis_ctrl_dma_write_desc_imm_en = 0;
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assign m_axis_ctrl_dma_write_desc_len = 0;
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assign m_axis_ctrl_dma_write_desc_tag = 0;
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assign m_axis_ctrl_dma_write_desc_valid = 1'b0;
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assign ctrl_dma_ram_wr_cmd_ready = 1'b1;
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assign ctrl_dma_ram_wr_done = ctrl_dma_ram_wr_cmd_valid;
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assign ctrl_dma_ram_rd_cmd_ready = ctrl_dma_ram_rd_resp_ready;
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assign ctrl_dma_ram_rd_resp_data = 0;
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assign ctrl_dma_ram_rd_resp_valid = ctrl_dma_ram_rd_cmd_valid;
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/*
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* Ethernet (direct MAC interface - lowest latency raw traffic)
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*/
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@ -571,28 +741,70 @@ assign m_axis_if_rx_tdest = s_axis_if_rx_tdest;
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assign m_axis_if_rx_tuser = s_axis_if_rx_tuser;
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/*
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* DMA interface (control)
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* DDR
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*/
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assign m_axis_ctrl_dma_read_desc_dma_addr = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_ram_sel = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_ram_addr = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_len = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_tag = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_valid = 1'b0;
|
||||
assign m_axis_ctrl_dma_write_desc_dma_addr = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_ram_sel = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_ram_addr = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_imm = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_imm_en = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_len = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_tag = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_valid = 1'b0;
|
||||
assign m_axi_ddr_awid = 0;
|
||||
assign m_axi_ddr_awaddr = 0;
|
||||
assign m_axi_ddr_awlen = 0;
|
||||
assign m_axi_ddr_awsize = 0;
|
||||
assign m_axi_ddr_awburst = 0;
|
||||
assign m_axi_ddr_awlock = 0;
|
||||
assign m_axi_ddr_awcache = 0;
|
||||
assign m_axi_ddr_awprot = 0;
|
||||
assign m_axi_ddr_awqos = 0;
|
||||
assign m_axi_ddr_awuser = 0;
|
||||
assign m_axi_ddr_awvalid = 0;
|
||||
assign m_axi_ddr_wdata = 0;
|
||||
assign m_axi_ddr_wstrb = 0;
|
||||
assign m_axi_ddr_wlast = 0;
|
||||
assign m_axi_ddr_wuser = 0;
|
||||
assign m_axi_ddr_wvalid = 0;
|
||||
assign m_axi_ddr_bready = 0;
|
||||
assign m_axi_ddr_arid = 0;
|
||||
assign m_axi_ddr_araddr = 0;
|
||||
assign m_axi_ddr_arlen = 0;
|
||||
assign m_axi_ddr_arsize = 0;
|
||||
assign m_axi_ddr_arburst = 0;
|
||||
assign m_axi_ddr_arlock = 0;
|
||||
assign m_axi_ddr_arcache = 0;
|
||||
assign m_axi_ddr_arprot = 0;
|
||||
assign m_axi_ddr_arqos = 0;
|
||||
assign m_axi_ddr_aruser = 0;
|
||||
assign m_axi_ddr_arvalid = 0;
|
||||
assign m_axi_ddr_rready = 0;
|
||||
|
||||
assign ctrl_dma_ram_wr_cmd_ready = 1'b1;
|
||||
assign ctrl_dma_ram_wr_done = ctrl_dma_ram_wr_cmd_valid;
|
||||
assign ctrl_dma_ram_rd_cmd_ready = ctrl_dma_ram_rd_resp_ready;
|
||||
assign ctrl_dma_ram_rd_resp_data = 0;
|
||||
assign ctrl_dma_ram_rd_resp_valid = ctrl_dma_ram_rd_cmd_valid;
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
assign m_axi_hbm_awid = 0;
|
||||
assign m_axi_hbm_awaddr = 0;
|
||||
assign m_axi_hbm_awlen = 0;
|
||||
assign m_axi_hbm_awsize = 0;
|
||||
assign m_axi_hbm_awburst = 0;
|
||||
assign m_axi_hbm_awlock = 0;
|
||||
assign m_axi_hbm_awcache = 0;
|
||||
assign m_axi_hbm_awprot = 0;
|
||||
assign m_axi_hbm_awqos = 0;
|
||||
assign m_axi_hbm_awuser = 0;
|
||||
assign m_axi_hbm_awvalid = 0;
|
||||
assign m_axi_hbm_wdata = 0;
|
||||
assign m_axi_hbm_wstrb = 0;
|
||||
assign m_axi_hbm_wlast = 0;
|
||||
assign m_axi_hbm_wuser = 0;
|
||||
assign m_axi_hbm_wvalid = 0;
|
||||
assign m_axi_hbm_bready = 0;
|
||||
assign m_axi_hbm_arid = 0;
|
||||
assign m_axi_hbm_araddr = 0;
|
||||
assign m_axi_hbm_arlen = 0;
|
||||
assign m_axi_hbm_arsize = 0;
|
||||
assign m_axi_hbm_arburst = 0;
|
||||
assign m_axi_hbm_arlock = 0;
|
||||
assign m_axi_hbm_arcache = 0;
|
||||
assign m_axi_hbm_arprot = 0;
|
||||
assign m_axi_hbm_arqos = 0;
|
||||
assign m_axi_hbm_aruser = 0;
|
||||
assign m_axi_hbm_arvalid = 0;
|
||||
assign m_axi_hbm_rready = 0;
|
||||
|
||||
/*
|
||||
* Statistics increment output
|
||||
|
||||
@ -68,6 +68,50 @@ module mqnic_app_block #
|
||||
parameter MAX_TX_SIZE = 9214,
|
||||
parameter MAX_RX_SIZE = 9214,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 1,
|
||||
parameter DDR_ENABLE = 0,
|
||||
parameter DDR_GROUP_SIZE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 256,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_AWUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_AWUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_WUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_WUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_BUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_BUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_ARUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_ARUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_RUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_RUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
parameter AXI_DDR_FIXED_BURST = 0,
|
||||
parameter AXI_DDR_WRAP_BURST = 0,
|
||||
parameter HBM_CH = 1,
|
||||
parameter HBM_ENABLE = 0,
|
||||
parameter HBM_GROUP_SIZE = 1,
|
||||
parameter AXI_HBM_DATA_WIDTH = 256,
|
||||
parameter AXI_HBM_ADDR_WIDTH = 32,
|
||||
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
|
||||
parameter AXI_HBM_ID_WIDTH = 8,
|
||||
parameter AXI_HBM_AWUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_AWUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_WUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_WUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_BUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_BUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_ARUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_ARUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_RUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_RUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_MAX_BURST_LEN = 256,
|
||||
parameter AXI_HBM_NARROW_BURST = 0,
|
||||
parameter AXI_HBM_FIXED_BURST = 0,
|
||||
parameter AXI_HBM_WRAP_BURST = 0,
|
||||
|
||||
// Application configuration
|
||||
parameter APP_ID = 32'h12340001,
|
||||
parameter APP_CTRL_ENABLE = 1,
|
||||
@ -447,6 +491,108 @@ module mqnic_app_block #
|
||||
output wire [IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0] m_axis_if_rx_tdest,
|
||||
output wire [IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] m_axis_if_rx_tuser,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
input wire [HBM_CH-1:0] hbm_clk,
|
||||
input wire [HBM_CH-1:0] hbm_rst,
|
||||
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
|
||||
output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_awready,
|
||||
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
|
||||
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
|
||||
output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_wready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
|
||||
input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_bready,
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
|
||||
output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_arready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
|
||||
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
|
||||
input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_rready,
|
||||
|
||||
input wire [HBM_CH-1:0] hbm_status,
|
||||
|
||||
/*
|
||||
* Statistics increment output
|
||||
*/
|
||||
@ -527,6 +673,54 @@ assign m_axil_ctrl_arprot = 0;
|
||||
assign m_axil_ctrl_arvalid = 1'b0;
|
||||
assign m_axil_ctrl_rready = 1'b1;
|
||||
|
||||
/*
|
||||
* DMA interface (control)
|
||||
*/
|
||||
assign m_axis_ctrl_dma_read_desc_dma_addr = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_ram_sel = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_ram_addr = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_len = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_tag = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_valid = 1'b0;
|
||||
assign m_axis_ctrl_dma_write_desc_dma_addr = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_ram_sel = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_ram_addr = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_imm = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_imm_en = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_len = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_tag = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_valid = 1'b0;
|
||||
|
||||
assign ctrl_dma_ram_wr_cmd_ready = 1'b1;
|
||||
assign ctrl_dma_ram_wr_done = ctrl_dma_ram_wr_cmd_valid;
|
||||
assign ctrl_dma_ram_rd_cmd_ready = ctrl_dma_ram_rd_resp_ready;
|
||||
assign ctrl_dma_ram_rd_resp_data = 0;
|
||||
assign ctrl_dma_ram_rd_resp_valid = ctrl_dma_ram_rd_cmd_valid;
|
||||
|
||||
/*
|
||||
* DMA interface (data)
|
||||
*/
|
||||
assign m_axis_data_dma_read_desc_dma_addr = 0;
|
||||
assign m_axis_data_dma_read_desc_ram_sel = 0;
|
||||
assign m_axis_data_dma_read_desc_ram_addr = 0;
|
||||
assign m_axis_data_dma_read_desc_len = 0;
|
||||
assign m_axis_data_dma_read_desc_tag = 0;
|
||||
assign m_axis_data_dma_read_desc_valid = 1'b0;
|
||||
assign m_axis_data_dma_write_desc_dma_addr = 0;
|
||||
assign m_axis_data_dma_write_desc_ram_sel = 0;
|
||||
assign m_axis_data_dma_write_desc_ram_addr = 0;
|
||||
assign m_axis_data_dma_write_desc_imm = 0;
|
||||
assign m_axis_data_dma_write_desc_imm_en = 0;
|
||||
assign m_axis_data_dma_write_desc_len = 0;
|
||||
assign m_axis_data_dma_write_desc_tag = 0;
|
||||
assign m_axis_data_dma_write_desc_valid = 1'b0;
|
||||
|
||||
assign data_dma_ram_wr_cmd_ready = 1'b1;
|
||||
assign data_dma_ram_wr_done = data_dma_ram_wr_cmd_valid;
|
||||
assign data_dma_ram_rd_cmd_ready = data_dma_ram_rd_resp_ready;
|
||||
assign data_dma_ram_rd_resp_data = 0;
|
||||
assign data_dma_ram_rd_resp_valid = data_dma_ram_rd_cmd_valid;
|
||||
|
||||
/*
|
||||
* Ethernet (direct MAC interface - lowest latency raw traffic)
|
||||
*/
|
||||
@ -598,52 +792,70 @@ assign m_axis_if_rx_tdest = s_axis_if_rx_tdest;
|
||||
assign m_axis_if_rx_tuser = s_axis_if_rx_tuser;
|
||||
|
||||
/*
|
||||
* DMA interface (control)
|
||||
* DDR
|
||||
*/
|
||||
assign m_axis_ctrl_dma_read_desc_dma_addr = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_ram_sel = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_ram_addr = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_len = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_tag = 0;
|
||||
assign m_axis_ctrl_dma_read_desc_valid = 1'b0;
|
||||
assign m_axis_ctrl_dma_write_desc_dma_addr = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_ram_sel = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_ram_addr = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_imm = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_imm_en = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_len = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_tag = 0;
|
||||
assign m_axis_ctrl_dma_write_desc_valid = 1'b0;
|
||||
|
||||
assign ctrl_dma_ram_wr_cmd_ready = 1'b1;
|
||||
assign ctrl_dma_ram_wr_done = ctrl_dma_ram_wr_cmd_valid;
|
||||
assign ctrl_dma_ram_rd_cmd_ready = ctrl_dma_ram_rd_resp_ready;
|
||||
assign ctrl_dma_ram_rd_resp_data = 0;
|
||||
assign ctrl_dma_ram_rd_resp_valid = ctrl_dma_ram_rd_cmd_valid;
|
||||
assign m_axi_ddr_awid = 0;
|
||||
assign m_axi_ddr_awaddr = 0;
|
||||
assign m_axi_ddr_awlen = 0;
|
||||
assign m_axi_ddr_awsize = 0;
|
||||
assign m_axi_ddr_awburst = 0;
|
||||
assign m_axi_ddr_awlock = 0;
|
||||
assign m_axi_ddr_awcache = 0;
|
||||
assign m_axi_ddr_awprot = 0;
|
||||
assign m_axi_ddr_awqos = 0;
|
||||
assign m_axi_ddr_awuser = 0;
|
||||
assign m_axi_ddr_awvalid = 0;
|
||||
assign m_axi_ddr_wdata = 0;
|
||||
assign m_axi_ddr_wstrb = 0;
|
||||
assign m_axi_ddr_wlast = 0;
|
||||
assign m_axi_ddr_wuser = 0;
|
||||
assign m_axi_ddr_wvalid = 0;
|
||||
assign m_axi_ddr_bready = 0;
|
||||
assign m_axi_ddr_arid = 0;
|
||||
assign m_axi_ddr_araddr = 0;
|
||||
assign m_axi_ddr_arlen = 0;
|
||||
assign m_axi_ddr_arsize = 0;
|
||||
assign m_axi_ddr_arburst = 0;
|
||||
assign m_axi_ddr_arlock = 0;
|
||||
assign m_axi_ddr_arcache = 0;
|
||||
assign m_axi_ddr_arprot = 0;
|
||||
assign m_axi_ddr_arqos = 0;
|
||||
assign m_axi_ddr_aruser = 0;
|
||||
assign m_axi_ddr_arvalid = 0;
|
||||
assign m_axi_ddr_rready = 0;
|
||||
|
||||
/*
|
||||
* DMA interface (data)
|
||||
* HBM
|
||||
*/
|
||||
assign m_axis_data_dma_read_desc_dma_addr = 0;
|
||||
assign m_axis_data_dma_read_desc_ram_sel = 0;
|
||||
assign m_axis_data_dma_read_desc_ram_addr = 0;
|
||||
assign m_axis_data_dma_read_desc_len = 0;
|
||||
assign m_axis_data_dma_read_desc_tag = 0;
|
||||
assign m_axis_data_dma_read_desc_valid = 1'b0;
|
||||
assign m_axis_data_dma_write_desc_dma_addr = 0;
|
||||
assign m_axis_data_dma_write_desc_ram_sel = 0;
|
||||
assign m_axis_data_dma_write_desc_ram_addr = 0;
|
||||
assign m_axis_data_dma_write_desc_imm = 0;
|
||||
assign m_axis_data_dma_write_desc_imm_en = 0;
|
||||
assign m_axis_data_dma_write_desc_len = 0;
|
||||
assign m_axis_data_dma_write_desc_tag = 0;
|
||||
assign m_axis_data_dma_write_desc_valid = 1'b0;
|
||||
|
||||
assign data_dma_ram_wr_cmd_ready = 1'b1;
|
||||
assign data_dma_ram_wr_done = data_dma_ram_wr_cmd_valid;
|
||||
assign data_dma_ram_rd_cmd_ready = data_dma_ram_rd_resp_ready;
|
||||
assign data_dma_ram_rd_resp_data = 0;
|
||||
assign data_dma_ram_rd_resp_valid = data_dma_ram_rd_cmd_valid;
|
||||
assign m_axi_hbm_awid = 0;
|
||||
assign m_axi_hbm_awaddr = 0;
|
||||
assign m_axi_hbm_awlen = 0;
|
||||
assign m_axi_hbm_awsize = 0;
|
||||
assign m_axi_hbm_awburst = 0;
|
||||
assign m_axi_hbm_awlock = 0;
|
||||
assign m_axi_hbm_awcache = 0;
|
||||
assign m_axi_hbm_awprot = 0;
|
||||
assign m_axi_hbm_awqos = 0;
|
||||
assign m_axi_hbm_awuser = 0;
|
||||
assign m_axi_hbm_awvalid = 0;
|
||||
assign m_axi_hbm_wdata = 0;
|
||||
assign m_axi_hbm_wstrb = 0;
|
||||
assign m_axi_hbm_wlast = 0;
|
||||
assign m_axi_hbm_wuser = 0;
|
||||
assign m_axi_hbm_wvalid = 0;
|
||||
assign m_axi_hbm_bready = 0;
|
||||
assign m_axi_hbm_arid = 0;
|
||||
assign m_axi_hbm_araddr = 0;
|
||||
assign m_axi_hbm_arlen = 0;
|
||||
assign m_axi_hbm_arsize = 0;
|
||||
assign m_axi_hbm_arburst = 0;
|
||||
assign m_axi_hbm_arlock = 0;
|
||||
assign m_axi_hbm_arcache = 0;
|
||||
assign m_axi_hbm_arprot = 0;
|
||||
assign m_axi_hbm_arqos = 0;
|
||||
assign m_axi_hbm_aruser = 0;
|
||||
assign m_axi_hbm_arvalid = 0;
|
||||
assign m_axi_hbm_rready = 0;
|
||||
|
||||
/*
|
||||
* Statistics increment output
|
||||
|
||||
@ -118,6 +118,50 @@ module mqnic_core #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 1,
|
||||
parameter DDR_ENABLE = 0,
|
||||
parameter DDR_GROUP_SIZE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 256,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_AWUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_AWUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_WUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_WUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_BUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_BUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_ARUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_ARUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_RUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_RUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
parameter AXI_DDR_FIXED_BURST = 0,
|
||||
parameter AXI_DDR_WRAP_BURST = 0,
|
||||
parameter HBM_CH = 1,
|
||||
parameter HBM_ENABLE = 0,
|
||||
parameter HBM_GROUP_SIZE = 1,
|
||||
parameter AXI_HBM_DATA_WIDTH = 256,
|
||||
parameter AXI_HBM_ADDR_WIDTH = 32,
|
||||
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
|
||||
parameter AXI_HBM_ID_WIDTH = 8,
|
||||
parameter AXI_HBM_AWUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_AWUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_WUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_WUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_BUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_BUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_ARUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_ARUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_RUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_RUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_MAX_BURST_LEN = 256,
|
||||
parameter AXI_HBM_NARROW_BURST = 0,
|
||||
parameter AXI_HBM_FIXED_BURST = 0,
|
||||
parameter AXI_HBM_WRAP_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -416,6 +460,108 @@ module mqnic_core #
|
||||
|
||||
input wire [PORT_COUNT-1:0] rx_status,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
input wire [HBM_CH-1:0] hbm_clk,
|
||||
input wire [HBM_CH-1:0] hbm_rst,
|
||||
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
|
||||
output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_awready,
|
||||
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
|
||||
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
|
||||
output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_wready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
|
||||
input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_bready,
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
|
||||
output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_arready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
|
||||
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
|
||||
input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_rready,
|
||||
|
||||
input wire [HBM_CH-1:0] hbm_status,
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
@ -2956,6 +3102,50 @@ if (APP_ENABLE) begin : app
|
||||
.MAX_TX_SIZE(MAX_TX_SIZE),
|
||||
.MAX_RX_SIZE(MAX_RX_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(DDR_GROUP_SIZE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE),
|
||||
.AXI_DDR_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH),
|
||||
.AXI_DDR_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE),
|
||||
.AXI_DDR_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH),
|
||||
.AXI_DDR_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE),
|
||||
.AXI_DDR_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH),
|
||||
.AXI_DDR_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE),
|
||||
.AXI_DDR_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH),
|
||||
.AXI_DDR_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE),
|
||||
.AXI_DDR_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(AXI_DDR_FIXED_BURST),
|
||||
.AXI_DDR_WRAP_BURST(AXI_DDR_WRAP_BURST),
|
||||
.HBM_CH(HBM_CH),
|
||||
.HBM_ENABLE(HBM_ENABLE),
|
||||
.HBM_GROUP_SIZE(HBM_GROUP_SIZE),
|
||||
.AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
|
||||
.AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
|
||||
.AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
|
||||
.AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH),
|
||||
.AXI_HBM_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE),
|
||||
.AXI_HBM_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH),
|
||||
.AXI_HBM_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE),
|
||||
.AXI_HBM_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH),
|
||||
.AXI_HBM_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE),
|
||||
.AXI_HBM_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH),
|
||||
.AXI_HBM_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE),
|
||||
.AXI_HBM_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH),
|
||||
.AXI_HBM_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE),
|
||||
.AXI_HBM_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH),
|
||||
.AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
|
||||
.AXI_HBM_NARROW_BURST(AXI_HBM_NARROW_BURST),
|
||||
.AXI_HBM_FIXED_BURST(AXI_HBM_FIXED_BURST),
|
||||
.AXI_HBM_WRAP_BURST(AXI_HBM_WRAP_BURST),
|
||||
|
||||
// Application configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_CTRL_ENABLE(APP_CTRL_ENABLE),
|
||||
@ -3333,6 +3523,108 @@ if (APP_ENABLE) begin : app
|
||||
.m_axis_if_rx_tdest(app_m_axis_if_rx_tdest),
|
||||
.m_axis_if_rx_tuser(app_m_axis_if_rx_tuser),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(m_axi_ddr_awuser),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(m_axi_ddr_wuser),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(m_axi_ddr_buser),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(m_axi_ddr_aruser),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(m_axi_ddr_ruser),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(hbm_clk),
|
||||
.hbm_rst(hbm_rst),
|
||||
|
||||
.m_axi_hbm_awid(m_axi_hbm_awid),
|
||||
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
|
||||
.m_axi_hbm_awlen(m_axi_hbm_awlen),
|
||||
.m_axi_hbm_awsize(m_axi_hbm_awsize),
|
||||
.m_axi_hbm_awburst(m_axi_hbm_awburst),
|
||||
.m_axi_hbm_awlock(m_axi_hbm_awlock),
|
||||
.m_axi_hbm_awcache(m_axi_hbm_awcache),
|
||||
.m_axi_hbm_awprot(m_axi_hbm_awprot),
|
||||
.m_axi_hbm_awqos(m_axi_hbm_awqos),
|
||||
.m_axi_hbm_awuser(m_axi_hbm_awuser),
|
||||
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
|
||||
.m_axi_hbm_awready(m_axi_hbm_awready),
|
||||
.m_axi_hbm_wdata(m_axi_hbm_wdata),
|
||||
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
|
||||
.m_axi_hbm_wlast(m_axi_hbm_wlast),
|
||||
.m_axi_hbm_wuser(m_axi_hbm_wuser),
|
||||
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
|
||||
.m_axi_hbm_wready(m_axi_hbm_wready),
|
||||
.m_axi_hbm_bid(m_axi_hbm_bid),
|
||||
.m_axi_hbm_bresp(m_axi_hbm_bresp),
|
||||
.m_axi_hbm_buser(m_axi_hbm_buser),
|
||||
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
|
||||
.m_axi_hbm_bready(m_axi_hbm_bready),
|
||||
.m_axi_hbm_arid(m_axi_hbm_arid),
|
||||
.m_axi_hbm_araddr(m_axi_hbm_araddr),
|
||||
.m_axi_hbm_arlen(m_axi_hbm_arlen),
|
||||
.m_axi_hbm_arsize(m_axi_hbm_arsize),
|
||||
.m_axi_hbm_arburst(m_axi_hbm_arburst),
|
||||
.m_axi_hbm_arlock(m_axi_hbm_arlock),
|
||||
.m_axi_hbm_arcache(m_axi_hbm_arcache),
|
||||
.m_axi_hbm_arprot(m_axi_hbm_arprot),
|
||||
.m_axi_hbm_arqos(m_axi_hbm_arqos),
|
||||
.m_axi_hbm_aruser(m_axi_hbm_aruser),
|
||||
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
|
||||
.m_axi_hbm_arready(m_axi_hbm_arready),
|
||||
.m_axi_hbm_rid(m_axi_hbm_rid),
|
||||
.m_axi_hbm_rdata(m_axi_hbm_rdata),
|
||||
.m_axi_hbm_rresp(m_axi_hbm_rresp),
|
||||
.m_axi_hbm_rlast(m_axi_hbm_rlast),
|
||||
.m_axi_hbm_ruser(m_axi_hbm_ruser),
|
||||
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
|
||||
.m_axi_hbm_rready(m_axi_hbm_rready),
|
||||
|
||||
.hbm_status(hbm_status),
|
||||
|
||||
/*
|
||||
* Statistics increment output
|
||||
*/
|
||||
@ -3493,6 +3785,66 @@ end else begin
|
||||
assign app_m_axis_if_rx_tdest = 0;
|
||||
assign app_m_axis_if_rx_tuser = 0;
|
||||
|
||||
assign m_axi_ddr_awid = 0;
|
||||
assign m_axi_ddr_awaddr = 0;
|
||||
assign m_axi_ddr_awlen = 0;
|
||||
assign m_axi_ddr_awsize = 0;
|
||||
assign m_axi_ddr_awburst = 0;
|
||||
assign m_axi_ddr_awlock = 0;
|
||||
assign m_axi_ddr_awcache = 0;
|
||||
assign m_axi_ddr_awprot = 0;
|
||||
assign m_axi_ddr_awqos = 0;
|
||||
assign m_axi_ddr_awuser = 0;
|
||||
assign m_axi_ddr_awvalid = 0;
|
||||
assign m_axi_ddr_wdata = 0;
|
||||
assign m_axi_ddr_wstrb = 0;
|
||||
assign m_axi_ddr_wlast = 0;
|
||||
assign m_axi_ddr_wuser = 0;
|
||||
assign m_axi_ddr_wvalid = 0;
|
||||
assign m_axi_ddr_bready = 0;
|
||||
assign m_axi_ddr_arid = 0;
|
||||
assign m_axi_ddr_araddr = 0;
|
||||
assign m_axi_ddr_arlen = 0;
|
||||
assign m_axi_ddr_arsize = 0;
|
||||
assign m_axi_ddr_arburst = 0;
|
||||
assign m_axi_ddr_arlock = 0;
|
||||
assign m_axi_ddr_arcache = 0;
|
||||
assign m_axi_ddr_arprot = 0;
|
||||
assign m_axi_ddr_arqos = 0;
|
||||
assign m_axi_ddr_aruser = 0;
|
||||
assign m_axi_ddr_arvalid = 0;
|
||||
assign m_axi_ddr_rready = 0;
|
||||
|
||||
assign m_axi_hbm_awid = 0;
|
||||
assign m_axi_hbm_awaddr = 0;
|
||||
assign m_axi_hbm_awlen = 0;
|
||||
assign m_axi_hbm_awsize = 0;
|
||||
assign m_axi_hbm_awburst = 0;
|
||||
assign m_axi_hbm_awlock = 0;
|
||||
assign m_axi_hbm_awcache = 0;
|
||||
assign m_axi_hbm_awprot = 0;
|
||||
assign m_axi_hbm_awqos = 0;
|
||||
assign m_axi_hbm_awuser = 0;
|
||||
assign m_axi_hbm_awvalid = 0;
|
||||
assign m_axi_hbm_wdata = 0;
|
||||
assign m_axi_hbm_wstrb = 0;
|
||||
assign m_axi_hbm_wlast = 0;
|
||||
assign m_axi_hbm_wuser = 0;
|
||||
assign m_axi_hbm_wvalid = 0;
|
||||
assign m_axi_hbm_bready = 0;
|
||||
assign m_axi_hbm_arid = 0;
|
||||
assign m_axi_hbm_araddr = 0;
|
||||
assign m_axi_hbm_arlen = 0;
|
||||
assign m_axi_hbm_arsize = 0;
|
||||
assign m_axi_hbm_arburst = 0;
|
||||
assign m_axi_hbm_arlock = 0;
|
||||
assign m_axi_hbm_arcache = 0;
|
||||
assign m_axi_hbm_arprot = 0;
|
||||
assign m_axi_hbm_arqos = 0;
|
||||
assign m_axi_hbm_aruser = 0;
|
||||
assign m_axi_hbm_arvalid = 0;
|
||||
assign m_axi_hbm_rready = 0;
|
||||
|
||||
assign axis_app_stat_tdata = 0;
|
||||
assign axis_app_stat_tid = 0;
|
||||
assign axis_app_stat_tvalid = 1'b0;
|
||||
|
||||
@ -118,6 +118,50 @@ module mqnic_core_axi #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 1,
|
||||
parameter DDR_ENABLE = 0,
|
||||
parameter DDR_GROUP_SIZE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 256,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_AWUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_AWUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_WUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_WUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_BUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_BUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_ARUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_ARUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_RUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_RUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
parameter AXI_DDR_FIXED_BURST = 0,
|
||||
parameter AXI_DDR_WRAP_BURST = 0,
|
||||
parameter HBM_CH = 1,
|
||||
parameter HBM_ENABLE = 0,
|
||||
parameter HBM_GROUP_SIZE = 1,
|
||||
parameter AXI_HBM_DATA_WIDTH = 256,
|
||||
parameter AXI_HBM_ADDR_WIDTH = 32,
|
||||
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
|
||||
parameter AXI_HBM_ID_WIDTH = 8,
|
||||
parameter AXI_HBM_AWUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_AWUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_WUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_WUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_BUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_BUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_ARUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_ARUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_RUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_RUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_MAX_BURST_LEN = 256,
|
||||
parameter AXI_HBM_NARROW_BURST = 0,
|
||||
parameter AXI_HBM_FIXED_BURST = 0,
|
||||
parameter AXI_HBM_WRAP_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -378,6 +422,109 @@ module mqnic_core_axi #
|
||||
|
||||
input wire [PORT_COUNT-1:0] rx_status,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
input wire [HBM_CH-1:0] hbm_clk,
|
||||
input wire [HBM_CH-1:0] hbm_rst,
|
||||
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
|
||||
output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_awready,
|
||||
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
|
||||
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
|
||||
output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_wready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
|
||||
input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_bready,
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
|
||||
output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_arready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
|
||||
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
|
||||
input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_rready,
|
||||
|
||||
input wire [HBM_CH-1:0] hbm_status,
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
@ -882,6 +1029,50 @@ mqnic_core #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(DDR_GROUP_SIZE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE),
|
||||
.AXI_DDR_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH),
|
||||
.AXI_DDR_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE),
|
||||
.AXI_DDR_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH),
|
||||
.AXI_DDR_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE),
|
||||
.AXI_DDR_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH),
|
||||
.AXI_DDR_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE),
|
||||
.AXI_DDR_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH),
|
||||
.AXI_DDR_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE),
|
||||
.AXI_DDR_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(AXI_DDR_FIXED_BURST),
|
||||
.AXI_DDR_WRAP_BURST(AXI_DDR_WRAP_BURST),
|
||||
.HBM_CH(HBM_CH),
|
||||
.HBM_ENABLE(HBM_ENABLE),
|
||||
.HBM_GROUP_SIZE(HBM_GROUP_SIZE),
|
||||
.AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
|
||||
.AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
|
||||
.AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
|
||||
.AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH),
|
||||
.AXI_HBM_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE),
|
||||
.AXI_HBM_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH),
|
||||
.AXI_HBM_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE),
|
||||
.AXI_HBM_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH),
|
||||
.AXI_HBM_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE),
|
||||
.AXI_HBM_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH),
|
||||
.AXI_HBM_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE),
|
||||
.AXI_HBM_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH),
|
||||
.AXI_HBM_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE),
|
||||
.AXI_HBM_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH),
|
||||
.AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
|
||||
.AXI_HBM_NARROW_BURST(AXI_HBM_NARROW_BURST),
|
||||
.AXI_HBM_FIXED_BURST(AXI_HBM_FIXED_BURST),
|
||||
.AXI_HBM_WRAP_BURST(AXI_HBM_WRAP_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1154,6 +1345,108 @@ core_inst (
|
||||
|
||||
.rx_status(rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(m_axi_ddr_awuser),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(m_axi_ddr_wuser),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(m_axi_ddr_buser),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(m_axi_ddr_aruser),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(m_axi_ddr_ruser),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(hbm_clk),
|
||||
.hbm_rst(hbm_rst),
|
||||
|
||||
.m_axi_hbm_awid(m_axi_hbm_awid),
|
||||
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
|
||||
.m_axi_hbm_awlen(m_axi_hbm_awlen),
|
||||
.m_axi_hbm_awsize(m_axi_hbm_awsize),
|
||||
.m_axi_hbm_awburst(m_axi_hbm_awburst),
|
||||
.m_axi_hbm_awlock(m_axi_hbm_awlock),
|
||||
.m_axi_hbm_awcache(m_axi_hbm_awcache),
|
||||
.m_axi_hbm_awprot(m_axi_hbm_awprot),
|
||||
.m_axi_hbm_awqos(m_axi_hbm_awqos),
|
||||
.m_axi_hbm_awuser(m_axi_hbm_awuser),
|
||||
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
|
||||
.m_axi_hbm_awready(m_axi_hbm_awready),
|
||||
.m_axi_hbm_wdata(m_axi_hbm_wdata),
|
||||
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
|
||||
.m_axi_hbm_wlast(m_axi_hbm_wlast),
|
||||
.m_axi_hbm_wuser(m_axi_hbm_wuser),
|
||||
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
|
||||
.m_axi_hbm_wready(m_axi_hbm_wready),
|
||||
.m_axi_hbm_bid(m_axi_hbm_bid),
|
||||
.m_axi_hbm_bresp(m_axi_hbm_bresp),
|
||||
.m_axi_hbm_buser(m_axi_hbm_buser),
|
||||
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
|
||||
.m_axi_hbm_bready(m_axi_hbm_bready),
|
||||
.m_axi_hbm_arid(m_axi_hbm_arid),
|
||||
.m_axi_hbm_araddr(m_axi_hbm_araddr),
|
||||
.m_axi_hbm_arlen(m_axi_hbm_arlen),
|
||||
.m_axi_hbm_arsize(m_axi_hbm_arsize),
|
||||
.m_axi_hbm_arburst(m_axi_hbm_arburst),
|
||||
.m_axi_hbm_arlock(m_axi_hbm_arlock),
|
||||
.m_axi_hbm_arcache(m_axi_hbm_arcache),
|
||||
.m_axi_hbm_arprot(m_axi_hbm_arprot),
|
||||
.m_axi_hbm_arqos(m_axi_hbm_arqos),
|
||||
.m_axi_hbm_aruser(m_axi_hbm_aruser),
|
||||
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
|
||||
.m_axi_hbm_arready(m_axi_hbm_arready),
|
||||
.m_axi_hbm_rid(m_axi_hbm_rid),
|
||||
.m_axi_hbm_rdata(m_axi_hbm_rdata),
|
||||
.m_axi_hbm_rresp(m_axi_hbm_rresp),
|
||||
.m_axi_hbm_rlast(m_axi_hbm_rlast),
|
||||
.m_axi_hbm_ruser(m_axi_hbm_ruser),
|
||||
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
|
||||
.m_axi_hbm_rready(m_axi_hbm_rready),
|
||||
|
||||
.hbm_status(hbm_status),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -118,6 +118,50 @@ module mqnic_core_pcie #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 1,
|
||||
parameter DDR_ENABLE = 0,
|
||||
parameter DDR_GROUP_SIZE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 256,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_AWUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_AWUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_WUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_WUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_BUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_BUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_ARUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_ARUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_RUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_RUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
parameter AXI_DDR_FIXED_BURST = 0,
|
||||
parameter AXI_DDR_WRAP_BURST = 0,
|
||||
parameter HBM_CH = 1,
|
||||
parameter HBM_ENABLE = 0,
|
||||
parameter HBM_GROUP_SIZE = 1,
|
||||
parameter AXI_HBM_DATA_WIDTH = 256,
|
||||
parameter AXI_HBM_ADDR_WIDTH = 32,
|
||||
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
|
||||
parameter AXI_HBM_ID_WIDTH = 8,
|
||||
parameter AXI_HBM_AWUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_AWUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_WUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_WUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_BUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_BUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_ARUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_ARUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_RUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_RUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_MAX_BURST_LEN = 256,
|
||||
parameter AXI_HBM_NARROW_BURST = 0,
|
||||
parameter AXI_HBM_FIXED_BURST = 0,
|
||||
parameter AXI_HBM_WRAP_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -392,6 +436,107 @@ module mqnic_core_pcie #
|
||||
|
||||
input wire [PORT_COUNT-1:0] rx_status,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
input wire [HBM_CH-1:0] hbm_clk,
|
||||
input wire [HBM_CH-1:0] hbm_rst,
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
|
||||
output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_awready,
|
||||
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
|
||||
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
|
||||
output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_wready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
|
||||
input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_bready,
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
|
||||
output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_arready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
|
||||
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
|
||||
input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_rready,
|
||||
|
||||
input wire [HBM_CH-1:0] hbm_status,
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
@ -1514,6 +1659,50 @@ mqnic_core #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(DDR_GROUP_SIZE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE),
|
||||
.AXI_DDR_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH),
|
||||
.AXI_DDR_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE),
|
||||
.AXI_DDR_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH),
|
||||
.AXI_DDR_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE),
|
||||
.AXI_DDR_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH),
|
||||
.AXI_DDR_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE),
|
||||
.AXI_DDR_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH),
|
||||
.AXI_DDR_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE),
|
||||
.AXI_DDR_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(AXI_DDR_FIXED_BURST),
|
||||
.AXI_DDR_WRAP_BURST(AXI_DDR_WRAP_BURST),
|
||||
.HBM_CH(HBM_CH),
|
||||
.HBM_ENABLE(HBM_ENABLE),
|
||||
.HBM_GROUP_SIZE(HBM_GROUP_SIZE),
|
||||
.AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
|
||||
.AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
|
||||
.AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
|
||||
.AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH),
|
||||
.AXI_HBM_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE),
|
||||
.AXI_HBM_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH),
|
||||
.AXI_HBM_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE),
|
||||
.AXI_HBM_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH),
|
||||
.AXI_HBM_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE),
|
||||
.AXI_HBM_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH),
|
||||
.AXI_HBM_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE),
|
||||
.AXI_HBM_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH),
|
||||
.AXI_HBM_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE),
|
||||
.AXI_HBM_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH),
|
||||
.AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
|
||||
.AXI_HBM_NARROW_BURST(AXI_HBM_NARROW_BURST),
|
||||
.AXI_HBM_FIXED_BURST(AXI_HBM_FIXED_BURST),
|
||||
.AXI_HBM_WRAP_BURST(AXI_HBM_WRAP_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1810,6 +1999,108 @@ core_inst (
|
||||
|
||||
.rx_status(rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(m_axi_ddr_awuser),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(m_axi_ddr_wuser),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(m_axi_ddr_buser),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(m_axi_ddr_aruser),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(m_axi_ddr_ruser),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(hbm_clk),
|
||||
.hbm_rst(hbm_rst),
|
||||
|
||||
.m_axi_hbm_awid(m_axi_hbm_awid),
|
||||
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
|
||||
.m_axi_hbm_awlen(m_axi_hbm_awlen),
|
||||
.m_axi_hbm_awsize(m_axi_hbm_awsize),
|
||||
.m_axi_hbm_awburst(m_axi_hbm_awburst),
|
||||
.m_axi_hbm_awlock(m_axi_hbm_awlock),
|
||||
.m_axi_hbm_awcache(m_axi_hbm_awcache),
|
||||
.m_axi_hbm_awprot(m_axi_hbm_awprot),
|
||||
.m_axi_hbm_awqos(m_axi_hbm_awqos),
|
||||
.m_axi_hbm_awuser(m_axi_hbm_awuser),
|
||||
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
|
||||
.m_axi_hbm_awready(m_axi_hbm_awready),
|
||||
.m_axi_hbm_wdata(m_axi_hbm_wdata),
|
||||
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
|
||||
.m_axi_hbm_wlast(m_axi_hbm_wlast),
|
||||
.m_axi_hbm_wuser(m_axi_hbm_wuser),
|
||||
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
|
||||
.m_axi_hbm_wready(m_axi_hbm_wready),
|
||||
.m_axi_hbm_bid(m_axi_hbm_bid),
|
||||
.m_axi_hbm_bresp(m_axi_hbm_bresp),
|
||||
.m_axi_hbm_buser(m_axi_hbm_buser),
|
||||
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
|
||||
.m_axi_hbm_bready(m_axi_hbm_bready),
|
||||
.m_axi_hbm_arid(m_axi_hbm_arid),
|
||||
.m_axi_hbm_araddr(m_axi_hbm_araddr),
|
||||
.m_axi_hbm_arlen(m_axi_hbm_arlen),
|
||||
.m_axi_hbm_arsize(m_axi_hbm_arsize),
|
||||
.m_axi_hbm_arburst(m_axi_hbm_arburst),
|
||||
.m_axi_hbm_arlock(m_axi_hbm_arlock),
|
||||
.m_axi_hbm_arcache(m_axi_hbm_arcache),
|
||||
.m_axi_hbm_arprot(m_axi_hbm_arprot),
|
||||
.m_axi_hbm_arqos(m_axi_hbm_arqos),
|
||||
.m_axi_hbm_aruser(m_axi_hbm_aruser),
|
||||
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
|
||||
.m_axi_hbm_arready(m_axi_hbm_arready),
|
||||
.m_axi_hbm_rid(m_axi_hbm_rid),
|
||||
.m_axi_hbm_rdata(m_axi_hbm_rdata),
|
||||
.m_axi_hbm_rresp(m_axi_hbm_rresp),
|
||||
.m_axi_hbm_rlast(m_axi_hbm_rlast),
|
||||
.m_axi_hbm_ruser(m_axi_hbm_ruser),
|
||||
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
|
||||
.m_axi_hbm_rready(m_axi_hbm_rready),
|
||||
|
||||
.hbm_status(hbm_status),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -118,6 +118,50 @@ module mqnic_core_pcie_ptile #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 1,
|
||||
parameter DDR_ENABLE = 0,
|
||||
parameter DDR_GROUP_SIZE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 256,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_AWUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_AWUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_WUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_WUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_BUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_BUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_ARUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_ARUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_RUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_RUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
parameter AXI_DDR_FIXED_BURST = 0,
|
||||
parameter AXI_DDR_WRAP_BURST = 0,
|
||||
parameter HBM_CH = 1,
|
||||
parameter HBM_ENABLE = 0,
|
||||
parameter HBM_GROUP_SIZE = 1,
|
||||
parameter AXI_HBM_DATA_WIDTH = 256,
|
||||
parameter AXI_HBM_ADDR_WIDTH = 32,
|
||||
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
|
||||
parameter AXI_HBM_ID_WIDTH = 8,
|
||||
parameter AXI_HBM_AWUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_AWUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_WUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_WUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_BUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_BUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_ARUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_ARUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_RUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_RUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_MAX_BURST_LEN = 256,
|
||||
parameter AXI_HBM_NARROW_BURST = 0,
|
||||
parameter AXI_HBM_FIXED_BURST = 0,
|
||||
parameter AXI_HBM_WRAP_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -341,6 +385,108 @@ module mqnic_core_pcie_ptile #
|
||||
|
||||
input wire [PORT_COUNT-1:0] eth_rx_status,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
input wire [HBM_CH-1:0] hbm_clk,
|
||||
input wire [HBM_CH-1:0] hbm_rst,
|
||||
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
|
||||
output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_awready,
|
||||
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
|
||||
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
|
||||
output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_wready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
|
||||
input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_bready,
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
|
||||
output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_arready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
|
||||
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
|
||||
input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_rready,
|
||||
|
||||
input wire [HBM_CH-1:0] hbm_status,
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
@ -679,6 +825,50 @@ mqnic_core_pcie #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(DDR_GROUP_SIZE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE),
|
||||
.AXI_DDR_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH),
|
||||
.AXI_DDR_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE),
|
||||
.AXI_DDR_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH),
|
||||
.AXI_DDR_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE),
|
||||
.AXI_DDR_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH),
|
||||
.AXI_DDR_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE),
|
||||
.AXI_DDR_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH),
|
||||
.AXI_DDR_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE),
|
||||
.AXI_DDR_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(AXI_DDR_FIXED_BURST),
|
||||
.AXI_DDR_WRAP_BURST(AXI_DDR_WRAP_BURST),
|
||||
.HBM_CH(HBM_CH),
|
||||
.HBM_ENABLE(HBM_ENABLE),
|
||||
.HBM_GROUP_SIZE(HBM_GROUP_SIZE),
|
||||
.AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
|
||||
.AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
|
||||
.AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
|
||||
.AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH),
|
||||
.AXI_HBM_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE),
|
||||
.AXI_HBM_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH),
|
||||
.AXI_HBM_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE),
|
||||
.AXI_HBM_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH),
|
||||
.AXI_HBM_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE),
|
||||
.AXI_HBM_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH),
|
||||
.AXI_HBM_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE),
|
||||
.AXI_HBM_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH),
|
||||
.AXI_HBM_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE),
|
||||
.AXI_HBM_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH),
|
||||
.AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
|
||||
.AXI_HBM_NARROW_BURST(AXI_HBM_NARROW_BURST),
|
||||
.AXI_HBM_FIXED_BURST(AXI_HBM_FIXED_BURST),
|
||||
.AXI_HBM_WRAP_BURST(AXI_HBM_WRAP_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -951,6 +1141,108 @@ core_pcie_inst (
|
||||
|
||||
.rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(m_axi_ddr_awuser),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(m_axi_ddr_wuser),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(m_axi_ddr_buser),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(m_axi_ddr_aruser),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(m_axi_ddr_ruser),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(hbm_clk),
|
||||
.hbm_rst(hbm_rst),
|
||||
|
||||
.m_axi_hbm_awid(m_axi_hbm_awid),
|
||||
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
|
||||
.m_axi_hbm_awlen(m_axi_hbm_awlen),
|
||||
.m_axi_hbm_awsize(m_axi_hbm_awsize),
|
||||
.m_axi_hbm_awburst(m_axi_hbm_awburst),
|
||||
.m_axi_hbm_awlock(m_axi_hbm_awlock),
|
||||
.m_axi_hbm_awcache(m_axi_hbm_awcache),
|
||||
.m_axi_hbm_awprot(m_axi_hbm_awprot),
|
||||
.m_axi_hbm_awqos(m_axi_hbm_awqos),
|
||||
.m_axi_hbm_awuser(m_axi_hbm_awuser),
|
||||
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
|
||||
.m_axi_hbm_awready(m_axi_hbm_awready),
|
||||
.m_axi_hbm_wdata(m_axi_hbm_wdata),
|
||||
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
|
||||
.m_axi_hbm_wlast(m_axi_hbm_wlast),
|
||||
.m_axi_hbm_wuser(m_axi_hbm_wuser),
|
||||
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
|
||||
.m_axi_hbm_wready(m_axi_hbm_wready),
|
||||
.m_axi_hbm_bid(m_axi_hbm_bid),
|
||||
.m_axi_hbm_bresp(m_axi_hbm_bresp),
|
||||
.m_axi_hbm_buser(m_axi_hbm_buser),
|
||||
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
|
||||
.m_axi_hbm_bready(m_axi_hbm_bready),
|
||||
.m_axi_hbm_arid(m_axi_hbm_arid),
|
||||
.m_axi_hbm_araddr(m_axi_hbm_araddr),
|
||||
.m_axi_hbm_arlen(m_axi_hbm_arlen),
|
||||
.m_axi_hbm_arsize(m_axi_hbm_arsize),
|
||||
.m_axi_hbm_arburst(m_axi_hbm_arburst),
|
||||
.m_axi_hbm_arlock(m_axi_hbm_arlock),
|
||||
.m_axi_hbm_arcache(m_axi_hbm_arcache),
|
||||
.m_axi_hbm_arprot(m_axi_hbm_arprot),
|
||||
.m_axi_hbm_arqos(m_axi_hbm_arqos),
|
||||
.m_axi_hbm_aruser(m_axi_hbm_aruser),
|
||||
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
|
||||
.m_axi_hbm_arready(m_axi_hbm_arready),
|
||||
.m_axi_hbm_rid(m_axi_hbm_rid),
|
||||
.m_axi_hbm_rdata(m_axi_hbm_rdata),
|
||||
.m_axi_hbm_rresp(m_axi_hbm_rresp),
|
||||
.m_axi_hbm_rlast(m_axi_hbm_rlast),
|
||||
.m_axi_hbm_ruser(m_axi_hbm_ruser),
|
||||
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
|
||||
.m_axi_hbm_rready(m_axi_hbm_rready),
|
||||
|
||||
.hbm_status(hbm_status),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -118,6 +118,50 @@ module mqnic_core_pcie_s10 #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 1,
|
||||
parameter DDR_ENABLE = 0,
|
||||
parameter DDR_GROUP_SIZE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 256,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_AWUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_AWUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_WUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_WUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_BUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_BUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_ARUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_ARUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_RUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_RUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
parameter AXI_DDR_FIXED_BURST = 0,
|
||||
parameter AXI_DDR_WRAP_BURST = 0,
|
||||
parameter HBM_CH = 1,
|
||||
parameter HBM_ENABLE = 0,
|
||||
parameter HBM_GROUP_SIZE = 1,
|
||||
parameter AXI_HBM_DATA_WIDTH = 256,
|
||||
parameter AXI_HBM_ADDR_WIDTH = 32,
|
||||
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
|
||||
parameter AXI_HBM_ID_WIDTH = 8,
|
||||
parameter AXI_HBM_AWUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_AWUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_WUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_WUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_BUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_BUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_ARUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_ARUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_RUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_RUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_MAX_BURST_LEN = 256,
|
||||
parameter AXI_HBM_NARROW_BURST = 0,
|
||||
parameter AXI_HBM_FIXED_BURST = 0,
|
||||
parameter AXI_HBM_WRAP_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -337,6 +381,108 @@ module mqnic_core_pcie_s10 #
|
||||
|
||||
input wire [PORT_COUNT-1:0] eth_rx_status,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
input wire [HBM_CH-1:0] hbm_clk,
|
||||
input wire [HBM_CH-1:0] hbm_rst,
|
||||
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
|
||||
output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_awready,
|
||||
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
|
||||
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
|
||||
output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_wready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
|
||||
input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_bready,
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
|
||||
output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_arready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
|
||||
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
|
||||
input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_rready,
|
||||
|
||||
input wire [HBM_CH-1:0] hbm_status,
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
@ -688,6 +834,50 @@ mqnic_core_pcie #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(DDR_GROUP_SIZE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE),
|
||||
.AXI_DDR_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH),
|
||||
.AXI_DDR_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE),
|
||||
.AXI_DDR_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH),
|
||||
.AXI_DDR_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE),
|
||||
.AXI_DDR_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH),
|
||||
.AXI_DDR_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE),
|
||||
.AXI_DDR_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH),
|
||||
.AXI_DDR_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE),
|
||||
.AXI_DDR_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(AXI_DDR_FIXED_BURST),
|
||||
.AXI_DDR_WRAP_BURST(AXI_DDR_WRAP_BURST),
|
||||
.HBM_CH(HBM_CH),
|
||||
.HBM_ENABLE(HBM_ENABLE),
|
||||
.HBM_GROUP_SIZE(HBM_GROUP_SIZE),
|
||||
.AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
|
||||
.AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
|
||||
.AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
|
||||
.AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH),
|
||||
.AXI_HBM_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE),
|
||||
.AXI_HBM_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH),
|
||||
.AXI_HBM_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE),
|
||||
.AXI_HBM_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH),
|
||||
.AXI_HBM_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE),
|
||||
.AXI_HBM_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH),
|
||||
.AXI_HBM_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE),
|
||||
.AXI_HBM_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH),
|
||||
.AXI_HBM_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE),
|
||||
.AXI_HBM_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH),
|
||||
.AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
|
||||
.AXI_HBM_NARROW_BURST(AXI_HBM_NARROW_BURST),
|
||||
.AXI_HBM_FIXED_BURST(AXI_HBM_FIXED_BURST),
|
||||
.AXI_HBM_WRAP_BURST(AXI_HBM_WRAP_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -960,6 +1150,108 @@ core_pcie_inst (
|
||||
|
||||
.rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(m_axi_ddr_awuser),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(m_axi_ddr_wuser),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(m_axi_ddr_buser),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(m_axi_ddr_aruser),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(m_axi_ddr_ruser),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(hbm_clk),
|
||||
.hbm_rst(hbm_rst),
|
||||
|
||||
.m_axi_hbm_awid(m_axi_hbm_awid),
|
||||
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
|
||||
.m_axi_hbm_awlen(m_axi_hbm_awlen),
|
||||
.m_axi_hbm_awsize(m_axi_hbm_awsize),
|
||||
.m_axi_hbm_awburst(m_axi_hbm_awburst),
|
||||
.m_axi_hbm_awlock(m_axi_hbm_awlock),
|
||||
.m_axi_hbm_awcache(m_axi_hbm_awcache),
|
||||
.m_axi_hbm_awprot(m_axi_hbm_awprot),
|
||||
.m_axi_hbm_awqos(m_axi_hbm_awqos),
|
||||
.m_axi_hbm_awuser(m_axi_hbm_awuser),
|
||||
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
|
||||
.m_axi_hbm_awready(m_axi_hbm_awready),
|
||||
.m_axi_hbm_wdata(m_axi_hbm_wdata),
|
||||
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
|
||||
.m_axi_hbm_wlast(m_axi_hbm_wlast),
|
||||
.m_axi_hbm_wuser(m_axi_hbm_wuser),
|
||||
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
|
||||
.m_axi_hbm_wready(m_axi_hbm_wready),
|
||||
.m_axi_hbm_bid(m_axi_hbm_bid),
|
||||
.m_axi_hbm_bresp(m_axi_hbm_bresp),
|
||||
.m_axi_hbm_buser(m_axi_hbm_buser),
|
||||
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
|
||||
.m_axi_hbm_bready(m_axi_hbm_bready),
|
||||
.m_axi_hbm_arid(m_axi_hbm_arid),
|
||||
.m_axi_hbm_araddr(m_axi_hbm_araddr),
|
||||
.m_axi_hbm_arlen(m_axi_hbm_arlen),
|
||||
.m_axi_hbm_arsize(m_axi_hbm_arsize),
|
||||
.m_axi_hbm_arburst(m_axi_hbm_arburst),
|
||||
.m_axi_hbm_arlock(m_axi_hbm_arlock),
|
||||
.m_axi_hbm_arcache(m_axi_hbm_arcache),
|
||||
.m_axi_hbm_arprot(m_axi_hbm_arprot),
|
||||
.m_axi_hbm_arqos(m_axi_hbm_arqos),
|
||||
.m_axi_hbm_aruser(m_axi_hbm_aruser),
|
||||
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
|
||||
.m_axi_hbm_arready(m_axi_hbm_arready),
|
||||
.m_axi_hbm_rid(m_axi_hbm_rid),
|
||||
.m_axi_hbm_rdata(m_axi_hbm_rdata),
|
||||
.m_axi_hbm_rresp(m_axi_hbm_rresp),
|
||||
.m_axi_hbm_rlast(m_axi_hbm_rlast),
|
||||
.m_axi_hbm_ruser(m_axi_hbm_ruser),
|
||||
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
|
||||
.m_axi_hbm_rready(m_axi_hbm_rready),
|
||||
|
||||
.hbm_status(hbm_status),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -130,6 +130,50 @@ module mqnic_core_pcie_us #
|
||||
parameter APP_GPIO_IN_WIDTH = 32,
|
||||
parameter APP_GPIO_OUT_WIDTH = 32,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 1,
|
||||
parameter DDR_ENABLE = 0,
|
||||
parameter DDR_GROUP_SIZE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 256,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_AWUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_AWUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_WUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_WUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_BUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_BUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_ARUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_ARUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_RUSER_ENABLE = 0,
|
||||
parameter AXI_DDR_RUSER_WIDTH = 1,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
parameter AXI_DDR_FIXED_BURST = 0,
|
||||
parameter AXI_DDR_WRAP_BURST = 0,
|
||||
parameter HBM_CH = 1,
|
||||
parameter HBM_ENABLE = 0,
|
||||
parameter HBM_GROUP_SIZE = 1,
|
||||
parameter AXI_HBM_DATA_WIDTH = 256,
|
||||
parameter AXI_HBM_ADDR_WIDTH = 32,
|
||||
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
|
||||
parameter AXI_HBM_ID_WIDTH = 8,
|
||||
parameter AXI_HBM_AWUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_AWUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_WUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_WUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_BUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_BUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_ARUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_ARUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_RUSER_ENABLE = 0,
|
||||
parameter AXI_HBM_RUSER_WIDTH = 1,
|
||||
parameter AXI_HBM_MAX_BURST_LEN = 256,
|
||||
parameter AXI_HBM_NARROW_BURST = 0,
|
||||
parameter AXI_HBM_FIXED_BURST = 0,
|
||||
parameter AXI_HBM_WRAP_BURST = 0,
|
||||
|
||||
// DMA interface configuration
|
||||
parameter DMA_IMM_ENABLE = 0,
|
||||
parameter DMA_IMM_WIDTH = 32,
|
||||
@ -396,6 +440,108 @@ module mqnic_core_pcie_us #
|
||||
|
||||
input wire [PORT_COUNT-1:0] eth_rx_status,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
input wire [HBM_CH-1:0] hbm_clk,
|
||||
input wire [HBM_CH-1:0] hbm_rst,
|
||||
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
|
||||
output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_awready,
|
||||
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
|
||||
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
|
||||
output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_wready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
|
||||
input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_bready,
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
|
||||
output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_arready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
|
||||
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
|
||||
input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_rready,
|
||||
|
||||
input wire [HBM_CH-1:0] hbm_status,
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
@ -809,6 +955,50 @@ mqnic_core_pcie #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(DDR_GROUP_SIZE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE),
|
||||
.AXI_DDR_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH),
|
||||
.AXI_DDR_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE),
|
||||
.AXI_DDR_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH),
|
||||
.AXI_DDR_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE),
|
||||
.AXI_DDR_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH),
|
||||
.AXI_DDR_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE),
|
||||
.AXI_DDR_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH),
|
||||
.AXI_DDR_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE),
|
||||
.AXI_DDR_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(AXI_DDR_FIXED_BURST),
|
||||
.AXI_DDR_WRAP_BURST(AXI_DDR_WRAP_BURST),
|
||||
.HBM_CH(HBM_CH),
|
||||
.HBM_ENABLE(HBM_ENABLE),
|
||||
.HBM_GROUP_SIZE(HBM_GROUP_SIZE),
|
||||
.AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
|
||||
.AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
|
||||
.AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
|
||||
.AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH),
|
||||
.AXI_HBM_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE),
|
||||
.AXI_HBM_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH),
|
||||
.AXI_HBM_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE),
|
||||
.AXI_HBM_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH),
|
||||
.AXI_HBM_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE),
|
||||
.AXI_HBM_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH),
|
||||
.AXI_HBM_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE),
|
||||
.AXI_HBM_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH),
|
||||
.AXI_HBM_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE),
|
||||
.AXI_HBM_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH),
|
||||
.AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
|
||||
.AXI_HBM_NARROW_BURST(AXI_HBM_NARROW_BURST),
|
||||
.AXI_HBM_FIXED_BURST(AXI_HBM_FIXED_BURST),
|
||||
.AXI_HBM_WRAP_BURST(AXI_HBM_WRAP_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1081,6 +1271,108 @@ core_pcie_inst (
|
||||
|
||||
.rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(m_axi_ddr_awuser),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(m_axi_ddr_wuser),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(m_axi_ddr_buser),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(m_axi_ddr_aruser),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(m_axi_ddr_ruser),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(hbm_clk),
|
||||
.hbm_rst(hbm_rst),
|
||||
|
||||
.m_axi_hbm_awid(m_axi_hbm_awid),
|
||||
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
|
||||
.m_axi_hbm_awlen(m_axi_hbm_awlen),
|
||||
.m_axi_hbm_awsize(m_axi_hbm_awsize),
|
||||
.m_axi_hbm_awburst(m_axi_hbm_awburst),
|
||||
.m_axi_hbm_awlock(m_axi_hbm_awlock),
|
||||
.m_axi_hbm_awcache(m_axi_hbm_awcache),
|
||||
.m_axi_hbm_awprot(m_axi_hbm_awprot),
|
||||
.m_axi_hbm_awqos(m_axi_hbm_awqos),
|
||||
.m_axi_hbm_awuser(m_axi_hbm_awuser),
|
||||
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
|
||||
.m_axi_hbm_awready(m_axi_hbm_awready),
|
||||
.m_axi_hbm_wdata(m_axi_hbm_wdata),
|
||||
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
|
||||
.m_axi_hbm_wlast(m_axi_hbm_wlast),
|
||||
.m_axi_hbm_wuser(m_axi_hbm_wuser),
|
||||
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
|
||||
.m_axi_hbm_wready(m_axi_hbm_wready),
|
||||
.m_axi_hbm_bid(m_axi_hbm_bid),
|
||||
.m_axi_hbm_bresp(m_axi_hbm_bresp),
|
||||
.m_axi_hbm_buser(m_axi_hbm_buser),
|
||||
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
|
||||
.m_axi_hbm_bready(m_axi_hbm_bready),
|
||||
.m_axi_hbm_arid(m_axi_hbm_arid),
|
||||
.m_axi_hbm_araddr(m_axi_hbm_araddr),
|
||||
.m_axi_hbm_arlen(m_axi_hbm_arlen),
|
||||
.m_axi_hbm_arsize(m_axi_hbm_arsize),
|
||||
.m_axi_hbm_arburst(m_axi_hbm_arburst),
|
||||
.m_axi_hbm_arlock(m_axi_hbm_arlock),
|
||||
.m_axi_hbm_arcache(m_axi_hbm_arcache),
|
||||
.m_axi_hbm_arprot(m_axi_hbm_arprot),
|
||||
.m_axi_hbm_arqos(m_axi_hbm_arqos),
|
||||
.m_axi_hbm_aruser(m_axi_hbm_aruser),
|
||||
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
|
||||
.m_axi_hbm_arready(m_axi_hbm_arready),
|
||||
.m_axi_hbm_rid(m_axi_hbm_rid),
|
||||
.m_axi_hbm_rdata(m_axi_hbm_rdata),
|
||||
.m_axi_hbm_rresp(m_axi_hbm_rresp),
|
||||
.m_axi_hbm_rlast(m_axi_hbm_rlast),
|
||||
.m_axi_hbm_ruser(m_axi_hbm_ruser),
|
||||
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
|
||||
.m_axi_hbm_rready(m_axi_hbm_rready),
|
||||
|
||||
.hbm_status(hbm_status),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user