diff --git a/docs/source/modules/mqnic_core.rst b/docs/source/modules/mqnic_core.rst index 316ccac47..66281fb18 100644 --- a/docs/source/modules/mqnic_core.rst +++ b/docs/source/modules/mqnic_core.rst @@ -253,6 +253,174 @@ Parameters Receive scratchpad RAM size per interface, default ``32768``. +.. object:: DDR_CH + + Number of DDR memory interfaces, default ``1``. + +.. object:: DDR_ENABLE + + Enable DDR memory interfaces, default ``0``. + +.. object:: DDR_GROUP_SIZE + + DDR channel group size, default ``1``. All channels in each group share the same address space. + +.. object:: AXI_DDR_DATA_WIDTH + + DDR memory interface AXI data width, default ``256``. + +.. object:: AXI_DDR_ADDR_WIDTH + + DDR memory interface AXI address width, default ``32``. + +.. object:: AXI_DDR_STRB_WIDTH + + DDR memory interface AXI strobe width, default ``(AXI_DDR_DATA_WIDTH/8)``. + +.. object:: AXI_DDR_ID_WIDTH + + DDR memory interface AXI ID width, default ``8``. + +.. object:: AXI_DDR_AWUSER_ENABLE + + DDR memory interface AXI AWUSER signal enable, default ``0``. + +.. object:: AXI_DDR_AWUSER_WIDTH + + DDR memory interface AXI AWUSER signal width, default ``1``. + +.. object:: AXI_DDR_WUSER_ENABLE + + DDR memory interface AXI WUSER signal enable, default ``0``. + +.. object:: AXI_DDR_WUSER_WIDTH + + DDR memory interface AXI WUSER signal width, default ``1``. + +.. object:: AXI_DDR_BUSER_ENABLE + + DDR memory interface AXI BUSER signal enable, default ``0``. + +.. object:: AXI_DDR_BUSER_WIDTH + + DDR memory interface AXI BUSER signal width, default ``1``. + +.. object:: AXI_DDR_ARUSER_ENABLE + + DDR memory interface AXI ARUSER signal enable, default ``0``. + +.. object:: AXI_DDR_ARUSER_WIDTH + + DDR memory interface AXI ARUSER signal width, default ``1``. + +.. object:: AXI_DDR_RUSER_ENABLE + + DDR memory interface AXI RUSER signal enable, default ``0``. + +.. object:: AXI_DDR_RUSER_WIDTH + + DDR memory interface AXI RUSER signal width, default ``1``. + +.. object:: AXI_DDR_MAX_BURST_LEN + + DDR memory interface max AXI burst length, default ``256``. + +.. object:: AXI_DDR_NARROW_BURST + + DDR memory interface AXI narrow burst support, default ``0``. + +.. object:: AXI_DDR_FIXED_BURST + + DDR memory interface AXI fixed burst support, default ``0``. + +.. object:: AXI_DDR_WRAP_BURST + + DDR memory interface AXI wrap burst support, default ``0``. + +.. object:: HBM_CH + + Number of HBM memory interfaces, default ``1``. + +.. object:: HBM_ENABLE + + Enable HBM memory interfaces, default ``0``. + +.. object:: HBM_GROUP_SIZE + + HBM channel group size, default ``1``. All channels in each group share the same address space. + +.. object:: AXI_HBM_DATA_WIDTH + + HBM memory interface AXI data width, default ``256``. + +.. object:: AXI_HBM_AHBM_WIDTH + + HBM memory interface AXI address width, default ``32``. + +.. object:: AXI_HBM_STRB_WIDTH + + HBM memory interface AXI strobe width, default ``(AXI_HBM_DATA_WIDTH/8)``. + +.. object:: AXI_HBM_ID_WIDTH + + HBM memory interface AXI ID width, default ``8``. + +.. object:: AXI_HBM_AWUSER_ENABLE + + HBM memory interface AXI AWUSER signal enable, default ``0``. + +.. object:: AXI_HBM_AWUSER_WIDTH + + HBM memory interface AXI AWUSER signal width, default ``1``. + +.. object:: AXI_HBM_WUSER_ENABLE + + HBM memory interface AXI WUSER signal enable, default ``0``. + +.. object:: AXI_HBM_WUSER_WIDTH + + HBM memory interface AXI WUSER signal width, default ``1``. + +.. object:: AXI_HBM_BUSER_ENABLE + + HBM memory interface AXI BUSER signal enable, default ``0``. + +.. object:: AXI_HBM_BUSER_WIDTH + + HBM memory interface AXI BUSER signal width, default ``1``. + +.. object:: AXI_HBM_ARUSER_ENABLE + + HBM memory interface AXI ARUSER signal enable, default ``0``. + +.. object:: AXI_HBM_ARUSER_WIDTH + + HBM memory interface AXI ARUSER signal width, default ``1``. + +.. object:: AXI_HBM_RUSER_ENABLE + + HBM memory interface AXI RUSER signal enable, default ``0``. + +.. object:: AXI_HBM_RUSER_WIDTH + + HBM memory interface AXI RUSER signal width, default ``1``. + +.. object:: AXI_HBM_MAX_BURST_LEN + + HBM memory interface max AXI burst length, default ``256``. + +.. object:: AXI_HBM_NARROW_BURST + + HBM memory interface AXI narrow burst support, default ``0``. + +.. object:: AXI_HBM_FIXED_BURST + + HBM memory interface AXI fixed burst support, default ``0``. + +.. object:: AXI_HBM_WRAP_BURST + + HBM memory interface AXI wrap burst support, default ``0``. + .. object:: APP_ID Application ID, default ``0``. diff --git a/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v b/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v index dfb8a98a9..9e8a94e7d 100644 --- a/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v +++ b/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v @@ -68,6 +68,50 @@ module mqnic_app_block # parameter MAX_TX_SIZE = 9214, parameter MAX_RX_SIZE = 9214, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 0, + parameter DDR_GROUP_SIZE = 1, + parameter AXI_DDR_DATA_WIDTH = 256, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_AWUSER_ENABLE = 0, + parameter AXI_DDR_AWUSER_WIDTH = 1, + parameter AXI_DDR_WUSER_ENABLE = 0, + parameter AXI_DDR_WUSER_WIDTH = 1, + parameter AXI_DDR_BUSER_ENABLE = 0, + parameter AXI_DDR_BUSER_WIDTH = 1, + parameter AXI_DDR_ARUSER_ENABLE = 0, + parameter AXI_DDR_ARUSER_WIDTH = 1, + parameter AXI_DDR_RUSER_ENABLE = 0, + parameter AXI_DDR_RUSER_WIDTH = 1, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + parameter AXI_DDR_FIXED_BURST = 0, + parameter AXI_DDR_WRAP_BURST = 0, + parameter HBM_CH = 1, + parameter HBM_ENABLE = 0, + parameter HBM_GROUP_SIZE = 1, + parameter AXI_HBM_DATA_WIDTH = 256, + parameter AXI_HBM_ADDR_WIDTH = 32, + parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), + parameter AXI_HBM_ID_WIDTH = 8, + parameter AXI_HBM_AWUSER_ENABLE = 0, + parameter AXI_HBM_AWUSER_WIDTH = 1, + parameter AXI_HBM_WUSER_ENABLE = 0, + parameter AXI_HBM_WUSER_WIDTH = 1, + parameter AXI_HBM_BUSER_ENABLE = 0, + parameter AXI_HBM_BUSER_WIDTH = 1, + parameter AXI_HBM_ARUSER_ENABLE = 0, + parameter AXI_HBM_ARUSER_WIDTH = 1, + parameter AXI_HBM_RUSER_ENABLE = 0, + parameter AXI_HBM_RUSER_WIDTH = 1, + parameter AXI_HBM_MAX_BURST_LEN = 256, + parameter AXI_HBM_NARROW_BURST = 0, + parameter AXI_HBM_FIXED_BURST = 0, + parameter AXI_HBM_WRAP_BURST = 0, + // Application configuration parameter APP_ID = 32'h12348001, parameter APP_CTRL_ENABLE = 1, @@ -447,6 +491,108 @@ module mqnic_app_block # output wire [IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0] m_axis_if_rx_tdest, output wire [IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] m_axis_if_rx_tuser, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * HBM + */ + input wire [HBM_CH-1:0] hbm_clk, + input wire [HBM_CH-1:0] hbm_rst, + + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, + output wire [HBM_CH-1:0] m_axi_hbm_awlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, + output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser, + output wire [HBM_CH-1:0] m_axi_hbm_awvalid, + input wire [HBM_CH-1:0] m_axi_hbm_awready, + output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, + output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, + output wire [HBM_CH-1:0] m_axi_hbm_wlast, + output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser, + output wire [HBM_CH-1:0] m_axi_hbm_wvalid, + input wire [HBM_CH-1:0] m_axi_hbm_wready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, + input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, + input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser, + input wire [HBM_CH-1:0] m_axi_hbm_bvalid, + output wire [HBM_CH-1:0] m_axi_hbm_bready, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, + output wire [HBM_CH-1:0] m_axi_hbm_arlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, + output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser, + output wire [HBM_CH-1:0] m_axi_hbm_arvalid, + input wire [HBM_CH-1:0] m_axi_hbm_arready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, + input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, + input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, + input wire [HBM_CH-1:0] m_axi_hbm_rlast, + input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser, + input wire [HBM_CH-1:0] m_axi_hbm_rvalid, + output wire [HBM_CH-1:0] m_axi_hbm_rready, + + input wire [HBM_CH-1:0] hbm_status, + /* * Statistics increment output */ @@ -500,6 +646,30 @@ assign m_axil_ctrl_arprot = 0; assign m_axil_ctrl_arvalid = 1'b0; assign m_axil_ctrl_rready = 1'b1; +/* + * DMA interface (control) + */ +assign m_axis_ctrl_dma_read_desc_dma_addr = 0; +assign m_axis_ctrl_dma_read_desc_ram_sel = 0; +assign m_axis_ctrl_dma_read_desc_ram_addr = 0; +assign m_axis_ctrl_dma_read_desc_len = 0; +assign m_axis_ctrl_dma_read_desc_tag = 0; +assign m_axis_ctrl_dma_read_desc_valid = 1'b0; +assign m_axis_ctrl_dma_write_desc_dma_addr = 0; +assign m_axis_ctrl_dma_write_desc_ram_sel = 0; +assign m_axis_ctrl_dma_write_desc_ram_addr = 0; +assign m_axis_ctrl_dma_write_desc_imm = 0; +assign m_axis_ctrl_dma_write_desc_imm_en = 0; +assign m_axis_ctrl_dma_write_desc_len = 0; +assign m_axis_ctrl_dma_write_desc_tag = 0; +assign m_axis_ctrl_dma_write_desc_valid = 1'b0; + +assign ctrl_dma_ram_wr_cmd_ready = 1'b1; +assign ctrl_dma_ram_wr_done = ctrl_dma_ram_wr_cmd_valid; +assign ctrl_dma_ram_rd_cmd_ready = ctrl_dma_ram_rd_resp_ready; +assign ctrl_dma_ram_rd_resp_data = 0; +assign ctrl_dma_ram_rd_resp_valid = ctrl_dma_ram_rd_cmd_valid; + /* * Ethernet (direct MAC interface - lowest latency raw traffic) */ @@ -571,28 +741,70 @@ assign m_axis_if_rx_tdest = s_axis_if_rx_tdest; assign m_axis_if_rx_tuser = s_axis_if_rx_tuser; /* - * DMA interface (control) + * DDR */ -assign m_axis_ctrl_dma_read_desc_dma_addr = 0; -assign m_axis_ctrl_dma_read_desc_ram_sel = 0; -assign m_axis_ctrl_dma_read_desc_ram_addr = 0; -assign m_axis_ctrl_dma_read_desc_len = 0; -assign m_axis_ctrl_dma_read_desc_tag = 0; -assign m_axis_ctrl_dma_read_desc_valid = 1'b0; -assign m_axis_ctrl_dma_write_desc_dma_addr = 0; -assign m_axis_ctrl_dma_write_desc_ram_sel = 0; -assign m_axis_ctrl_dma_write_desc_ram_addr = 0; -assign m_axis_ctrl_dma_write_desc_imm = 0; -assign m_axis_ctrl_dma_write_desc_imm_en = 0; -assign m_axis_ctrl_dma_write_desc_len = 0; -assign m_axis_ctrl_dma_write_desc_tag = 0; -assign m_axis_ctrl_dma_write_desc_valid = 1'b0; +assign m_axi_ddr_awid = 0; +assign m_axi_ddr_awaddr = 0; +assign m_axi_ddr_awlen = 0; +assign m_axi_ddr_awsize = 0; +assign m_axi_ddr_awburst = 0; +assign m_axi_ddr_awlock = 0; +assign m_axi_ddr_awcache = 0; +assign m_axi_ddr_awprot = 0; +assign m_axi_ddr_awqos = 0; +assign m_axi_ddr_awuser = 0; +assign m_axi_ddr_awvalid = 0; +assign m_axi_ddr_wdata = 0; +assign m_axi_ddr_wstrb = 0; +assign m_axi_ddr_wlast = 0; +assign m_axi_ddr_wuser = 0; +assign m_axi_ddr_wvalid = 0; +assign m_axi_ddr_bready = 0; +assign m_axi_ddr_arid = 0; +assign m_axi_ddr_araddr = 0; +assign m_axi_ddr_arlen = 0; +assign m_axi_ddr_arsize = 0; +assign m_axi_ddr_arburst = 0; +assign m_axi_ddr_arlock = 0; +assign m_axi_ddr_arcache = 0; +assign m_axi_ddr_arprot = 0; +assign m_axi_ddr_arqos = 0; +assign m_axi_ddr_aruser = 0; +assign m_axi_ddr_arvalid = 0; +assign m_axi_ddr_rready = 0; -assign ctrl_dma_ram_wr_cmd_ready = 1'b1; -assign ctrl_dma_ram_wr_done = ctrl_dma_ram_wr_cmd_valid; -assign ctrl_dma_ram_rd_cmd_ready = ctrl_dma_ram_rd_resp_ready; -assign ctrl_dma_ram_rd_resp_data = 0; -assign ctrl_dma_ram_rd_resp_valid = ctrl_dma_ram_rd_cmd_valid; +/* + * HBM + */ +assign m_axi_hbm_awid = 0; +assign m_axi_hbm_awaddr = 0; +assign m_axi_hbm_awlen = 0; +assign m_axi_hbm_awsize = 0; +assign m_axi_hbm_awburst = 0; +assign m_axi_hbm_awlock = 0; +assign m_axi_hbm_awcache = 0; +assign m_axi_hbm_awprot = 0; +assign m_axi_hbm_awqos = 0; +assign m_axi_hbm_awuser = 0; +assign m_axi_hbm_awvalid = 0; +assign m_axi_hbm_wdata = 0; +assign m_axi_hbm_wstrb = 0; +assign m_axi_hbm_wlast = 0; +assign m_axi_hbm_wuser = 0; +assign m_axi_hbm_wvalid = 0; +assign m_axi_hbm_bready = 0; +assign m_axi_hbm_arid = 0; +assign m_axi_hbm_araddr = 0; +assign m_axi_hbm_arlen = 0; +assign m_axi_hbm_arsize = 0; +assign m_axi_hbm_arburst = 0; +assign m_axi_hbm_arlock = 0; +assign m_axi_hbm_arcache = 0; +assign m_axi_hbm_arprot = 0; +assign m_axi_hbm_arqos = 0; +assign m_axi_hbm_aruser = 0; +assign m_axi_hbm_arvalid = 0; +assign m_axi_hbm_rready = 0; /* * Statistics increment output diff --git a/fpga/app/template/rtl/mqnic_app_block.v b/fpga/app/template/rtl/mqnic_app_block.v index 6c91d79f1..adc586929 100644 --- a/fpga/app/template/rtl/mqnic_app_block.v +++ b/fpga/app/template/rtl/mqnic_app_block.v @@ -68,6 +68,50 @@ module mqnic_app_block # parameter MAX_TX_SIZE = 9214, parameter MAX_RX_SIZE = 9214, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 0, + parameter DDR_GROUP_SIZE = 1, + parameter AXI_DDR_DATA_WIDTH = 256, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_AWUSER_ENABLE = 0, + parameter AXI_DDR_AWUSER_WIDTH = 1, + parameter AXI_DDR_WUSER_ENABLE = 0, + parameter AXI_DDR_WUSER_WIDTH = 1, + parameter AXI_DDR_BUSER_ENABLE = 0, + parameter AXI_DDR_BUSER_WIDTH = 1, + parameter AXI_DDR_ARUSER_ENABLE = 0, + parameter AXI_DDR_ARUSER_WIDTH = 1, + parameter AXI_DDR_RUSER_ENABLE = 0, + parameter AXI_DDR_RUSER_WIDTH = 1, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + parameter AXI_DDR_FIXED_BURST = 0, + parameter AXI_DDR_WRAP_BURST = 0, + parameter HBM_CH = 1, + parameter HBM_ENABLE = 0, + parameter HBM_GROUP_SIZE = 1, + parameter AXI_HBM_DATA_WIDTH = 256, + parameter AXI_HBM_ADDR_WIDTH = 32, + parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), + parameter AXI_HBM_ID_WIDTH = 8, + parameter AXI_HBM_AWUSER_ENABLE = 0, + parameter AXI_HBM_AWUSER_WIDTH = 1, + parameter AXI_HBM_WUSER_ENABLE = 0, + parameter AXI_HBM_WUSER_WIDTH = 1, + parameter AXI_HBM_BUSER_ENABLE = 0, + parameter AXI_HBM_BUSER_WIDTH = 1, + parameter AXI_HBM_ARUSER_ENABLE = 0, + parameter AXI_HBM_ARUSER_WIDTH = 1, + parameter AXI_HBM_RUSER_ENABLE = 0, + parameter AXI_HBM_RUSER_WIDTH = 1, + parameter AXI_HBM_MAX_BURST_LEN = 256, + parameter AXI_HBM_NARROW_BURST = 0, + parameter AXI_HBM_FIXED_BURST = 0, + parameter AXI_HBM_WRAP_BURST = 0, + // Application configuration parameter APP_ID = 32'h12340001, parameter APP_CTRL_ENABLE = 1, @@ -447,6 +491,108 @@ module mqnic_app_block # output wire [IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0] m_axis_if_rx_tdest, output wire [IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] m_axis_if_rx_tuser, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * HBM + */ + input wire [HBM_CH-1:0] hbm_clk, + input wire [HBM_CH-1:0] hbm_rst, + + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, + output wire [HBM_CH-1:0] m_axi_hbm_awlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, + output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser, + output wire [HBM_CH-1:0] m_axi_hbm_awvalid, + input wire [HBM_CH-1:0] m_axi_hbm_awready, + output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, + output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, + output wire [HBM_CH-1:0] m_axi_hbm_wlast, + output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser, + output wire [HBM_CH-1:0] m_axi_hbm_wvalid, + input wire [HBM_CH-1:0] m_axi_hbm_wready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, + input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, + input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser, + input wire [HBM_CH-1:0] m_axi_hbm_bvalid, + output wire [HBM_CH-1:0] m_axi_hbm_bready, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, + output wire [HBM_CH-1:0] m_axi_hbm_arlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, + output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser, + output wire [HBM_CH-1:0] m_axi_hbm_arvalid, + input wire [HBM_CH-1:0] m_axi_hbm_arready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, + input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, + input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, + input wire [HBM_CH-1:0] m_axi_hbm_rlast, + input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser, + input wire [HBM_CH-1:0] m_axi_hbm_rvalid, + output wire [HBM_CH-1:0] m_axi_hbm_rready, + + input wire [HBM_CH-1:0] hbm_status, + /* * Statistics increment output */ @@ -527,6 +673,54 @@ assign m_axil_ctrl_arprot = 0; assign m_axil_ctrl_arvalid = 1'b0; assign m_axil_ctrl_rready = 1'b1; +/* + * DMA interface (control) + */ +assign m_axis_ctrl_dma_read_desc_dma_addr = 0; +assign m_axis_ctrl_dma_read_desc_ram_sel = 0; +assign m_axis_ctrl_dma_read_desc_ram_addr = 0; +assign m_axis_ctrl_dma_read_desc_len = 0; +assign m_axis_ctrl_dma_read_desc_tag = 0; +assign m_axis_ctrl_dma_read_desc_valid = 1'b0; +assign m_axis_ctrl_dma_write_desc_dma_addr = 0; +assign m_axis_ctrl_dma_write_desc_ram_sel = 0; +assign m_axis_ctrl_dma_write_desc_ram_addr = 0; +assign m_axis_ctrl_dma_write_desc_imm = 0; +assign m_axis_ctrl_dma_write_desc_imm_en = 0; +assign m_axis_ctrl_dma_write_desc_len = 0; +assign m_axis_ctrl_dma_write_desc_tag = 0; +assign m_axis_ctrl_dma_write_desc_valid = 1'b0; + +assign ctrl_dma_ram_wr_cmd_ready = 1'b1; +assign ctrl_dma_ram_wr_done = ctrl_dma_ram_wr_cmd_valid; +assign ctrl_dma_ram_rd_cmd_ready = ctrl_dma_ram_rd_resp_ready; +assign ctrl_dma_ram_rd_resp_data = 0; +assign ctrl_dma_ram_rd_resp_valid = ctrl_dma_ram_rd_cmd_valid; + +/* + * DMA interface (data) + */ +assign m_axis_data_dma_read_desc_dma_addr = 0; +assign m_axis_data_dma_read_desc_ram_sel = 0; +assign m_axis_data_dma_read_desc_ram_addr = 0; +assign m_axis_data_dma_read_desc_len = 0; +assign m_axis_data_dma_read_desc_tag = 0; +assign m_axis_data_dma_read_desc_valid = 1'b0; +assign m_axis_data_dma_write_desc_dma_addr = 0; +assign m_axis_data_dma_write_desc_ram_sel = 0; +assign m_axis_data_dma_write_desc_ram_addr = 0; +assign m_axis_data_dma_write_desc_imm = 0; +assign m_axis_data_dma_write_desc_imm_en = 0; +assign m_axis_data_dma_write_desc_len = 0; +assign m_axis_data_dma_write_desc_tag = 0; +assign m_axis_data_dma_write_desc_valid = 1'b0; + +assign data_dma_ram_wr_cmd_ready = 1'b1; +assign data_dma_ram_wr_done = data_dma_ram_wr_cmd_valid; +assign data_dma_ram_rd_cmd_ready = data_dma_ram_rd_resp_ready; +assign data_dma_ram_rd_resp_data = 0; +assign data_dma_ram_rd_resp_valid = data_dma_ram_rd_cmd_valid; + /* * Ethernet (direct MAC interface - lowest latency raw traffic) */ @@ -598,52 +792,70 @@ assign m_axis_if_rx_tdest = s_axis_if_rx_tdest; assign m_axis_if_rx_tuser = s_axis_if_rx_tuser; /* - * DMA interface (control) + * DDR */ -assign m_axis_ctrl_dma_read_desc_dma_addr = 0; -assign m_axis_ctrl_dma_read_desc_ram_sel = 0; -assign m_axis_ctrl_dma_read_desc_ram_addr = 0; -assign m_axis_ctrl_dma_read_desc_len = 0; -assign m_axis_ctrl_dma_read_desc_tag = 0; -assign m_axis_ctrl_dma_read_desc_valid = 1'b0; -assign m_axis_ctrl_dma_write_desc_dma_addr = 0; -assign m_axis_ctrl_dma_write_desc_ram_sel = 0; -assign m_axis_ctrl_dma_write_desc_ram_addr = 0; -assign m_axis_ctrl_dma_write_desc_imm = 0; -assign m_axis_ctrl_dma_write_desc_imm_en = 0; -assign m_axis_ctrl_dma_write_desc_len = 0; -assign m_axis_ctrl_dma_write_desc_tag = 0; -assign m_axis_ctrl_dma_write_desc_valid = 1'b0; - -assign ctrl_dma_ram_wr_cmd_ready = 1'b1; -assign ctrl_dma_ram_wr_done = ctrl_dma_ram_wr_cmd_valid; -assign ctrl_dma_ram_rd_cmd_ready = ctrl_dma_ram_rd_resp_ready; -assign ctrl_dma_ram_rd_resp_data = 0; -assign ctrl_dma_ram_rd_resp_valid = ctrl_dma_ram_rd_cmd_valid; +assign m_axi_ddr_awid = 0; +assign m_axi_ddr_awaddr = 0; +assign m_axi_ddr_awlen = 0; +assign m_axi_ddr_awsize = 0; +assign m_axi_ddr_awburst = 0; +assign m_axi_ddr_awlock = 0; +assign m_axi_ddr_awcache = 0; +assign m_axi_ddr_awprot = 0; +assign m_axi_ddr_awqos = 0; +assign m_axi_ddr_awuser = 0; +assign m_axi_ddr_awvalid = 0; +assign m_axi_ddr_wdata = 0; +assign m_axi_ddr_wstrb = 0; +assign m_axi_ddr_wlast = 0; +assign m_axi_ddr_wuser = 0; +assign m_axi_ddr_wvalid = 0; +assign m_axi_ddr_bready = 0; +assign m_axi_ddr_arid = 0; +assign m_axi_ddr_araddr = 0; +assign m_axi_ddr_arlen = 0; +assign m_axi_ddr_arsize = 0; +assign m_axi_ddr_arburst = 0; +assign m_axi_ddr_arlock = 0; +assign m_axi_ddr_arcache = 0; +assign m_axi_ddr_arprot = 0; +assign m_axi_ddr_arqos = 0; +assign m_axi_ddr_aruser = 0; +assign m_axi_ddr_arvalid = 0; +assign m_axi_ddr_rready = 0; /* - * DMA interface (data) + * HBM */ -assign m_axis_data_dma_read_desc_dma_addr = 0; -assign m_axis_data_dma_read_desc_ram_sel = 0; -assign m_axis_data_dma_read_desc_ram_addr = 0; -assign m_axis_data_dma_read_desc_len = 0; -assign m_axis_data_dma_read_desc_tag = 0; -assign m_axis_data_dma_read_desc_valid = 1'b0; -assign m_axis_data_dma_write_desc_dma_addr = 0; -assign m_axis_data_dma_write_desc_ram_sel = 0; -assign m_axis_data_dma_write_desc_ram_addr = 0; -assign m_axis_data_dma_write_desc_imm = 0; -assign m_axis_data_dma_write_desc_imm_en = 0; -assign m_axis_data_dma_write_desc_len = 0; -assign m_axis_data_dma_write_desc_tag = 0; -assign m_axis_data_dma_write_desc_valid = 1'b0; - -assign data_dma_ram_wr_cmd_ready = 1'b1; -assign data_dma_ram_wr_done = data_dma_ram_wr_cmd_valid; -assign data_dma_ram_rd_cmd_ready = data_dma_ram_rd_resp_ready; -assign data_dma_ram_rd_resp_data = 0; -assign data_dma_ram_rd_resp_valid = data_dma_ram_rd_cmd_valid; +assign m_axi_hbm_awid = 0; +assign m_axi_hbm_awaddr = 0; +assign m_axi_hbm_awlen = 0; +assign m_axi_hbm_awsize = 0; +assign m_axi_hbm_awburst = 0; +assign m_axi_hbm_awlock = 0; +assign m_axi_hbm_awcache = 0; +assign m_axi_hbm_awprot = 0; +assign m_axi_hbm_awqos = 0; +assign m_axi_hbm_awuser = 0; +assign m_axi_hbm_awvalid = 0; +assign m_axi_hbm_wdata = 0; +assign m_axi_hbm_wstrb = 0; +assign m_axi_hbm_wlast = 0; +assign m_axi_hbm_wuser = 0; +assign m_axi_hbm_wvalid = 0; +assign m_axi_hbm_bready = 0; +assign m_axi_hbm_arid = 0; +assign m_axi_hbm_araddr = 0; +assign m_axi_hbm_arlen = 0; +assign m_axi_hbm_arsize = 0; +assign m_axi_hbm_arburst = 0; +assign m_axi_hbm_arlock = 0; +assign m_axi_hbm_arcache = 0; +assign m_axi_hbm_arprot = 0; +assign m_axi_hbm_arqos = 0; +assign m_axi_hbm_aruser = 0; +assign m_axi_hbm_arvalid = 0; +assign m_axi_hbm_rready = 0; /* * Statistics increment output diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index 62d57725d..15d872364 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -118,6 +118,50 @@ module mqnic_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 0, + parameter DDR_GROUP_SIZE = 1, + parameter AXI_DDR_DATA_WIDTH = 256, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_AWUSER_ENABLE = 0, + parameter AXI_DDR_AWUSER_WIDTH = 1, + parameter AXI_DDR_WUSER_ENABLE = 0, + parameter AXI_DDR_WUSER_WIDTH = 1, + parameter AXI_DDR_BUSER_ENABLE = 0, + parameter AXI_DDR_BUSER_WIDTH = 1, + parameter AXI_DDR_ARUSER_ENABLE = 0, + parameter AXI_DDR_ARUSER_WIDTH = 1, + parameter AXI_DDR_RUSER_ENABLE = 0, + parameter AXI_DDR_RUSER_WIDTH = 1, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + parameter AXI_DDR_FIXED_BURST = 0, + parameter AXI_DDR_WRAP_BURST = 0, + parameter HBM_CH = 1, + parameter HBM_ENABLE = 0, + parameter HBM_GROUP_SIZE = 1, + parameter AXI_HBM_DATA_WIDTH = 256, + parameter AXI_HBM_ADDR_WIDTH = 32, + parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), + parameter AXI_HBM_ID_WIDTH = 8, + parameter AXI_HBM_AWUSER_ENABLE = 0, + parameter AXI_HBM_AWUSER_WIDTH = 1, + parameter AXI_HBM_WUSER_ENABLE = 0, + parameter AXI_HBM_WUSER_WIDTH = 1, + parameter AXI_HBM_BUSER_ENABLE = 0, + parameter AXI_HBM_BUSER_WIDTH = 1, + parameter AXI_HBM_ARUSER_ENABLE = 0, + parameter AXI_HBM_ARUSER_WIDTH = 1, + parameter AXI_HBM_RUSER_ENABLE = 0, + parameter AXI_HBM_RUSER_WIDTH = 1, + parameter AXI_HBM_MAX_BURST_LEN = 256, + parameter AXI_HBM_NARROW_BURST = 0, + parameter AXI_HBM_FIXED_BURST = 0, + parameter AXI_HBM_WRAP_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -416,6 +460,108 @@ module mqnic_core # input wire [PORT_COUNT-1:0] rx_status, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * HBM + */ + input wire [HBM_CH-1:0] hbm_clk, + input wire [HBM_CH-1:0] hbm_rst, + + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, + output wire [HBM_CH-1:0] m_axi_hbm_awlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, + output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser, + output wire [HBM_CH-1:0] m_axi_hbm_awvalid, + input wire [HBM_CH-1:0] m_axi_hbm_awready, + output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, + output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, + output wire [HBM_CH-1:0] m_axi_hbm_wlast, + output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser, + output wire [HBM_CH-1:0] m_axi_hbm_wvalid, + input wire [HBM_CH-1:0] m_axi_hbm_wready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, + input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, + input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser, + input wire [HBM_CH-1:0] m_axi_hbm_bvalid, + output wire [HBM_CH-1:0] m_axi_hbm_bready, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, + output wire [HBM_CH-1:0] m_axi_hbm_arlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, + output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser, + output wire [HBM_CH-1:0] m_axi_hbm_arvalid, + input wire [HBM_CH-1:0] m_axi_hbm_arready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, + input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, + input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, + input wire [HBM_CH-1:0] m_axi_hbm_rlast, + input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser, + input wire [HBM_CH-1:0] m_axi_hbm_rvalid, + output wire [HBM_CH-1:0] m_axi_hbm_rready, + + input wire [HBM_CH-1:0] hbm_status, + /* * Statistics increment input */ @@ -2956,6 +3102,50 @@ if (APP_ENABLE) begin : app .MAX_TX_SIZE(MAX_TX_SIZE), .MAX_RX_SIZE(MAX_RX_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(DDR_GROUP_SIZE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE), + .AXI_DDR_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH), + .AXI_DDR_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE), + .AXI_DDR_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH), + .AXI_DDR_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE), + .AXI_DDR_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH), + .AXI_DDR_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE), + .AXI_DDR_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH), + .AXI_DDR_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE), + .AXI_DDR_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(AXI_DDR_FIXED_BURST), + .AXI_DDR_WRAP_BURST(AXI_DDR_WRAP_BURST), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE), + .AXI_HBM_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH), + .AXI_HBM_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE), + .AXI_HBM_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH), + .AXI_HBM_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE), + .AXI_HBM_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH), + .AXI_HBM_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE), + .AXI_HBM_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH), + .AXI_HBM_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE), + .AXI_HBM_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + .AXI_HBM_NARROW_BURST(AXI_HBM_NARROW_BURST), + .AXI_HBM_FIXED_BURST(AXI_HBM_FIXED_BURST), + .AXI_HBM_WRAP_BURST(AXI_HBM_WRAP_BURST), + // Application configuration .APP_ID(APP_ID), .APP_CTRL_ENABLE(APP_CTRL_ENABLE), @@ -3333,6 +3523,108 @@ if (APP_ENABLE) begin : app .m_axis_if_rx_tdest(app_m_axis_if_rx_tdest), .m_axis_if_rx_tuser(app_m_axis_if_rx_tuser), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(m_axi_ddr_awuser), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(m_axi_ddr_wuser), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(m_axi_ddr_buser), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(m_axi_ddr_aruser), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(m_axi_ddr_ruser), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awuser(m_axi_hbm_awuser), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wuser(m_axi_hbm_wuser), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_buser(m_axi_hbm_buser), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_aruser(m_axi_hbm_aruser), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_ruser(m_axi_hbm_ruser), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + /* * Statistics increment output */ @@ -3493,6 +3785,66 @@ end else begin assign app_m_axis_if_rx_tdest = 0; assign app_m_axis_if_rx_tuser = 0; + assign m_axi_ddr_awid = 0; + assign m_axi_ddr_awaddr = 0; + assign m_axi_ddr_awlen = 0; + assign m_axi_ddr_awsize = 0; + assign m_axi_ddr_awburst = 0; + assign m_axi_ddr_awlock = 0; + assign m_axi_ddr_awcache = 0; + assign m_axi_ddr_awprot = 0; + assign m_axi_ddr_awqos = 0; + assign m_axi_ddr_awuser = 0; + assign m_axi_ddr_awvalid = 0; + assign m_axi_ddr_wdata = 0; + assign m_axi_ddr_wstrb = 0; + assign m_axi_ddr_wlast = 0; + assign m_axi_ddr_wuser = 0; + assign m_axi_ddr_wvalid = 0; + assign m_axi_ddr_bready = 0; + assign m_axi_ddr_arid = 0; + assign m_axi_ddr_araddr = 0; + assign m_axi_ddr_arlen = 0; + assign m_axi_ddr_arsize = 0; + assign m_axi_ddr_arburst = 0; + assign m_axi_ddr_arlock = 0; + assign m_axi_ddr_arcache = 0; + assign m_axi_ddr_arprot = 0; + assign m_axi_ddr_arqos = 0; + assign m_axi_ddr_aruser = 0; + assign m_axi_ddr_arvalid = 0; + assign m_axi_ddr_rready = 0; + + assign m_axi_hbm_awid = 0; + assign m_axi_hbm_awaddr = 0; + assign m_axi_hbm_awlen = 0; + assign m_axi_hbm_awsize = 0; + assign m_axi_hbm_awburst = 0; + assign m_axi_hbm_awlock = 0; + assign m_axi_hbm_awcache = 0; + assign m_axi_hbm_awprot = 0; + assign m_axi_hbm_awqos = 0; + assign m_axi_hbm_awuser = 0; + assign m_axi_hbm_awvalid = 0; + assign m_axi_hbm_wdata = 0; + assign m_axi_hbm_wstrb = 0; + assign m_axi_hbm_wlast = 0; + assign m_axi_hbm_wuser = 0; + assign m_axi_hbm_wvalid = 0; + assign m_axi_hbm_bready = 0; + assign m_axi_hbm_arid = 0; + assign m_axi_hbm_araddr = 0; + assign m_axi_hbm_arlen = 0; + assign m_axi_hbm_arsize = 0; + assign m_axi_hbm_arburst = 0; + assign m_axi_hbm_arlock = 0; + assign m_axi_hbm_arcache = 0; + assign m_axi_hbm_arprot = 0; + assign m_axi_hbm_arqos = 0; + assign m_axi_hbm_aruser = 0; + assign m_axi_hbm_arvalid = 0; + assign m_axi_hbm_rready = 0; + assign axis_app_stat_tdata = 0; assign axis_app_stat_tid = 0; assign axis_app_stat_tvalid = 1'b0; diff --git a/fpga/common/rtl/mqnic_core_axi.v b/fpga/common/rtl/mqnic_core_axi.v index 5219052ef..eed53e193 100644 --- a/fpga/common/rtl/mqnic_core_axi.v +++ b/fpga/common/rtl/mqnic_core_axi.v @@ -118,6 +118,50 @@ module mqnic_core_axi # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 0, + parameter DDR_GROUP_SIZE = 1, + parameter AXI_DDR_DATA_WIDTH = 256, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_AWUSER_ENABLE = 0, + parameter AXI_DDR_AWUSER_WIDTH = 1, + parameter AXI_DDR_WUSER_ENABLE = 0, + parameter AXI_DDR_WUSER_WIDTH = 1, + parameter AXI_DDR_BUSER_ENABLE = 0, + parameter AXI_DDR_BUSER_WIDTH = 1, + parameter AXI_DDR_ARUSER_ENABLE = 0, + parameter AXI_DDR_ARUSER_WIDTH = 1, + parameter AXI_DDR_RUSER_ENABLE = 0, + parameter AXI_DDR_RUSER_WIDTH = 1, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + parameter AXI_DDR_FIXED_BURST = 0, + parameter AXI_DDR_WRAP_BURST = 0, + parameter HBM_CH = 1, + parameter HBM_ENABLE = 0, + parameter HBM_GROUP_SIZE = 1, + parameter AXI_HBM_DATA_WIDTH = 256, + parameter AXI_HBM_ADDR_WIDTH = 32, + parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), + parameter AXI_HBM_ID_WIDTH = 8, + parameter AXI_HBM_AWUSER_ENABLE = 0, + parameter AXI_HBM_AWUSER_WIDTH = 1, + parameter AXI_HBM_WUSER_ENABLE = 0, + parameter AXI_HBM_WUSER_WIDTH = 1, + parameter AXI_HBM_BUSER_ENABLE = 0, + parameter AXI_HBM_BUSER_WIDTH = 1, + parameter AXI_HBM_ARUSER_ENABLE = 0, + parameter AXI_HBM_ARUSER_WIDTH = 1, + parameter AXI_HBM_RUSER_ENABLE = 0, + parameter AXI_HBM_RUSER_WIDTH = 1, + parameter AXI_HBM_MAX_BURST_LEN = 256, + parameter AXI_HBM_NARROW_BURST = 0, + parameter AXI_HBM_FIXED_BURST = 0, + parameter AXI_HBM_WRAP_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -378,6 +422,109 @@ module mqnic_core_axi # input wire [PORT_COUNT-1:0] rx_status, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * HBM + */ + input wire [HBM_CH-1:0] hbm_clk, + input wire [HBM_CH-1:0] hbm_rst, + + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, + output wire [HBM_CH-1:0] m_axi_hbm_awlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, + output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser, + output wire [HBM_CH-1:0] m_axi_hbm_awvalid, + input wire [HBM_CH-1:0] m_axi_hbm_awready, + output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, + output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, + output wire [HBM_CH-1:0] m_axi_hbm_wlast, + output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser, + output wire [HBM_CH-1:0] m_axi_hbm_wvalid, + input wire [HBM_CH-1:0] m_axi_hbm_wready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, + input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, + input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser, + input wire [HBM_CH-1:0] m_axi_hbm_bvalid, + output wire [HBM_CH-1:0] m_axi_hbm_bready, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, + output wire [HBM_CH-1:0] m_axi_hbm_arlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, + output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser, + output wire [HBM_CH-1:0] m_axi_hbm_arvalid, + input wire [HBM_CH-1:0] m_axi_hbm_arready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, + input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, + input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, + input wire [HBM_CH-1:0] m_axi_hbm_rlast, + input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser, + input wire [HBM_CH-1:0] m_axi_hbm_rvalid, + output wire [HBM_CH-1:0] m_axi_hbm_rready, + + input wire [HBM_CH-1:0] hbm_status, + /* * Statistics increment input */ @@ -882,6 +1029,50 @@ mqnic_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(DDR_GROUP_SIZE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE), + .AXI_DDR_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH), + .AXI_DDR_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE), + .AXI_DDR_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH), + .AXI_DDR_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE), + .AXI_DDR_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH), + .AXI_DDR_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE), + .AXI_DDR_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH), + .AXI_DDR_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE), + .AXI_DDR_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(AXI_DDR_FIXED_BURST), + .AXI_DDR_WRAP_BURST(AXI_DDR_WRAP_BURST), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE), + .AXI_HBM_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH), + .AXI_HBM_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE), + .AXI_HBM_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH), + .AXI_HBM_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE), + .AXI_HBM_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH), + .AXI_HBM_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE), + .AXI_HBM_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH), + .AXI_HBM_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE), + .AXI_HBM_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + .AXI_HBM_NARROW_BURST(AXI_HBM_NARROW_BURST), + .AXI_HBM_FIXED_BURST(AXI_HBM_FIXED_BURST), + .AXI_HBM_WRAP_BURST(AXI_HBM_WRAP_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1154,6 +1345,108 @@ core_inst ( .rx_status(rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(m_axi_ddr_awuser), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(m_axi_ddr_wuser), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(m_axi_ddr_buser), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(m_axi_ddr_aruser), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(m_axi_ddr_ruser), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awuser(m_axi_hbm_awuser), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wuser(m_axi_hbm_wuser), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_buser(m_axi_hbm_buser), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_aruser(m_axi_hbm_aruser), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_ruser(m_axi_hbm_ruser), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + /* * Statistics input */ diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v index 358e9ba43..5ac394bc9 100644 --- a/fpga/common/rtl/mqnic_core_pcie.v +++ b/fpga/common/rtl/mqnic_core_pcie.v @@ -118,6 +118,50 @@ module mqnic_core_pcie # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 0, + parameter DDR_GROUP_SIZE = 1, + parameter AXI_DDR_DATA_WIDTH = 256, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_AWUSER_ENABLE = 0, + parameter AXI_DDR_AWUSER_WIDTH = 1, + parameter AXI_DDR_WUSER_ENABLE = 0, + parameter AXI_DDR_WUSER_WIDTH = 1, + parameter AXI_DDR_BUSER_ENABLE = 0, + parameter AXI_DDR_BUSER_WIDTH = 1, + parameter AXI_DDR_ARUSER_ENABLE = 0, + parameter AXI_DDR_ARUSER_WIDTH = 1, + parameter AXI_DDR_RUSER_ENABLE = 0, + parameter AXI_DDR_RUSER_WIDTH = 1, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + parameter AXI_DDR_FIXED_BURST = 0, + parameter AXI_DDR_WRAP_BURST = 0, + parameter HBM_CH = 1, + parameter HBM_ENABLE = 0, + parameter HBM_GROUP_SIZE = 1, + parameter AXI_HBM_DATA_WIDTH = 256, + parameter AXI_HBM_ADDR_WIDTH = 32, + parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), + parameter AXI_HBM_ID_WIDTH = 8, + parameter AXI_HBM_AWUSER_ENABLE = 0, + parameter AXI_HBM_AWUSER_WIDTH = 1, + parameter AXI_HBM_WUSER_ENABLE = 0, + parameter AXI_HBM_WUSER_WIDTH = 1, + parameter AXI_HBM_BUSER_ENABLE = 0, + parameter AXI_HBM_BUSER_WIDTH = 1, + parameter AXI_HBM_ARUSER_ENABLE = 0, + parameter AXI_HBM_ARUSER_WIDTH = 1, + parameter AXI_HBM_RUSER_ENABLE = 0, + parameter AXI_HBM_RUSER_WIDTH = 1, + parameter AXI_HBM_MAX_BURST_LEN = 256, + parameter AXI_HBM_NARROW_BURST = 0, + parameter AXI_HBM_FIXED_BURST = 0, + parameter AXI_HBM_WRAP_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -392,6 +436,107 @@ module mqnic_core_pcie # input wire [PORT_COUNT-1:0] rx_status, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * HBM + */ + input wire [HBM_CH-1:0] hbm_clk, + input wire [HBM_CH-1:0] hbm_rst, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, + output wire [HBM_CH-1:0] m_axi_hbm_awlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, + output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser, + output wire [HBM_CH-1:0] m_axi_hbm_awvalid, + input wire [HBM_CH-1:0] m_axi_hbm_awready, + output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, + output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, + output wire [HBM_CH-1:0] m_axi_hbm_wlast, + output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser, + output wire [HBM_CH-1:0] m_axi_hbm_wvalid, + input wire [HBM_CH-1:0] m_axi_hbm_wready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, + input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, + input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser, + input wire [HBM_CH-1:0] m_axi_hbm_bvalid, + output wire [HBM_CH-1:0] m_axi_hbm_bready, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, + output wire [HBM_CH-1:0] m_axi_hbm_arlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, + output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser, + output wire [HBM_CH-1:0] m_axi_hbm_arvalid, + input wire [HBM_CH-1:0] m_axi_hbm_arready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, + input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, + input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, + input wire [HBM_CH-1:0] m_axi_hbm_rlast, + input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser, + input wire [HBM_CH-1:0] m_axi_hbm_rvalid, + output wire [HBM_CH-1:0] m_axi_hbm_rready, + + input wire [HBM_CH-1:0] hbm_status, + /* * Statistics increment input */ @@ -1514,6 +1659,50 @@ mqnic_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(DDR_GROUP_SIZE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE), + .AXI_DDR_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH), + .AXI_DDR_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE), + .AXI_DDR_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH), + .AXI_DDR_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE), + .AXI_DDR_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH), + .AXI_DDR_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE), + .AXI_DDR_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH), + .AXI_DDR_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE), + .AXI_DDR_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(AXI_DDR_FIXED_BURST), + .AXI_DDR_WRAP_BURST(AXI_DDR_WRAP_BURST), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE), + .AXI_HBM_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH), + .AXI_HBM_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE), + .AXI_HBM_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH), + .AXI_HBM_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE), + .AXI_HBM_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH), + .AXI_HBM_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE), + .AXI_HBM_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH), + .AXI_HBM_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE), + .AXI_HBM_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + .AXI_HBM_NARROW_BURST(AXI_HBM_NARROW_BURST), + .AXI_HBM_FIXED_BURST(AXI_HBM_FIXED_BURST), + .AXI_HBM_WRAP_BURST(AXI_HBM_WRAP_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1810,6 +1999,108 @@ core_inst ( .rx_status(rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(m_axi_ddr_awuser), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(m_axi_ddr_wuser), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(m_axi_ddr_buser), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(m_axi_ddr_aruser), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(m_axi_ddr_ruser), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awuser(m_axi_hbm_awuser), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wuser(m_axi_hbm_wuser), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_buser(m_axi_hbm_buser), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_aruser(m_axi_hbm_aruser), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_ruser(m_axi_hbm_ruser), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + /* * Statistics input */ diff --git a/fpga/common/rtl/mqnic_core_pcie_ptile.v b/fpga/common/rtl/mqnic_core_pcie_ptile.v index 6ffb463e1..e0c9634de 100644 --- a/fpga/common/rtl/mqnic_core_pcie_ptile.v +++ b/fpga/common/rtl/mqnic_core_pcie_ptile.v @@ -118,6 +118,50 @@ module mqnic_core_pcie_ptile # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 0, + parameter DDR_GROUP_SIZE = 1, + parameter AXI_DDR_DATA_WIDTH = 256, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_AWUSER_ENABLE = 0, + parameter AXI_DDR_AWUSER_WIDTH = 1, + parameter AXI_DDR_WUSER_ENABLE = 0, + parameter AXI_DDR_WUSER_WIDTH = 1, + parameter AXI_DDR_BUSER_ENABLE = 0, + parameter AXI_DDR_BUSER_WIDTH = 1, + parameter AXI_DDR_ARUSER_ENABLE = 0, + parameter AXI_DDR_ARUSER_WIDTH = 1, + parameter AXI_DDR_RUSER_ENABLE = 0, + parameter AXI_DDR_RUSER_WIDTH = 1, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + parameter AXI_DDR_FIXED_BURST = 0, + parameter AXI_DDR_WRAP_BURST = 0, + parameter HBM_CH = 1, + parameter HBM_ENABLE = 0, + parameter HBM_GROUP_SIZE = 1, + parameter AXI_HBM_DATA_WIDTH = 256, + parameter AXI_HBM_ADDR_WIDTH = 32, + parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), + parameter AXI_HBM_ID_WIDTH = 8, + parameter AXI_HBM_AWUSER_ENABLE = 0, + parameter AXI_HBM_AWUSER_WIDTH = 1, + parameter AXI_HBM_WUSER_ENABLE = 0, + parameter AXI_HBM_WUSER_WIDTH = 1, + parameter AXI_HBM_BUSER_ENABLE = 0, + parameter AXI_HBM_BUSER_WIDTH = 1, + parameter AXI_HBM_ARUSER_ENABLE = 0, + parameter AXI_HBM_ARUSER_WIDTH = 1, + parameter AXI_HBM_RUSER_ENABLE = 0, + parameter AXI_HBM_RUSER_WIDTH = 1, + parameter AXI_HBM_MAX_BURST_LEN = 256, + parameter AXI_HBM_NARROW_BURST = 0, + parameter AXI_HBM_FIXED_BURST = 0, + parameter AXI_HBM_WRAP_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -341,6 +385,108 @@ module mqnic_core_pcie_ptile # input wire [PORT_COUNT-1:0] eth_rx_status, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * HBM + */ + input wire [HBM_CH-1:0] hbm_clk, + input wire [HBM_CH-1:0] hbm_rst, + + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, + output wire [HBM_CH-1:0] m_axi_hbm_awlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, + output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser, + output wire [HBM_CH-1:0] m_axi_hbm_awvalid, + input wire [HBM_CH-1:0] m_axi_hbm_awready, + output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, + output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, + output wire [HBM_CH-1:0] m_axi_hbm_wlast, + output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser, + output wire [HBM_CH-1:0] m_axi_hbm_wvalid, + input wire [HBM_CH-1:0] m_axi_hbm_wready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, + input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, + input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser, + input wire [HBM_CH-1:0] m_axi_hbm_bvalid, + output wire [HBM_CH-1:0] m_axi_hbm_bready, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, + output wire [HBM_CH-1:0] m_axi_hbm_arlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, + output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser, + output wire [HBM_CH-1:0] m_axi_hbm_arvalid, + input wire [HBM_CH-1:0] m_axi_hbm_arready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, + input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, + input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, + input wire [HBM_CH-1:0] m_axi_hbm_rlast, + input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser, + input wire [HBM_CH-1:0] m_axi_hbm_rvalid, + output wire [HBM_CH-1:0] m_axi_hbm_rready, + + input wire [HBM_CH-1:0] hbm_status, + /* * Statistics increment input */ @@ -679,6 +825,50 @@ mqnic_core_pcie #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(DDR_GROUP_SIZE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE), + .AXI_DDR_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH), + .AXI_DDR_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE), + .AXI_DDR_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH), + .AXI_DDR_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE), + .AXI_DDR_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH), + .AXI_DDR_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE), + .AXI_DDR_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH), + .AXI_DDR_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE), + .AXI_DDR_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(AXI_DDR_FIXED_BURST), + .AXI_DDR_WRAP_BURST(AXI_DDR_WRAP_BURST), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE), + .AXI_HBM_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH), + .AXI_HBM_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE), + .AXI_HBM_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH), + .AXI_HBM_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE), + .AXI_HBM_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH), + .AXI_HBM_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE), + .AXI_HBM_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH), + .AXI_HBM_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE), + .AXI_HBM_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + .AXI_HBM_NARROW_BURST(AXI_HBM_NARROW_BURST), + .AXI_HBM_FIXED_BURST(AXI_HBM_FIXED_BURST), + .AXI_HBM_WRAP_BURST(AXI_HBM_WRAP_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -951,6 +1141,108 @@ core_pcie_inst ( .rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(m_axi_ddr_awuser), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(m_axi_ddr_wuser), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(m_axi_ddr_buser), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(m_axi_ddr_aruser), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(m_axi_ddr_ruser), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awuser(m_axi_hbm_awuser), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wuser(m_axi_hbm_wuser), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_buser(m_axi_hbm_buser), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_aruser(m_axi_hbm_aruser), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_ruser(m_axi_hbm_ruser), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + /* * Statistics input */ diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v index 3561ae6a2..c5493b5e2 100644 --- a/fpga/common/rtl/mqnic_core_pcie_s10.v +++ b/fpga/common/rtl/mqnic_core_pcie_s10.v @@ -118,6 +118,50 @@ module mqnic_core_pcie_s10 # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 0, + parameter DDR_GROUP_SIZE = 1, + parameter AXI_DDR_DATA_WIDTH = 256, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_AWUSER_ENABLE = 0, + parameter AXI_DDR_AWUSER_WIDTH = 1, + parameter AXI_DDR_WUSER_ENABLE = 0, + parameter AXI_DDR_WUSER_WIDTH = 1, + parameter AXI_DDR_BUSER_ENABLE = 0, + parameter AXI_DDR_BUSER_WIDTH = 1, + parameter AXI_DDR_ARUSER_ENABLE = 0, + parameter AXI_DDR_ARUSER_WIDTH = 1, + parameter AXI_DDR_RUSER_ENABLE = 0, + parameter AXI_DDR_RUSER_WIDTH = 1, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + parameter AXI_DDR_FIXED_BURST = 0, + parameter AXI_DDR_WRAP_BURST = 0, + parameter HBM_CH = 1, + parameter HBM_ENABLE = 0, + parameter HBM_GROUP_SIZE = 1, + parameter AXI_HBM_DATA_WIDTH = 256, + parameter AXI_HBM_ADDR_WIDTH = 32, + parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), + parameter AXI_HBM_ID_WIDTH = 8, + parameter AXI_HBM_AWUSER_ENABLE = 0, + parameter AXI_HBM_AWUSER_WIDTH = 1, + parameter AXI_HBM_WUSER_ENABLE = 0, + parameter AXI_HBM_WUSER_WIDTH = 1, + parameter AXI_HBM_BUSER_ENABLE = 0, + parameter AXI_HBM_BUSER_WIDTH = 1, + parameter AXI_HBM_ARUSER_ENABLE = 0, + parameter AXI_HBM_ARUSER_WIDTH = 1, + parameter AXI_HBM_RUSER_ENABLE = 0, + parameter AXI_HBM_RUSER_WIDTH = 1, + parameter AXI_HBM_MAX_BURST_LEN = 256, + parameter AXI_HBM_NARROW_BURST = 0, + parameter AXI_HBM_FIXED_BURST = 0, + parameter AXI_HBM_WRAP_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -337,6 +381,108 @@ module mqnic_core_pcie_s10 # input wire [PORT_COUNT-1:0] eth_rx_status, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * HBM + */ + input wire [HBM_CH-1:0] hbm_clk, + input wire [HBM_CH-1:0] hbm_rst, + + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, + output wire [HBM_CH-1:0] m_axi_hbm_awlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, + output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser, + output wire [HBM_CH-1:0] m_axi_hbm_awvalid, + input wire [HBM_CH-1:0] m_axi_hbm_awready, + output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, + output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, + output wire [HBM_CH-1:0] m_axi_hbm_wlast, + output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser, + output wire [HBM_CH-1:0] m_axi_hbm_wvalid, + input wire [HBM_CH-1:0] m_axi_hbm_wready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, + input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, + input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser, + input wire [HBM_CH-1:0] m_axi_hbm_bvalid, + output wire [HBM_CH-1:0] m_axi_hbm_bready, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, + output wire [HBM_CH-1:0] m_axi_hbm_arlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, + output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser, + output wire [HBM_CH-1:0] m_axi_hbm_arvalid, + input wire [HBM_CH-1:0] m_axi_hbm_arready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, + input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, + input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, + input wire [HBM_CH-1:0] m_axi_hbm_rlast, + input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser, + input wire [HBM_CH-1:0] m_axi_hbm_rvalid, + output wire [HBM_CH-1:0] m_axi_hbm_rready, + + input wire [HBM_CH-1:0] hbm_status, + /* * Statistics increment input */ @@ -688,6 +834,50 @@ mqnic_core_pcie #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(DDR_GROUP_SIZE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE), + .AXI_DDR_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH), + .AXI_DDR_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE), + .AXI_DDR_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH), + .AXI_DDR_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE), + .AXI_DDR_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH), + .AXI_DDR_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE), + .AXI_DDR_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH), + .AXI_DDR_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE), + .AXI_DDR_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(AXI_DDR_FIXED_BURST), + .AXI_DDR_WRAP_BURST(AXI_DDR_WRAP_BURST), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE), + .AXI_HBM_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH), + .AXI_HBM_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE), + .AXI_HBM_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH), + .AXI_HBM_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE), + .AXI_HBM_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH), + .AXI_HBM_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE), + .AXI_HBM_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH), + .AXI_HBM_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE), + .AXI_HBM_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + .AXI_HBM_NARROW_BURST(AXI_HBM_NARROW_BURST), + .AXI_HBM_FIXED_BURST(AXI_HBM_FIXED_BURST), + .AXI_HBM_WRAP_BURST(AXI_HBM_WRAP_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -960,6 +1150,108 @@ core_pcie_inst ( .rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(m_axi_ddr_awuser), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(m_axi_ddr_wuser), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(m_axi_ddr_buser), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(m_axi_ddr_aruser), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(m_axi_ddr_ruser), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awuser(m_axi_hbm_awuser), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wuser(m_axi_hbm_wuser), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_buser(m_axi_hbm_buser), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_aruser(m_axi_hbm_aruser), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_ruser(m_axi_hbm_ruser), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + /* * Statistics input */ diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v index 0bd7d5719..d0b21d442 100644 --- a/fpga/common/rtl/mqnic_core_pcie_us.v +++ b/fpga/common/rtl/mqnic_core_pcie_us.v @@ -130,6 +130,50 @@ module mqnic_core_pcie_us # parameter APP_GPIO_IN_WIDTH = 32, parameter APP_GPIO_OUT_WIDTH = 32, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 0, + parameter DDR_GROUP_SIZE = 1, + parameter AXI_DDR_DATA_WIDTH = 256, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_AWUSER_ENABLE = 0, + parameter AXI_DDR_AWUSER_WIDTH = 1, + parameter AXI_DDR_WUSER_ENABLE = 0, + parameter AXI_DDR_WUSER_WIDTH = 1, + parameter AXI_DDR_BUSER_ENABLE = 0, + parameter AXI_DDR_BUSER_WIDTH = 1, + parameter AXI_DDR_ARUSER_ENABLE = 0, + parameter AXI_DDR_ARUSER_WIDTH = 1, + parameter AXI_DDR_RUSER_ENABLE = 0, + parameter AXI_DDR_RUSER_WIDTH = 1, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + parameter AXI_DDR_FIXED_BURST = 0, + parameter AXI_DDR_WRAP_BURST = 0, + parameter HBM_CH = 1, + parameter HBM_ENABLE = 0, + parameter HBM_GROUP_SIZE = 1, + parameter AXI_HBM_DATA_WIDTH = 256, + parameter AXI_HBM_ADDR_WIDTH = 32, + parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), + parameter AXI_HBM_ID_WIDTH = 8, + parameter AXI_HBM_AWUSER_ENABLE = 0, + parameter AXI_HBM_AWUSER_WIDTH = 1, + parameter AXI_HBM_WUSER_ENABLE = 0, + parameter AXI_HBM_WUSER_WIDTH = 1, + parameter AXI_HBM_BUSER_ENABLE = 0, + parameter AXI_HBM_BUSER_WIDTH = 1, + parameter AXI_HBM_ARUSER_ENABLE = 0, + parameter AXI_HBM_ARUSER_WIDTH = 1, + parameter AXI_HBM_RUSER_ENABLE = 0, + parameter AXI_HBM_RUSER_WIDTH = 1, + parameter AXI_HBM_MAX_BURST_LEN = 256, + parameter AXI_HBM_NARROW_BURST = 0, + parameter AXI_HBM_FIXED_BURST = 0, + parameter AXI_HBM_WRAP_BURST = 0, + // DMA interface configuration parameter DMA_IMM_ENABLE = 0, parameter DMA_IMM_WIDTH = 32, @@ -396,6 +440,108 @@ module mqnic_core_pcie_us # input wire [PORT_COUNT-1:0] eth_rx_status, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] m_axi_ddr_awuser, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] m_axi_ddr_wuser, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] m_axi_ddr_buser, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] m_axi_ddr_aruser, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] m_axi_ddr_ruser, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * HBM + */ + input wire [HBM_CH-1:0] hbm_clk, + input wire [HBM_CH-1:0] hbm_rst, + + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, + output wire [HBM_CH-1:0] m_axi_hbm_awlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, + output wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] m_axi_hbm_awuser, + output wire [HBM_CH-1:0] m_axi_hbm_awvalid, + input wire [HBM_CH-1:0] m_axi_hbm_awready, + output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, + output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, + output wire [HBM_CH-1:0] m_axi_hbm_wlast, + output wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] m_axi_hbm_wuser, + output wire [HBM_CH-1:0] m_axi_hbm_wvalid, + input wire [HBM_CH-1:0] m_axi_hbm_wready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, + input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, + input wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] m_axi_hbm_buser, + input wire [HBM_CH-1:0] m_axi_hbm_bvalid, + output wire [HBM_CH-1:0] m_axi_hbm_bready, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, + output wire [HBM_CH-1:0] m_axi_hbm_arlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, + output wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] m_axi_hbm_aruser, + output wire [HBM_CH-1:0] m_axi_hbm_arvalid, + input wire [HBM_CH-1:0] m_axi_hbm_arready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, + input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, + input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, + input wire [HBM_CH-1:0] m_axi_hbm_rlast, + input wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] m_axi_hbm_ruser, + input wire [HBM_CH-1:0] m_axi_hbm_rvalid, + output wire [HBM_CH-1:0] m_axi_hbm_rready, + + input wire [HBM_CH-1:0] hbm_status, + /* * Statistics increment input */ @@ -809,6 +955,50 @@ mqnic_core_pcie #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(DDR_GROUP_SIZE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE), + .AXI_DDR_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH), + .AXI_DDR_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE), + .AXI_DDR_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH), + .AXI_DDR_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE), + .AXI_DDR_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH), + .AXI_DDR_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE), + .AXI_DDR_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH), + .AXI_DDR_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE), + .AXI_DDR_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(AXI_DDR_FIXED_BURST), + .AXI_DDR_WRAP_BURST(AXI_DDR_WRAP_BURST), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE), + .AXI_HBM_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH), + .AXI_HBM_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE), + .AXI_HBM_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH), + .AXI_HBM_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE), + .AXI_HBM_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH), + .AXI_HBM_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE), + .AXI_HBM_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH), + .AXI_HBM_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE), + .AXI_HBM_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + .AXI_HBM_NARROW_BURST(AXI_HBM_NARROW_BURST), + .AXI_HBM_FIXED_BURST(AXI_HBM_FIXED_BURST), + .AXI_HBM_WRAP_BURST(AXI_HBM_WRAP_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1081,6 +1271,108 @@ core_pcie_inst ( .rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(m_axi_ddr_awuser), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(m_axi_ddr_wuser), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(m_axi_ddr_buser), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(m_axi_ddr_aruser), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(m_axi_ddr_ruser), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awuser(m_axi_hbm_awuser), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wuser(m_axi_hbm_wuser), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_buser(m_axi_hbm_buser), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_aruser(m_axi_hbm_aruser), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_ruser(m_axi_hbm_ruser), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + /* * Statistics input */