diff --git a/tb/axis_adapter/Makefile b/tb/axis_adapter/Makefile
index 9f9110dca..3e06415e4 100644
--- a/tb/axis_adapter/Makefile
+++ b/tb/axis_adapter/Makefile
@@ -32,19 +32,18 @@ MODULE   = test_$(DUT)
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-export PARAM_S_DATA_WIDTH ?= 8
-export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_M_DATA_WIDTH ?= 8
-export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_LAST_ENABLE ?= 1
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
+export PARAM_S_DATA_WIDTH := 8
+export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
+export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_M_DATA_WIDTH := 8
+export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
+export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_arb_mux/Makefile b/tb/axis_arb_mux/Makefile
index 194d8975e..a75b88be8 100644
--- a/tb/axis_arb_mux/Makefile
+++ b/tb/axis_arb_mux/Makefile
@@ -38,20 +38,20 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
 VERILOG_SOURCES += ../../rtl/priority_encoder.v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_ID_ENABLE ?= 1
-export PARAM_S_ID_WIDTH ?= 8
-export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())")
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_LAST_ENABLE ?= 1
-export PARAM_UPDATE_TID ?= 1
-export PARAM_ARB_TYPE_ROUND_ROBIN ?= 0
-export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_ID_ENABLE := 1
+export PARAM_S_ID_WIDTH := 8
+export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())")
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_LAST_ENABLE := 1
+export PARAM_UPDATE_TID := 1
+export PARAM_ARB_TYPE_ROUND_ROBIN := 0
+export PARAM_ARB_LSB_HIGH_PRIORITY := 1
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_async_fifo/Makefile b/tb/axis_async_fifo/Makefile
index 792f5532c..70c29fd77 100644
--- a/tb/axis_async_fifo/Makefile
+++ b/tb/axis_async_fifo/Makefile
@@ -32,25 +32,25 @@ MODULE   = test_$(DUT)
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-export PARAM_DEPTH ?= 1024
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_LAST_ENABLE ?= 1
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_RAM_PIPELINE ?= 1
-export PARAM_OUTPUT_FIFO_ENABLE ?= 0
-export PARAM_FRAME_FIFO ?= 1
-export PARAM_USER_BAD_FRAME_VALUE ?= 1
-export PARAM_USER_BAD_FRAME_MASK ?= 1
-export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO)
-export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME)
-export PARAM_DROP_WHEN_FULL ?= 0
+export PARAM_DEPTH := 1024
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_LAST_ENABLE := 1
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_RAM_PIPELINE := 1
+export PARAM_OUTPUT_FIFO_ENABLE := 0
+export PARAM_FRAME_FIFO := 1
+export PARAM_USER_BAD_FRAME_VALUE := 1
+export PARAM_USER_BAD_FRAME_MASK := 1
+export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
+export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
+export PARAM_DROP_WHEN_FULL := 0
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_async_fifo_adapter/Makefile b/tb/axis_async_fifo_adapter/Makefile
index 7c7d65f93..90cca22fe 100644
--- a/tb/axis_async_fifo_adapter/Makefile
+++ b/tb/axis_async_fifo_adapter/Makefile
@@ -34,28 +34,28 @@ VERILOG_SOURCES += ../../rtl/axis_async_fifo.v
 VERILOG_SOURCES += ../../rtl/axis_adapter.v
 
 # module parameters
-export PARAM_DEPTH ?= 1024
-export PARAM_S_DATA_WIDTH ?= 8
-export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_M_DATA_WIDTH ?= 8
-export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_LAST_ENABLE ?= 1
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_RAM_PIPELINE ?= 1
-export PARAM_OUTPUT_FIFO_ENABLE ?= 0
-export PARAM_FRAME_FIFO ?= 1
-export PARAM_USER_BAD_FRAME_VALUE ?= 1
-export PARAM_USER_BAD_FRAME_MASK ?= 1
-export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO)
-export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME)
-export PARAM_DROP_WHEN_FULL ?= 0
+export PARAM_DEPTH := 1024
+export PARAM_S_DATA_WIDTH := 8
+export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
+export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_M_DATA_WIDTH := 8
+export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
+export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_LAST_ENABLE := 1
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_RAM_PIPELINE := 1
+export PARAM_OUTPUT_FIFO_ENABLE := 0
+export PARAM_FRAME_FIFO := 1
+export PARAM_USER_BAD_FRAME_VALUE := 1
+export PARAM_USER_BAD_FRAME_MASK := 1
+export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
+export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
+export PARAM_DROP_WHEN_FULL := 0
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_broadcast/Makefile b/tb/axis_broadcast/Makefile
index afef17eca..51989b311 100644
--- a/tb/axis_broadcast/Makefile
+++ b/tb/axis_broadcast/Makefile
@@ -36,16 +36,16 @@ VERILOG_SOURCES += $(WRAPPER).v
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_LAST_ENABLE ?= 1
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_LAST_ENABLE := 1
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_cobs_decode/Makefile b/tb/axis_cobs_decode/Makefile
index 535c69dbe..45723c8b3 100644
--- a/tb/axis_cobs_decode/Makefile
+++ b/tb/axis_cobs_decode/Makefile
@@ -32,7 +32,7 @@ MODULE   = test_$(DUT)
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-# export PARAM_APPEND_ZERO ?= 0
+# export PARAM_NAME := 0
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_cobs_encode/Makefile b/tb/axis_cobs_encode/Makefile
index e0b47bc58..1b700a680 100644
--- a/tb/axis_cobs_encode/Makefile
+++ b/tb/axis_cobs_encode/Makefile
@@ -33,7 +33,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 VERILOG_SOURCES += ../../rtl/axis_fifo.v
 
 # module parameters
-export PARAM_APPEND_ZERO ?= 0
+export PARAM_APPEND_ZERO := 0
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_demux/Makefile b/tb/axis_demux/Makefile
index 1a304bffc..745c2aca3 100644
--- a/tb/axis_demux/Makefile
+++ b/tb/axis_demux/Makefile
@@ -36,17 +36,17 @@ VERILOG_SOURCES += $(WRAPPER).v
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_M_DEST_WIDTH ?= 8
-export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(PORTS)-1).bit_length())")
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_TDEST_ROUTE ?= 1
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_M_DEST_WIDTH := 8
+export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(PORTS)-1).bit_length())")
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_TDEST_ROUTE := 1
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_fifo/Makefile b/tb/axis_fifo/Makefile
index cd64ead7e..d22bb2aa8 100644
--- a/tb/axis_fifo/Makefile
+++ b/tb/axis_fifo/Makefile
@@ -32,25 +32,25 @@ MODULE   = test_$(DUT)
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-export PARAM_DEPTH ?= 1024
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_LAST_ENABLE ?= 1
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_RAM_PIPELINE ?= 1
-export PARAM_OUTPUT_FIFO_ENABLE ?= 0
-export PARAM_FRAME_FIFO ?= 1
-export PARAM_USER_BAD_FRAME_VALUE ?= 1
-export PARAM_USER_BAD_FRAME_MASK ?= 1
-export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO)
-export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME)
-export PARAM_DROP_WHEN_FULL ?= 0
+export PARAM_DEPTH := 1024
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_LAST_ENABLE := 1
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_RAM_PIPELINE := 1
+export PARAM_OUTPUT_FIFO_ENABLE := 0
+export PARAM_FRAME_FIFO := 1
+export PARAM_USER_BAD_FRAME_VALUE := 1
+export PARAM_USER_BAD_FRAME_MASK := 1
+export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
+export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
+export PARAM_DROP_WHEN_FULL := 0
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_fifo_adapter/Makefile b/tb/axis_fifo_adapter/Makefile
index bda1e8c98..e53ca10b3 100644
--- a/tb/axis_fifo_adapter/Makefile
+++ b/tb/axis_fifo_adapter/Makefile
@@ -34,28 +34,28 @@ VERILOG_SOURCES += ../../rtl/axis_fifo.v
 VERILOG_SOURCES += ../../rtl/axis_adapter.v
 
 # module parameters
-export PARAM_DEPTH ?= 1024
-export PARAM_S_DATA_WIDTH ?= 8
-export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_M_DATA_WIDTH ?= 8
-export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_LAST_ENABLE ?= 1
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_RAM_PIPELINE ?= 1
-export PARAM_OUTPUT_FIFO_ENABLE ?= 0
-export PARAM_FRAME_FIFO ?= 1
-export PARAM_USER_BAD_FRAME_VALUE ?= 1
-export PARAM_USER_BAD_FRAME_MASK ?= 1
-export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO)
-export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME)
-export PARAM_DROP_WHEN_FULL ?= 0
+export PARAM_DEPTH := 1024
+export PARAM_S_DATA_WIDTH := 8
+export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
+export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_M_DATA_WIDTH := 8
+export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
+export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_LAST_ENABLE := 1
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_RAM_PIPELINE := 1
+export PARAM_OUTPUT_FIFO_ENABLE := 0
+export PARAM_FRAME_FIFO := 1
+export PARAM_USER_BAD_FRAME_VALUE := 1
+export PARAM_USER_BAD_FRAME_MASK := 1
+export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
+export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
+export PARAM_DROP_WHEN_FULL := 0
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_frame_length_adjust/Makefile b/tb/axis_frame_length_adjust/Makefile
index 60983e25a..fe56f6089 100644
--- a/tb/axis_frame_length_adjust/Makefile
+++ b/tb/axis_frame_length_adjust/Makefile
@@ -32,16 +32,16 @@ MODULE   = test_$(DUT)
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_LEN_WIDTH ?= 16
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_LEN_WIDTH := 16
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_frame_length_adjust_fifo/Makefile b/tb/axis_frame_length_adjust_fifo/Makefile
index aac62b210..ba9d56f85 100644
--- a/tb/axis_frame_length_adjust_fifo/Makefile
+++ b/tb/axis_frame_length_adjust_fifo/Makefile
@@ -34,18 +34,18 @@ VERILOG_SOURCES += ../../rtl/axis_frame_length_adjust.v
 VERILOG_SOURCES += ../../rtl/axis_fifo.v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_LEN_WIDTH ?= 16
-export PARAM_FRAME_FIFO_DEPTH ?= 1024
-export PARAM_HEADER_FIFO_DEPTH ?= 8
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_LEN_WIDTH := 16
+export PARAM_FRAME_FIFO_DEPTH := 1024
+export PARAM_HEADER_FIFO_DEPTH := 8
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_mux/Makefile b/tb/axis_mux/Makefile
index c5d945d34..102c3dc4e 100644
--- a/tb/axis_mux/Makefile
+++ b/tb/axis_mux/Makefile
@@ -36,15 +36,15 @@ VERILOG_SOURCES += $(WRAPPER).v
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_pipeline_fifo/Makefile b/tb/axis_pipeline_fifo/Makefile
index f60a41da1..43eb02ca0 100644
--- a/tb/axis_pipeline_fifo/Makefile
+++ b/tb/axis_pipeline_fifo/Makefile
@@ -32,17 +32,17 @@ MODULE   = test_$(DUT)
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_LAST_ENABLE ?= 1
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_LENGTH ?= 2
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_LAST_ENABLE := 1
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_LENGTH := 2
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_pipeline_register/Makefile b/tb/axis_pipeline_register/Makefile
index a36c6995e..7de3306b9 100644
--- a/tb/axis_pipeline_register/Makefile
+++ b/tb/axis_pipeline_register/Makefile
@@ -33,18 +33,18 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 VERILOG_SOURCES += ../../rtl/axis_register.v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_LAST_ENABLE ?= 1
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_REG_TYPE ?= 2
-export PARAM_LENGTH ?= 2
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_LAST_ENABLE := 1
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_REG_TYPE := 2
+export PARAM_LENGTH := 2
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_ram_switch/Makefile b/tb/axis_ram_switch/Makefile
index 674c2bed2..68398ad46 100644
--- a/tb/axis_ram_switch/Makefile
+++ b/tb/axis_ram_switch/Makefile
@@ -40,30 +40,30 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
 VERILOG_SOURCES += ../../rtl/priority_encoder.v
 
 # module parameters
-export PARAM_FIFO_DEPTH ?= 4096
-export PARAM_CMD_FIFO_DEPTH ?= 32
-export PARAM_SPEEDUP ?= 0
-export PARAM_S_DATA_WIDTH ?= 8
-export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_M_DATA_WIDTH ?= 8
-export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_ID_ENABLE ?= 1
-export PARAM_S_ID_WIDTH ?= 16
-export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
-export PARAM_M_DEST_WIDTH ?= 8
-export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())")
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_USER_BAD_FRAME_VALUE ?= 1
-export PARAM_USER_BAD_FRAME_MASK ?= 1
-export PARAM_DROP_BAD_FRAME ?= 0
-export PARAM_DROP_WHEN_FULL ?= 0
-export PARAM_UPDATE_TID ?= 1
-export PARAM_ARB_TYPE_ROUND_ROBIN ?= 1
-export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
-export PARAM_RAM_PIPELINE ?= 2
+export PARAM_FIFO_DEPTH := 4096
+export PARAM_CMD_FIFO_DEPTH := 32
+export PARAM_SPEEDUP := 0
+export PARAM_S_DATA_WIDTH := 8
+export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
+export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_M_DATA_WIDTH := 8
+export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
+export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_ID_ENABLE := 1
+export PARAM_S_ID_WIDTH := 16
+export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
+export PARAM_M_DEST_WIDTH := 8
+export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())")
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_USER_BAD_FRAME_VALUE := 1
+export PARAM_USER_BAD_FRAME_MASK := 1
+export PARAM_DROP_BAD_FRAME := 0
+export PARAM_DROP_WHEN_FULL := 0
+export PARAM_UPDATE_TID := 1
+export PARAM_ARB_TYPE_ROUND_ROBIN := 1
+export PARAM_ARB_LSB_HIGH_PRIORITY := 1
+export PARAM_RAM_PIPELINE := 2
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_rate_limit/Makefile b/tb/axis_rate_limit/Makefile
index 858372c43..40bf6b3cc 100644
--- a/tb/axis_rate_limit/Makefile
+++ b/tb/axis_rate_limit/Makefile
@@ -32,16 +32,16 @@ MODULE   = test_$(DUT)
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_LAST_ENABLE ?= 1
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_LAST_ENABLE := 1
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_register/Makefile b/tb/axis_register/Makefile
index 9015a57c9..7ba3d180e 100644
--- a/tb/axis_register/Makefile
+++ b/tb/axis_register/Makefile
@@ -32,17 +32,17 @@ MODULE   = test_$(DUT)
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_LAST_ENABLE ?= 1
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_REG_TYPE ?= 2
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_LAST_ENABLE := 1
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_REG_TYPE := 2
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_srl_fifo/Makefile b/tb/axis_srl_fifo/Makefile
index 2d25adf0d..80a2946e7 100644
--- a/tb/axis_srl_fifo/Makefile
+++ b/tb/axis_srl_fifo/Makefile
@@ -32,16 +32,16 @@ MODULE   = test_$(DUT)
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-export PARAM_DEPTH ?= 1024
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
+export PARAM_DEPTH := 1024
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_srl_register/Makefile b/tb/axis_srl_register/Makefile
index 7a6e63cf1..733fc42ee 100644
--- a/tb/axis_srl_register/Makefile
+++ b/tb/axis_srl_register/Makefile
@@ -32,16 +32,16 @@ MODULE   = test_$(DUT)
 VERILOG_SOURCES += ../../rtl/$(DUT).v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_LAST_ENABLE ?= 1
-export PARAM_ID_ENABLE ?= 1
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_ENABLE ?= 1
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_LAST_ENABLE := 1
+export PARAM_ID_ENABLE := 1
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_ENABLE := 1
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tb/axis_switch/Makefile b/tb/axis_switch/Makefile
index 229f5f8c8..ef7b1a719 100644
--- a/tb/axis_switch/Makefile
+++ b/tb/axis_switch/Makefile
@@ -40,21 +40,21 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
 VERILOG_SOURCES += ../../rtl/priority_encoder.v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
-export PARAM_ID_ENABLE ?= 1
-export PARAM_S_ID_WIDTH ?= 16
-export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
-export PARAM_M_DEST_WIDTH ?= 8
-export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())")
-export PARAM_USER_ENABLE ?= 1
-export PARAM_USER_WIDTH ?= 1
-export PARAM_UPDATE_TID ?= 1
-export PARAM_S_REG_TYPE ?= 0
-export PARAM_M_REG_TYPE ?= 2
-export PARAM_ARB_TYPE_ROUND_ROBIN ?= 1
-export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
+export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
+export PARAM_ID_ENABLE := 1
+export PARAM_S_ID_WIDTH := 16
+export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
+export PARAM_M_DEST_WIDTH := 8
+export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())")
+export PARAM_USER_ENABLE := 1
+export PARAM_USER_WIDTH := 1
+export PARAM_UPDATE_TID := 1
+export PARAM_S_REG_TYPE := 0
+export PARAM_M_REG_TYPE := 2
+export PARAM_ARB_TYPE_ROUND_ROBIN := 1
+export PARAM_ARB_LSB_HIGH_PRIORITY := 1
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst