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Add documentation on port-level register blocks

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich 2023-02-01 18:49:15 -08:00
parent d3eb4ee473
commit 96bb163038
3 changed files with 132 additions and 2 deletions
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4
docs/source/rb/index.rst
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@ -64,8 +64,8 @@ The NIC register space is constructed from a linked list of register blocks. Ea
0xFFFFFFFF 0x00000100 :ref:`rb_fw_id`
0x0000C000 0x00000100 :ref:`rb_if`
0x0000C001 0x00000400 :ref:`rb_if_ctrl`
0x0000C002 0x00000200 port
0x0000C003 0x00000200 port_ctrl
0x0000C002 0x00000200 :ref:`rb_port`
0x0000C003 0x00000200 :ref:`rb_port_ctrl`
0x0000C004 0x00000300 :ref:`rb_sched_block`
0x0000C005 0x00000200 application
0x0000C006 0x00000100 stats

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docs/source/rb/port.rst Normal file
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.. _rb_port:
===================
Port register block
===================
The port register block has a header with type 0x0000C002, version 0x00000200, and indicates where the port control register blocks are located in the control register space.
.. table::
======== ============= ====== ====== ====== ====== =============
Address Field 31..24 23..16 15..8 7..0 Reset value
======== ============= ====== ====== ====== ====== =============
RBB+0x00 Type Vendor ID Type RO 0x0000C002
-------- ------------- -------------- -------------- -------------
RBB+0x04 Version Major Minor Patch Meta RO 0x00000200
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x08 Next pointer Pointer to next register block RO -
-------- ------------- ------------------------------ -------------
RBB+0x0C Offset Offset to port region RO -
======== ============= ============================== =============
See :ref:`rb_overview` for definitions of the standard register block header fields.
.. object:: Offset
The offset field contains the offset to the start of the port region, relative to the start of the current region.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x0C Offset to port region RO -
======== ============================== =============

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docs/source/rb/port_ctrl.rst Normal file
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.. _rb_port_ctrl:
===========================
Port control register block
===========================
The port control register block has a header with type 0x0000C003, version 0x00000200, and contains several port-level control registers.
.. table::
======== ============= ====== ====== ====== ====== =============
Address Field 31..24 23..16 15..8 7..0 Reset value
======== ============= ====== ====== ====== ====== =============
RBB+0x00 Type Vendor ID Type RO 0x0000C003
-------- ------------- -------------- -------------- -------------
RBB+0x04 Version Major Minor Patch Meta RO 0x00000200
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x08 Next pointer Pointer to next register block RO -
-------- ------------- ------------------------------ -------------
RBB+0x0C Features Port feature bits RO -
-------- ------------- ------------------------------ -------------
RBB+0x10 TX status TX status RO -
-------- ------------- ------------------------------ -------------
RBB+0x14 RX status RX status RO -
======== ============= ============================== =============
See :ref:`rb_overview` for definitions of the standard register block header fields.
.. object:: Features
The features field contains all of the port-level feature bits, indicating the state of various optional features that can be enabled via Verilog parameters during synthesis.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x0C Interface feature bits RO -
======== ============================== =============
Currently implemented feature bits:
.. table::
=== =======================
Bit Feature
=== =======================
\- None implemented
=== =======================
.. object:: TX status
The TX status field contains some high-level status information about the transmit size of the link associated with the port.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x10 TX status RO -
======== ============================== =============
Status bits:
.. table::
=== =======================
Bit Function
=== =======================
0 TX status (link is ready)
1 TX reset status (MAC TX is in reset)
=== =======================
.. object:: RX status
The RX status field contains some high-level status information about the receive side of the link associated with the port.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x14 RX status RO -
======== ============================== =============
Status bits:
.. table::
=== =======================
Bit Function
=== =======================
0 RX status (link is ready)
1 RX reset status (MAC RX is in reset)
=== =======================