From 96cefbe0c188fdad9fe8fdec41623c416e9ba719 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 31 Oct 2018 21:42:28 -0700 Subject: [PATCH] Convert generated eth_arb_mux to verilog parametrized module --- rtl/eth_arb_mux.py | 186 ------------------ rtl/eth_arb_mux.v | 316 ++++++++++++++++++++++++++++++ rtl/eth_arb_mux_2.v | 150 -------------- rtl/eth_arb_mux_4.v | 196 ------------------- rtl/eth_arb_mux_64.py | 190 ------------------ rtl/eth_arb_mux_64_2.v | 156 --------------- rtl/eth_arb_mux_64_4.v | 206 ------------------- tb/test_eth_arb_mux_4.py | 363 ++++++++++++++-------------------- tb/test_eth_arb_mux_4.v | 261 ++++++++++--------------- tb/test_eth_arb_mux_64_4.py | 380 ++++++++++++++---------------------- tb/test_eth_arb_mux_64_4.v | 276 ++++++++++---------------- 11 files changed, 825 insertions(+), 1855 deletions(-) delete mode 100755 rtl/eth_arb_mux.py create mode 100644 rtl/eth_arb_mux.v delete mode 100644 rtl/eth_arb_mux_2.v delete mode 100644 rtl/eth_arb_mux_4.v delete mode 100755 rtl/eth_arb_mux_64.py delete mode 100644 rtl/eth_arb_mux_64_2.v delete mode 100644 rtl/eth_arb_mux_64_4.v diff --git a/rtl/eth_arb_mux.py b/rtl/eth_arb_mux.py deleted file mode 100755 index 0e35ec61b..000000000 --- a/rtl/eth_arb_mux.py +++ /dev/null @@ -1,186 +0,0 @@ -#!/usr/bin/env python -""" -Generates an arbitrated Ethernet mux with the specified number of ports -""" - -from __future__ import print_function - -import argparse -import math -from jinja2 import Template - -def main(): - parser = argparse.ArgumentParser(description=__doc__.strip()) - parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports") - parser.add_argument('-n', '--name', type=str, help="module name") - parser.add_argument('-o', '--output', type=str, help="output file name") - - args = parser.parse_args() - - try: - generate(**args.__dict__) - except IOError as ex: - print(ex) - exit(1) - -def generate(ports=4, name=None, output=None): - if name is None: - name = "eth_arb_mux_{0}".format(ports) - - if output is None: - output = name + ".v" - - print("Opening file '{0}'...".format(output)) - - output_file = open(output, 'w') - - print("Generating {0} port Ethernet arbitrated mux {1}...".format(ports, name)) - - select_width = int(math.ceil(math.log(ports, 2))) - - t = Template(u"""/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`timescale 1ns / 1ps - -/* - * Ethernet {{n}} port arbitrated multiplexer - */ -module {{name}} # -( - // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY", - // LSB priority: "LOW", "HIGH" - parameter LSB_PRIORITY = "HIGH" -) -( - input wire clk, - input wire rst, - - /* - * Ethernet frame inputs - */ -{%- for p in ports %} - input wire input_{{p}}_eth_hdr_valid, - output wire input_{{p}}_eth_hdr_ready, - input wire [47:0] input_{{p}}_eth_dest_mac, - input wire [47:0] input_{{p}}_eth_src_mac, - input wire [15:0] input_{{p}}_eth_type, - input wire [7:0] input_{{p}}_eth_payload_tdata, - input wire input_{{p}}_eth_payload_tvalid, - output wire input_{{p}}_eth_payload_tready, - input wire input_{{p}}_eth_payload_tlast, - input wire input_{{p}}_eth_payload_tuser, -{% endfor %} - /* - * Ethernet frame output - */ - output wire output_eth_hdr_valid, - input wire output_eth_hdr_ready, - output wire [47:0] output_eth_dest_mac, - output wire [47:0] output_eth_src_mac, - output wire [15:0] output_eth_type, - output wire [7:0] output_eth_payload_tdata, - output wire output_eth_payload_tvalid, - input wire output_eth_payload_tready, - output wire output_eth_payload_tlast, - output wire output_eth_payload_tuser -); - -wire [{{n-1}}:0] request; -wire [{{n-1}}:0] acknowledge; -wire [{{n-1}}:0] grant; -wire grant_valid; -wire [{{w-1}}:0] grant_encoded; -{% for p in ports %} -assign acknowledge[{{p}}] = input_{{p}}_eth_payload_tvalid & input_{{p}}_eth_payload_tready & input_{{p}}_eth_payload_tlast; -assign request[{{p}}] = input_{{p}}_eth_hdr_valid; -{%- endfor %} - -// mux instance -eth_mux_{{n}} -mux_inst ( - .clk(clk), - .rst(rst), -{%- for p in ports %} - .input_{{p}}_eth_hdr_valid(input_{{p}}_eth_hdr_valid & grant[{{p}}]), - .input_{{p}}_eth_hdr_ready(input_{{p}}_eth_hdr_ready), - .input_{{p}}_eth_dest_mac(input_{{p}}_eth_dest_mac), - .input_{{p}}_eth_src_mac(input_{{p}}_eth_src_mac), - .input_{{p}}_eth_type(input_{{p}}_eth_type), - .input_{{p}}_eth_payload_tdata(input_{{p}}_eth_payload_tdata), - .input_{{p}}_eth_payload_tvalid(input_{{p}}_eth_payload_tvalid & grant[{{p}}]), - .input_{{p}}_eth_payload_tready(input_{{p}}_eth_payload_tready), - .input_{{p}}_eth_payload_tlast(input_{{p}}_eth_payload_tlast), - .input_{{p}}_eth_payload_tuser(input_{{p}}_eth_payload_tuser), -{%- endfor %} - .output_eth_hdr_valid(output_eth_hdr_valid), - .output_eth_hdr_ready(output_eth_hdr_ready), - .output_eth_dest_mac(output_eth_dest_mac), - .output_eth_src_mac(output_eth_src_mac), - .output_eth_type(output_eth_type), - .output_eth_payload_tdata(output_eth_payload_tdata), - .output_eth_payload_tvalid(output_eth_payload_tvalid), - .output_eth_payload_tready(output_eth_payload_tready), - .output_eth_payload_tlast(output_eth_payload_tlast), - .output_eth_payload_tuser(output_eth_payload_tuser), - .enable(grant_valid), - .select(grant_encoded) -); - -// arbiter instance -arbiter #( - .PORTS({{n}}), - .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE"), - .LSB_PRIORITY(LSB_PRIORITY) -) -arb_inst ( - .clk(clk), - .rst(rst), - .request(request), - .acknowledge(acknowledge), - .grant(grant), - .grant_valid(grant_valid), - .grant_encoded(grant_encoded) -); - -endmodule - -""") - - output_file.write(t.render( - n=ports, - w=select_width, - name=name, - ports=range(ports) - )) - - print("Done") - -if __name__ == "__main__": - main() - diff --git a/rtl/eth_arb_mux.v b/rtl/eth_arb_mux.v new file mode 100644 index 000000000..a4d6d7cf9 --- /dev/null +++ b/rtl/eth_arb_mux.v @@ -0,0 +1,316 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Ethernet arbitrated multiplexer + */ +module eth_arb_mux # +( + parameter S_COUNT = 4, + parameter DATA_WIDTH = 8, + parameter KEEP_ENABLE = (DATA_WIDTH>8), + parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter ID_ENABLE = 0, + parameter ID_WIDTH = 8, + parameter DEST_ENABLE = 0, + parameter DEST_WIDTH = 8, + parameter USER_ENABLE = 1, + parameter USER_WIDTH = 1, + // arbitration type: "PRIORITY" or "ROUND_ROBIN" + parameter ARB_TYPE = "PRIORITY", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "HIGH" +) +( + input wire clk, + input wire rst, + + /* + * Ethernet frame inputs + */ + input wire [S_COUNT-1:0] s_eth_hdr_valid, + output wire [S_COUNT-1:0] s_eth_hdr_ready, + input wire [S_COUNT*48-1:0] s_eth_dest_mac, + input wire [S_COUNT*48-1:0] s_eth_src_mac, + input wire [S_COUNT*16-1:0] s_eth_type, + input wire [S_COUNT*DATA_WIDTH-1:0] s_eth_payload_axis_tdata, + input wire [S_COUNT*KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep, + input wire [S_COUNT-1:0] s_eth_payload_axis_tvalid, + output wire [S_COUNT-1:0] s_eth_payload_axis_tready, + input wire [S_COUNT-1:0] s_eth_payload_axis_tlast, + input wire [S_COUNT*ID_WIDTH-1:0] s_eth_payload_axis_tid, + input wire [S_COUNT*DEST_WIDTH-1:0] s_eth_payload_axis_tdest, + input wire [S_COUNT*USER_WIDTH-1:0] s_eth_payload_axis_tuser, + + /* + * Ethernet frame output + */ + output wire m_eth_hdr_valid, + input wire m_eth_hdr_ready, + output wire [47:0] m_eth_dest_mac, + output wire [47:0] m_eth_src_mac, + output wire [15:0] m_eth_type, + output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata, + output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep, + output wire m_eth_payload_axis_tvalid, + input wire m_eth_payload_axis_tready, + output wire m_eth_payload_axis_tlast, + output wire [ID_WIDTH-1:0] m_eth_payload_axis_tid, + output wire [DEST_WIDTH-1:0] m_eth_payload_axis_tdest, + output wire [USER_WIDTH-1:0] m_eth_payload_axis_tuser +); + +parameter CL_S_COUNT = $clog2(S_COUNT); + +reg frame_reg = 1'b0, frame_next; + +reg s_eth_hdr_ready_mask_reg = 1'b0, s_eth_hdr_ready_mask_next; + +reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next; +reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next; +reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next; +reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next; + +wire [S_COUNT-1:0] request; +wire [S_COUNT-1:0] acknowledge; +wire [S_COUNT-1:0] grant; +wire grant_valid; +wire [CL_S_COUNT-1:0] grant_encoded; + +// internal datapath +reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int; +reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int; +reg m_eth_payload_axis_tvalid_int; +reg m_eth_payload_axis_tready_int_reg = 1'b0; +reg m_eth_payload_axis_tlast_int; +reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_int; +reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_int; +reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_int; +wire m_eth_payload_axis_tready_int_early; + +assign s_eth_hdr_ready = (!s_eth_hdr_ready_mask_reg && grant_valid) << grant_encoded; + +assign s_eth_payload_axis_tready = (m_eth_payload_axis_tready_int_reg && grant_valid) << grant_encoded; + +assign m_eth_hdr_valid = m_eth_hdr_valid_reg; +assign m_eth_dest_mac = m_eth_dest_mac_reg; +assign m_eth_src_mac = m_eth_src_mac_reg; +assign m_eth_type = m_eth_type_reg; + +// mux for incoming packet +wire [DATA_WIDTH-1:0] current_s_tdata = s_eth_payload_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH]; +wire [KEEP_WIDTH-1:0] current_s_tkeep = s_eth_payload_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH]; +wire current_s_tvalid = s_eth_payload_axis_tvalid[grant_encoded]; +wire current_s_tready = s_eth_payload_axis_tready[grant_encoded]; +wire current_s_tlast = s_eth_payload_axis_tlast[grant_encoded]; +wire [ID_WIDTH-1:0] current_s_tid = s_eth_payload_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH]; +wire [DEST_WIDTH-1:0] current_s_tdest = s_eth_payload_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH]; +wire [USER_WIDTH-1:0] current_s_tuser = s_eth_payload_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH]; + +// arbiter instance +arbiter #( + .PORTS(S_COUNT), + .TYPE(ARB_TYPE), + .BLOCK("ACKNOWLEDGE"), + .LSB_PRIORITY(LSB_PRIORITY) +) +arb_inst ( + .clk(clk), + .rst(rst), + .request(request), + .acknowledge(acknowledge), + .grant(grant), + .grant_valid(grant_valid), + .grant_encoded(grant_encoded) +); + +generate + genvar n; + + for (n = 0; n < S_COUNT; n = n + 1) begin + assign request[n] = s_eth_hdr_valid[n] && !grant[n]; + assign acknowledge[n] = grant[n] && s_eth_payload_axis_tvalid[n] && s_eth_payload_axis_tready[n] && s_eth_payload_axis_tlast[n]; + end +endgenerate + +always @* begin + frame_next = frame_reg; + + s_eth_hdr_ready_mask_next = s_eth_hdr_ready_mask_reg; + + m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready; + m_eth_dest_mac_next = m_eth_dest_mac_reg; + m_eth_src_mac_next = m_eth_src_mac_reg; + m_eth_type_next = m_eth_type_reg; + + if (s_eth_payload_axis_tvalid[grant_encoded] && s_eth_payload_axis_tready[grant_encoded]) begin + // end of frame detection + if (s_eth_payload_axis_tlast[grant_encoded]) begin + frame_next = 1'b0; + s_eth_hdr_ready_mask_next = 1'b0; + end + end + + if (!frame_reg && grant_valid) begin + // start of frame + frame_next = 1'b1; + + s_eth_hdr_ready_mask_next = 1'b1; + + m_eth_hdr_valid_next = 1'b1; + m_eth_dest_mac_next = s_eth_dest_mac[grant_encoded*48 +: 48]; + m_eth_src_mac_next = s_eth_src_mac[grant_encoded*48 +: 48]; + m_eth_type_next = s_eth_type[grant_encoded*16 +: 16]; + end + + // pass through selected packet data + m_eth_payload_axis_tdata_int = current_s_tdata; + m_eth_payload_axis_tkeep_int = current_s_tkeep; + m_eth_payload_axis_tvalid_int = current_s_tvalid && m_eth_payload_axis_tready_int_reg && grant_valid; + m_eth_payload_axis_tlast_int = current_s_tlast; + m_eth_payload_axis_tid_int = current_s_tid; + m_eth_payload_axis_tdest_int = current_s_tdest; + m_eth_payload_axis_tuser_int = current_s_tuser; +end + +always @(posedge clk) begin + if (rst) begin + frame_reg <= 1'b0; + s_eth_hdr_ready_mask_reg <= 1'b0; + m_eth_hdr_valid_reg <= 1'b0; + end else begin + frame_reg <= frame_next; + s_eth_hdr_ready_mask_reg <= s_eth_hdr_ready_mask_next; + m_eth_hdr_valid_reg <= m_eth_hdr_valid_next; + end + + m_eth_dest_mac_reg <= m_eth_dest_mac_next; + m_eth_src_mac_reg <= m_eth_src_mac_next; + m_eth_type_reg <= m_eth_type_next; +end + +// output datapath logic +reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next; +reg m_eth_payload_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}}; + +reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next; +reg temp_m_eth_payload_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] temp_m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] temp_m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] temp_m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}}; + +// datapath control +reg store_axis_int_to_output; +reg store_axis_int_to_temp; +reg store_eth_payload_axis_temp_to_output; + +assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg; +assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? m_eth_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; +assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg; +assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg; +assign m_eth_payload_axis_tid = ID_ENABLE ? m_eth_payload_axis_tid_reg : {ID_WIDTH{1'b0}}; +assign m_eth_payload_axis_tdest = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}}; +assign m_eth_payload_axis_tuser = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}}; + +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int)); + +always @* begin + // transfer sink ready state to source + m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg; + temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg; + + store_axis_int_to_output = 1'b0; + store_axis_int_to_temp = 1'b0; + store_eth_payload_axis_temp_to_output = 1'b0; + + if (m_eth_payload_axis_tready_int_reg) begin + // input is ready + if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin + // output is ready or currently not valid, transfer data to output + m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int; + store_axis_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int; + store_axis_int_to_temp = 1'b1; + end + end else if (m_eth_payload_axis_tready) begin + // input is not ready, but output is ready + m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg; + temp_m_eth_payload_axis_tvalid_next = 1'b0; + store_eth_payload_axis_temp_to_output = 1'b1; + end +end + +always @(posedge clk) begin + if (rst) begin + m_eth_payload_axis_tvalid_reg <= 1'b0; + m_eth_payload_axis_tready_int_reg <= 1'b0; + temp_m_eth_payload_axis_tvalid_reg <= 1'b0; + end else begin + m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next; + m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early; + temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next; + end + + // datapath + if (store_axis_int_to_output) begin + m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int; + m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int; + m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int; + m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int; + m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int; + m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int; + end else if (store_eth_payload_axis_temp_to_output) begin + m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg; + m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg; + m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg; + m_eth_payload_axis_tid_reg <= temp_m_eth_payload_axis_tid_reg; + m_eth_payload_axis_tdest_reg <= temp_m_eth_payload_axis_tdest_reg; + m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg; + end + + if (store_axis_int_to_temp) begin + temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int; + temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int; + temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int; + temp_m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int; + temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int; + temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int; + end +end + +endmodule diff --git a/rtl/eth_arb_mux_2.v b/rtl/eth_arb_mux_2.v deleted file mode 100644 index 705830b81..000000000 --- a/rtl/eth_arb_mux_2.v +++ /dev/null @@ -1,150 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`timescale 1ns / 1ps - -/* - * Ethernet 2 port arbitrated multiplexer - */ -module eth_arb_mux_2 # -( - // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY", - // LSB priority: "LOW", "HIGH" - parameter LSB_PRIORITY = "HIGH" -) -( - input wire clk, - input wire rst, - - /* - * Ethernet frame inputs - */ - input wire input_0_eth_hdr_valid, - output wire input_0_eth_hdr_ready, - input wire [47:0] input_0_eth_dest_mac, - input wire [47:0] input_0_eth_src_mac, - input wire [15:0] input_0_eth_type, - input wire [7:0] input_0_eth_payload_tdata, - input wire input_0_eth_payload_tvalid, - output wire input_0_eth_payload_tready, - input wire input_0_eth_payload_tlast, - input wire input_0_eth_payload_tuser, - - input wire input_1_eth_hdr_valid, - output wire input_1_eth_hdr_ready, - input wire [47:0] input_1_eth_dest_mac, - input wire [47:0] input_1_eth_src_mac, - input wire [15:0] input_1_eth_type, - input wire [7:0] input_1_eth_payload_tdata, - input wire input_1_eth_payload_tvalid, - output wire input_1_eth_payload_tready, - input wire input_1_eth_payload_tlast, - input wire input_1_eth_payload_tuser, - - /* - * Ethernet frame output - */ - output wire output_eth_hdr_valid, - input wire output_eth_hdr_ready, - output wire [47:0] output_eth_dest_mac, - output wire [47:0] output_eth_src_mac, - output wire [15:0] output_eth_type, - output wire [7:0] output_eth_payload_tdata, - output wire output_eth_payload_tvalid, - input wire output_eth_payload_tready, - output wire output_eth_payload_tlast, - output wire output_eth_payload_tuser -); - -wire [1:0] request; -wire [1:0] acknowledge; -wire [1:0] grant; -wire grant_valid; -wire [0:0] grant_encoded; - -assign acknowledge[0] = input_0_eth_payload_tvalid & input_0_eth_payload_tready & input_0_eth_payload_tlast; -assign request[0] = input_0_eth_hdr_valid; -assign acknowledge[1] = input_1_eth_payload_tvalid & input_1_eth_payload_tready & input_1_eth_payload_tlast; -assign request[1] = input_1_eth_hdr_valid; - -// mux instance -eth_mux_2 -mux_inst ( - .clk(clk), - .rst(rst), - .input_0_eth_hdr_valid(input_0_eth_hdr_valid & grant[0]), - .input_0_eth_hdr_ready(input_0_eth_hdr_ready), - .input_0_eth_dest_mac(input_0_eth_dest_mac), - .input_0_eth_src_mac(input_0_eth_src_mac), - .input_0_eth_type(input_0_eth_type), - .input_0_eth_payload_tdata(input_0_eth_payload_tdata), - .input_0_eth_payload_tvalid(input_0_eth_payload_tvalid & grant[0]), - .input_0_eth_payload_tready(input_0_eth_payload_tready), - .input_0_eth_payload_tlast(input_0_eth_payload_tlast), - .input_0_eth_payload_tuser(input_0_eth_payload_tuser), - .input_1_eth_hdr_valid(input_1_eth_hdr_valid & grant[1]), - .input_1_eth_hdr_ready(input_1_eth_hdr_ready), - .input_1_eth_dest_mac(input_1_eth_dest_mac), - .input_1_eth_src_mac(input_1_eth_src_mac), - .input_1_eth_type(input_1_eth_type), - .input_1_eth_payload_tdata(input_1_eth_payload_tdata), - .input_1_eth_payload_tvalid(input_1_eth_payload_tvalid & grant[1]), - .input_1_eth_payload_tready(input_1_eth_payload_tready), - .input_1_eth_payload_tlast(input_1_eth_payload_tlast), - .input_1_eth_payload_tuser(input_1_eth_payload_tuser), - .output_eth_hdr_valid(output_eth_hdr_valid), - .output_eth_hdr_ready(output_eth_hdr_ready), - .output_eth_dest_mac(output_eth_dest_mac), - .output_eth_src_mac(output_eth_src_mac), - .output_eth_type(output_eth_type), - .output_eth_payload_tdata(output_eth_payload_tdata), - .output_eth_payload_tvalid(output_eth_payload_tvalid), - .output_eth_payload_tready(output_eth_payload_tready), - .output_eth_payload_tlast(output_eth_payload_tlast), - .output_eth_payload_tuser(output_eth_payload_tuser), - .enable(grant_valid), - .select(grant_encoded) -); - -// arbiter instance -arbiter #( - .PORTS(2), - .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE"), - .LSB_PRIORITY(LSB_PRIORITY) -) -arb_inst ( - .clk(clk), - .rst(rst), - .request(request), - .acknowledge(acknowledge), - .grant(grant), - .grant_valid(grant_valid), - .grant_encoded(grant_encoded) -); - -endmodule diff --git a/rtl/eth_arb_mux_4.v b/rtl/eth_arb_mux_4.v deleted file mode 100644 index 3a8c1e6e0..000000000 --- a/rtl/eth_arb_mux_4.v +++ /dev/null @@ -1,196 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`timescale 1ns / 1ps - -/* - * Ethernet 4 port arbitrated multiplexer - */ -module eth_arb_mux_4 # -( - // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY", - // LSB priority: "LOW", "HIGH" - parameter LSB_PRIORITY = "HIGH" -) -( - input wire clk, - input wire rst, - - /* - * Ethernet frame inputs - */ - input wire input_0_eth_hdr_valid, - output wire input_0_eth_hdr_ready, - input wire [47:0] input_0_eth_dest_mac, - input wire [47:0] input_0_eth_src_mac, - input wire [15:0] input_0_eth_type, - input wire [7:0] input_0_eth_payload_tdata, - input wire input_0_eth_payload_tvalid, - output wire input_0_eth_payload_tready, - input wire input_0_eth_payload_tlast, - input wire input_0_eth_payload_tuser, - - input wire input_1_eth_hdr_valid, - output wire input_1_eth_hdr_ready, - input wire [47:0] input_1_eth_dest_mac, - input wire [47:0] input_1_eth_src_mac, - input wire [15:0] input_1_eth_type, - input wire [7:0] input_1_eth_payload_tdata, - input wire input_1_eth_payload_tvalid, - output wire input_1_eth_payload_tready, - input wire input_1_eth_payload_tlast, - input wire input_1_eth_payload_tuser, - - input wire input_2_eth_hdr_valid, - output wire input_2_eth_hdr_ready, - input wire [47:0] input_2_eth_dest_mac, - input wire [47:0] input_2_eth_src_mac, - input wire [15:0] input_2_eth_type, - input wire [7:0] input_2_eth_payload_tdata, - input wire input_2_eth_payload_tvalid, - output wire input_2_eth_payload_tready, - input wire input_2_eth_payload_tlast, - input wire input_2_eth_payload_tuser, - - input wire input_3_eth_hdr_valid, - output wire input_3_eth_hdr_ready, - input wire [47:0] input_3_eth_dest_mac, - input wire [47:0] input_3_eth_src_mac, - input wire [15:0] input_3_eth_type, - input wire [7:0] input_3_eth_payload_tdata, - input wire input_3_eth_payload_tvalid, - output wire input_3_eth_payload_tready, - input wire input_3_eth_payload_tlast, - input wire input_3_eth_payload_tuser, - - /* - * Ethernet frame output - */ - output wire output_eth_hdr_valid, - input wire output_eth_hdr_ready, - output wire [47:0] output_eth_dest_mac, - output wire [47:0] output_eth_src_mac, - output wire [15:0] output_eth_type, - output wire [7:0] output_eth_payload_tdata, - output wire output_eth_payload_tvalid, - input wire output_eth_payload_tready, - output wire output_eth_payload_tlast, - output wire output_eth_payload_tuser -); - -wire [3:0] request; -wire [3:0] acknowledge; -wire [3:0] grant; -wire grant_valid; -wire [1:0] grant_encoded; - -assign acknowledge[0] = input_0_eth_payload_tvalid & input_0_eth_payload_tready & input_0_eth_payload_tlast; -assign request[0] = input_0_eth_hdr_valid; -assign acknowledge[1] = input_1_eth_payload_tvalid & input_1_eth_payload_tready & input_1_eth_payload_tlast; -assign request[1] = input_1_eth_hdr_valid; -assign acknowledge[2] = input_2_eth_payload_tvalid & input_2_eth_payload_tready & input_2_eth_payload_tlast; -assign request[2] = input_2_eth_hdr_valid; -assign acknowledge[3] = input_3_eth_payload_tvalid & input_3_eth_payload_tready & input_3_eth_payload_tlast; -assign request[3] = input_3_eth_hdr_valid; - -// mux instance -eth_mux_4 -mux_inst ( - .clk(clk), - .rst(rst), - .input_0_eth_hdr_valid(input_0_eth_hdr_valid & grant[0]), - .input_0_eth_hdr_ready(input_0_eth_hdr_ready), - .input_0_eth_dest_mac(input_0_eth_dest_mac), - .input_0_eth_src_mac(input_0_eth_src_mac), - .input_0_eth_type(input_0_eth_type), - .input_0_eth_payload_tdata(input_0_eth_payload_tdata), - .input_0_eth_payload_tvalid(input_0_eth_payload_tvalid & grant[0]), - .input_0_eth_payload_tready(input_0_eth_payload_tready), - .input_0_eth_payload_tlast(input_0_eth_payload_tlast), - .input_0_eth_payload_tuser(input_0_eth_payload_tuser), - .input_1_eth_hdr_valid(input_1_eth_hdr_valid & grant[1]), - .input_1_eth_hdr_ready(input_1_eth_hdr_ready), - .input_1_eth_dest_mac(input_1_eth_dest_mac), - .input_1_eth_src_mac(input_1_eth_src_mac), - .input_1_eth_type(input_1_eth_type), - .input_1_eth_payload_tdata(input_1_eth_payload_tdata), - .input_1_eth_payload_tvalid(input_1_eth_payload_tvalid & grant[1]), - .input_1_eth_payload_tready(input_1_eth_payload_tready), - .input_1_eth_payload_tlast(input_1_eth_payload_tlast), - .input_1_eth_payload_tuser(input_1_eth_payload_tuser), - .input_2_eth_hdr_valid(input_2_eth_hdr_valid & grant[2]), - .input_2_eth_hdr_ready(input_2_eth_hdr_ready), - .input_2_eth_dest_mac(input_2_eth_dest_mac), - .input_2_eth_src_mac(input_2_eth_src_mac), - .input_2_eth_type(input_2_eth_type), - .input_2_eth_payload_tdata(input_2_eth_payload_tdata), - .input_2_eth_payload_tvalid(input_2_eth_payload_tvalid & grant[2]), - .input_2_eth_payload_tready(input_2_eth_payload_tready), - .input_2_eth_payload_tlast(input_2_eth_payload_tlast), - .input_2_eth_payload_tuser(input_2_eth_payload_tuser), - .input_3_eth_hdr_valid(input_3_eth_hdr_valid & grant[3]), - .input_3_eth_hdr_ready(input_3_eth_hdr_ready), - .input_3_eth_dest_mac(input_3_eth_dest_mac), - .input_3_eth_src_mac(input_3_eth_src_mac), - .input_3_eth_type(input_3_eth_type), - .input_3_eth_payload_tdata(input_3_eth_payload_tdata), - .input_3_eth_payload_tvalid(input_3_eth_payload_tvalid & grant[3]), - .input_3_eth_payload_tready(input_3_eth_payload_tready), - .input_3_eth_payload_tlast(input_3_eth_payload_tlast), - .input_3_eth_payload_tuser(input_3_eth_payload_tuser), - .output_eth_hdr_valid(output_eth_hdr_valid), - .output_eth_hdr_ready(output_eth_hdr_ready), - .output_eth_dest_mac(output_eth_dest_mac), - .output_eth_src_mac(output_eth_src_mac), - .output_eth_type(output_eth_type), - .output_eth_payload_tdata(output_eth_payload_tdata), - .output_eth_payload_tvalid(output_eth_payload_tvalid), - .output_eth_payload_tready(output_eth_payload_tready), - .output_eth_payload_tlast(output_eth_payload_tlast), - .output_eth_payload_tuser(output_eth_payload_tuser), - .enable(grant_valid), - .select(grant_encoded) -); - -// arbiter instance -arbiter #( - .PORTS(4), - .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE"), - .LSB_PRIORITY(LSB_PRIORITY) -) -arb_inst ( - .clk(clk), - .rst(rst), - .request(request), - .acknowledge(acknowledge), - .grant(grant), - .grant_valid(grant_valid), - .grant_encoded(grant_encoded) -); - -endmodule diff --git a/rtl/eth_arb_mux_64.py b/rtl/eth_arb_mux_64.py deleted file mode 100755 index 7ed719d01..000000000 --- a/rtl/eth_arb_mux_64.py +++ /dev/null @@ -1,190 +0,0 @@ -#!/usr/bin/env python -""" -Generates an arbitrated Ethernet mux with the specified number of ports -""" - -from __future__ import print_function - -import argparse -import math -from jinja2 import Template - -def main(): - parser = argparse.ArgumentParser(description=__doc__.strip()) - parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports") - parser.add_argument('-n', '--name', type=str, help="module name") - parser.add_argument('-o', '--output', type=str, help="output file name") - - args = parser.parse_args() - - try: - generate(**args.__dict__) - except IOError as ex: - print(ex) - exit(1) - -def generate(ports=4, name=None, output=None): - if name is None: - name = "eth_arb_mux_64_{0}".format(ports) - - if output is None: - output = name + ".v" - - print("Opening file '{0}'...".format(output)) - - output_file = open(output, 'w') - - print("Generating {0} port Ethernet arbitrated mux {1}...".format(ports, name)) - - select_width = int(math.ceil(math.log(ports, 2))) - - t = Template(u"""/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`timescale 1ns / 1ps - -/* - * Ethernet {{n}} port arbitrated multiplexer (64 bit datapath) - */ -module {{name}} # -( - // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY", - // LSB priority: "LOW", "HIGH" - parameter LSB_PRIORITY = "HIGH" -) -( - input wire clk, - input wire rst, - - /* - * Ethernet frame inputs - */ -{%- for p in ports %} - input wire input_{{p}}_eth_hdr_valid, - output wire input_{{p}}_eth_hdr_ready, - input wire [47:0] input_{{p}}_eth_dest_mac, - input wire [47:0] input_{{p}}_eth_src_mac, - input wire [15:0] input_{{p}}_eth_type, - input wire [63:0] input_{{p}}_eth_payload_tdata, - input wire [7:0] input_{{p}}_eth_payload_tkeep, - input wire input_{{p}}_eth_payload_tvalid, - output wire input_{{p}}_eth_payload_tready, - input wire input_{{p}}_eth_payload_tlast, - input wire input_{{p}}_eth_payload_tuser, -{% endfor %} - /* - * Ethernet frame output - */ - output wire output_eth_hdr_valid, - input wire output_eth_hdr_ready, - output wire [47:0] output_eth_dest_mac, - output wire [47:0] output_eth_src_mac, - output wire [15:0] output_eth_type, - output wire [63:0] output_eth_payload_tdata, - output wire [7:0] output_eth_payload_tkeep, - output wire output_eth_payload_tvalid, - input wire output_eth_payload_tready, - output wire output_eth_payload_tlast, - output wire output_eth_payload_tuser -); - -wire [{{n-1}}:0] request; -wire [{{n-1}}:0] acknowledge; -wire [{{n-1}}:0] grant; -wire grant_valid; -wire [{{w-1}}:0] grant_encoded; -{% for p in ports %} -assign acknowledge[{{p}}] = input_{{p}}_eth_payload_tvalid & input_{{p}}_eth_payload_tready & input_{{p}}_eth_payload_tlast; -assign request[{{p}}] = input_{{p}}_eth_hdr_valid; -{%- endfor %} - -// mux instance -eth_mux_64_{{n}} -mux_inst ( - .clk(clk), - .rst(rst), -{%- for p in ports %} - .input_{{p}}_eth_hdr_valid(input_{{p}}_eth_hdr_valid & grant[{{p}}]), - .input_{{p}}_eth_hdr_ready(input_{{p}}_eth_hdr_ready), - .input_{{p}}_eth_dest_mac(input_{{p}}_eth_dest_mac), - .input_{{p}}_eth_src_mac(input_{{p}}_eth_src_mac), - .input_{{p}}_eth_type(input_{{p}}_eth_type), - .input_{{p}}_eth_payload_tdata(input_{{p}}_eth_payload_tdata), - .input_{{p}}_eth_payload_tkeep(input_{{p}}_eth_payload_tkeep), - .input_{{p}}_eth_payload_tvalid(input_{{p}}_eth_payload_tvalid & grant[{{p}}]), - .input_{{p}}_eth_payload_tready(input_{{p}}_eth_payload_tready), - .input_{{p}}_eth_payload_tlast(input_{{p}}_eth_payload_tlast), - .input_{{p}}_eth_payload_tuser(input_{{p}}_eth_payload_tuser), -{%- endfor %} - .output_eth_hdr_valid(output_eth_hdr_valid), - .output_eth_hdr_ready(output_eth_hdr_ready), - .output_eth_dest_mac(output_eth_dest_mac), - .output_eth_src_mac(output_eth_src_mac), - .output_eth_type(output_eth_type), - .output_eth_payload_tdata(output_eth_payload_tdata), - .output_eth_payload_tkeep(output_eth_payload_tkeep), - .output_eth_payload_tvalid(output_eth_payload_tvalid), - .output_eth_payload_tready(output_eth_payload_tready), - .output_eth_payload_tlast(output_eth_payload_tlast), - .output_eth_payload_tuser(output_eth_payload_tuser), - .enable(grant_valid), - .select(grant_encoded) -); - -// arbiter instance -arbiter #( - .PORTS({{n}}), - .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE"), - .LSB_PRIORITY(LSB_PRIORITY) -) -arb_inst ( - .clk(clk), - .rst(rst), - .request(request), - .acknowledge(acknowledge), - .grant(grant), - .grant_valid(grant_valid), - .grant_encoded(grant_encoded) -); - -endmodule - -""") - - output_file.write(t.render( - n=ports, - w=select_width, - name=name, - ports=range(ports) - )) - - print("Done") - -if __name__ == "__main__": - main() - diff --git a/rtl/eth_arb_mux_64_2.v b/rtl/eth_arb_mux_64_2.v deleted file mode 100644 index 7e8553be4..000000000 --- a/rtl/eth_arb_mux_64_2.v +++ /dev/null @@ -1,156 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`timescale 1ns / 1ps - -/* - * Ethernet 2 port arbitrated multiplexer (64 bit datapath) - */ -module eth_arb_mux_64_2 # -( - // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY", - // LSB priority: "LOW", "HIGH" - parameter LSB_PRIORITY = "HIGH" -) -( - input wire clk, - input wire rst, - - /* - * Ethernet frame inputs - */ - input wire input_0_eth_hdr_valid, - output wire input_0_eth_hdr_ready, - input wire [47:0] input_0_eth_dest_mac, - input wire [47:0] input_0_eth_src_mac, - input wire [15:0] input_0_eth_type, - input wire [63:0] input_0_eth_payload_tdata, - input wire [7:0] input_0_eth_payload_tkeep, - input wire input_0_eth_payload_tvalid, - output wire input_0_eth_payload_tready, - input wire input_0_eth_payload_tlast, - input wire input_0_eth_payload_tuser, - - input wire input_1_eth_hdr_valid, - output wire input_1_eth_hdr_ready, - input wire [47:0] input_1_eth_dest_mac, - input wire [47:0] input_1_eth_src_mac, - input wire [15:0] input_1_eth_type, - input wire [63:0] input_1_eth_payload_tdata, - input wire [7:0] input_1_eth_payload_tkeep, - input wire input_1_eth_payload_tvalid, - output wire input_1_eth_payload_tready, - input wire input_1_eth_payload_tlast, - input wire input_1_eth_payload_tuser, - - /* - * Ethernet frame output - */ - output wire output_eth_hdr_valid, - input wire output_eth_hdr_ready, - output wire [47:0] output_eth_dest_mac, - output wire [47:0] output_eth_src_mac, - output wire [15:0] output_eth_type, - output wire [63:0] output_eth_payload_tdata, - output wire [7:0] output_eth_payload_tkeep, - output wire output_eth_payload_tvalid, - input wire output_eth_payload_tready, - output wire output_eth_payload_tlast, - output wire output_eth_payload_tuser -); - -wire [1:0] request; -wire [1:0] acknowledge; -wire [1:0] grant; -wire grant_valid; -wire [0:0] grant_encoded; - -assign acknowledge[0] = input_0_eth_payload_tvalid & input_0_eth_payload_tready & input_0_eth_payload_tlast; -assign request[0] = input_0_eth_hdr_valid; -assign acknowledge[1] = input_1_eth_payload_tvalid & input_1_eth_payload_tready & input_1_eth_payload_tlast; -assign request[1] = input_1_eth_hdr_valid; - -// mux instance -eth_mux_64_2 -mux_inst ( - .clk(clk), - .rst(rst), - .input_0_eth_hdr_valid(input_0_eth_hdr_valid & grant[0]), - .input_0_eth_hdr_ready(input_0_eth_hdr_ready), - .input_0_eth_dest_mac(input_0_eth_dest_mac), - .input_0_eth_src_mac(input_0_eth_src_mac), - .input_0_eth_type(input_0_eth_type), - .input_0_eth_payload_tdata(input_0_eth_payload_tdata), - .input_0_eth_payload_tkeep(input_0_eth_payload_tkeep), - .input_0_eth_payload_tvalid(input_0_eth_payload_tvalid & grant[0]), - .input_0_eth_payload_tready(input_0_eth_payload_tready), - .input_0_eth_payload_tlast(input_0_eth_payload_tlast), - .input_0_eth_payload_tuser(input_0_eth_payload_tuser), - .input_1_eth_hdr_valid(input_1_eth_hdr_valid & grant[1]), - .input_1_eth_hdr_ready(input_1_eth_hdr_ready), - .input_1_eth_dest_mac(input_1_eth_dest_mac), - .input_1_eth_src_mac(input_1_eth_src_mac), - .input_1_eth_type(input_1_eth_type), - .input_1_eth_payload_tdata(input_1_eth_payload_tdata), - .input_1_eth_payload_tkeep(input_1_eth_payload_tkeep), - .input_1_eth_payload_tvalid(input_1_eth_payload_tvalid & grant[1]), - .input_1_eth_payload_tready(input_1_eth_payload_tready), - .input_1_eth_payload_tlast(input_1_eth_payload_tlast), - .input_1_eth_payload_tuser(input_1_eth_payload_tuser), - .output_eth_hdr_valid(output_eth_hdr_valid), - .output_eth_hdr_ready(output_eth_hdr_ready), - .output_eth_dest_mac(output_eth_dest_mac), - .output_eth_src_mac(output_eth_src_mac), - .output_eth_type(output_eth_type), - .output_eth_payload_tdata(output_eth_payload_tdata), - .output_eth_payload_tkeep(output_eth_payload_tkeep), - .output_eth_payload_tvalid(output_eth_payload_tvalid), - .output_eth_payload_tready(output_eth_payload_tready), - .output_eth_payload_tlast(output_eth_payload_tlast), - .output_eth_payload_tuser(output_eth_payload_tuser), - .enable(grant_valid), - .select(grant_encoded) -); - -// arbiter instance -arbiter #( - .PORTS(2), - .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE"), - .LSB_PRIORITY(LSB_PRIORITY) -) -arb_inst ( - .clk(clk), - .rst(rst), - .request(request), - .acknowledge(acknowledge), - .grant(grant), - .grant_valid(grant_valid), - .grant_encoded(grant_encoded) -); - -endmodule diff --git a/rtl/eth_arb_mux_64_4.v b/rtl/eth_arb_mux_64_4.v deleted file mode 100644 index b46b088c4..000000000 --- a/rtl/eth_arb_mux_64_4.v +++ /dev/null @@ -1,206 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`timescale 1ns / 1ps - -/* - * Ethernet 4 port arbitrated multiplexer (64 bit datapath) - */ -module eth_arb_mux_64_4 # -( - // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY", - // LSB priority: "LOW", "HIGH" - parameter LSB_PRIORITY = "HIGH" -) -( - input wire clk, - input wire rst, - - /* - * Ethernet frame inputs - */ - input wire input_0_eth_hdr_valid, - output wire input_0_eth_hdr_ready, - input wire [47:0] input_0_eth_dest_mac, - input wire [47:0] input_0_eth_src_mac, - input wire [15:0] input_0_eth_type, - input wire [63:0] input_0_eth_payload_tdata, - input wire [7:0] input_0_eth_payload_tkeep, - input wire input_0_eth_payload_tvalid, - output wire input_0_eth_payload_tready, - input wire input_0_eth_payload_tlast, - input wire input_0_eth_payload_tuser, - - input wire input_1_eth_hdr_valid, - output wire input_1_eth_hdr_ready, - input wire [47:0] input_1_eth_dest_mac, - input wire [47:0] input_1_eth_src_mac, - input wire [15:0] input_1_eth_type, - input wire [63:0] input_1_eth_payload_tdata, - input wire [7:0] input_1_eth_payload_tkeep, - input wire input_1_eth_payload_tvalid, - output wire input_1_eth_payload_tready, - input wire input_1_eth_payload_tlast, - input wire input_1_eth_payload_tuser, - - input wire input_2_eth_hdr_valid, - output wire input_2_eth_hdr_ready, - input wire [47:0] input_2_eth_dest_mac, - input wire [47:0] input_2_eth_src_mac, - input wire [15:0] input_2_eth_type, - input wire [63:0] input_2_eth_payload_tdata, - input wire [7:0] input_2_eth_payload_tkeep, - input wire input_2_eth_payload_tvalid, - output wire input_2_eth_payload_tready, - input wire input_2_eth_payload_tlast, - input wire input_2_eth_payload_tuser, - - input wire input_3_eth_hdr_valid, - output wire input_3_eth_hdr_ready, - input wire [47:0] input_3_eth_dest_mac, - input wire [47:0] input_3_eth_src_mac, - input wire [15:0] input_3_eth_type, - input wire [63:0] input_3_eth_payload_tdata, - input wire [7:0] input_3_eth_payload_tkeep, - input wire input_3_eth_payload_tvalid, - output wire input_3_eth_payload_tready, - input wire input_3_eth_payload_tlast, - input wire input_3_eth_payload_tuser, - - /* - * Ethernet frame output - */ - output wire output_eth_hdr_valid, - input wire output_eth_hdr_ready, - output wire [47:0] output_eth_dest_mac, - output wire [47:0] output_eth_src_mac, - output wire [15:0] output_eth_type, - output wire [63:0] output_eth_payload_tdata, - output wire [7:0] output_eth_payload_tkeep, - output wire output_eth_payload_tvalid, - input wire output_eth_payload_tready, - output wire output_eth_payload_tlast, - output wire output_eth_payload_tuser -); - -wire [3:0] request; -wire [3:0] acknowledge; -wire [3:0] grant; -wire grant_valid; -wire [1:0] grant_encoded; - -assign acknowledge[0] = input_0_eth_payload_tvalid & input_0_eth_payload_tready & input_0_eth_payload_tlast; -assign request[0] = input_0_eth_hdr_valid; -assign acknowledge[1] = input_1_eth_payload_tvalid & input_1_eth_payload_tready & input_1_eth_payload_tlast; -assign request[1] = input_1_eth_hdr_valid; -assign acknowledge[2] = input_2_eth_payload_tvalid & input_2_eth_payload_tready & input_2_eth_payload_tlast; -assign request[2] = input_2_eth_hdr_valid; -assign acknowledge[3] = input_3_eth_payload_tvalid & input_3_eth_payload_tready & input_3_eth_payload_tlast; -assign request[3] = input_3_eth_hdr_valid; - -// mux instance -eth_mux_64_4 -mux_inst ( - .clk(clk), - .rst(rst), - .input_0_eth_hdr_valid(input_0_eth_hdr_valid & grant[0]), - .input_0_eth_hdr_ready(input_0_eth_hdr_ready), - .input_0_eth_dest_mac(input_0_eth_dest_mac), - .input_0_eth_src_mac(input_0_eth_src_mac), - .input_0_eth_type(input_0_eth_type), - .input_0_eth_payload_tdata(input_0_eth_payload_tdata), - .input_0_eth_payload_tkeep(input_0_eth_payload_tkeep), - .input_0_eth_payload_tvalid(input_0_eth_payload_tvalid & grant[0]), - .input_0_eth_payload_tready(input_0_eth_payload_tready), - .input_0_eth_payload_tlast(input_0_eth_payload_tlast), - .input_0_eth_payload_tuser(input_0_eth_payload_tuser), - .input_1_eth_hdr_valid(input_1_eth_hdr_valid & grant[1]), - .input_1_eth_hdr_ready(input_1_eth_hdr_ready), - .input_1_eth_dest_mac(input_1_eth_dest_mac), - .input_1_eth_src_mac(input_1_eth_src_mac), - .input_1_eth_type(input_1_eth_type), - .input_1_eth_payload_tdata(input_1_eth_payload_tdata), - .input_1_eth_payload_tkeep(input_1_eth_payload_tkeep), - .input_1_eth_payload_tvalid(input_1_eth_payload_tvalid & grant[1]), - .input_1_eth_payload_tready(input_1_eth_payload_tready), - .input_1_eth_payload_tlast(input_1_eth_payload_tlast), - .input_1_eth_payload_tuser(input_1_eth_payload_tuser), - .input_2_eth_hdr_valid(input_2_eth_hdr_valid & grant[2]), - .input_2_eth_hdr_ready(input_2_eth_hdr_ready), - .input_2_eth_dest_mac(input_2_eth_dest_mac), - .input_2_eth_src_mac(input_2_eth_src_mac), - .input_2_eth_type(input_2_eth_type), - .input_2_eth_payload_tdata(input_2_eth_payload_tdata), - .input_2_eth_payload_tkeep(input_2_eth_payload_tkeep), - .input_2_eth_payload_tvalid(input_2_eth_payload_tvalid & grant[2]), - .input_2_eth_payload_tready(input_2_eth_payload_tready), - .input_2_eth_payload_tlast(input_2_eth_payload_tlast), - .input_2_eth_payload_tuser(input_2_eth_payload_tuser), - .input_3_eth_hdr_valid(input_3_eth_hdr_valid & grant[3]), - .input_3_eth_hdr_ready(input_3_eth_hdr_ready), - .input_3_eth_dest_mac(input_3_eth_dest_mac), - .input_3_eth_src_mac(input_3_eth_src_mac), - .input_3_eth_type(input_3_eth_type), - .input_3_eth_payload_tdata(input_3_eth_payload_tdata), - .input_3_eth_payload_tkeep(input_3_eth_payload_tkeep), - .input_3_eth_payload_tvalid(input_3_eth_payload_tvalid & grant[3]), - .input_3_eth_payload_tready(input_3_eth_payload_tready), - .input_3_eth_payload_tlast(input_3_eth_payload_tlast), - .input_3_eth_payload_tuser(input_3_eth_payload_tuser), - .output_eth_hdr_valid(output_eth_hdr_valid), - .output_eth_hdr_ready(output_eth_hdr_ready), - .output_eth_dest_mac(output_eth_dest_mac), - .output_eth_src_mac(output_eth_src_mac), - .output_eth_type(output_eth_type), - .output_eth_payload_tdata(output_eth_payload_tdata), - .output_eth_payload_tkeep(output_eth_payload_tkeep), - .output_eth_payload_tvalid(output_eth_payload_tvalid), - .output_eth_payload_tready(output_eth_payload_tready), - .output_eth_payload_tlast(output_eth_payload_tlast), - .output_eth_payload_tuser(output_eth_payload_tuser), - .enable(grant_valid), - .select(grant_encoded) -); - -// arbiter instance -arbiter #( - .PORTS(4), - .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE"), - .LSB_PRIORITY(LSB_PRIORITY) -) -arb_inst ( - .clk(clk), - .rst(rst), - .request(request), - .acknowledge(acknowledge), - .grant(grant), - .grant_valid(grant_valid), - .grant_encoded(grant_encoded) -); - -endmodule diff --git a/tb/test_eth_arb_mux_4.py b/tb/test_eth_arb_mux_4.py index 55f2308e8..bd4c62c4b 100755 --- a/tb/test_eth_arb_mux_4.py +++ b/tb/test_eth_arb_mux_4.py @@ -28,13 +28,12 @@ import os import eth_ep -module = 'eth_arb_mux_4' -testbench = 'test_%s' % module +module = 'eth_arb_mux' +testbench = 'test_%s_4' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_mux_4.v") srcs.append("../lib/axis/rtl/arbiter.v") srcs.append("../lib/axis/rtl/priority_encoder.v") srcs.append("%s.v" % testbench) @@ -45,164 +44,118 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) def bench(): + # Parameters + S_COUNT = 4 + DATA_WIDTH = 8 + KEEP_ENABLE = (DATA_WIDTH>8) + KEEP_WIDTH = (DATA_WIDTH/8) + ID_ENABLE = 1 + ID_WIDTH = 8 + DEST_ENABLE = 1 + DEST_WIDTH = 8 + USER_ENABLE = 1 + USER_WIDTH = 1 + ARB_TYPE = "PRIORITY" + LSB_PRIORITY = "HIGH" + # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - input_0_eth_hdr_valid = Signal(bool(0)) - input_0_eth_dest_mac = Signal(intbv(0)[48:]) - input_0_eth_src_mac = Signal(intbv(0)[48:]) - input_0_eth_type = Signal(intbv(0)[16:]) - input_0_eth_payload_tdata = Signal(intbv(0)[8:]) - input_0_eth_payload_tvalid = Signal(bool(0)) - input_0_eth_payload_tlast = Signal(bool(0)) - input_0_eth_payload_tuser = Signal(bool(0)) - input_1_eth_hdr_valid = Signal(bool(0)) - input_1_eth_dest_mac = Signal(intbv(0)[48:]) - input_1_eth_src_mac = Signal(intbv(0)[48:]) - input_1_eth_type = Signal(intbv(0)[16:]) - input_1_eth_payload_tdata = Signal(intbv(0)[8:]) - input_1_eth_payload_tvalid = Signal(bool(0)) - input_1_eth_payload_tlast = Signal(bool(0)) - input_1_eth_payload_tuser = Signal(bool(0)) - input_2_eth_hdr_valid = Signal(bool(0)) - input_2_eth_dest_mac = Signal(intbv(0)[48:]) - input_2_eth_src_mac = Signal(intbv(0)[48:]) - input_2_eth_type = Signal(intbv(0)[16:]) - input_2_eth_payload_tdata = Signal(intbv(0)[8:]) - input_2_eth_payload_tvalid = Signal(bool(0)) - input_2_eth_payload_tlast = Signal(bool(0)) - input_2_eth_payload_tuser = Signal(bool(0)) - input_3_eth_hdr_valid = Signal(bool(0)) - input_3_eth_dest_mac = Signal(intbv(0)[48:]) - input_3_eth_src_mac = Signal(intbv(0)[48:]) - input_3_eth_type = Signal(intbv(0)[16:]) - input_3_eth_payload_tdata = Signal(intbv(0)[8:]) - input_3_eth_payload_tvalid = Signal(bool(0)) - input_3_eth_payload_tlast = Signal(bool(0)) - input_3_eth_payload_tuser = Signal(bool(0)) + s_eth_hdr_valid_list = [Signal(bool(0)) for i in range(S_COUNT)] + s_eth_dest_mac_list = [Signal(intbv(0)[48:]) for i in range(S_COUNT)] + s_eth_src_mac_list = [Signal(intbv(0)[48:]) for i in range(S_COUNT)] + s_eth_type_list = [Signal(intbv(0)[16:]) for i in range(S_COUNT)] + s_eth_payload_axis_tdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(S_COUNT)] + s_eth_payload_axis_tkeep_list = [Signal(intbv(1)[KEEP_WIDTH:]) for i in range(S_COUNT)] + s_eth_payload_axis_tvalid_list = [Signal(bool(0)) for i in range(S_COUNT)] + s_eth_payload_axis_tlast_list = [Signal(bool(0)) for i in range(S_COUNT)] + s_eth_payload_axis_tid_list = [Signal(intbv(0)[ID_WIDTH:]) for i in range(S_COUNT)] + s_eth_payload_axis_tdest_list = [Signal(intbv(0)[DEST_WIDTH:]) for i in range(S_COUNT)] + s_eth_payload_axis_tuser_list = [Signal(intbv(0)[USER_WIDTH:]) for i in range(S_COUNT)] - output_eth_payload_tready = Signal(bool(0)) - output_eth_hdr_ready = Signal(bool(0)) + s_eth_hdr_valid = ConcatSignal(*reversed(s_eth_hdr_valid_list)) + s_eth_dest_mac = ConcatSignal(*reversed(s_eth_dest_mac_list)) + s_eth_src_mac = ConcatSignal(*reversed(s_eth_src_mac_list)) + s_eth_type = ConcatSignal(*reversed(s_eth_type_list)) + s_eth_payload_axis_tdata = ConcatSignal(*reversed(s_eth_payload_axis_tdata_list)) + s_eth_payload_axis_tkeep = ConcatSignal(*reversed(s_eth_payload_axis_tkeep_list)) + s_eth_payload_axis_tvalid = ConcatSignal(*reversed(s_eth_payload_axis_tvalid_list)) + s_eth_payload_axis_tlast = ConcatSignal(*reversed(s_eth_payload_axis_tlast_list)) + s_eth_payload_axis_tid = ConcatSignal(*reversed(s_eth_payload_axis_tid_list)) + s_eth_payload_axis_tdest = ConcatSignal(*reversed(s_eth_payload_axis_tdest_list)) + s_eth_payload_axis_tuser = ConcatSignal(*reversed(s_eth_payload_axis_tuser_list)) + + m_eth_hdr_ready = Signal(bool(0)) + m_eth_payload_axis_tready = Signal(bool(0)) # Outputs - input_0_eth_hdr_ready = Signal(bool(0)) - input_0_eth_payload_tready = Signal(bool(0)) - input_1_eth_hdr_ready = Signal(bool(0)) - input_1_eth_payload_tready = Signal(bool(0)) - input_2_eth_hdr_ready = Signal(bool(0)) - input_2_eth_payload_tready = Signal(bool(0)) - input_3_eth_hdr_ready = Signal(bool(0)) - input_3_eth_payload_tready = Signal(bool(0)) + s_eth_hdr_ready = Signal(intbv(0)[S_COUNT:]) + s_eth_payload_axis_tready = Signal(intbv(0)[S_COUNT:]) - output_eth_hdr_valid = Signal(bool(0)) - output_eth_dest_mac = Signal(intbv(0)[48:]) - output_eth_src_mac = Signal(intbv(0)[48:]) - output_eth_type = Signal(intbv(0)[16:]) - output_eth_payload_tdata = Signal(intbv(0)[8:]) - output_eth_payload_tvalid = Signal(bool(0)) - output_eth_payload_tlast = Signal(bool(0)) - output_eth_payload_tuser = Signal(bool(0)) + s_eth_hdr_ready_list = [s_eth_hdr_ready(i) for i in range(S_COUNT)] + s_eth_payload_axis_tready_list = [s_eth_payload_axis_tready(i) for i in range(S_COUNT)] + + m_eth_hdr_valid = Signal(bool(0)) + m_eth_dest_mac = Signal(intbv(0)[48:]) + m_eth_src_mac = Signal(intbv(0)[48:]) + m_eth_type = Signal(intbv(0)[16:]) + m_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) + m_eth_payload_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:]) + m_eth_payload_axis_tvalid = Signal(bool(0)) + m_eth_payload_axis_tlast = Signal(bool(0)) + m_eth_payload_axis_tid = Signal(intbv(0)[ID_WIDTH:]) + m_eth_payload_axis_tdest = Signal(intbv(0)[DEST_WIDTH:]) + m_eth_payload_axis_tuser = Signal(intbv(0)[USER_WIDTH:]) # sources and sinks - source_0_pause = Signal(bool(0)) - source_1_pause = Signal(bool(0)) - source_2_pause = Signal(bool(0)) - source_3_pause = Signal(bool(0)) + source_pause_list = [] + source_list = [] + source_logic_list = [] sink_pause = Signal(bool(0)) - source_0 = eth_ep.EthFrameSource() + for k in range(S_COUNT): + s = eth_ep.EthFrameSource() + p = Signal(bool(0)) - source_0_logic = source_0.create_logic( - clk, - rst, - eth_hdr_ready=input_0_eth_hdr_ready, - eth_hdr_valid=input_0_eth_hdr_valid, - eth_dest_mac=input_0_eth_dest_mac, - eth_src_mac=input_0_eth_src_mac, - eth_type=input_0_eth_type, - eth_payload_tdata=input_0_eth_payload_tdata, - eth_payload_tvalid=input_0_eth_payload_tvalid, - eth_payload_tready=input_0_eth_payload_tready, - eth_payload_tlast=input_0_eth_payload_tlast, - eth_payload_tuser=input_0_eth_payload_tuser, - pause=source_0_pause, - name='source_0' - ) + source_list.append(s) + source_pause_list.append(p) - source_1 = eth_ep.EthFrameSource() - - source_1_logic = source_1.create_logic( - clk, - rst, - eth_hdr_ready=input_1_eth_hdr_ready, - eth_hdr_valid=input_1_eth_hdr_valid, - eth_dest_mac=input_1_eth_dest_mac, - eth_src_mac=input_1_eth_src_mac, - eth_type=input_1_eth_type, - eth_payload_tdata=input_1_eth_payload_tdata, - eth_payload_tvalid=input_1_eth_payload_tvalid, - eth_payload_tready=input_1_eth_payload_tready, - eth_payload_tlast=input_1_eth_payload_tlast, - eth_payload_tuser=input_1_eth_payload_tuser, - pause=source_1_pause, - name='source_1' - ) - - source_2 = eth_ep.EthFrameSource() - - source_2_logic = source_2.create_logic( - clk, - rst, - eth_hdr_ready=input_2_eth_hdr_ready, - eth_hdr_valid=input_2_eth_hdr_valid, - eth_dest_mac=input_2_eth_dest_mac, - eth_src_mac=input_2_eth_src_mac, - eth_type=input_2_eth_type, - eth_payload_tdata=input_2_eth_payload_tdata, - eth_payload_tvalid=input_2_eth_payload_tvalid, - eth_payload_tready=input_2_eth_payload_tready, - eth_payload_tlast=input_2_eth_payload_tlast, - eth_payload_tuser=input_2_eth_payload_tuser, - pause=source_2_pause, - name='source_2' - ) - - source_3 = eth_ep.EthFrameSource() - - source_3_logic = source_3.create_logic( - clk, - rst, - eth_hdr_ready=input_3_eth_hdr_ready, - eth_hdr_valid=input_3_eth_hdr_valid, - eth_dest_mac=input_3_eth_dest_mac, - eth_src_mac=input_3_eth_src_mac, - eth_type=input_3_eth_type, - eth_payload_tdata=input_3_eth_payload_tdata, - eth_payload_tvalid=input_3_eth_payload_tvalid, - eth_payload_tready=input_3_eth_payload_tready, - eth_payload_tlast=input_3_eth_payload_tlast, - eth_payload_tuser=input_3_eth_payload_tuser, - pause=source_3_pause, - name='source_3' - ) + source_logic_list.append(s.create_logic( + clk, + rst, + eth_hdr_ready=s_eth_hdr_ready_list[k], + eth_hdr_valid=s_eth_hdr_valid_list[k], + eth_dest_mac=s_eth_dest_mac_list[k], + eth_src_mac=s_eth_src_mac_list[k], + eth_type=s_eth_type_list[k], + eth_payload_tdata=s_eth_payload_axis_tdata_list[k], + eth_payload_tkeep=s_eth_payload_axis_tkeep_list[k], + eth_payload_tvalid=s_eth_payload_axis_tvalid_list[k], + eth_payload_tready=s_eth_payload_axis_tready_list[k], + eth_payload_tlast=s_eth_payload_axis_tlast_list[k], + eth_payload_tuser=s_eth_payload_axis_tuser_list[k], + pause=p, + name='source_%d' % k + )) sink = eth_ep.EthFrameSink() sink_logic = sink.create_logic( clk, rst, - eth_hdr_ready=output_eth_hdr_ready, - eth_hdr_valid=output_eth_hdr_valid, - eth_dest_mac=output_eth_dest_mac, - eth_src_mac=output_eth_src_mac, - eth_type=output_eth_type, - eth_payload_tdata=output_eth_payload_tdata, - eth_payload_tvalid=output_eth_payload_tvalid, - eth_payload_tready=output_eth_payload_tready, - eth_payload_tlast=output_eth_payload_tlast, - eth_payload_tuser=output_eth_payload_tuser, + eth_hdr_ready=m_eth_hdr_ready, + eth_hdr_valid=m_eth_hdr_valid, + eth_dest_mac=m_eth_dest_mac, + eth_src_mac=m_eth_src_mac, + eth_type=m_eth_type, + eth_payload_tdata=m_eth_payload_axis_tdata, + eth_payload_tkeep=m_eth_payload_axis_tkeep, + eth_payload_tvalid=m_eth_payload_axis_tvalid, + eth_payload_tready=m_eth_payload_axis_tready, + eth_payload_tlast=m_eth_payload_axis_tlast, + eth_payload_tuser=m_eth_payload_axis_tuser, pause=sink_pause, name='sink' ) @@ -217,57 +170,33 @@ def bench(): rst=rst, current_test=current_test, - input_0_eth_hdr_valid=input_0_eth_hdr_valid, - input_0_eth_hdr_ready=input_0_eth_hdr_ready, - input_0_eth_dest_mac=input_0_eth_dest_mac, - input_0_eth_src_mac=input_0_eth_src_mac, - input_0_eth_type=input_0_eth_type, - input_0_eth_payload_tdata=input_0_eth_payload_tdata, - input_0_eth_payload_tvalid=input_0_eth_payload_tvalid, - input_0_eth_payload_tready=input_0_eth_payload_tready, - input_0_eth_payload_tlast=input_0_eth_payload_tlast, - input_0_eth_payload_tuser=input_0_eth_payload_tuser, - input_1_eth_hdr_valid=input_1_eth_hdr_valid, - input_1_eth_hdr_ready=input_1_eth_hdr_ready, - input_1_eth_dest_mac=input_1_eth_dest_mac, - input_1_eth_src_mac=input_1_eth_src_mac, - input_1_eth_type=input_1_eth_type, - input_1_eth_payload_tdata=input_1_eth_payload_tdata, - input_1_eth_payload_tvalid=input_1_eth_payload_tvalid, - input_1_eth_payload_tready=input_1_eth_payload_tready, - input_1_eth_payload_tlast=input_1_eth_payload_tlast, - input_1_eth_payload_tuser=input_1_eth_payload_tuser, - input_2_eth_hdr_valid=input_2_eth_hdr_valid, - input_2_eth_hdr_ready=input_2_eth_hdr_ready, - input_2_eth_dest_mac=input_2_eth_dest_mac, - input_2_eth_src_mac=input_2_eth_src_mac, - input_2_eth_type=input_2_eth_type, - input_2_eth_payload_tdata=input_2_eth_payload_tdata, - input_2_eth_payload_tvalid=input_2_eth_payload_tvalid, - input_2_eth_payload_tready=input_2_eth_payload_tready, - input_2_eth_payload_tlast=input_2_eth_payload_tlast, - input_2_eth_payload_tuser=input_2_eth_payload_tuser, - input_3_eth_hdr_valid=input_3_eth_hdr_valid, - input_3_eth_hdr_ready=input_3_eth_hdr_ready, - input_3_eth_dest_mac=input_3_eth_dest_mac, - input_3_eth_src_mac=input_3_eth_src_mac, - input_3_eth_type=input_3_eth_type, - input_3_eth_payload_tdata=input_3_eth_payload_tdata, - input_3_eth_payload_tvalid=input_3_eth_payload_tvalid, - input_3_eth_payload_tready=input_3_eth_payload_tready, - input_3_eth_payload_tlast=input_3_eth_payload_tlast, - input_3_eth_payload_tuser=input_3_eth_payload_tuser, + s_eth_hdr_valid=s_eth_hdr_valid, + s_eth_hdr_ready=s_eth_hdr_ready, + s_eth_dest_mac=s_eth_dest_mac, + s_eth_src_mac=s_eth_src_mac, + s_eth_type=s_eth_type, + s_eth_payload_axis_tdata=s_eth_payload_axis_tdata, + s_eth_payload_axis_tkeep=s_eth_payload_axis_tkeep, + s_eth_payload_axis_tvalid=s_eth_payload_axis_tvalid, + s_eth_payload_axis_tready=s_eth_payload_axis_tready, + s_eth_payload_axis_tlast=s_eth_payload_axis_tlast, + s_eth_payload_axis_tid=s_eth_payload_axis_tid, + s_eth_payload_axis_tdest=s_eth_payload_axis_tdest, + s_eth_payload_axis_tuser=s_eth_payload_axis_tuser, - output_eth_hdr_valid=output_eth_hdr_valid, - output_eth_hdr_ready=output_eth_hdr_ready, - output_eth_dest_mac=output_eth_dest_mac, - output_eth_src_mac=output_eth_src_mac, - output_eth_type=output_eth_type, - output_eth_payload_tdata=output_eth_payload_tdata, - output_eth_payload_tvalid=output_eth_payload_tvalid, - output_eth_payload_tready=output_eth_payload_tready, - output_eth_payload_tlast=output_eth_payload_tlast, - output_eth_payload_tuser=output_eth_payload_tuser + m_eth_hdr_valid=m_eth_hdr_valid, + m_eth_hdr_ready=m_eth_hdr_ready, + m_eth_dest_mac=m_eth_dest_mac, + m_eth_src_mac=m_eth_src_mac, + m_eth_type=m_eth_type, + m_eth_payload_axis_tdata=m_eth_payload_axis_tdata, + m_eth_payload_axis_tkeep=m_eth_payload_axis_tkeep, + m_eth_payload_axis_tvalid=m_eth_payload_axis_tvalid, + m_eth_payload_axis_tready=m_eth_payload_axis_tready, + m_eth_payload_axis_tlast=m_eth_payload_axis_tlast, + m_eth_payload_axis_tid=m_eth_payload_axis_tid, + m_eth_payload_axis_tdest=m_eth_payload_axis_tdest, + m_eth_payload_axis_tuser=m_eth_payload_axis_tuser ) @always(delay(4)) @@ -297,7 +226,7 @@ def bench(): test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(32)) - source_0.send(test_frame) + source_list[0].send(test_frame) yield sink.wait() rx_frame = sink.recv() @@ -316,7 +245,7 @@ def bench(): test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(32)) - source_1.send(test_frame) + source_list[1].send(test_frame) yield sink.wait() rx_frame = sink.recv() @@ -340,8 +269,8 @@ def bench(): test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(32)) - source_0.send(test_frame1) - source_0.send(test_frame2) + source_list[0].send(test_frame1) + source_list[0].send(test_frame2) yield sink.wait() rx_frame = sink.recv() @@ -370,8 +299,8 @@ def bench(): test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(32)) - source_1.send(test_frame1) - source_2.send(test_frame2) + source_list[1].send(test_frame1) + source_list[2].send(test_frame2) yield sink.wait() rx_frame = sink.recv() @@ -400,23 +329,23 @@ def bench(): test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(32)) - source_1.send(test_frame1) - source_2.send(test_frame2) + source_list[1].send(test_frame1) + source_list[2].send(test_frame2) yield clk.posedge yield clk.posedge - while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: - source_0_pause.next = True - source_1_pause.next = True - source_2_pause.next = True - source_3_pause.next = True + while s_eth_payload_axis_tvalid: + source_pause_list[0].next = True + source_pause_list[1].next = True + source_pause_list[2].next = True + source_pause_list[3].next = True yield clk.posedge yield clk.posedge yield clk.posedge - source_0_pause.next = False - source_1_pause.next = False - source_2_pause.next = False - source_3_pause.next = False + source_pause_list[0].next = False + source_pause_list[1].next = False + source_pause_list[2].next = False + source_pause_list[3].next = False yield clk.posedge yield sink.wait() @@ -446,12 +375,12 @@ def bench(): test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(32)) - source_1.send(test_frame1) - source_2.send(test_frame2) + source_list[1].send(test_frame1) + source_list[2].send(test_frame2) yield clk.posedge yield clk.posedge - while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + while s_eth_payload_axis_tvalid: sink_pause.next = True yield clk.posedge yield clk.posedge @@ -486,17 +415,17 @@ def bench(): test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(32)) - source_1.send(test_frame1) - source_2.send(test_frame2) - source_2.send(test_frame2) - source_2.send(test_frame2) - source_2.send(test_frame2) - source_2.send(test_frame2) + source_list[1].send(test_frame1) + source_list[2].send(test_frame2) + source_list[2].send(test_frame2) + source_list[2].send(test_frame2) + source_list[2].send(test_frame2) + source_list[2].send(test_frame2) yield clk.posedge yield delay(800) yield clk.posedge - source_1.send(test_frame1) + source_list[1].send(test_frame1) yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_eth_arb_mux_4.v b/tb/test_eth_arb_mux_4.v index 55e8bb8dd..6c98fb762 100644 --- a/tb/test_eth_arb_mux_4.v +++ b/tb/test_eth_arb_mux_4.v @@ -27,69 +27,59 @@ THE SOFTWARE. `timescale 1ns / 1ps /* - * Testbench for eth_arb_mux_4 + * Testbench for eth_arb_mux */ module test_eth_arb_mux_4; +// Parameters +parameter S_COUNT = 4; +parameter DATA_WIDTH = 8; +parameter KEEP_ENABLE = (DATA_WIDTH>8); +parameter KEEP_WIDTH = (DATA_WIDTH/8); +parameter ID_ENABLE = 1; +parameter ID_WIDTH = 8; +parameter DEST_ENABLE = 1; +parameter DEST_WIDTH = 8; +parameter USER_ENABLE = 1; +parameter USER_WIDTH = 1; +parameter ARB_TYPE = "PRIORITY"; +parameter LSB_PRIORITY = "HIGH"; + // Inputs reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg input_0_eth_hdr_valid = 0; -reg [47:0] input_0_eth_dest_mac = 0; -reg [47:0] input_0_eth_src_mac = 0; -reg [15:0] input_0_eth_type = 0; -reg [7:0] input_0_eth_payload_tdata = 0; -reg input_0_eth_payload_tvalid = 0; -reg input_0_eth_payload_tlast = 0; -reg input_0_eth_payload_tuser = 0; -reg input_1_eth_hdr_valid = 0; -reg [47:0] input_1_eth_dest_mac = 0; -reg [47:0] input_1_eth_src_mac = 0; -reg [15:0] input_1_eth_type = 0; -reg [7:0] input_1_eth_payload_tdata = 0; -reg input_1_eth_payload_tvalid = 0; -reg input_1_eth_payload_tlast = 0; -reg input_1_eth_payload_tuser = 0; -reg input_2_eth_hdr_valid = 0; -reg [47:0] input_2_eth_dest_mac = 0; -reg [47:0] input_2_eth_src_mac = 0; -reg [15:0] input_2_eth_type = 0; -reg [7:0] input_2_eth_payload_tdata = 0; -reg input_2_eth_payload_tvalid = 0; -reg input_2_eth_payload_tlast = 0; -reg input_2_eth_payload_tuser = 0; -reg input_3_eth_hdr_valid = 0; -reg [47:0] input_3_eth_dest_mac = 0; -reg [47:0] input_3_eth_src_mac = 0; -reg [15:0] input_3_eth_type = 0; -reg [7:0] input_3_eth_payload_tdata = 0; -reg input_3_eth_payload_tvalid = 0; -reg input_3_eth_payload_tlast = 0; -reg input_3_eth_payload_tuser = 0; +reg [S_COUNT-1:0] s_eth_hdr_valid = 0; +reg [S_COUNT*48-1:0] s_eth_dest_mac = 0; +reg [S_COUNT*48-1:0] s_eth_src_mac = 0; +reg [S_COUNT*16-1:0] s_eth_type = 0; +reg [S_COUNT*DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0; +reg [S_COUNT*KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0; +reg [S_COUNT-1:0] s_eth_payload_axis_tvalid = 0; +reg [S_COUNT-1:0] s_eth_payload_axis_tlast = 0; +reg [S_COUNT*ID_WIDTH-1:0] s_eth_payload_axis_tid = 0; +reg [S_COUNT*DEST_WIDTH-1:0] s_eth_payload_axis_tdest = 0; +reg [S_COUNT*USER_WIDTH-1:0] s_eth_payload_axis_tuser = 0; -reg output_eth_hdr_ready = 0; -reg output_eth_payload_tready = 0; +reg m_eth_hdr_ready = 0; +reg m_eth_payload_axis_tready = 0; // Outputs -wire input_0_eth_payload_tready; -wire input_0_eth_hdr_ready; -wire input_1_eth_payload_tready; -wire input_1_eth_hdr_ready; -wire input_2_eth_payload_tready; -wire input_2_eth_hdr_ready; -wire input_3_eth_payload_tready; -wire input_3_eth_hdr_ready; +wire [S_COUNT-1:0] s_eth_hdr_ready; +wire [S_COUNT-1:0] s_eth_payload_axis_tready; -wire output_eth_hdr_valid; -wire [47:0] output_eth_dest_mac; -wire [47:0] output_eth_src_mac; -wire [15:0] output_eth_type; -wire [7:0] output_eth_payload_tdata; -wire output_eth_payload_tvalid; -wire output_eth_payload_tlast; -wire output_eth_payload_tuser; +wire m_eth_hdr_valid; +wire [47:0] m_eth_dest_mac; +wire [47:0] m_eth_src_mac; +wire [15:0] m_eth_type; +wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata; +wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep; +wire m_eth_payload_axis_tvalid; +wire m_eth_payload_axis_tlast; +wire [ID_WIDTH-1:0] m_eth_payload_axis_tid; +wire [DEST_WIDTH-1:0] m_eth_payload_axis_tdest; +wire [USER_WIDTH-1:0] m_eth_payload_axis_tuser; initial begin // myhdl integration @@ -97,58 +87,34 @@ initial begin clk, rst, current_test, - input_0_eth_hdr_valid, - input_0_eth_dest_mac, - input_0_eth_src_mac, - input_0_eth_type, - input_0_eth_payload_tdata, - input_0_eth_payload_tvalid, - input_0_eth_payload_tlast, - input_0_eth_payload_tuser, - input_1_eth_hdr_valid, - input_1_eth_dest_mac, - input_1_eth_src_mac, - input_1_eth_type, - input_1_eth_payload_tdata, - input_1_eth_payload_tvalid, - input_1_eth_payload_tlast, - input_1_eth_payload_tuser, - input_2_eth_hdr_valid, - input_2_eth_dest_mac, - input_2_eth_src_mac, - input_2_eth_type, - input_2_eth_payload_tdata, - input_2_eth_payload_tvalid, - input_2_eth_payload_tlast, - input_2_eth_payload_tuser, - input_3_eth_hdr_valid, - input_3_eth_dest_mac, - input_3_eth_src_mac, - input_3_eth_type, - input_3_eth_payload_tdata, - input_3_eth_payload_tvalid, - input_3_eth_payload_tlast, - input_3_eth_payload_tuser, - output_eth_hdr_ready, - output_eth_payload_tready + s_eth_hdr_valid, + s_eth_dest_mac, + s_eth_src_mac, + s_eth_type, + s_eth_payload_axis_tdata, + s_eth_payload_axis_tkeep, + s_eth_payload_axis_tvalid, + s_eth_payload_axis_tlast, + s_eth_payload_axis_tid, + s_eth_payload_axis_tdest, + s_eth_payload_axis_tuser, + m_eth_hdr_ready, + m_eth_payload_axis_tready ); $to_myhdl( - input_0_eth_hdr_ready, - input_0_eth_payload_tready, - input_1_eth_hdr_ready, - input_1_eth_payload_tready, - input_2_eth_hdr_ready, - input_2_eth_payload_tready, - input_3_eth_hdr_ready, - input_3_eth_payload_tready, - output_eth_hdr_valid, - output_eth_dest_mac, - output_eth_src_mac, - output_eth_type, - output_eth_payload_tdata, - output_eth_payload_tvalid, - output_eth_payload_tlast, - output_eth_payload_tuser + s_eth_hdr_ready, + s_eth_payload_axis_tready, + m_eth_hdr_valid, + m_eth_dest_mac, + m_eth_src_mac, + m_eth_type, + m_eth_payload_axis_tdata, + m_eth_payload_axis_tkeep, + m_eth_payload_axis_tvalid, + m_eth_payload_axis_tlast, + m_eth_payload_axis_tid, + m_eth_payload_axis_tdest, + m_eth_payload_axis_tuser ); // dump file @@ -156,62 +122,51 @@ initial begin $dumpvars(0, test_eth_arb_mux_4); end -eth_arb_mux_4 +eth_arb_mux #( + .S_COUNT(S_COUNT), + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(KEEP_ENABLE), + .KEEP_WIDTH(KEEP_WIDTH), + .ID_ENABLE(ID_ENABLE), + .ID_WIDTH(ID_WIDTH), + .DEST_ENABLE(DEST_ENABLE), + .DEST_WIDTH(DEST_WIDTH), + .USER_ENABLE(USER_ENABLE), + .USER_WIDTH(USER_WIDTH), + .ARB_TYPE(ARB_TYPE), + .LSB_PRIORITY(LSB_PRIORITY) +) UUT ( .clk(clk), .rst(rst), // Ethernet frame inputs - .input_0_eth_hdr_valid(input_0_eth_hdr_valid), - .input_0_eth_hdr_ready(input_0_eth_hdr_ready), - .input_0_eth_dest_mac(input_0_eth_dest_mac), - .input_0_eth_src_mac(input_0_eth_src_mac), - .input_0_eth_type(input_0_eth_type), - .input_0_eth_payload_tdata(input_0_eth_payload_tdata), - .input_0_eth_payload_tvalid(input_0_eth_payload_tvalid), - .input_0_eth_payload_tready(input_0_eth_payload_tready), - .input_0_eth_payload_tlast(input_0_eth_payload_tlast), - .input_0_eth_payload_tuser(input_0_eth_payload_tuser), - .input_1_eth_hdr_valid(input_1_eth_hdr_valid), - .input_1_eth_hdr_ready(input_1_eth_hdr_ready), - .input_1_eth_dest_mac(input_1_eth_dest_mac), - .input_1_eth_src_mac(input_1_eth_src_mac), - .input_1_eth_type(input_1_eth_type), - .input_1_eth_payload_tdata(input_1_eth_payload_tdata), - .input_1_eth_payload_tvalid(input_1_eth_payload_tvalid), - .input_1_eth_payload_tready(input_1_eth_payload_tready), - .input_1_eth_payload_tlast(input_1_eth_payload_tlast), - .input_1_eth_payload_tuser(input_1_eth_payload_tuser), - .input_2_eth_hdr_valid(input_2_eth_hdr_valid), - .input_2_eth_hdr_ready(input_2_eth_hdr_ready), - .input_2_eth_dest_mac(input_2_eth_dest_mac), - .input_2_eth_src_mac(input_2_eth_src_mac), - .input_2_eth_type(input_2_eth_type), - .input_2_eth_payload_tdata(input_2_eth_payload_tdata), - .input_2_eth_payload_tvalid(input_2_eth_payload_tvalid), - .input_2_eth_payload_tready(input_2_eth_payload_tready), - .input_2_eth_payload_tlast(input_2_eth_payload_tlast), - .input_2_eth_payload_tuser(input_2_eth_payload_tuser), - .input_3_eth_hdr_valid(input_3_eth_hdr_valid), - .input_3_eth_hdr_ready(input_3_eth_hdr_ready), - .input_3_eth_dest_mac(input_3_eth_dest_mac), - .input_3_eth_src_mac(input_3_eth_src_mac), - .input_3_eth_type(input_3_eth_type), - .input_3_eth_payload_tdata(input_3_eth_payload_tdata), - .input_3_eth_payload_tvalid(input_3_eth_payload_tvalid), - .input_3_eth_payload_tready(input_3_eth_payload_tready), - .input_3_eth_payload_tlast(input_3_eth_payload_tlast), - .input_3_eth_payload_tuser(input_3_eth_payload_tuser), - // Eth frame output - .output_eth_hdr_valid(output_eth_hdr_valid), - .output_eth_hdr_ready(output_eth_hdr_ready), - .output_eth_dest_mac(output_eth_dest_mac), - .output_eth_src_mac(output_eth_src_mac), - .output_eth_type(output_eth_type), - .output_eth_payload_tdata(output_eth_payload_tdata), - .output_eth_payload_tvalid(output_eth_payload_tvalid), - .output_eth_payload_tready(output_eth_payload_tready), - .output_eth_payload_tlast(output_eth_payload_tlast), - .output_eth_payload_tuser(output_eth_payload_tuser) + .s_eth_hdr_valid(s_eth_hdr_valid), + .s_eth_hdr_ready(s_eth_hdr_ready), + .s_eth_dest_mac(s_eth_dest_mac), + .s_eth_src_mac(s_eth_src_mac), + .s_eth_type(s_eth_type), + .s_eth_payload_axis_tdata(s_eth_payload_axis_tdata), + .s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep), + .s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(s_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(s_eth_payload_axis_tlast), + .s_eth_payload_axis_tid(s_eth_payload_axis_tid), + .s_eth_payload_axis_tdest(s_eth_payload_axis_tdest), + .s_eth_payload_axis_tuser(s_eth_payload_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(m_eth_hdr_valid), + .m_eth_hdr_ready(m_eth_hdr_ready), + .m_eth_dest_mac(m_eth_dest_mac), + .m_eth_src_mac(m_eth_src_mac), + .m_eth_type(m_eth_type), + .m_eth_payload_axis_tdata(m_eth_payload_axis_tdata), + .m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep), + .m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(m_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(m_eth_payload_axis_tlast), + .m_eth_payload_axis_tid(m_eth_payload_axis_tid), + .m_eth_payload_axis_tdest(m_eth_payload_axis_tdest), + .m_eth_payload_axis_tuser(m_eth_payload_axis_tuser) ); endmodule diff --git a/tb/test_eth_arb_mux_64_4.py b/tb/test_eth_arb_mux_64_4.py index e90d9208c..86104b6d6 100755 --- a/tb/test_eth_arb_mux_64_4.py +++ b/tb/test_eth_arb_mux_64_4.py @@ -28,13 +28,12 @@ import os import eth_ep -module = 'eth_arb_mux_64_4' -testbench = 'test_%s' % module +module = 'eth_arb_mux' +testbench = 'test_%s_64_4' % module srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_mux_64_4.v") srcs.append("../lib/axis/rtl/arbiter.v") srcs.append("../lib/axis/rtl/priority_encoder.v") srcs.append("%s.v" % testbench) @@ -45,174 +44,118 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) def bench(): + # Parameters + S_COUNT = 4 + DATA_WIDTH = 64 + KEEP_ENABLE = (DATA_WIDTH>8) + KEEP_WIDTH = (DATA_WIDTH/8) + ID_ENABLE = 1 + ID_WIDTH = 8 + DEST_ENABLE = 1 + DEST_WIDTH = 8 + USER_ENABLE = 1 + USER_WIDTH = 1 + ARB_TYPE = "PRIORITY" + LSB_PRIORITY = "HIGH" + # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - input_0_eth_hdr_valid = Signal(bool(0)) - input_0_eth_dest_mac = Signal(intbv(0)[48:]) - input_0_eth_src_mac = Signal(intbv(0)[48:]) - input_0_eth_type = Signal(intbv(0)[16:]) - input_0_eth_payload_tdata = Signal(intbv(0)[64:]) - input_0_eth_payload_tkeep = Signal(intbv(0)[8:]) - input_0_eth_payload_tvalid = Signal(bool(0)) - input_0_eth_payload_tlast = Signal(bool(0)) - input_0_eth_payload_tuser = Signal(bool(0)) - input_1_eth_hdr_valid = Signal(bool(0)) - input_1_eth_dest_mac = Signal(intbv(0)[48:]) - input_1_eth_src_mac = Signal(intbv(0)[48:]) - input_1_eth_type = Signal(intbv(0)[16:]) - input_1_eth_payload_tdata = Signal(intbv(0)[64:]) - input_1_eth_payload_tkeep = Signal(intbv(0)[8:]) - input_1_eth_payload_tvalid = Signal(bool(0)) - input_1_eth_payload_tlast = Signal(bool(0)) - input_1_eth_payload_tuser = Signal(bool(0)) - input_2_eth_hdr_valid = Signal(bool(0)) - input_2_eth_dest_mac = Signal(intbv(0)[48:]) - input_2_eth_src_mac = Signal(intbv(0)[48:]) - input_2_eth_type = Signal(intbv(0)[16:]) - input_2_eth_payload_tdata = Signal(intbv(0)[64:]) - input_2_eth_payload_tkeep = Signal(intbv(0)[8:]) - input_2_eth_payload_tvalid = Signal(bool(0)) - input_2_eth_payload_tlast = Signal(bool(0)) - input_2_eth_payload_tuser = Signal(bool(0)) - input_3_eth_hdr_valid = Signal(bool(0)) - input_3_eth_dest_mac = Signal(intbv(0)[48:]) - input_3_eth_src_mac = Signal(intbv(0)[48:]) - input_3_eth_type = Signal(intbv(0)[16:]) - input_3_eth_payload_tdata = Signal(intbv(0)[64:]) - input_3_eth_payload_tkeep = Signal(intbv(0)[8:]) - input_3_eth_payload_tvalid = Signal(bool(0)) - input_3_eth_payload_tlast = Signal(bool(0)) - input_3_eth_payload_tuser = Signal(bool(0)) + s_eth_hdr_valid_list = [Signal(bool(0)) for i in range(S_COUNT)] + s_eth_dest_mac_list = [Signal(intbv(0)[48:]) for i in range(S_COUNT)] + s_eth_src_mac_list = [Signal(intbv(0)[48:]) for i in range(S_COUNT)] + s_eth_type_list = [Signal(intbv(0)[16:]) for i in range(S_COUNT)] + s_eth_payload_axis_tdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(S_COUNT)] + s_eth_payload_axis_tkeep_list = [Signal(intbv(1)[KEEP_WIDTH:]) for i in range(S_COUNT)] + s_eth_payload_axis_tvalid_list = [Signal(bool(0)) for i in range(S_COUNT)] + s_eth_payload_axis_tlast_list = [Signal(bool(0)) for i in range(S_COUNT)] + s_eth_payload_axis_tid_list = [Signal(intbv(0)[ID_WIDTH:]) for i in range(S_COUNT)] + s_eth_payload_axis_tdest_list = [Signal(intbv(0)[DEST_WIDTH:]) for i in range(S_COUNT)] + s_eth_payload_axis_tuser_list = [Signal(intbv(0)[USER_WIDTH:]) for i in range(S_COUNT)] - output_eth_payload_tready = Signal(bool(0)) - output_eth_hdr_ready = Signal(bool(0)) + s_eth_hdr_valid = ConcatSignal(*reversed(s_eth_hdr_valid_list)) + s_eth_dest_mac = ConcatSignal(*reversed(s_eth_dest_mac_list)) + s_eth_src_mac = ConcatSignal(*reversed(s_eth_src_mac_list)) + s_eth_type = ConcatSignal(*reversed(s_eth_type_list)) + s_eth_payload_axis_tdata = ConcatSignal(*reversed(s_eth_payload_axis_tdata_list)) + s_eth_payload_axis_tkeep = ConcatSignal(*reversed(s_eth_payload_axis_tkeep_list)) + s_eth_payload_axis_tvalid = ConcatSignal(*reversed(s_eth_payload_axis_tvalid_list)) + s_eth_payload_axis_tlast = ConcatSignal(*reversed(s_eth_payload_axis_tlast_list)) + s_eth_payload_axis_tid = ConcatSignal(*reversed(s_eth_payload_axis_tid_list)) + s_eth_payload_axis_tdest = ConcatSignal(*reversed(s_eth_payload_axis_tdest_list)) + s_eth_payload_axis_tuser = ConcatSignal(*reversed(s_eth_payload_axis_tuser_list)) + + m_eth_hdr_ready = Signal(bool(0)) + m_eth_payload_axis_tready = Signal(bool(0)) # Outputs - input_0_eth_hdr_ready = Signal(bool(0)) - input_0_eth_payload_tready = Signal(bool(0)) - input_1_eth_hdr_ready = Signal(bool(0)) - input_1_eth_payload_tready = Signal(bool(0)) - input_2_eth_hdr_ready = Signal(bool(0)) - input_2_eth_payload_tready = Signal(bool(0)) - input_3_eth_hdr_ready = Signal(bool(0)) - input_3_eth_payload_tready = Signal(bool(0)) + s_eth_hdr_ready = Signal(intbv(0)[S_COUNT:]) + s_eth_payload_axis_tready = Signal(intbv(0)[S_COUNT:]) - output_eth_hdr_valid = Signal(bool(0)) - output_eth_dest_mac = Signal(intbv(0)[48:]) - output_eth_src_mac = Signal(intbv(0)[48:]) - output_eth_type = Signal(intbv(0)[16:]) - output_eth_payload_tdata = Signal(intbv(0)[64:]) - output_eth_payload_tkeep = Signal(intbv(0)[8:]) - output_eth_payload_tvalid = Signal(bool(0)) - output_eth_payload_tlast = Signal(bool(0)) - output_eth_payload_tuser = Signal(bool(0)) + s_eth_hdr_ready_list = [s_eth_hdr_ready(i) for i in range(S_COUNT)] + s_eth_payload_axis_tready_list = [s_eth_payload_axis_tready(i) for i in range(S_COUNT)] + + m_eth_hdr_valid = Signal(bool(0)) + m_eth_dest_mac = Signal(intbv(0)[48:]) + m_eth_src_mac = Signal(intbv(0)[48:]) + m_eth_type = Signal(intbv(0)[16:]) + m_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) + m_eth_payload_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:]) + m_eth_payload_axis_tvalid = Signal(bool(0)) + m_eth_payload_axis_tlast = Signal(bool(0)) + m_eth_payload_axis_tid = Signal(intbv(0)[ID_WIDTH:]) + m_eth_payload_axis_tdest = Signal(intbv(0)[DEST_WIDTH:]) + m_eth_payload_axis_tuser = Signal(intbv(0)[USER_WIDTH:]) # sources and sinks - source_0_pause = Signal(bool(0)) - source_1_pause = Signal(bool(0)) - source_2_pause = Signal(bool(0)) - source_3_pause = Signal(bool(0)) + source_pause_list = [] + source_list = [] + source_logic_list = [] sink_pause = Signal(bool(0)) - source_0 = eth_ep.EthFrameSource() + for k in range(S_COUNT): + s = eth_ep.EthFrameSource() + p = Signal(bool(0)) - source_0_logic = source_0.create_logic( - clk, - rst, - eth_hdr_ready=input_0_eth_hdr_ready, - eth_hdr_valid=input_0_eth_hdr_valid, - eth_dest_mac=input_0_eth_dest_mac, - eth_src_mac=input_0_eth_src_mac, - eth_type=input_0_eth_type, - eth_payload_tdata=input_0_eth_payload_tdata, - eth_payload_tkeep=input_0_eth_payload_tkeep, - eth_payload_tvalid=input_0_eth_payload_tvalid, - eth_payload_tready=input_0_eth_payload_tready, - eth_payload_tlast=input_0_eth_payload_tlast, - eth_payload_tuser=input_0_eth_payload_tuser, - pause=source_0_pause, - name='source_0' - ) + source_list.append(s) + source_pause_list.append(p) - source_1 = eth_ep.EthFrameSource() - - source_1_logic = source_1.create_logic( - clk, - rst, - eth_hdr_ready=input_1_eth_hdr_ready, - eth_hdr_valid=input_1_eth_hdr_valid, - eth_dest_mac=input_1_eth_dest_mac, - eth_src_mac=input_1_eth_src_mac, - eth_type=input_1_eth_type, - eth_payload_tdata=input_1_eth_payload_tdata, - eth_payload_tkeep=input_1_eth_payload_tkeep, - eth_payload_tvalid=input_1_eth_payload_tvalid, - eth_payload_tready=input_1_eth_payload_tready, - eth_payload_tlast=input_1_eth_payload_tlast, - eth_payload_tuser=input_1_eth_payload_tuser, - pause=source_1_pause, - name='source_1' - ) - - source_2 = eth_ep.EthFrameSource() - - source_2_logic = source_2.create_logic( - clk, - rst, - eth_hdr_ready=input_2_eth_hdr_ready, - eth_hdr_valid=input_2_eth_hdr_valid, - eth_dest_mac=input_2_eth_dest_mac, - eth_src_mac=input_2_eth_src_mac, - eth_type=input_2_eth_type, - eth_payload_tdata=input_2_eth_payload_tdata, - eth_payload_tkeep=input_2_eth_payload_tkeep, - eth_payload_tvalid=input_2_eth_payload_tvalid, - eth_payload_tready=input_2_eth_payload_tready, - eth_payload_tlast=input_2_eth_payload_tlast, - eth_payload_tuser=input_2_eth_payload_tuser, - pause=source_2_pause, - name='source_2' - ) - - source_3 = eth_ep.EthFrameSource() - - source_3_logic = source_3.create_logic( - clk, - rst, - eth_hdr_ready=input_3_eth_hdr_ready, - eth_hdr_valid=input_3_eth_hdr_valid, - eth_dest_mac=input_3_eth_dest_mac, - eth_src_mac=input_3_eth_src_mac, - eth_type=input_3_eth_type, - eth_payload_tdata=input_3_eth_payload_tdata, - eth_payload_tkeep=input_3_eth_payload_tkeep, - eth_payload_tvalid=input_3_eth_payload_tvalid, - eth_payload_tready=input_3_eth_payload_tready, - eth_payload_tlast=input_3_eth_payload_tlast, - eth_payload_tuser=input_3_eth_payload_tuser, - pause=source_3_pause, - name='source_3' - ) + source_logic_list.append(s.create_logic( + clk, + rst, + eth_hdr_ready=s_eth_hdr_ready_list[k], + eth_hdr_valid=s_eth_hdr_valid_list[k], + eth_dest_mac=s_eth_dest_mac_list[k], + eth_src_mac=s_eth_src_mac_list[k], + eth_type=s_eth_type_list[k], + eth_payload_tdata=s_eth_payload_axis_tdata_list[k], + eth_payload_tkeep=s_eth_payload_axis_tkeep_list[k], + eth_payload_tvalid=s_eth_payload_axis_tvalid_list[k], + eth_payload_tready=s_eth_payload_axis_tready_list[k], + eth_payload_tlast=s_eth_payload_axis_tlast_list[k], + eth_payload_tuser=s_eth_payload_axis_tuser_list[k], + pause=p, + name='source_%d' % k + )) sink = eth_ep.EthFrameSink() sink_logic = sink.create_logic( clk, rst, - eth_hdr_ready=output_eth_hdr_ready, - eth_hdr_valid=output_eth_hdr_valid, - eth_dest_mac=output_eth_dest_mac, - eth_src_mac=output_eth_src_mac, - eth_type=output_eth_type, - eth_payload_tdata=output_eth_payload_tdata, - eth_payload_tkeep=output_eth_payload_tkeep, - eth_payload_tvalid=output_eth_payload_tvalid, - eth_payload_tready=output_eth_payload_tready, - eth_payload_tlast=output_eth_payload_tlast, - eth_payload_tuser=output_eth_payload_tuser, + eth_hdr_ready=m_eth_hdr_ready, + eth_hdr_valid=m_eth_hdr_valid, + eth_dest_mac=m_eth_dest_mac, + eth_src_mac=m_eth_src_mac, + eth_type=m_eth_type, + eth_payload_tdata=m_eth_payload_axis_tdata, + eth_payload_tkeep=m_eth_payload_axis_tkeep, + eth_payload_tvalid=m_eth_payload_axis_tvalid, + eth_payload_tready=m_eth_payload_axis_tready, + eth_payload_tlast=m_eth_payload_axis_tlast, + eth_payload_tuser=m_eth_payload_axis_tuser, pause=sink_pause, name='sink' ) @@ -227,62 +170,33 @@ def bench(): rst=rst, current_test=current_test, - input_0_eth_hdr_valid=input_0_eth_hdr_valid, - input_0_eth_hdr_ready=input_0_eth_hdr_ready, - input_0_eth_dest_mac=input_0_eth_dest_mac, - input_0_eth_src_mac=input_0_eth_src_mac, - input_0_eth_type=input_0_eth_type, - input_0_eth_payload_tdata=input_0_eth_payload_tdata, - input_0_eth_payload_tkeep=input_0_eth_payload_tkeep, - input_0_eth_payload_tvalid=input_0_eth_payload_tvalid, - input_0_eth_payload_tready=input_0_eth_payload_tready, - input_0_eth_payload_tlast=input_0_eth_payload_tlast, - input_0_eth_payload_tuser=input_0_eth_payload_tuser, - input_1_eth_hdr_valid=input_1_eth_hdr_valid, - input_1_eth_hdr_ready=input_1_eth_hdr_ready, - input_1_eth_dest_mac=input_1_eth_dest_mac, - input_1_eth_src_mac=input_1_eth_src_mac, - input_1_eth_type=input_1_eth_type, - input_1_eth_payload_tdata=input_1_eth_payload_tdata, - input_1_eth_payload_tkeep=input_1_eth_payload_tkeep, - input_1_eth_payload_tvalid=input_1_eth_payload_tvalid, - input_1_eth_payload_tready=input_1_eth_payload_tready, - input_1_eth_payload_tlast=input_1_eth_payload_tlast, - input_1_eth_payload_tuser=input_1_eth_payload_tuser, - input_2_eth_hdr_valid=input_2_eth_hdr_valid, - input_2_eth_hdr_ready=input_2_eth_hdr_ready, - input_2_eth_dest_mac=input_2_eth_dest_mac, - input_2_eth_src_mac=input_2_eth_src_mac, - input_2_eth_type=input_2_eth_type, - input_2_eth_payload_tdata=input_2_eth_payload_tdata, - input_2_eth_payload_tkeep=input_2_eth_payload_tkeep, - input_2_eth_payload_tvalid=input_2_eth_payload_tvalid, - input_2_eth_payload_tready=input_2_eth_payload_tready, - input_2_eth_payload_tlast=input_2_eth_payload_tlast, - input_2_eth_payload_tuser=input_2_eth_payload_tuser, - input_3_eth_hdr_valid=input_3_eth_hdr_valid, - input_3_eth_hdr_ready=input_3_eth_hdr_ready, - input_3_eth_dest_mac=input_3_eth_dest_mac, - input_3_eth_src_mac=input_3_eth_src_mac, - input_3_eth_type=input_3_eth_type, - input_3_eth_payload_tdata=input_3_eth_payload_tdata, - input_3_eth_payload_tkeep=input_3_eth_payload_tkeep, - input_3_eth_payload_tvalid=input_3_eth_payload_tvalid, - input_3_eth_payload_tready=input_3_eth_payload_tready, - input_3_eth_payload_tlast=input_3_eth_payload_tlast, - input_3_eth_payload_tuser=input_3_eth_payload_tuser, + s_eth_hdr_valid=s_eth_hdr_valid, + s_eth_hdr_ready=s_eth_hdr_ready, + s_eth_dest_mac=s_eth_dest_mac, + s_eth_src_mac=s_eth_src_mac, + s_eth_type=s_eth_type, + s_eth_payload_axis_tdata=s_eth_payload_axis_tdata, + s_eth_payload_axis_tkeep=s_eth_payload_axis_tkeep, + s_eth_payload_axis_tvalid=s_eth_payload_axis_tvalid, + s_eth_payload_axis_tready=s_eth_payload_axis_tready, + s_eth_payload_axis_tlast=s_eth_payload_axis_tlast, + s_eth_payload_axis_tid=s_eth_payload_axis_tid, + s_eth_payload_axis_tdest=s_eth_payload_axis_tdest, + s_eth_payload_axis_tuser=s_eth_payload_axis_tuser, - output_eth_hdr_valid=output_eth_hdr_valid, - output_eth_hdr_ready=output_eth_hdr_ready, - output_eth_dest_mac=output_eth_dest_mac, - output_eth_src_mac=output_eth_src_mac, - output_eth_type=output_eth_type, - output_eth_payload_tdata=output_eth_payload_tdata, - output_eth_payload_tkeep=output_eth_payload_tkeep, - output_eth_payload_tvalid=output_eth_payload_tvalid, - output_eth_payload_tready=output_eth_payload_tready, - output_eth_payload_tlast=output_eth_payload_tlast, - output_eth_payload_tuser=output_eth_payload_tuser + m_eth_hdr_valid=m_eth_hdr_valid, + m_eth_hdr_ready=m_eth_hdr_ready, + m_eth_dest_mac=m_eth_dest_mac, + m_eth_src_mac=m_eth_src_mac, + m_eth_type=m_eth_type, + m_eth_payload_axis_tdata=m_eth_payload_axis_tdata, + m_eth_payload_axis_tkeep=m_eth_payload_axis_tkeep, + m_eth_payload_axis_tvalid=m_eth_payload_axis_tvalid, + m_eth_payload_axis_tready=m_eth_payload_axis_tready, + m_eth_payload_axis_tlast=m_eth_payload_axis_tlast, + m_eth_payload_axis_tid=m_eth_payload_axis_tid, + m_eth_payload_axis_tdest=m_eth_payload_axis_tdest, + m_eth_payload_axis_tuser=m_eth_payload_axis_tuser ) @always(delay(4)) @@ -312,7 +226,7 @@ def bench(): test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(32)) - source_0.send(test_frame) + source_list[0].send(test_frame) yield sink.wait() rx_frame = sink.recv() @@ -331,7 +245,7 @@ def bench(): test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(32)) - source_1.send(test_frame) + source_list[1].send(test_frame) yield sink.wait() rx_frame = sink.recv() @@ -355,8 +269,8 @@ def bench(): test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(32)) - source_0.send(test_frame1) - source_0.send(test_frame2) + source_list[0].send(test_frame1) + source_list[0].send(test_frame2) yield sink.wait() rx_frame = sink.recv() @@ -385,8 +299,8 @@ def bench(): test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(32)) - source_1.send(test_frame1) - source_2.send(test_frame2) + source_list[1].send(test_frame1) + source_list[2].send(test_frame2) yield sink.wait() rx_frame = sink.recv() @@ -415,23 +329,23 @@ def bench(): test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(32)) - source_1.send(test_frame1) - source_2.send(test_frame2) + source_list[1].send(test_frame1) + source_list[2].send(test_frame2) yield clk.posedge yield clk.posedge - while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: - source_0_pause.next = True - source_1_pause.next = True - source_2_pause.next = True - source_3_pause.next = True + while s_eth_payload_axis_tvalid: + source_pause_list[0].next = True + source_pause_list[1].next = True + source_pause_list[2].next = True + source_pause_list[3].next = True yield clk.posedge yield clk.posedge yield clk.posedge - source_0_pause.next = False - source_1_pause.next = False - source_2_pause.next = False - source_3_pause.next = False + source_pause_list[0].next = False + source_pause_list[1].next = False + source_pause_list[2].next = False + source_pause_list[3].next = False yield clk.posedge yield sink.wait() @@ -461,12 +375,12 @@ def bench(): test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(32)) - source_1.send(test_frame1) - source_2.send(test_frame2) + source_list[1].send(test_frame1) + source_list[2].send(test_frame2) yield clk.posedge yield clk.posedge - while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + while s_eth_payload_axis_tvalid: sink_pause.next = True yield clk.posedge yield clk.posedge @@ -501,17 +415,17 @@ def bench(): test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(32)) - source_1.send(test_frame1) - source_2.send(test_frame2) - source_2.send(test_frame2) - source_2.send(test_frame2) - source_2.send(test_frame2) - source_2.send(test_frame2) + source_list[1].send(test_frame1) + source_list[2].send(test_frame2) + source_list[2].send(test_frame2) + source_list[2].send(test_frame2) + source_list[2].send(test_frame2) + source_list[2].send(test_frame2) yield clk.posedge - yield delay(150) + yield delay(120) yield clk.posedge - source_1.send(test_frame1) + source_list[1].send(test_frame1) yield sink.wait() rx_frame = sink.recv() diff --git a/tb/test_eth_arb_mux_64_4.v b/tb/test_eth_arb_mux_64_4.v index 3a8c30d77..ed74367ab 100644 --- a/tb/test_eth_arb_mux_64_4.v +++ b/tb/test_eth_arb_mux_64_4.v @@ -27,74 +27,59 @@ THE SOFTWARE. `timescale 1ns / 1ps /* - * Testbench for eth_arb_mux_64_4 + * Testbench for eth_arb_mux */ module test_eth_arb_mux_64_4; +// Parameters +parameter S_COUNT = 4; +parameter DATA_WIDTH = 64; +parameter KEEP_ENABLE = (DATA_WIDTH>8); +parameter KEEP_WIDTH = (DATA_WIDTH/8); +parameter ID_ENABLE = 1; +parameter ID_WIDTH = 8; +parameter DEST_ENABLE = 1; +parameter DEST_WIDTH = 8; +parameter USER_ENABLE = 1; +parameter USER_WIDTH = 1; +parameter ARB_TYPE = "PRIORITY"; +parameter LSB_PRIORITY = "HIGH"; + // Inputs reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg input_0_eth_hdr_valid = 0; -reg [47:0] input_0_eth_dest_mac = 0; -reg [47:0] input_0_eth_src_mac = 0; -reg [15:0] input_0_eth_type = 0; -reg [63:0] input_0_eth_payload_tdata = 0; -reg [7:0] input_0_eth_payload_tkeep = 0; -reg input_0_eth_payload_tvalid = 0; -reg input_0_eth_payload_tlast = 0; -reg input_0_eth_payload_tuser = 0; -reg input_1_eth_hdr_valid = 0; -reg [47:0] input_1_eth_dest_mac = 0; -reg [47:0] input_1_eth_src_mac = 0; -reg [15:0] input_1_eth_type = 0; -reg [63:0] input_1_eth_payload_tdata = 0; -reg [7:0] input_1_eth_payload_tkeep = 0; -reg input_1_eth_payload_tvalid = 0; -reg input_1_eth_payload_tlast = 0; -reg input_1_eth_payload_tuser = 0; -reg input_2_eth_hdr_valid = 0; -reg [47:0] input_2_eth_dest_mac = 0; -reg [47:0] input_2_eth_src_mac = 0; -reg [15:0] input_2_eth_type = 0; -reg [63:0] input_2_eth_payload_tdata = 0; -reg [7:0] input_2_eth_payload_tkeep = 0; -reg input_2_eth_payload_tvalid = 0; -reg input_2_eth_payload_tlast = 0; -reg input_2_eth_payload_tuser = 0; -reg input_3_eth_hdr_valid = 0; -reg [47:0] input_3_eth_dest_mac = 0; -reg [47:0] input_3_eth_src_mac = 0; -reg [15:0] input_3_eth_type = 0; -reg [63:0] input_3_eth_payload_tdata = 0; -reg [7:0] input_3_eth_payload_tkeep = 0; -reg input_3_eth_payload_tvalid = 0; -reg input_3_eth_payload_tlast = 0; -reg input_3_eth_payload_tuser = 0; +reg [S_COUNT-1:0] s_eth_hdr_valid = 0; +reg [S_COUNT*48-1:0] s_eth_dest_mac = 0; +reg [S_COUNT*48-1:0] s_eth_src_mac = 0; +reg [S_COUNT*16-1:0] s_eth_type = 0; +reg [S_COUNT*DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0; +reg [S_COUNT*KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0; +reg [S_COUNT-1:0] s_eth_payload_axis_tvalid = 0; +reg [S_COUNT-1:0] s_eth_payload_axis_tlast = 0; +reg [S_COUNT*ID_WIDTH-1:0] s_eth_payload_axis_tid = 0; +reg [S_COUNT*DEST_WIDTH-1:0] s_eth_payload_axis_tdest = 0; +reg [S_COUNT*USER_WIDTH-1:0] s_eth_payload_axis_tuser = 0; -reg output_eth_hdr_ready = 0; -reg output_eth_payload_tready = 0; +reg m_eth_hdr_ready = 0; +reg m_eth_payload_axis_tready = 0; // Outputs -wire input_0_eth_payload_tready; -wire input_0_eth_hdr_ready; -wire input_1_eth_payload_tready; -wire input_1_eth_hdr_ready; -wire input_2_eth_payload_tready; -wire input_2_eth_hdr_ready; -wire input_3_eth_payload_tready; -wire input_3_eth_hdr_ready; +wire [S_COUNT-1:0] s_eth_hdr_ready; +wire [S_COUNT-1:0] s_eth_payload_axis_tready; -wire output_eth_hdr_valid; -wire [47:0] output_eth_dest_mac; -wire [47:0] output_eth_src_mac; -wire [15:0] output_eth_type; -wire [63:0] output_eth_payload_tdata; -wire [7:0] output_eth_payload_tkeep; -wire output_eth_payload_tvalid; -wire output_eth_payload_tlast; -wire output_eth_payload_tuser; +wire m_eth_hdr_valid; +wire [47:0] m_eth_dest_mac; +wire [47:0] m_eth_src_mac; +wire [15:0] m_eth_type; +wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata; +wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep; +wire m_eth_payload_axis_tvalid; +wire m_eth_payload_axis_tlast; +wire [ID_WIDTH-1:0] m_eth_payload_axis_tid; +wire [DEST_WIDTH-1:0] m_eth_payload_axis_tdest; +wire [USER_WIDTH-1:0] m_eth_payload_axis_tuser; initial begin // myhdl integration @@ -102,63 +87,34 @@ initial begin clk, rst, current_test, - input_0_eth_hdr_valid, - input_0_eth_dest_mac, - input_0_eth_src_mac, - input_0_eth_type, - input_0_eth_payload_tdata, - input_0_eth_payload_tkeep, - input_0_eth_payload_tvalid, - input_0_eth_payload_tlast, - input_0_eth_payload_tuser, - input_1_eth_hdr_valid, - input_1_eth_dest_mac, - input_1_eth_src_mac, - input_1_eth_type, - input_1_eth_payload_tdata, - input_1_eth_payload_tkeep, - input_1_eth_payload_tvalid, - input_1_eth_payload_tlast, - input_1_eth_payload_tuser, - input_2_eth_hdr_valid, - input_2_eth_dest_mac, - input_2_eth_src_mac, - input_2_eth_type, - input_2_eth_payload_tdata, - input_2_eth_payload_tkeep, - input_2_eth_payload_tvalid, - input_2_eth_payload_tlast, - input_2_eth_payload_tuser, - input_3_eth_hdr_valid, - input_3_eth_dest_mac, - input_3_eth_src_mac, - input_3_eth_type, - input_3_eth_payload_tdata, - input_3_eth_payload_tkeep, - input_3_eth_payload_tvalid, - input_3_eth_payload_tlast, - input_3_eth_payload_tuser, - output_eth_hdr_ready, - output_eth_payload_tready + s_eth_hdr_valid, + s_eth_dest_mac, + s_eth_src_mac, + s_eth_type, + s_eth_payload_axis_tdata, + s_eth_payload_axis_tkeep, + s_eth_payload_axis_tvalid, + s_eth_payload_axis_tlast, + s_eth_payload_axis_tid, + s_eth_payload_axis_tdest, + s_eth_payload_axis_tuser, + m_eth_hdr_ready, + m_eth_payload_axis_tready ); $to_myhdl( - input_0_eth_hdr_ready, - input_0_eth_payload_tready, - input_1_eth_hdr_ready, - input_1_eth_payload_tready, - input_2_eth_hdr_ready, - input_2_eth_payload_tready, - input_3_eth_hdr_ready, - input_3_eth_payload_tready, - output_eth_hdr_valid, - output_eth_dest_mac, - output_eth_src_mac, - output_eth_type, - output_eth_payload_tdata, - output_eth_payload_tkeep, - output_eth_payload_tvalid, - output_eth_payload_tlast, - output_eth_payload_tuser + s_eth_hdr_ready, + s_eth_payload_axis_tready, + m_eth_hdr_valid, + m_eth_dest_mac, + m_eth_src_mac, + m_eth_type, + m_eth_payload_axis_tdata, + m_eth_payload_axis_tkeep, + m_eth_payload_axis_tvalid, + m_eth_payload_axis_tlast, + m_eth_payload_axis_tid, + m_eth_payload_axis_tdest, + m_eth_payload_axis_tuser ); // dump file @@ -166,67 +122,51 @@ initial begin $dumpvars(0, test_eth_arb_mux_64_4); end -eth_arb_mux_64_4 +eth_arb_mux #( + .S_COUNT(S_COUNT), + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(KEEP_ENABLE), + .KEEP_WIDTH(KEEP_WIDTH), + .ID_ENABLE(ID_ENABLE), + .ID_WIDTH(ID_WIDTH), + .DEST_ENABLE(DEST_ENABLE), + .DEST_WIDTH(DEST_WIDTH), + .USER_ENABLE(USER_ENABLE), + .USER_WIDTH(USER_WIDTH), + .ARB_TYPE(ARB_TYPE), + .LSB_PRIORITY(LSB_PRIORITY) +) UUT ( .clk(clk), .rst(rst), // Ethernet frame inputs - .input_0_eth_hdr_valid(input_0_eth_hdr_valid), - .input_0_eth_hdr_ready(input_0_eth_hdr_ready), - .input_0_eth_dest_mac(input_0_eth_dest_mac), - .input_0_eth_src_mac(input_0_eth_src_mac), - .input_0_eth_type(input_0_eth_type), - .input_0_eth_payload_tdata(input_0_eth_payload_tdata), - .input_0_eth_payload_tkeep(input_0_eth_payload_tkeep), - .input_0_eth_payload_tvalid(input_0_eth_payload_tvalid), - .input_0_eth_payload_tready(input_0_eth_payload_tready), - .input_0_eth_payload_tlast(input_0_eth_payload_tlast), - .input_0_eth_payload_tuser(input_0_eth_payload_tuser), - .input_1_eth_hdr_valid(input_1_eth_hdr_valid), - .input_1_eth_hdr_ready(input_1_eth_hdr_ready), - .input_1_eth_dest_mac(input_1_eth_dest_mac), - .input_1_eth_src_mac(input_1_eth_src_mac), - .input_1_eth_type(input_1_eth_type), - .input_1_eth_payload_tdata(input_1_eth_payload_tdata), - .input_1_eth_payload_tkeep(input_1_eth_payload_tkeep), - .input_1_eth_payload_tvalid(input_1_eth_payload_tvalid), - .input_1_eth_payload_tready(input_1_eth_payload_tready), - .input_1_eth_payload_tlast(input_1_eth_payload_tlast), - .input_1_eth_payload_tuser(input_1_eth_payload_tuser), - .input_2_eth_hdr_valid(input_2_eth_hdr_valid), - .input_2_eth_hdr_ready(input_2_eth_hdr_ready), - .input_2_eth_dest_mac(input_2_eth_dest_mac), - .input_2_eth_src_mac(input_2_eth_src_mac), - .input_2_eth_type(input_2_eth_type), - .input_2_eth_payload_tdata(input_2_eth_payload_tdata), - .input_2_eth_payload_tkeep(input_2_eth_payload_tkeep), - .input_2_eth_payload_tvalid(input_2_eth_payload_tvalid), - .input_2_eth_payload_tready(input_2_eth_payload_tready), - .input_2_eth_payload_tlast(input_2_eth_payload_tlast), - .input_2_eth_payload_tuser(input_2_eth_payload_tuser), - .input_3_eth_hdr_valid(input_3_eth_hdr_valid), - .input_3_eth_hdr_ready(input_3_eth_hdr_ready), - .input_3_eth_dest_mac(input_3_eth_dest_mac), - .input_3_eth_src_mac(input_3_eth_src_mac), - .input_3_eth_type(input_3_eth_type), - .input_3_eth_payload_tdata(input_3_eth_payload_tdata), - .input_3_eth_payload_tkeep(input_3_eth_payload_tkeep), - .input_3_eth_payload_tvalid(input_3_eth_payload_tvalid), - .input_3_eth_payload_tready(input_3_eth_payload_tready), - .input_3_eth_payload_tlast(input_3_eth_payload_tlast), - .input_3_eth_payload_tuser(input_3_eth_payload_tuser), - // Eth frame output - .output_eth_hdr_valid(output_eth_hdr_valid), - .output_eth_hdr_ready(output_eth_hdr_ready), - .output_eth_dest_mac(output_eth_dest_mac), - .output_eth_src_mac(output_eth_src_mac), - .output_eth_type(output_eth_type), - .output_eth_payload_tdata(output_eth_payload_tdata), - .output_eth_payload_tkeep(output_eth_payload_tkeep), - .output_eth_payload_tvalid(output_eth_payload_tvalid), - .output_eth_payload_tready(output_eth_payload_tready), - .output_eth_payload_tlast(output_eth_payload_tlast), - .output_eth_payload_tuser(output_eth_payload_tuser) + .s_eth_hdr_valid(s_eth_hdr_valid), + .s_eth_hdr_ready(s_eth_hdr_ready), + .s_eth_dest_mac(s_eth_dest_mac), + .s_eth_src_mac(s_eth_src_mac), + .s_eth_type(s_eth_type), + .s_eth_payload_axis_tdata(s_eth_payload_axis_tdata), + .s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep), + .s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(s_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(s_eth_payload_axis_tlast), + .s_eth_payload_axis_tid(s_eth_payload_axis_tid), + .s_eth_payload_axis_tdest(s_eth_payload_axis_tdest), + .s_eth_payload_axis_tuser(s_eth_payload_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(m_eth_hdr_valid), + .m_eth_hdr_ready(m_eth_hdr_ready), + .m_eth_dest_mac(m_eth_dest_mac), + .m_eth_src_mac(m_eth_src_mac), + .m_eth_type(m_eth_type), + .m_eth_payload_axis_tdata(m_eth_payload_axis_tdata), + .m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep), + .m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(m_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(m_eth_payload_axis_tlast), + .m_eth_payload_axis_tid(m_eth_payload_axis_tid), + .m_eth_payload_axis_tdest(m_eth_payload_axis_tdest), + .m_eth_payload_axis_tuser(m_eth_payload_axis_tuser) ); endmodule