From 97e3daa36c251c71f52c4d63f12a9cea86aa88f6 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 8 Sep 2021 16:44:58 -0700 Subject: [PATCH] Extract information from design instead of env vars --- .../tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 10 ++++------ .../fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +--- .../fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py | 4 +--- .../fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +--- 4 files changed, 7 insertions(+), 15 deletions(-) diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 09b0cf748..2011d6b9a 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -67,8 +67,6 @@ class TB(object): def __init__(self, dut): self.dut = dut - self.BAR0_APERTURE = int(os.getenv("PARAM_AXIL_CTRL_ADDR_WIDTH")) - self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) @@ -267,7 +265,7 @@ class TB(object): self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5 - self.dev.functions[0].configure_bar(0, 2**self.BAR0_APERTURE, ext=True, prefetch=True) + self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) # Ethernet self.port_mac = [] @@ -275,15 +273,15 @@ class TB(object): clock_period = 3.102 speed = 10e9 - if int(os.getenv("PARAM_AXIS_ETH_SYNC_DATA_WIDTH")) == 64: + if len(dut.core_pcie_inst.core_inst.iface[0].port[0].rx_fifo_inst.m_axis_tdata) == 64: # 10G clock_period = 6.4 speed = 10e9 - elif int(os.getenv("PARAM_AXIS_ETH_SYNC_DATA_WIDTH")) == 128: + elif len(dut.core_pcie_inst.core_inst.iface[0].port[0].rx_fifo_inst.m_axis_tdata) == 128: # 25G clock_period = 2.56 speed = 25e9 - elif int(os.getenv("PARAM_AXIS_ETH_SYNC_DATA_WIDTH")) == 512: + elif len(dut.core_pcie_inst.core_inst.iface[0].port[0].rx_fifo_inst.m_axis_tdata) == 512: # 100G clock_period = 3.102 speed = 100e9 diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index 2da00682c..d85812bb1 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -66,8 +66,6 @@ class TB(object): def __init__(self, dut): self.dut = dut - self.BAR0_APERTURE = int(os.getenv("PARAM_AXIL_CTRL_ADDR_WIDTH")) - self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) @@ -266,7 +264,7 @@ class TB(object): self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5 - self.dev.functions[0].configure_bar(0, 2**self.BAR0_APERTURE, ext=True, prefetch=True) + self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) # Ethernet cocotb.fork(Clock(dut.qsfp_0_rx_clk, 3.102, units="ns").start()) diff --git a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py index 387b82f42..1a3974ca5 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -66,8 +66,6 @@ class TB(object): def __init__(self, dut): self.dut = dut - self.BAR0_APERTURE = int(os.getenv("PARAM_AXIL_CTRL_ADDR_WIDTH")) - self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) @@ -266,7 +264,7 @@ class TB(object): self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5 - self.dev.functions[0].configure_bar(0, 2**self.BAR0_APERTURE, ext=True, prefetch=True) + self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) # Ethernet cocotb.fork(Clock(dut.qsfp_0_rx_clk_0, 6.4, units="ns").start()) diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index e53d2ed40..40142e1cc 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -66,8 +66,6 @@ class TB(object): def __init__(self, dut): self.dut = dut - self.BAR0_APERTURE = int(os.getenv("PARAM_AXIL_CTRL_ADDR_WIDTH")) - self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) @@ -266,7 +264,7 @@ class TB(object): self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5 - self.dev.functions[0].configure_bar(0, 2**self.BAR0_APERTURE, ext=True, prefetch=True) + self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) # Ethernet cocotb.fork(Clock(dut.qsfp_0_rx_clk_0, 2.56, units="ns").start())