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Rework resource management in testbenches, driver, and utils

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-05-01 22:04:43 -07:00
parent 1c7ae0ee73
commit 9834f8365c
56 changed files with 496 additions and 260 deletions
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4
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -468,7 +468,7 @@ async def run_test_nic(dut):
tb.log.info("Enable queues")
for interface in tb.driver.interfaces:
await interface.sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(interface.txq_count):
for k in range(len(interface.txq)):
await interface.sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete
@ -661,7 +661,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(block.interface.txq_count):
for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else:

4
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -468,7 +468,7 @@ async def run_test_nic(dut):
tb.log.info("Enable queues")
for interface in tb.driver.interfaces:
await interface.sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(interface.txq_count):
for k in range(len(interface.txq)):
await interface.sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete
@ -661,7 +661,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(block.interface.txq_count):
for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else:

141
fpga/common/tb/mqnic.py
View File

@ -312,6 +312,23 @@ MQNIC_CPL_SIZE = 32
MQNIC_EVENT_SIZE = 32
class Resource:
def __init__(self, count, parent, stride):
self.count = count
self.parent = parent
self.stride = stride
self.windows = {}
def get_count(self):
return self.count
def get_window(self, index):
if index not in self.windows:
self.windows[index] = self.parent.create_window(index*self.stride, self.stride)
return self.windows[index]
class RegBlock(Window):
def __init__(self, parent, offset, size, base=0, **kwargs):
super().__init__(parent, offset, size, base, **kwargs)
@ -1176,21 +1193,11 @@ class Interface:
self.max_tx_mtu = 0
self.max_rx_mtu = 0
self.eq_offset = None
self.eq_count = None
self.eq_stride = None
self.txq_offset = None
self.txq_count = None
self.txq_stride = None
self.tx_cq_offset = None
self.tx_cq_count = None
self.tx_cq_stride = None
self.rxq_offset = None
self.rxq_count = None
self.rxq_stride = None
self.rx_cq_offset = None
self.rx_cq_count = None
self.rx_cq_stride = None
self.eq_res = None
self.txq_res = None
self.tx_cq_res = None
self.rxq_res = None
self.rx_cq_res = None
self.port_count = None
self.sched_block_count = None
@ -1237,63 +1244,73 @@ class Interface:
self.eq_rb = self.reg_blocks.find(MQNIC_RB_EQM_TYPE, MQNIC_RB_EQM_VER)
self.eq_offset = await self.eq_rb.read_dword(MQNIC_RB_EQM_REG_OFFSET)
self.eq_count = await self.eq_rb.read_dword(MQNIC_RB_EQM_REG_COUNT)
self.eq_stride = await self.eq_rb.read_dword(MQNIC_RB_EQM_REG_STRIDE)
offset = await self.eq_rb.read_dword(MQNIC_RB_EQM_REG_OFFSET)
count = await self.eq_rb.read_dword(MQNIC_RB_EQM_REG_COUNT)
stride = await self.eq_rb.read_dword(MQNIC_RB_EQM_REG_STRIDE)
self.log.info("EQ offset: 0x%08x", self.eq_offset)
self.log.info("EQ count: %d", self.eq_count)
self.log.info("EQ stride: 0x%08x", self.eq_stride)
self.log.info("EQ offset: 0x%08x", offset)
self.log.info("EQ count: %d", count)
self.log.info("EQ stride: 0x%08x", stride)
self.eq_count = min(self.eq_count, MQNIC_MAX_EQ)
count = min(count, MQNIC_MAX_EQ)
self.eq_res = Resource(count, self.hw_regs.create_window(offset), stride)
self.txq_rb = self.reg_blocks.find(MQNIC_RB_TX_QM_TYPE, MQNIC_RB_TX_QM_VER)
self.txq_offset = await self.txq_rb.read_dword(MQNIC_RB_TX_QM_REG_OFFSET)
self.txq_count = await self.txq_rb.read_dword(MQNIC_RB_TX_QM_REG_COUNT)
self.txq_stride = await self.txq_rb.read_dword(MQNIC_RB_TX_QM_REG_STRIDE)
offset = await self.txq_rb.read_dword(MQNIC_RB_TX_QM_REG_OFFSET)
count = await self.txq_rb.read_dword(MQNIC_RB_TX_QM_REG_COUNT)
stride = await self.txq_rb.read_dword(MQNIC_RB_TX_QM_REG_STRIDE)
self.log.info("TXQ offset: 0x%08x", self.txq_offset)
self.log.info("TXQ count: %d", self.txq_count)
self.log.info("TXQ stride: 0x%08x", self.txq_stride)
self.log.info("TXQ offset: 0x%08x", offset)
self.log.info("TXQ count: %d", count)
self.log.info("TXQ stride: 0x%08x", stride)
self.txq_count = min(self.txq_count, MQNIC_MAX_TXQ)
count = min(count, MQNIC_MAX_TXQ)
self.txq_res = Resource(count, self.hw_regs.create_window(offset), stride)
self.tx_cq_rb = self.reg_blocks.find(MQNIC_RB_TX_CQM_TYPE, MQNIC_RB_TX_CQM_VER)
self.tx_cq_offset = await self.tx_cq_rb.read_dword(MQNIC_RB_TX_CQM_REG_OFFSET)
self.tx_cq_count = await self.tx_cq_rb.read_dword(MQNIC_RB_TX_CQM_REG_COUNT)
self.tx_cq_stride = await self.tx_cq_rb.read_dword(MQNIC_RB_TX_CQM_REG_STRIDE)
offset = await self.tx_cq_rb.read_dword(MQNIC_RB_TX_CQM_REG_OFFSET)
count = await self.tx_cq_rb.read_dword(MQNIC_RB_TX_CQM_REG_COUNT)
stride = await self.tx_cq_rb.read_dword(MQNIC_RB_TX_CQM_REG_STRIDE)
self.log.info("TX CQ offset: 0x%08x", self.tx_cq_offset)
self.log.info("TX CQ count: %d", self.tx_cq_count)
self.log.info("TX CQ stride: 0x%08x", self.tx_cq_stride)
self.log.info("TX CQ offset: 0x%08x", offset)
self.log.info("TX CQ count: %d", count)
self.log.info("TX CQ stride: 0x%08x", stride)
self.tx_cq_count = min(self.tx_cq_count, MQNIC_MAX_TX_CQ)
count = min(count, MQNIC_MAX_TX_CQ)
self.tx_cq_res = Resource(count, self.hw_regs.create_window(offset), stride)
self.rxq_rb = self.reg_blocks.find(MQNIC_RB_RX_QM_TYPE, MQNIC_RB_RX_QM_VER)
self.rxq_offset = await self.rxq_rb.read_dword(MQNIC_RB_RX_QM_REG_OFFSET)
self.rxq_count = await self.rxq_rb.read_dword(MQNIC_RB_RX_QM_REG_COUNT)
self.rxq_stride = await self.rxq_rb.read_dword(MQNIC_RB_RX_QM_REG_STRIDE)
offset = await self.rxq_rb.read_dword(MQNIC_RB_RX_QM_REG_OFFSET)
count = await self.rxq_rb.read_dword(MQNIC_RB_RX_QM_REG_COUNT)
stride = await self.rxq_rb.read_dword(MQNIC_RB_RX_QM_REG_STRIDE)
self.log.info("RXQ offset: 0x%08x", self.rxq_offset)
self.log.info("RXQ count: %d", self.rxq_count)
self.log.info("RXQ stride: 0x%08x", self.rxq_stride)
self.log.info("RXQ offset: 0x%08x", offset)
self.log.info("RXQ count: %d", count)
self.log.info("RXQ stride: 0x%08x", stride)
self.rxq_count = min(self.rxq_count, MQNIC_MAX_RXQ)
count = min(count, MQNIC_MAX_RXQ)
self.rxq_res = Resource(count, self.hw_regs.create_window(offset), stride)
self.rx_cq_rb = self.reg_blocks.find(MQNIC_RB_RX_CQM_TYPE, MQNIC_RB_RX_CQM_VER)
self.rx_cq_offset = await self.rx_cq_rb.read_dword(MQNIC_RB_RX_CQM_REG_OFFSET)
self.rx_cq_count = await self.rx_cq_rb.read_dword(MQNIC_RB_RX_CQM_REG_COUNT)
self.rx_cq_stride = await self.rx_cq_rb.read_dword(MQNIC_RB_RX_CQM_REG_STRIDE)
offset = await self.rx_cq_rb.read_dword(MQNIC_RB_RX_CQM_REG_OFFSET)
count = await self.rx_cq_rb.read_dword(MQNIC_RB_RX_CQM_REG_COUNT)
stride = await self.rx_cq_rb.read_dword(MQNIC_RB_RX_CQM_REG_STRIDE)
self.log.info("RX CQ offset: 0x%08x", self.rx_cq_offset)
self.log.info("RX CQ count: %d", self.rx_cq_count)
self.log.info("RX CQ stride: 0x%08x", self.rx_cq_stride)
self.log.info("RX CQ offset: 0x%08x", offset)
self.log.info("RX CQ count: %d", count)
self.log.info("RX CQ stride: 0x%08x", stride)
self.rx_cq_count = min(self.rx_cq_count, MQNIC_MAX_RX_CQ)
count = min(count, MQNIC_MAX_RX_CQ)
self.rx_cq_res = Resource(count, self.hw_regs.create_window(offset), stride)
self.rx_queue_map_rb = self.reg_blocks.find(MQNIC_RB_RX_QUEUE_MAP_TYPE, MQNIC_RB_RX_QUEUE_MAP_VER)
@ -1318,28 +1335,28 @@ class Interface:
self.ports = []
self.sched_blocks = []
for k in range(self.eq_count):
eq = Eq(self, k, self.hw_regs.create_window(self.eq_offset + k*self.eq_stride, self.eq_stride))
for k in range(self.eq_res.get_count()):
eq = Eq(self, k, self.eq_res.get_window(k))
await eq.init()
self.eq.append(eq)
for k in range(self.txq_count):
txq = Txq(self, k, self.hw_regs.create_window(self.txq_offset + k*self.txq_stride, self.txq_stride))
for k in range(self.txq_res.get_count()):
txq = Txq(self, k, self.txq_res.get_window(k))
await txq.init()
self.txq.append(txq)
for k in range(self.tx_cq_count):
cq = Cq(self, k, self.hw_regs.create_window(self.tx_cq_offset + k*self.tx_cq_stride, self.tx_cq_stride))
for k in range(self.tx_cq_res.get_count()):
cq = Cq(self, k, self.tx_cq_res.get_window(k))
await cq.init()
self.tx_cq.append(cq)
for k in range(self.rxq_count):
rxq = Rxq(self, k, self.hw_regs.create_window(self.rxq_offset + k*self.rxq_stride, self.rxq_stride))
for k in range(self.rxq_res.get_count()):
rxq = Rxq(self, k, self.rxq_res.get_window(k))
await rxq.init()
self.rxq.append(rxq)
for k in range(self.rx_cq_count):
cq = Cq(self, k, self.hw_regs.create_window(self.rx_cq_offset + k*self.rx_cq_stride, self.rx_cq_stride))
for k in range(self.rx_cq_res.get_count()):
cq = Cq(self, k, self.rx_cq_res.get_window(k))
await cq.init()
self.rx_cq.append(cq)
@ -1371,7 +1388,7 @@ class Interface:
for rxq in self.rxq:
cq = self.rx_cq[rxq.index]
await cq.alloc(1024, MQNIC_CPL_SIZE)
await cq.activate(self.eq[cq.cqn % self.eq_count])
await cq.activate(self.eq[cq.cqn % len(self.eq)])
await cq.arm()
await rxq.alloc(1024, MQNIC_DESC_SIZE*4)
await rxq.activate(cq)
@ -1379,7 +1396,7 @@ class Interface:
for txq in self.txq:
cq = self.tx_cq[txq.index]
await cq.alloc(1024, MQNIC_CPL_SIZE)
await cq.activate(self.eq[cq.cqn % self.eq_count])
await cq.activate(self.eq[cq.cqn % len(self.eq)])
await cq.arm()
await txq.alloc(1024, MQNIC_DESC_SIZE*4)
await txq.activate(cq)

6
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -248,7 +248,7 @@ async def run_test_nic(dut):
tb.log.info("Enable queues")
for interface in tb.driver.interfaces:
await interface.sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(interface.txq_count):
for k in range(len(interface.txq)):
await interface.sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete
@ -383,7 +383,7 @@ async def run_test_nic(dut):
tb.loopback_enable = True
for k in range(len(pkts)):
await tb.driver.interfaces[0].start_xmit(pkts[k], k % tb.driver.interfaces[0].txq_count)
await tb.driver.interfaces[0].start_xmit(pkts[k], k % len(tb.driver.interfaces[0].txq))
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
@ -460,7 +460,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(block.interface.txq_count):
for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else:

6
fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py
View File

@ -446,7 +446,7 @@ async def run_test_nic(dut):
tb.log.info("Enable queues")
for interface in tb.driver.interfaces:
await interface.sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(interface.txq_count):
for k in range(len(interface.txq)):
await interface.sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete
@ -581,7 +581,7 @@ async def run_test_nic(dut):
tb.loopback_enable = True
for k in range(len(pkts)):
await tb.driver.interfaces[0].start_xmit(pkts[k], k % tb.driver.interfaces[0].txq_count)
await tb.driver.interfaces[0].start_xmit(pkts[k], k % len(tb.driver.interfaces[0].txq))
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
@ -658,7 +658,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(block.interface.txq_count):
for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else:

6
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -394,7 +394,7 @@ async def run_test_nic(dut):
tb.log.info("Enable queues")
for interface in tb.driver.interfaces:
await interface.sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(interface.txq_count):
for k in range(len(interface.txq)):
await interface.sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete
@ -529,7 +529,7 @@ async def run_test_nic(dut):
tb.loopback_enable = True
for k in range(len(pkts)):
await tb.driver.interfaces[0].start_xmit(pkts[k], k % tb.driver.interfaces[0].txq_count)
await tb.driver.interfaces[0].start_xmit(pkts[k], k % len(tb.driver.interfaces[0].txq))
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
@ -606,7 +606,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(block.interface.txq_count):
for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else:

6
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -468,7 +468,7 @@ async def run_test_nic(dut):
tb.log.info("Enable queues")
for interface in tb.driver.interfaces:
await interface.sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(interface.txq_count):
for k in range(len(interface.txq)):
await interface.sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete
@ -603,7 +603,7 @@ async def run_test_nic(dut):
tb.loopback_enable = True
for k in range(len(pkts)):
await tb.driver.interfaces[0].start_xmit(pkts[k], k % tb.driver.interfaces[0].txq_count)
await tb.driver.interfaces[0].start_xmit(pkts[k], k % len(tb.driver.interfaces[0].txq))
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
@ -680,7 +680,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(block.interface.txq_count):
for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else:

8
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -468,7 +468,7 @@ async def run_test_nic(dut):
tb.log.info("Enable queues")
for interface in tb.driver.interfaces:
await interface.sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(interface.txq_count):
for k in range(len(interface.txq)):
await interface.sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete
@ -603,7 +603,7 @@ async def run_test_nic(dut):
tb.loopback_enable = True
for k in range(len(pkts)):
await tb.driver.interfaces[0].start_xmit(pkts[k], k % tb.driver.interfaces[0].txq_count)
await tb.driver.interfaces[0].start_xmit(pkts[k], k % len(tb.driver.interfaces[0].txq))
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
@ -680,7 +680,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(block.interface.txq_count):
for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else:
@ -742,7 +742,7 @@ async def run_test_nic(dut):
# enable queues with global enable off
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000001)
# configure slots

2
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -431,7 +431,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -499,7 +499,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -431,7 +431,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -499,7 +499,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -431,7 +431,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -499,7 +499,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -431,7 +431,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -499,7 +499,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -420,7 +420,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -488,7 +488,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -386,7 +386,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -420,7 +420,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -437,7 +437,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -777,7 +777,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -381,7 +381,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -551,7 +551,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -409,7 +409,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -434,7 +434,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -774,7 +774,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -475,7 +475,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -386,7 +386,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -374,7 +374,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -503,7 +503,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -403,7 +403,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -407,7 +407,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -435,7 +435,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -503,7 +503,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -429,7 +429,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -497,7 +497,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -511,7 +511,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -647,7 +647,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -204,7 +204,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
View File

@ -397,7 +397,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py
View File

@ -174,7 +174,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -432,7 +432,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -501,7 +501,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -501,7 +501,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -640,7 +640,7 @@ async def run_test_nic(dut):
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].txq_count):
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete

2
lib/mqnic/Makefile
View File

@ -22,7 +22,7 @@ all: $(LIB)
%.o: %.c
$(CC) $(ALL_CFLAGS) -c -o $@ $<
libmqnic.a: mqnic.o mqnic_if.o mqnic_port.o mqnic_sched_block.o mqnic_scheduler.o mqnic_clk_info.o mqnic_stats.o reg_if.o reg_block.o fpga_id.o
libmqnic.a: mqnic.o mqnic_res.o mqnic_if.o mqnic_port.o mqnic_sched_block.o mqnic_scheduler.o mqnic_clk_info.o mqnic_stats.o reg_if.o reg_block.o fpga_id.o
ar rcs $@ $^
install:

33
lib/mqnic/mqnic.h
View File

@ -45,6 +45,12 @@ either expressed or implied, of The Regents of the University of California.
struct mqnic;
struct mqnic_res {
unsigned int count;
volatile uint8_t *base;
unsigned int stride;
};
struct mqnic_sched {
struct mqnic *mqnic;
struct mqnic_if *interface;
@ -113,22 +119,11 @@ struct mqnic_if {
uint32_t rx_queue_map_indir_table_size;
volatile uint8_t *rx_queue_map_indir_table[MQNIC_MAX_PORTS];
uint32_t eq_offset;
uint32_t eq_count;
uint32_t eq_stride;
uint32_t txq_offset;
uint32_t txq_count;
uint32_t txq_stride;
uint32_t tx_cq_offset;
uint32_t tx_cq_count;
uint32_t tx_cq_stride;
uint32_t rxq_offset;
uint32_t rxq_count;
uint32_t rxq_stride;
uint32_t rx_cq_offset;
uint32_t rx_cq_count;
uint32_t rx_cq_stride;
struct mqnic_res *eq_res;
struct mqnic_res *txq_res;
struct mqnic_res *tx_cq_res;
struct mqnic_res *rxq_res;
struct mqnic_res *rx_cq_res;
uint32_t port_count;
struct mqnic_port *ports[MQNIC_MAX_PORTS];
@ -201,6 +196,12 @@ struct mqnic *mqnic_open(const char *dev_name);
void mqnic_close(struct mqnic *dev);
void mqnic_print_fw_id(struct mqnic *dev);
// mqnic_res.c
struct mqnic_res *mqnic_res_open(unsigned int count, volatile uint8_t *base, unsigned int stride);
void mqnic_res_close(struct mqnic_res *res);
unsigned int mqnic_res_get_count(struct mqnic_res *res);
volatile uint8_t *mqnic_res_get_addr(struct mqnic_res *res, int index);
// mqnic_if.c
struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *regs);
void mqnic_if_close(struct mqnic_if *interface);

82
lib/mqnic/mqnic_if.c
View File

@ -39,6 +39,7 @@ either expressed or implied, of The Regents of the University of California.
struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *regs)
{
struct mqnic_if *interface = calloc(1, sizeof(struct mqnic_if));
uint32_t count, offset, stride;
uint32_t val;
if (!interface)
@ -89,12 +90,17 @@ struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *r
goto fail;
}
interface->eq_offset = mqnic_reg_read32(interface->eq_rb->regs, MQNIC_RB_EQM_REG_OFFSET);
interface->eq_count = mqnic_reg_read32(interface->eq_rb->regs, MQNIC_RB_EQM_REG_COUNT);
interface->eq_stride = mqnic_reg_read32(interface->eq_rb->regs, MQNIC_RB_EQM_REG_STRIDE);
offset = mqnic_reg_read32(interface->eq_rb->regs, MQNIC_RB_EQM_REG_OFFSET);
count = mqnic_reg_read32(interface->eq_rb->regs, MQNIC_RB_EQM_REG_COUNT);
stride = mqnic_reg_read32(interface->eq_rb->regs, MQNIC_RB_EQM_REG_STRIDE);
if (interface->eq_count > MQNIC_MAX_EQ)
interface->eq_count = MQNIC_MAX_EQ;
if (count > MQNIC_MAX_EQ)
count = MQNIC_MAX_EQ;
interface->eq_res = mqnic_res_open(count, interface->regs + offset, stride);
if (!interface->eq_res)
goto fail;
interface->txq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_TX_QM_TYPE, MQNIC_RB_TX_QM_VER, 0);
@ -104,12 +110,17 @@ struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *r
goto fail;
}
interface->txq_offset = mqnic_reg_read32(interface->txq_rb->regs, MQNIC_RB_TX_QM_REG_OFFSET);
interface->txq_count = mqnic_reg_read32(interface->txq_rb->regs, MQNIC_RB_TX_QM_REG_COUNT);
interface->txq_stride = mqnic_reg_read32(interface->txq_rb->regs, MQNIC_RB_TX_QM_REG_STRIDE);
offset = mqnic_reg_read32(interface->txq_rb->regs, MQNIC_RB_TX_QM_REG_OFFSET);
count = mqnic_reg_read32(interface->txq_rb->regs, MQNIC_RB_TX_QM_REG_COUNT);
stride = mqnic_reg_read32(interface->txq_rb->regs, MQNIC_RB_TX_QM_REG_STRIDE);
if (interface->txq_count > MQNIC_MAX_TXQ)
interface->txq_count = MQNIC_MAX_TXQ;
if (count > MQNIC_MAX_TXQ)
count = MQNIC_MAX_TXQ;
interface->txq_res = mqnic_res_open(count, interface->regs + offset, stride);
if (!interface->txq_res)
goto fail;
interface->tx_cq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_TX_CQM_TYPE, MQNIC_RB_TX_CQM_VER, 0);
@ -119,12 +130,17 @@ struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *r
goto fail;
}
interface->tx_cq_offset = mqnic_reg_read32(interface->tx_cq_rb->regs, MQNIC_RB_TX_CQM_REG_OFFSET);
interface->tx_cq_count = mqnic_reg_read32(interface->tx_cq_rb->regs, MQNIC_RB_TX_CQM_REG_COUNT);
interface->tx_cq_stride = mqnic_reg_read32(interface->tx_cq_rb->regs, MQNIC_RB_TX_CQM_REG_STRIDE);
offset = mqnic_reg_read32(interface->tx_cq_rb->regs, MQNIC_RB_TX_CQM_REG_OFFSET);
count = mqnic_reg_read32(interface->tx_cq_rb->regs, MQNIC_RB_TX_CQM_REG_COUNT);
stride = mqnic_reg_read32(interface->tx_cq_rb->regs, MQNIC_RB_TX_CQM_REG_STRIDE);
if (interface->tx_cq_count > MQNIC_MAX_TX_CQ)
interface->tx_cq_count = MQNIC_MAX_TX_CQ;
if (count > MQNIC_MAX_TX_CQ)
count = MQNIC_MAX_TX_CQ;
interface->tx_cq_res = mqnic_res_open(count, interface->regs + offset, stride);
if (!interface->tx_cq_res)
goto fail;
interface->rxq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_RX_QM_TYPE, MQNIC_RB_RX_QM_VER, 0);
@ -134,12 +150,17 @@ struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *r
goto fail;
}
interface->rxq_offset = mqnic_reg_read32(interface->rxq_rb->regs, MQNIC_RB_RX_QM_REG_OFFSET);
interface->rxq_count = mqnic_reg_read32(interface->rxq_rb->regs, MQNIC_RB_RX_QM_REG_COUNT);
interface->rxq_stride = mqnic_reg_read32(interface->rxq_rb->regs, MQNIC_RB_RX_QM_REG_STRIDE);
offset = mqnic_reg_read32(interface->rxq_rb->regs, MQNIC_RB_RX_QM_REG_OFFSET);
count = mqnic_reg_read32(interface->rxq_rb->regs, MQNIC_RB_RX_QM_REG_COUNT);
stride = mqnic_reg_read32(interface->rxq_rb->regs, MQNIC_RB_RX_QM_REG_STRIDE);
if (interface->rxq_count > MQNIC_MAX_RXQ)
interface->rxq_count = MQNIC_MAX_RXQ;
if (count > MQNIC_MAX_RXQ)
count = MQNIC_MAX_RXQ;
interface->rxq_res = mqnic_res_open(count, interface->regs + offset, stride);
if (!interface->rxq_res)
goto fail;
interface->rx_cq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_RX_CQM_TYPE, MQNIC_RB_RX_CQM_VER, 0);
@ -149,12 +170,17 @@ struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *r
goto fail;
}
interface->rx_cq_offset = mqnic_reg_read32(interface->rx_cq_rb->regs, MQNIC_RB_RX_CQM_REG_OFFSET);
interface->rx_cq_count = mqnic_reg_read32(interface->rx_cq_rb->regs, MQNIC_RB_RX_CQM_REG_COUNT);
interface->rx_cq_stride = mqnic_reg_read32(interface->rx_cq_rb->regs, MQNIC_RB_RX_CQM_REG_STRIDE);
offset = mqnic_reg_read32(interface->rx_cq_rb->regs, MQNIC_RB_RX_CQM_REG_OFFSET);
count = mqnic_reg_read32(interface->rx_cq_rb->regs, MQNIC_RB_RX_CQM_REG_COUNT);
stride = mqnic_reg_read32(interface->rx_cq_rb->regs, MQNIC_RB_RX_CQM_REG_STRIDE);
if (interface->rx_cq_count > MQNIC_MAX_RX_CQ)
interface->rx_cq_count = MQNIC_MAX_RX_CQ;
if (count > MQNIC_MAX_RX_CQ)
count = MQNIC_MAX_RX_CQ;
interface->rx_cq_res = mqnic_res_open(count, interface->regs + offset, stride);
if (!interface->rx_cq_res)
goto fail;
interface->rx_queue_map_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_RX_QUEUE_MAP_TYPE, MQNIC_RB_RX_QUEUE_MAP_VER, 0);
@ -235,6 +261,12 @@ void mqnic_if_close(struct mqnic_if *interface)
interface->ports[k] = NULL;
}
mqnic_res_close(interface->eq_res);
mqnic_res_close(interface->txq_res);
mqnic_res_close(interface->tx_cq_res);
mqnic_res_close(interface->rxq_res);
mqnic_res_close(interface->rx_cq_res);
if (interface->rb_list)
mqnic_free_reg_block_list(interface->rb_list);

72
lib/mqnic/mqnic_res.c Normal file
View File

@ -0,0 +1,72 @@
/*
Copyright 2023, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
#include "mqnic.h"
#include <stdio.h>
#include <stdlib.h>
struct mqnic_res *mqnic_res_open(unsigned int count, volatile uint8_t *base, unsigned int stride)
{
struct mqnic_res *res = calloc(1, sizeof(struct mqnic_res));
if (!res)
return NULL;
res->count = count;
res->base = base;
res->stride = stride;
return res;
}
void mqnic_res_close(struct mqnic_res *res)
{
if (!res)
return;
free(res);
}
unsigned int mqnic_res_get_count(struct mqnic_res *res)
{
return res->count;
}
volatile uint8_t *mqnic_res_get_addr(struct mqnic_res *res, int index)
{
if (index < 0 || index >= res->count)
return NULL;
return res->base + index * res->stride;
}

1
modules/mqnic/Makefile
View File

@ -3,6 +3,7 @@ ifneq ($(KERNELRELEASE),)
# object files to build
obj-m += mqnic.o
mqnic-y += mqnic_main.o
mqnic-y += mqnic_res.o
mqnic-y += mqnic_reg_block.o
mqnic-y += mqnic_irq.o
mqnic-y += mqnic_dev.o

28
modules/mqnic/mqnic.h
View File

@ -79,6 +79,12 @@ extern unsigned int mqnic_link_status_poll;
struct mqnic_dev;
struct mqnic_if;
struct mqnic_res {
unsigned int count;
u8 __iomem *base;
unsigned int stride;
};
struct mqnic_reg_block {
u32 type;
u32 version;
@ -417,29 +423,25 @@ struct mqnic_if {
u32 max_tx_mtu;
u32 max_rx_mtu;
u32 eq_offset;
struct mqnic_res *eq_res;
struct mqnic_res *txq_res;
struct mqnic_res *tx_cq_res;
struct mqnic_res *rxq_res;
struct mqnic_res *rx_cq_res;
u32 eq_count;
u32 eq_stride;
struct mqnic_eq *eq[MQNIC_MAX_EQ];
u32 txq_offset;
u32 txq_count;
u32 txq_stride;
struct mqnic_ring *txq[MQNIC_MAX_TXQ];
u32 tx_cq_offset;
u32 tx_cq_count;
u32 tx_cq_stride;
struct mqnic_cq *tx_cq[MQNIC_MAX_TX_CQ];
u32 rxq_offset;
u32 rxq_count;
u32 rxq_stride;
struct mqnic_ring *rxq[MQNIC_MAX_RXQ];
u32 rx_cq_offset;
u32 rx_cq_count;
u32 rx_cq_stride;
struct mqnic_cq *rx_cq[MQNIC_MAX_RX_CQ];
u32 port_count;
@ -507,6 +509,12 @@ struct mqnic_priv {
// mqnic_main.c
// mqnic_res.c
struct mqnic_res *mqnic_create_res(unsigned int count, u8 __iomem *base, unsigned int stride);
void mqnic_destroy_res(struct mqnic_res *res);
unsigned int mqnic_res_get_count(struct mqnic_res *res);
u8 __iomem *mqnic_res_get_addr(struct mqnic_res *res, int index);
// mqnic_reg_block.c
struct mqnic_reg_block *mqnic_enumerate_reg_block_list(u8 __iomem *base, size_t offset, size_t size);
struct mqnic_reg_block *mqnic_find_reg_block(struct mqnic_reg_block *list, u32 type, u32 version, int index);

133
modules/mqnic/mqnic_if.c
View File

@ -42,6 +42,7 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __
struct mqnic_reg_block *rb;
int ret = 0;
int k;
u32 count, offset, stride;
u32 desc_block_size;
u32 val;
@ -99,15 +100,22 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __
goto fail;
}
interface->eq_offset = ioread32(interface->eq_rb->regs + MQNIC_RB_EQM_REG_OFFSET);
interface->eq_count = ioread32(interface->eq_rb->regs + MQNIC_RB_EQM_REG_COUNT);
interface->eq_stride = ioread32(interface->eq_rb->regs + MQNIC_RB_EQM_REG_STRIDE);
offset = ioread32(interface->eq_rb->regs + MQNIC_RB_EQM_REG_OFFSET);
count = ioread32(interface->eq_rb->regs + MQNIC_RB_EQM_REG_COUNT);
stride = ioread32(interface->eq_rb->regs + MQNIC_RB_EQM_REG_STRIDE);
dev_info(dev, "EQ offset: 0x%08x", interface->eq_offset);
dev_info(dev, "EQ count: %d", interface->eq_count);
dev_info(dev, "EQ stride: 0x%08x", interface->eq_stride);
dev_info(dev, "EQ offset: 0x%08x", offset);
dev_info(dev, "EQ count: %d", count);
dev_info(dev, "EQ stride: 0x%08x", stride);
interface->eq_count = min_t(u32, interface->eq_count, MQNIC_MAX_EQ);
count = min_t(u32, count, MQNIC_MAX_EQ);
interface->eq_res = mqnic_create_res(count, hw_addr + offset, stride);
if (IS_ERR_OR_NULL(interface->eq_res)) {
ret = PTR_ERR(interface->eq_res);
goto fail;
}
interface->txq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_TX_QM_TYPE, MQNIC_RB_TX_QM_VER, 0);
@ -117,15 +125,22 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __
goto fail;
}
interface->txq_offset = ioread32(interface->txq_rb->regs + MQNIC_RB_TX_QM_REG_OFFSET);
interface->txq_count = ioread32(interface->txq_rb->regs + MQNIC_RB_TX_QM_REG_COUNT);
interface->txq_stride = ioread32(interface->txq_rb->regs + MQNIC_RB_TX_QM_REG_STRIDE);
offset = ioread32(interface->txq_rb->regs + MQNIC_RB_TX_QM_REG_OFFSET);
count = ioread32(interface->txq_rb->regs + MQNIC_RB_TX_QM_REG_COUNT);
stride = ioread32(interface->txq_rb->regs + MQNIC_RB_TX_QM_REG_STRIDE);
dev_info(dev, "TXQ offset: 0x%08x", interface->txq_offset);
dev_info(dev, "TXQ count: %d", interface->txq_count);
dev_info(dev, "TXQ stride: 0x%08x", interface->txq_stride);
dev_info(dev, "TXQ offset: 0x%08x", offset);
dev_info(dev, "TXQ count: %d", count);
dev_info(dev, "TXQ stride: 0x%08x", stride);
interface->txq_count = min_t(u32, interface->txq_count, MQNIC_MAX_TXQ);
count = min_t(u32, count, MQNIC_MAX_TXQ);
interface->txq_res = mqnic_create_res(count, hw_addr + offset, stride);
if (IS_ERR_OR_NULL(interface->txq_res)) {
ret = PTR_ERR(interface->txq_res);
goto fail;
}
interface->tx_cq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_TX_CQM_TYPE, MQNIC_RB_TX_CQM_VER, 0);
@ -135,15 +150,22 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __
goto fail;
}
interface->tx_cq_offset = ioread32(interface->tx_cq_rb->regs + MQNIC_RB_TX_CQM_REG_OFFSET);
interface->tx_cq_count = ioread32(interface->tx_cq_rb->regs + MQNIC_RB_TX_CQM_REG_COUNT);
interface->tx_cq_stride = ioread32(interface->tx_cq_rb->regs + MQNIC_RB_TX_CQM_REG_STRIDE);
offset = ioread32(interface->tx_cq_rb->regs + MQNIC_RB_TX_CQM_REG_OFFSET);
count = ioread32(interface->tx_cq_rb->regs + MQNIC_RB_TX_CQM_REG_COUNT);
stride = ioread32(interface->tx_cq_rb->regs + MQNIC_RB_TX_CQM_REG_STRIDE);
dev_info(dev, "TX CQ offset: 0x%08x", interface->tx_cq_offset);
dev_info(dev, "TX CQ count: %d", interface->tx_cq_count);
dev_info(dev, "TX CQ stride: 0x%08x", interface->tx_cq_stride);
dev_info(dev, "TX CQ offset: 0x%08x", offset);
dev_info(dev, "TX CQ count: %d", count);
dev_info(dev, "TX CQ stride: 0x%08x", stride);
interface->tx_cq_count = min_t(u32, interface->tx_cq_count, MQNIC_MAX_TX_CQ);
count = min_t(u32, count, MQNIC_MAX_TX_CQ);
interface->tx_cq_res = mqnic_create_res(count, hw_addr + offset, stride);
if (IS_ERR_OR_NULL(interface->tx_cq_res)) {
ret = PTR_ERR(interface->tx_cq_res);
goto fail;
}
interface->rxq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_RX_QM_TYPE, MQNIC_RB_RX_QM_VER, 0);
@ -153,15 +175,22 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __
goto fail;
}
interface->rxq_offset = ioread32(interface->rxq_rb->regs + MQNIC_RB_RX_QM_REG_OFFSET);
interface->rxq_count = ioread32(interface->rxq_rb->regs + MQNIC_RB_RX_QM_REG_COUNT);
interface->rxq_stride = ioread32(interface->rxq_rb->regs + MQNIC_RB_RX_QM_REG_STRIDE);
offset = ioread32(interface->rxq_rb->regs + MQNIC_RB_RX_QM_REG_OFFSET);
count = ioread32(interface->rxq_rb->regs + MQNIC_RB_RX_QM_REG_COUNT);
stride = ioread32(interface->rxq_rb->regs + MQNIC_RB_RX_QM_REG_STRIDE);
dev_info(dev, "RXQ offset: 0x%08x", interface->rxq_offset);
dev_info(dev, "RXQ count: %d", interface->rxq_count);
dev_info(dev, "RXQ stride: 0x%08x", interface->rxq_stride);
dev_info(dev, "RXQ offset: 0x%08x", offset);
dev_info(dev, "RXQ count: %d", count);
dev_info(dev, "RXQ stride: 0x%08x", stride);
interface->rxq_count = min_t(u32, interface->rxq_count, MQNIC_MAX_RXQ);
count = min_t(u32, count, MQNIC_MAX_RXQ);
interface->rxq_res = mqnic_create_res(count, hw_addr + offset, stride);
if (IS_ERR_OR_NULL(interface->rxq_res)) {
ret = PTR_ERR(interface->rxq_res);
goto fail;
}
interface->rx_cq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_RX_CQM_TYPE, MQNIC_RB_RX_CQM_VER, 0);
@ -171,15 +200,22 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __
goto fail;
}
interface->rx_cq_offset = ioread32(interface->rx_cq_rb->regs + MQNIC_RB_RX_CQM_REG_OFFSET);
interface->rx_cq_count = ioread32(interface->rx_cq_rb->regs + MQNIC_RB_RX_CQM_REG_COUNT);
interface->rx_cq_stride = ioread32(interface->rx_cq_rb->regs + MQNIC_RB_RX_CQM_REG_STRIDE);
offset = ioread32(interface->rx_cq_rb->regs + MQNIC_RB_RX_CQM_REG_OFFSET);
count = ioread32(interface->rx_cq_rb->regs + MQNIC_RB_RX_CQM_REG_COUNT);
stride = ioread32(interface->rx_cq_rb->regs + MQNIC_RB_RX_CQM_REG_STRIDE);
dev_info(dev, "RX CQ offset: 0x%08x", interface->rx_cq_offset);
dev_info(dev, "RX CQ count: %d", interface->rx_cq_count);
dev_info(dev, "RX CQ stride: 0x%08x", interface->rx_cq_stride);
dev_info(dev, "RX CQ offset: 0x%08x", offset);
dev_info(dev, "RX CQ count: %d", count);
dev_info(dev, "RX CQ stride: 0x%08x", stride);
interface->rx_cq_count = min_t(u32, interface->rx_cq_count, MQNIC_MAX_RX_CQ);
count = min_t(u32, count, MQNIC_MAX_RX_CQ);
interface->rx_cq_res = mqnic_create_res(count, hw_addr + offset, stride);
if (IS_ERR_OR_NULL(interface->rx_cq_res)) {
ret = PTR_ERR(interface->rx_cq_res);
goto fail;
}
interface->rx_queue_map_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_RX_QUEUE_MAP_TYPE, MQNIC_RB_RX_QUEUE_MAP_VER, 0);
@ -204,9 +240,9 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __
}
// determine desc block size
iowrite32(0xf << 8, hw_addr + interface->txq_offset + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
interface->max_desc_block_size = 1 << ((ioread32(hw_addr + interface->txq_offset + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) >> 8) & 0xf);
iowrite32(0, hw_addr + interface->txq_offset + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
iowrite32(0xf << 8, mqnic_res_get_addr(interface->txq_res, 0) + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
interface->max_desc_block_size = 1 << ((ioread32(mqnic_res_get_addr(interface->txq_res, 0) + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) >> 8) & 0xf);
iowrite32(0, mqnic_res_get_addr(interface->txq_res, 0) + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
dev_info(dev, "Max desc block size: %d", interface->max_desc_block_size);
@ -215,9 +251,10 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __
desc_block_size = min_t(u32, interface->max_desc_block_size, 4);
// create rings
interface->eq_count = mqnic_res_get_count(interface->eq_res);
for (k = 0; k < interface->eq_count; k++) {
struct mqnic_eq *eq = mqnic_create_eq(interface, k,
hw_addr + interface->eq_offset + k * interface->eq_stride);
mqnic_res_get_addr(interface->eq_res, k));
if (IS_ERR_OR_NULL(eq)) {
ret = PTR_ERR(eq);
goto fail;
@ -234,9 +271,10 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __
mqnic_arm_eq(eq);
}
interface->txq_count = mqnic_res_get_count(interface->txq_res);
for (k = 0; k < interface->txq_count; k++) {
struct mqnic_ring *txq = mqnic_create_tx_ring(interface, k,
hw_addr + interface->txq_offset + k * interface->txq_stride);
mqnic_res_get_addr(interface->txq_res, k));
if (IS_ERR_OR_NULL(txq)) {
ret = PTR_ERR(txq);
goto fail;
@ -244,9 +282,10 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __
interface->txq[k] = txq;
}
interface->tx_cq_count = mqnic_res_get_count(interface->tx_cq_res);
for (k = 0; k < interface->tx_cq_count; k++) {
struct mqnic_cq *cq = mqnic_create_cq(interface, k,
hw_addr + interface->tx_cq_offset + k * interface->tx_cq_stride);
mqnic_res_get_addr(interface->tx_cq_res, k));
if (IS_ERR_OR_NULL(cq)) {
ret = PTR_ERR(cq);
goto fail;
@ -254,9 +293,10 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __
interface->tx_cq[k] = cq;
}
interface->rxq_count = mqnic_res_get_count(interface->rxq_res);
for (k = 0; k < interface->rxq_count; k++) {
struct mqnic_ring *rxq = mqnic_create_rx_ring(interface, k,
hw_addr + interface->rxq_offset + k * interface->rxq_stride);
mqnic_res_get_addr(interface->rxq_res, k));
if (IS_ERR_OR_NULL(rxq)) {
ret = PTR_ERR(rxq);
goto fail;
@ -264,9 +304,10 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __
interface->rxq[k] = rxq;
}
interface->rx_cq_count = mqnic_res_get_count(interface->rx_cq_res);
for (k = 0; k < interface->rx_cq_count; k++) {
struct mqnic_cq *cq = mqnic_create_cq(interface, k,
hw_addr + interface->rx_cq_offset + k * interface->rx_cq_stride);
mqnic_res_get_addr(interface->rx_cq_res, k));
if (IS_ERR_OR_NULL(cq)) {
ret = PTR_ERR(cq);
goto fail;
@ -397,6 +438,12 @@ void mqnic_destroy_interface(struct mqnic_if *interface)
}
}
mqnic_destroy_res(interface->eq_res);
mqnic_destroy_res(interface->txq_res);
mqnic_destroy_res(interface->tx_cq_res);
mqnic_destroy_res(interface->rxq_res);
mqnic_destroy_res(interface->rx_cq_res);
if (interface->rb_list)
mqnic_free_reg_block_list(interface->rb_list);

72
modules/mqnic/mqnic_res.c Normal file
View File

@ -0,0 +1,72 @@
// SPDX-License-Identifier: BSD-2-Clause-Views
/*
* Copyright 2023, The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of The Regents of the
* University of California.
*/
#include "mqnic.h"
struct mqnic_res *mqnic_create_res(unsigned int count, u8 __iomem *base, unsigned int stride)
{
struct mqnic_res *res;
res = kzalloc(sizeof(*res), GFP_KERNEL);
if (!res)
return ERR_PTR(-ENOMEM);
res->count = count;
res->base = base;
res->stride = stride;
return res;
}
void mqnic_destroy_res(struct mqnic_res *res)
{
if (!res)
return;
kfree(res);
}
unsigned int mqnic_res_get_count(struct mqnic_res *res)
{
return res->count;
}
u8 __iomem *mqnic_res_get_addr(struct mqnic_res *res, int index)
{
if (index < 0 || index >= res->count)
return NULL;
return res->base + index * res->stride;
}

24
utils/mqnic-config.c
View File

@ -182,25 +182,11 @@ int main(int argc, char *argv[])
printf("TX MTU: %d\n", mqnic_reg_read32(dev_interface->if_ctrl_rb->regs, MQNIC_RB_IF_CTRL_REG_TX_MTU));
printf("RX MTU: %d\n", mqnic_reg_read32(dev_interface->if_ctrl_rb->regs, MQNIC_RB_IF_CTRL_REG_RX_MTU));
printf("EQ offset: 0x%08x\n", dev_interface->eq_offset);
printf("EQ count: %d\n", dev_interface->eq_count);
printf("EQ stride: 0x%08x\n", dev_interface->eq_stride);
printf("TXQ offset: 0x%08x\n", dev_interface->txq_offset);
printf("TXQ count: %d\n", dev_interface->txq_count);
printf("TXQ stride: 0x%08x\n", dev_interface->txq_stride);
printf("TX CQ offset: 0x%08x\n", dev_interface->tx_cq_offset);
printf("TX CQ count: %d\n", dev_interface->tx_cq_count);
printf("TX CQ stride: 0x%08x\n", dev_interface->tx_cq_stride);
printf("RXQ offset: 0x%08x\n", dev_interface->rxq_offset);
printf("RXQ count: %d\n", dev_interface->rxq_count);
printf("RXQ stride: 0x%08x\n", dev_interface->rxq_stride);
printf("RX CQ offset: 0x%08x\n", dev_interface->rx_cq_offset);
printf("RX CQ count: %d\n", dev_interface->rx_cq_count);
printf("RX CQ stride: 0x%08x\n", dev_interface->rx_cq_stride);
printf("EQ count: %d\n", mqnic_res_get_count(dev_interface->eq_res));
printf("TXQ count: %d\n", mqnic_res_get_count(dev_interface->txq_res));
printf("TX CQ count: %d\n", mqnic_res_get_count(dev_interface->tx_cq_res));
printf("RXQ count: %d\n", mqnic_res_get_count(dev_interface->rxq_res));
printf("RX CQ count: %d\n", mqnic_res_get_count(dev_interface->rx_cq_res));
if (port < 0 || port >= dev_interface->port_count)
{

52
utils/mqnic-dump.c
View File

@ -249,25 +249,25 @@ int main(int argc, char *argv[])
printf("TX MTU: %d\n", mqnic_interface_get_tx_mtu(dev_interface));
printf("RX MTU: %d\n", mqnic_interface_get_rx_mtu(dev_interface));
printf("EQ offset: 0x%08x\n", dev_interface->eq_offset);
printf("EQ count: %d\n", dev_interface->eq_count);
printf("EQ stride: 0x%08x\n", dev_interface->eq_stride);
printf("EQ offset: 0x%08lx\n", dev_interface->eq_res->base - dev_interface->regs);
printf("EQ count: %d\n", mqnic_res_get_count(dev_interface->eq_res));
printf("EQ stride: 0x%08x\n", dev_interface->eq_res->stride);
printf("TXQ offset: 0x%08x\n", dev_interface->txq_offset);
printf("TXQ count: %d\n", dev_interface->txq_count);
printf("TXQ stride: 0x%08x\n", dev_interface->txq_stride);
printf("TXQ offset: 0x%08lx\n", dev_interface->txq_res->base - dev_interface->regs);
printf("TXQ count: %d\n", mqnic_res_get_count(dev_interface->txq_res));
printf("TXQ stride: 0x%08x\n", dev_interface->txq_res->stride);
printf("TX CQ offset: 0x%08x\n", dev_interface->tx_cq_offset);
printf("TX CQ count: %d\n", dev_interface->tx_cq_count);
printf("TX CQ stride: 0x%08x\n", dev_interface->tx_cq_stride);
printf("TX CQ offset: 0x%08lx\n", dev_interface->tx_cq_res->base - dev_interface->regs);
printf("TX CQ count: %d\n", mqnic_res_get_count(dev_interface->tx_cq_res));
printf("TX CQ stride: 0x%08x\n", dev_interface->tx_cq_res->stride);
printf("RXQ offset: 0x%08x\n", dev_interface->rxq_offset);
printf("RXQ count: %d\n", dev_interface->rxq_count);
printf("RXQ stride: 0x%08x\n", dev_interface->rxq_stride);
printf("RXQ offset: 0x%08lx\n", dev_interface->rxq_res->base - dev_interface->regs);
printf("RXQ count: %d\n", mqnic_res_get_count(dev_interface->rxq_res));
printf("RXQ stride: 0x%08x\n", dev_interface->rxq_res->stride);
printf("RX CQ offset: 0x%08x\n", dev_interface->rx_cq_offset);
printf("RX CQ count: %d\n", dev_interface->rx_cq_count);
printf("RX CQ stride: 0x%08x\n", dev_interface->rx_cq_stride);
printf("RX CQ offset: 0x%08lx\n", dev_interface->rx_cq_res->base - dev_interface->regs);
printf("RX CQ count: %d\n", mqnic_res_get_count(dev_interface->rx_cq_res));
printf("RX CQ stride: 0x%08x\n", dev_interface->rx_cq_res->stride);
for (int p = 0; p < dev_interface->port_count; p++)
{
@ -381,9 +381,9 @@ int main(int argc, char *argv[])
printf("TXQ info\n");
printf(" Queue Base Address E B LS CPL Head Tail Len\n");
for (int k = 0; k < dev_interface->txq_count; k++)
for (int k = 0; k < mqnic_res_get_count(dev_interface->txq_res); k++)
{
volatile uint8_t *base = dev_interface->regs+dev_interface->txq_offset+k*dev_interface->txq_stride;
volatile uint8_t *base = mqnic_res_get_addr(dev_interface->txq_res, k);
uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_QUEUE_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_QUEUE_BASE_ADDR_REG+4) << 32);
uint8_t active = (mqnic_reg_read32(base, MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) & MQNIC_QUEUE_ACTIVE_MASK) != 0;
@ -399,9 +399,9 @@ int main(int argc, char *argv[])
printf("TX CQ info\n");
printf(" Queue Base Address E LS A C Int Head Tail Len\n");
for (int k = 0; k < dev_interface->tx_cq_count; k++)
for (int k = 0; k < mqnic_res_get_count(dev_interface->tx_cq_res); k++)
{
volatile uint8_t *base = dev_interface->regs+dev_interface->tx_cq_offset+k*dev_interface->tx_cq_stride;
volatile uint8_t *base = mqnic_res_get_addr(dev_interface->tx_cq_res, k);
uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_CQ_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_CQ_BASE_ADDR_REG+4) << 32);
uint8_t active = (mqnic_reg_read32(base, MQNIC_CQ_ACTIVE_LOG_SIZE_REG) & MQNIC_CQ_ACTIVE_MASK) != 0;
@ -418,9 +418,9 @@ int main(int argc, char *argv[])
printf("RXQ info\n");
printf(" Queue Base Address E B LS CPL Head Tail Len\n");
for (int k = 0; k < dev_interface->rxq_count; k++)
for (int k = 0; k < mqnic_res_get_count(dev_interface->rxq_res); k++)
{
volatile uint8_t *base = dev_interface->regs+dev_interface->rxq_offset+k*dev_interface->rxq_stride;
volatile uint8_t *base = mqnic_res_get_addr(dev_interface->rxq_res, k);
uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_QUEUE_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_QUEUE_BASE_ADDR_REG+4) << 32);
uint8_t active = (mqnic_reg_read32(base, MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) & MQNIC_QUEUE_ACTIVE_MASK) != 0;
@ -436,9 +436,9 @@ int main(int argc, char *argv[])
printf("RX CQ info\n");
printf(" Queue Base Address E LS A C Int Head Tail Len\n");
for (int k = 0; k < dev_interface->rx_cq_count; k++)
for (int k = 0; k < mqnic_res_get_count(dev_interface->rx_cq_res); k++)
{
volatile uint8_t *base = dev_interface->regs+dev_interface->rx_cq_offset+k*dev_interface->rx_cq_stride;
volatile uint8_t *base = mqnic_res_get_addr(dev_interface->rx_cq_res, k);
uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_CQ_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_CQ_BASE_ADDR_REG+4) << 32);
uint8_t active = (mqnic_reg_read32(base, MQNIC_CQ_ACTIVE_LOG_SIZE_REG) & MQNIC_CQ_ACTIVE_MASK) != 0;
@ -455,9 +455,9 @@ int main(int argc, char *argv[])
printf("EQ info\n");
printf(" Queue Base Address E LS A C Int Head Tail Len\n");
for (int k = 0; k < dev_interface->eq_count; k++)
for (int k = 0; k < mqnic_res_get_count(dev_interface->eq_res); k++)
{
volatile uint8_t *base = dev_interface->regs+dev_interface->eq_offset+k*dev_interface->eq_stride;
volatile uint8_t *base = mqnic_res_get_addr(dev_interface->eq_res, k);
uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_EQ_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_EQ_BASE_ADDR_REG+4) << 32);
uint8_t active = (mqnic_reg_read32(base, MQNIC_EQ_ACTIVE_LOG_SIZE_REG) & MQNIC_EQ_ACTIVE_MASK) != 0;
@ -475,7 +475,7 @@ int main(int argc, char *argv[])
for (int k = 0; k < dev_sched_block->sched_count; k++)
{
printf("Scheduler block %d scheduler %d\n", sched_block, k);
for (int l = 0; l < dev_interface->txq_count; l++)
for (int l = 0; l < mqnic_res_get_count(dev_interface->txq_res); l++)
{
printf("Sched %2d queue %4d state: 0x%08x\n", k, l, mqnic_reg_read32(dev_sched_block->sched[k]->regs, l*4));
}