diff --git a/rtl/eth_mac_10g_fifo.v b/rtl/eth_mac_10g_fifo.v index 7bba80a28..4a393320c 100644 --- a/rtl/eth_mac_10g_fifo.v +++ b/rtl/eth_mac_10g_fifo.v @@ -55,7 +55,6 @@ module eth_mac_10g_fifo # parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME, parameter PTP_PERIOD_NS = 4'h6, parameter PTP_PERIOD_FNS = 16'h6666, - parameter PTP_USE_SAMPLE_CLOCK = 0, parameter TX_PTP_TS_ENABLE = 0, parameter RX_PTP_TS_ENABLE = TX_PTP_TS_ENABLE, parameter TX_PTP_TS_CTRL_IN_TUSER = 0, @@ -229,8 +228,7 @@ if (TX_PTP_TS_ENABLE) begin : tx_ptp ptp_clock_cdc #( .TS_WIDTH(PTP_TS_WIDTH), .NS_WIDTH(6), - .FNS_WIDTH(16), - .USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK) + .FNS_WIDTH(16) ) tx_ptp_cdc ( .input_clk(logic_clk), @@ -306,8 +304,7 @@ if (RX_PTP_TS_ENABLE) begin : rx_ptp ptp_clock_cdc #( .TS_WIDTH(PTP_TS_WIDTH), .NS_WIDTH(6), - .FNS_WIDTH(16), - .USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK) + .FNS_WIDTH(16) ) rx_ptp_cdc ( .input_clk(logic_clk), diff --git a/rtl/eth_mac_phy_10g_fifo.v b/rtl/eth_mac_phy_10g_fifo.v index 25c1a7ac4..9d219d30b 100644 --- a/rtl/eth_mac_phy_10g_fifo.v +++ b/rtl/eth_mac_phy_10g_fifo.v @@ -63,7 +63,6 @@ module eth_mac_phy_10g_fifo # parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME, parameter PTP_PERIOD_NS = 4'h6, parameter PTP_PERIOD_FNS = 16'h6666, - parameter PTP_USE_SAMPLE_CLOCK = 0, parameter TX_PTP_TS_ENABLE = 0, parameter RX_PTP_TS_ENABLE = TX_PTP_TS_ENABLE, parameter TX_PTP_TS_CTRL_IN_TUSER = 0, @@ -258,8 +257,7 @@ if (TX_PTP_TS_ENABLE) begin : tx_ptp ptp_clock_cdc #( .TS_WIDTH(PTP_TS_WIDTH), .NS_WIDTH(6), - .FNS_WIDTH(16), - .USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK) + .FNS_WIDTH(16) ) tx_ptp_cdc ( .input_clk(logic_clk), @@ -335,8 +333,7 @@ if (RX_PTP_TS_ENABLE) begin : rx_ptp ptp_clock_cdc #( .TS_WIDTH(PTP_TS_WIDTH), .NS_WIDTH(6), - .FNS_WIDTH(16), - .USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK) + .FNS_WIDTH(16) ) rx_ptp_cdc ( .input_clk(logic_clk), diff --git a/rtl/ptp_clock_cdc.v b/rtl/ptp_clock_cdc.v index 5dd32167a..19db941f8 100644 --- a/rtl/ptp_clock_cdc.v +++ b/rtl/ptp_clock_cdc.v @@ -36,7 +36,6 @@ module ptp_clock_cdc # parameter TS_WIDTH = 96, parameter NS_WIDTH = 4, parameter FNS_WIDTH = 16, - parameter USE_SAMPLE_CLOCK = 1, parameter LOG_RATE = 3, parameter PIPELINE_OUTPUT = 0 ) @@ -304,37 +303,35 @@ reg edge_2_reg = 1'b0; reg [3:0] active_reg = 0; always @(posedge sample_clk) begin - if (USE_SAMPLE_CLOCK) begin - // phase and frequency detector - if (dest_sync_sample_sync2_reg && !dest_sync_sample_sync3_reg) begin - if (src_sync_sample_sync2_reg && !src_sync_sample_sync3_reg) begin - edge_1_reg <= 1'b0; - edge_2_reg <= 1'b0; - end else begin - edge_1_reg <= !edge_2_reg; - edge_2_reg <= 1'b0; - end - end else if (src_sync_sample_sync2_reg && !src_sync_sample_sync3_reg) begin - edge_1_reg <= 1'b0; - edge_2_reg <= !edge_1_reg; - end - - // accumulator - sample_acc_reg <= $signed(sample_acc_reg) + $signed({1'b0, edge_2_reg}) - $signed({1'b0, edge_1_reg}); - - sample_cnt_reg <= sample_cnt_reg + 1; - + // phase and frequency detector + if (dest_sync_sample_sync2_reg && !dest_sync_sample_sync3_reg) begin if (src_sync_sample_sync2_reg && !src_sync_sample_sync3_reg) begin - active_reg[0] <= 1'b1; + edge_1_reg <= 1'b0; + edge_2_reg <= 1'b0; + end else begin + edge_1_reg <= !edge_2_reg; + edge_2_reg <= 1'b0; end + end else if (src_sync_sample_sync2_reg && !src_sync_sample_sync3_reg) begin + edge_1_reg <= 1'b0; + edge_2_reg <= !edge_1_reg; + end - if (sample_cnt_reg == 0) begin - active_reg <= {active_reg, src_sync_sample_sync2_reg && !src_sync_sample_sync3_reg}; - sample_acc_reg <= $signed({1'b0, edge_2_reg}) - $signed({1'b0, edge_1_reg}); - sample_acc_out_reg <= sample_acc_reg; - if (active_reg != 0) begin - sample_update_reg <= !sample_update_reg; - end + // accumulator + sample_acc_reg <= $signed(sample_acc_reg) + $signed({1'b0, edge_2_reg}) - $signed({1'b0, edge_1_reg}); + + sample_cnt_reg <= sample_cnt_reg + 1; + + if (src_sync_sample_sync2_reg && !src_sync_sample_sync3_reg) begin + active_reg[0] <= 1'b1; + end + + if (sample_cnt_reg == 0) begin + active_reg <= {active_reg, src_sync_sample_sync2_reg && !src_sync_sample_sync3_reg}; + sample_acc_reg <= $signed({1'b0, edge_2_reg}) - $signed({1'b0, edge_1_reg}); + sample_acc_out_reg <= sample_acc_reg; + if (active_reg != 0) begin + sample_update_reg <= !sample_update_reg; end end end @@ -348,50 +345,6 @@ end reg [SAMPLE_ACC_WIDTH-1:0] sample_acc_sync_reg = 0; reg sample_acc_sync_valid_reg = 0; -always @(posedge output_clk) begin - if (USE_SAMPLE_CLOCK) begin - // latch in synchronized counts from phase detector - sample_acc_sync_valid_reg <= 1'b0; - if (sample_update_sync2_reg ^ sample_update_sync3_reg) begin - sample_acc_sync_reg <= sample_acc_out_reg; - sample_acc_sync_valid_reg <= 1'b1; - end - end else begin - // phase and frequency detector - if (dest_sync_sync2_reg && !dest_sync_sync3_reg) begin - if (src_sync_sync2_reg && !src_sync_sync3_reg) begin - edge_1_reg <= 1'b0; - edge_2_reg <= 1'b0; - end else begin - edge_1_reg <= !edge_2_reg; - edge_2_reg <= 1'b0; - end - end else if (src_sync_sync2_reg && !src_sync_sync3_reg) begin - edge_1_reg <= 1'b0; - edge_2_reg <= !edge_1_reg; - end - - // accumulator - sample_acc_reg <= $signed(sample_acc_reg) + $signed({1'b0, edge_2_reg}) - $signed({1'b0, edge_1_reg}); - - sample_cnt_reg <= sample_cnt_reg + 1; - - if (src_sync_sync2_reg && !src_sync_sync3_reg) begin - active_reg[0] <= 1'b1; - end - - sample_acc_sync_valid_reg <= 1'b0; - if (sample_cnt_reg == 0) begin - active_reg <= {active_reg, src_sync_sync2_reg && !src_sync_sync3_reg}; - sample_acc_reg <= $signed({1'b0, edge_2_reg}) - $signed({1'b0, edge_1_reg}); - sample_acc_sync_reg <= sample_acc_reg; - if (active_reg != 0) begin - sample_acc_sync_valid_reg <= 1'b1; - end - end - end -end - reg [PHASE_ACC_WIDTH-1:0] dest_err_int_reg = 0, dest_err_int_next = 0; reg [1:0] dest_ovf; @@ -464,6 +417,13 @@ always @(posedge output_clk) begin dest_phase_inc_reg <= dest_phase_inc_next; dest_update_reg <= dest_update_next; + sample_acc_sync_valid_reg <= 1'b0; + if (sample_update_sync2_reg ^ sample_update_sync3_reg) begin + // latch in synchronized counts from phase detector + sample_acc_sync_reg <= sample_acc_out_reg; + sample_acc_sync_valid_reg <= 1'b1; + end + if (dest_update_reg) begin // capture local TS if (PIPELINE_OUTPUT > 0) begin diff --git a/tb/eth_mac_10g_fifo/Makefile b/tb/eth_mac_10g_fifo/Makefile index ae8109a08..2a85805e9 100644 --- a/tb/eth_mac_10g_fifo/Makefile +++ b/tb/eth_mac_10g_fifo/Makefile @@ -64,7 +64,6 @@ export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) export PARAM_PTP_PERIOD_NS := 6 export PARAM_PTP_PERIOD_FNS := 26214 -export PARAM_PTP_USE_SAMPLE_CLOCK := 0 export PARAM_TX_PTP_TS_ENABLE := 1 export PARAM_RX_PTP_TS_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_TX_PTP_TS_CTRL_IN_TUSER := $(PARAM_TX_PTP_TS_ENABLE) diff --git a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py index 0fe7ccaed..fe98b8de3 100644 --- a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py +++ b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py @@ -62,6 +62,7 @@ class TB: cocotb.start_soon(Clock(dut.logic_clk, self.clk_period, units="ns").start()) cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start()) cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start()) + cocotb.start_soon(Clock(dut.ptp_sample_clk, 9.9, units="ns").start()) self.xgmii_source = XgmiiSource(dut.xgmii_rxd, dut.xgmii_rxc, dut.rx_clk, dut.rx_rst) self.xgmii_sink = XgmiiSink(dut.xgmii_txd, dut.xgmii_txc, dut.tx_clk, dut.tx_rst) @@ -72,7 +73,6 @@ class TB: self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts_96, clock=dut.logic_clk) self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) - dut.ptp_sample_clk.setimmediatevalue(0) dut.ptp_ts_step.setimmediatevalue(0) dut.cfg_ifg.setimmediatevalue(0) @@ -138,7 +138,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): assert rx_frame.tdata == test_data assert frame_error == 0 - assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period) < tb.clk_period + assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period) < tb.clk_period*2 assert tb.axis_sink.empty() @@ -184,7 +184,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() assert rx_frame.ctrl is None - assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < tb.clk_period + assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < tb.clk_period*2 assert tb.xgmii_sink.empty() @@ -240,7 +240,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() assert rx_frame.ctrl is None - assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < tb.clk_period + assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < tb.clk_period*2 start_lane.append(rx_frame.start_lane) @@ -365,7 +365,6 @@ def test_eth_mac_10g_fifo(request, data_width, enable_dic): parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME'] parameters['PTP_PERIOD_NS'] = 0x6 if parameters['DATA_WIDTH'] == 64 else 0x3 parameters['PTP_PERIOD_FNS'] = 0x6666 if parameters['DATA_WIDTH'] == 64 else 0x3333 - parameters['PTP_USE_SAMPLE_CLOCK'] = 0 parameters['TX_PTP_TS_ENABLE'] = 1 parameters['RX_PTP_TS_ENABLE'] = parameters['TX_PTP_TS_ENABLE'] parameters['TX_PTP_TS_CTRL_IN_TUSER'] = parameters['TX_PTP_TS_ENABLE'] diff --git a/tb/eth_mac_phy_10g_fifo/Makefile b/tb/eth_mac_phy_10g_fifo/Makefile index c44570970..9d94621aa 100644 --- a/tb/eth_mac_phy_10g_fifo/Makefile +++ b/tb/eth_mac_phy_10g_fifo/Makefile @@ -69,7 +69,6 @@ export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) export PARAM_PTP_PERIOD_NS := 6 export PARAM_PTP_PERIOD_FNS := 26214 -export PARAM_PTP_USE_SAMPLE_CLOCK := 0 export PARAM_TX_PTP_TS_ENABLE := 1 export PARAM_RX_PTP_TS_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_TX_PTP_TS_CTRL_IN_TUSER := $(PARAM_TX_PTP_TS_ENABLE) diff --git a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py index a4cd1b617..6382e822a 100644 --- a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py +++ b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py @@ -73,6 +73,7 @@ class TB: cocotb.start_soon(Clock(dut.logic_clk, self.clk_period, units="ns").start()) cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start()) cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start()) + cocotb.start_soon(Clock(dut.ptp_sample_clk, 9.9, units="ns").start()) self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip) self.serdes_sink = BaseRSerdesSink(dut.serdes_tx_data, dut.serdes_tx_hdr, dut.tx_clk) @@ -83,7 +84,6 @@ class TB: self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts_96, clock=dut.logic_clk) self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) - dut.ptp_sample_clk.setimmediatevalue(0) dut.ptp_ts_step.setimmediatevalue(0) dut.cfg_ifg.setimmediatevalue(0) @@ -158,7 +158,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): assert rx_frame.tdata == test_data assert frame_error == 0 - assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*4) < tb.clk_period + assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*4) < tb.clk_period*2 assert tb.axis_sink.empty() @@ -204,7 +204,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() assert rx_frame.ctrl is None - assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*5) < tb.clk_period + assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*5) < tb.clk_period*2 assert tb.serdes_sink.empty() @@ -260,7 +260,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() assert rx_frame.ctrl is None - assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*5) < tb.clk_period + assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*5) < tb.clk_period*2 start_lane.append(rx_frame.start_lane) @@ -431,7 +431,6 @@ def test_eth_mac_phy_10g_fifo(request, data_width, enable_dic): parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME'] parameters['PTP_PERIOD_NS'] = 0x6 if parameters['DATA_WIDTH'] == 64 else 0x3 parameters['PTP_PERIOD_FNS'] = 0x6666 if parameters['DATA_WIDTH'] == 64 else 0x3333 - parameters['PTP_USE_SAMPLE_CLOCK'] = 0 parameters['TX_PTP_TS_ENABLE'] = 1 parameters['RX_PTP_TS_ENABLE'] = parameters['TX_PTP_TS_ENABLE'] parameters['TX_PTP_TS_CTRL_IN_TUSER'] = parameters['TX_PTP_TS_ENABLE'] diff --git a/tb/ptp_clock_cdc/Makefile b/tb/ptp_clock_cdc/Makefile index 2272408ed..2bf883844 100644 --- a/tb/ptp_clock_cdc/Makefile +++ b/tb/ptp_clock_cdc/Makefile @@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v export PARAM_TS_WIDTH := 96 export PARAM_NS_WIDTH := 4 export PARAM_FNS_WIDTH := 16 -export PARAM_USE_SAMPLE_CLOCK := 1 export PARAM_LOG_RATE := 3 export PARAM_PIPELINE_OUTPUT := 0 diff --git a/tb/ptp_clock_cdc/test_ptp_clock_cdc.py b/tb/ptp_clock_cdc/test_ptp_clock_cdc.py index 66cfd37a6..f3839ba33 100644 --- a/tb/ptp_clock_cdc/test_ptp_clock_cdc.py +++ b/tb/ptp_clock_cdc/test_ptp_clock_cdc.py @@ -229,9 +229,8 @@ lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -@pytest.mark.parametrize("sample_clock", [1, 0]) @pytest.mark.parametrize("ts_width", [96, 64]) -def test_ptp_clock_cdc(request, ts_width, sample_clock): +def test_ptp_clock_cdc(request, ts_width): dut = "ptp_clock_cdc" module = os.path.splitext(os.path.basename(__file__))[0] toplevel = dut @@ -245,7 +244,6 @@ def test_ptp_clock_cdc(request, ts_width, sample_clock): parameters['TS_WIDTH'] = ts_width parameters['NS_WIDTH'] = 4 parameters['FNS_WIDTH'] = 16 - parameters['USE_SAMPLE_CLOCK'] = sample_clock parameters['LOG_RATE'] = 3 parameters['PIPELINE_OUTPUT'] = 0