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Add flow control

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-09-09 19:01:36 -07:00
parent a169578cfd
commit 9963674c61
378 changed files with 10543 additions and 460 deletions
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2
docs/source/rb/if_ctrl.rst
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@ -62,6 +62,8 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
8 TX checksum offloading 8 TX checksum offloading
9 RX checksum offloading 9 RX checksum offloading
10 RX flow hash offloading 10 RX flow hash offloading
11 LFC (IEEE 802.3 annex 31B)
12 PFC (IEEE 802.3 annex 31D)
=== ======================= === =======================
.. object:: Port count .. object:: Port count

124
docs/source/rb/port_ctrl.rst
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@ -19,10 +19,30 @@ The port control register block has a header with type 0x0000C003, version 0x000
-------- ------------- ------------------------------ ------------- -------- ------------- ------------------------------ -------------
RBB+0x0C Features Port feature bits RO - RBB+0x0C Features Port feature bits RO -
-------- ------------- ------------------------------ ------------- -------- ------------- ------------------------------ -------------
RBB+0x10 TX status TX status RO - RBB+0x10 TX control TX control/status RW 0x00000000
-------- ------------- ------------------------------ ------------- -------- ------------- ------------------------------ -------------
RBB+0x14 RX status RX status RO - RBB+0x14 RX control RX control/status RW 0x00000000
======== ============= ============================== ============= -------- ------------- ------------------------------ -------------
RBB+0x18 FC ctrl RX quanta step TX quanta step RW -
-------- ------------- -------------- -------------- -------------
RBB+0x1C LFC ctrl ctrl LFC watermark RW 0x00000000
-------- ------------- ------ ---------------------- -------------
RBB+0x20 PFC ctrl 0 ctrl PFC watermark 0 RW 0x00000000
-------- ------------- ------ ---------------------- -------------
RBB+0x24 PFC ctrl 1 ctrl PFC watermark 1 RW 0x00000000
-------- ------------- ------ ---------------------- -------------
RBB+0x28 PFC ctrl 2 ctrl PFC watermark 2 RW 0x00000000
-------- ------------- ------ ---------------------- -------------
RBB+0x2C PFC ctrl 3 ctrl PFC watermark 3 RW 0x00000000
-------- ------------- ------ ---------------------- -------------
RBB+0x30 PFC ctrl 4 ctrl PFC watermark 4 RW 0x00000000
-------- ------------- ------ ---------------------- -------------
RBB+0x34 PFC ctrl 5 ctrl PFC watermark 5 RW 0x00000000
-------- ------------- ------ ---------------------- -------------
RBB+0x38 PFC ctrl 6 ctrl PFC watermark 6 RW 0x00000000
-------- ------------- ------ ---------------------- -------------
RBB+0x3C PFC ctrl 7 ctrl PFC watermark 7 RW 0x00000000
======== ============= ====== ====================== =============
See :ref:`rb_overview` for definitions of the standard register block header fields. See :ref:`rb_overview` for definitions of the standard register block header fields.
@ -45,19 +65,48 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
=== ======================= === =======================
Bit Feature Bit Feature
=== ======================= === =======================
\- None implemented 0 LFC (IEEE 802.3 annex 31B)
1 PFC (IEEE 802.3 annex 31D)
2 Internal MAC control
=== ======================= === =======================
.. object:: TX status .. object:: TX control/status
The TX status field contains some high-level status information about the transmit size of the link associated with the port. The TX control/status field contains some high-level control and status registers for the transmit side of the link associated with the port.
.. table:: .. table::
======== ====== ====== ====== ====== ============= ======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== ============= ======== ====== ====== ====== ====== =============
RBB+0x10 TX status RO - RBB+0x10 TX control/status RW 0x00000000
======== ============================== =============
Control bits:
.. table::
=== =======================
Bit Function
=== =======================
0 TX enable
8 TX pause control (halt TX traffic)
16 TX status (link is ready)
17 TX reset status (MAC TX is in reset)
24 TX pause req status
25 TX pause ack status
=== =======================
.. object:: RX control/status
The RX control/status field contains some high-level control and status registers for the receive side of the link associated with the port.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x14 RX control/status RO -
======== ============================== ============= ======== ============================== =============
Status bits: Status bits:
@ -67,29 +116,72 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
=== ======================= === =======================
Bit Function Bit Function
=== ======================= === =======================
0 TX status (link is ready) 0 RX enable
1 TX reset status (MAC TX is in reset) 8 RX pause control (halt RX traffic)
16 RX status (link is ready)
17 RX reset status (MAC RX is in reset)
24 RX pause req status
25 RX pause ack status
=== ======================= === =======================
.. object:: RX status .. object:: FC control
The RX status field contains some high-level status information about the receive side of the link associated with the port. The FC control field contains the quanta step size per clock cycle in units of 1/256 of one quanta for the internal MAC control layer. Default value is based on the MAC interface width.
.. table:: .. table::
======== ====== ====== ====== ====== ============= ======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== ============= ======== ====== ====== ====== ====== =============
RBB+0x14 RX status RO - RBB+0x18 RX quanta step TX quanta step RW -
======== ============================== ============= ======== ============== ============== =============
Status bits: .. object:: LFC control
The LFC control field contains control and status registers for link-level flow control (LFC) (IEEE 802.3 annex 31B pause frames).
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x1C ctrl LFC watermark RW 0x00000000
======== ====== ====================== =============
control bits:
.. table:: .. table::
=== ======================= === =======================
Bit Function Bit Function
=== ======================= === =======================
0 RX status (link is ready) 24 TX LFC en
1 RX reset status (MAC RX is in reset) 25 RX LFC en
28 TX LFC req
29 RX LFC req
=== =======================
.. object:: PFC control N
The PFC control field contains control and status registers for priority flow control (PFC) (IEEE 802.3 annex 31D PFC).
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x20 ctrl PFC watermark RW 0x00000000
======== ====== ====================== =============
control bits:
.. table::
=== =======================
Bit Function
=== =======================
24 TX PFC en
25 RX PFC en
28 TX PFC req
29 RX PFC req
=== ======================= === =======================

7
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
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@ -56,6 +56,10 @@ VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../rtl/mqnic_app_block_dma_bench.v VERILOG_SOURCES += ../../rtl/mqnic_app_block_dma_bench.v
VERILOG_SOURCES += ../../rtl/dma_bench.v VERILOG_SOURCES += ../../rtl/dma_bench.v
VERILOG_SOURCES += ../../rtl/dram_test_ch.v VERILOG_SOURCES += ../../rtl/dram_test_ch.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
@ -167,6 +171,9 @@ export PARAM_TX_TAG_WIDTH := 16
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_MAC_CTRL_ENABLE := 1
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 131072 export PARAM_RX_FIFO_DEPTH := 131072
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

48
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -3,6 +3,7 @@
import logging import logging
import os import os
import struct
import sys import sys
import scapy.utils import scapy.utils
@ -321,7 +322,11 @@ class TB(object):
self.port_mac.append(mac) self.port_mac.append(mac)
dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_tx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_lfc_req.setimmediatevalue(0)
dut.eth_rx_pfc_req.setimmediatevalue(0)
dut.eth_rx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
# DDR # DDR
self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value
@ -645,13 +650,16 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) await block.interface.set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(len(block.interface.txq)): for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(block.interface.sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else: else:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000)
await block.interface.ports[block.index].set_tx_ctrl(mqnic.MQNIC_PORT_TX_CTRL_EN)
await block.interface.ports[block.index].set_rx_ctrl(mqnic.MQNIC_PORT_RX_CTRL_EN)
count = 64 count = 64
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
@ -681,6 +689,35 @@ async def run_test_nic(dut):
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
if tb.driver.interfaces[0].if_feature_lfc:
tb.log.info("Test LFC pause frame RX")
await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN)
await tb.driver.hw_regs.read_dword(0)
lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000)
await tb.port_mac[0].rx.send(bytes(lfc_xoff))
count = 16
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
if tb.driver.interfaces[0].if_feature_rx_csum:
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
app_reg_blocks = mqnic.RegBlockList() app_reg_blocks = mqnic.RegBlockList()
await app_reg_blocks.enumerate_reg_blocks(tb.driver.app_hw_regs) await app_reg_blocks.enumerate_reg_blocks(tb.driver.app_hw_regs)
@ -974,6 +1011,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "mqnic_app_block_dma_bench.v"), os.path.join(rtl_dir, "mqnic_app_block_dma_bench.v"),
os.path.join(rtl_dir, "dma_bench.v"), os.path.join(rtl_dir, "dma_bench.v"),
os.path.join(rtl_dir, "dram_test_ch.v"), os.path.join(rtl_dir, "dram_test_ch.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"),
@ -1085,6 +1126,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['MAC_CTRL_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072 parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

7
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
View File

@ -54,6 +54,10 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../rtl/mqnic_app_block.v VERILOG_SOURCES += ../../rtl/mqnic_app_block.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
@ -161,6 +165,9 @@ export PARAM_TX_TAG_WIDTH := 16
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_MAC_CTRL_ENABLE := 1
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 131072 export PARAM_RX_FIFO_DEPTH := 131072
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

48
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -3,6 +3,7 @@
import logging import logging
import os import os
import struct
import sys import sys
import scapy.utils import scapy.utils
@ -321,7 +322,11 @@ class TB(object):
self.port_mac.append(mac) self.port_mac.append(mac)
dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_tx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_lfc_req.setimmediatevalue(0)
dut.eth_rx_pfc_req.setimmediatevalue(0)
dut.eth_rx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
# DDR # DDR
self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value
@ -645,13 +650,16 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) await block.interface.set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(len(block.interface.txq)): for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(block.interface.sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else: else:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000)
await block.interface.ports[block.index].set_tx_ctrl(mqnic.MQNIC_PORT_TX_CTRL_EN)
await block.interface.ports[block.index].set_rx_ctrl(mqnic.MQNIC_PORT_RX_CTRL_EN)
count = 64 count = 64
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
@ -681,6 +689,35 @@ async def run_test_nic(dut):
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
if tb.driver.interfaces[0].if_feature_lfc:
tb.log.info("Test LFC pause frame RX")
await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN)
await tb.driver.hw_regs.read_dword(0)
lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000)
await tb.port_mac[0].rx.send(bytes(lfc_xoff))
count = 16
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
if tb.driver.interfaces[0].if_feature_rx_csum:
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
tb.log.info("Read statistics counters") tb.log.info("Read statistics counters")
await Timer(2000, 'ns') await Timer(2000, 'ns')
@ -773,6 +810,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
os.path.join(rtl_dir, "mqnic_app_block.v"), os.path.join(rtl_dir, "mqnic_app_block.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"),
@ -881,6 +922,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['MAC_CTRL_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072 parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

86
fpga/common/rtl/cmac_gty_wrapper.v
View File

@ -130,6 +130,12 @@ module cmac_gty_wrapper #
output wire [15:0] tx_ptp_ts_tag, output wire [15:0] tx_ptp_ts_tag,
output wire tx_ptp_ts_valid, output wire tx_ptp_ts_valid,
input wire tx_enable,
input wire tx_lfc_en,
input wire tx_lfc_req,
input wire [7:0] tx_pfc_en,
input wire [7:0] tx_pfc_req,
output wire rx_clk, output wire rx_clk,
output wire rx_rst, output wire rx_rst,
@ -143,7 +149,14 @@ module cmac_gty_wrapper #
output wire rx_ptp_rst, output wire rx_ptp_rst,
input wire [79:0] rx_ptp_time, input wire [79:0] rx_ptp_time,
output wire rx_status input wire rx_enable,
output wire rx_status,
input wire rx_lfc_en,
output wire rx_lfc_req,
input wire rx_lfc_ack,
input wire [7:0] rx_pfc_en,
output wire [7:0] rx_pfc_req,
input wire [7:0] rx_pfc_ack
); );
reg [23:0] drp_addr_reg = 24'd0; reg [23:0] drp_addr_reg = 24'd0;
@ -1578,7 +1591,48 @@ cmac_usplus cmac_inst (
.stat_rx_packet_large(cmac_stat_rx_packet_large), .stat_rx_packet_large(cmac_stat_rx_packet_large),
.stat_rx_packet_small(cmac_stat_rx_packet_small), .stat_rx_packet_small(cmac_stat_rx_packet_small),
.ctl_rx_enable(cmac_ctl_rx_enable_reg), .stat_rx_pause(),
.stat_rx_pause_quanta0(),
.stat_rx_pause_quanta1(),
.stat_rx_pause_quanta2(),
.stat_rx_pause_quanta3(),
.stat_rx_pause_quanta4(),
.stat_rx_pause_quanta5(),
.stat_rx_pause_quanta6(),
.stat_rx_pause_quanta7(),
.stat_rx_pause_quanta8(),
.stat_rx_pause_req({rx_lfc_req, rx_pfc_req}),
.stat_rx_pause_valid(),
.stat_rx_user_pause(),
.ctl_rx_check_etype_gcp(1'b1),
.ctl_rx_check_etype_gpp(1'b1),
.ctl_rx_check_etype_pcp(1'b1),
.ctl_rx_check_etype_ppp(1'b1),
.ctl_rx_check_mcast_gcp(1'b1),
.ctl_rx_check_mcast_gpp(1'b1),
.ctl_rx_check_mcast_pcp(1'b1),
.ctl_rx_check_mcast_ppp(1'b1),
.ctl_rx_check_opcode_gcp(1'b1),
.ctl_rx_check_opcode_gpp(1'b1),
.ctl_rx_check_opcode_pcp(1'b1),
.ctl_rx_check_opcode_ppp(1'b1),
.ctl_rx_check_sa_gcp(1'b0),
.ctl_rx_check_sa_gpp(1'b0),
.ctl_rx_check_sa_pcp(1'b0),
.ctl_rx_check_sa_ppp(1'b0),
.ctl_rx_check_ucast_gcp(1'b0),
.ctl_rx_check_ucast_gpp(1'b0),
.ctl_rx_check_ucast_pcp(1'b0),
.ctl_rx_check_ucast_ppp(1'b0),
.ctl_rx_enable_gcp(rx_lfc_en),
.ctl_rx_enable_gpp(rx_lfc_en),
.ctl_rx_enable_pcp(rx_pfc_en != 0),
.ctl_rx_enable_ppp(rx_pfc_en != 0),
.ctl_rx_pause_ack({rx_lfc_ack, rx_pfc_ack}),
.ctl_rx_pause_enable({rx_lfc_en, rx_pfc_en}),
.ctl_rx_enable(cmac_ctl_rx_enable_reg && rx_enable),
.ctl_rx_force_resync(cmac_ctl_rx_force_resync_reg), .ctl_rx_force_resync(cmac_ctl_rx_force_resync_reg),
.ctl_rx_test_pattern(cmac_ctl_rx_test_pattern_reg), .ctl_rx_test_pattern(cmac_ctl_rx_test_pattern_reg),
@ -1658,7 +1712,7 @@ cmac_usplus cmac_inst (
.stat_tx_unicast(cmac_stat_tx_unicast), .stat_tx_unicast(cmac_stat_tx_unicast),
.stat_tx_vlan(cmac_stat_tx_vlan), .stat_tx_vlan(cmac_stat_tx_vlan),
.ctl_tx_enable(cmac_ctl_tx_enable_reg), .ctl_tx_enable(cmac_ctl_tx_enable_reg && tx_enable),
.ctl_tx_send_idle(cmac_ctl_tx_send_idle_reg), .ctl_tx_send_idle(cmac_ctl_tx_send_idle_reg),
.ctl_tx_send_rfi(cmac_ctl_tx_send_rfi_reg), .ctl_tx_send_rfi(cmac_ctl_tx_send_rfi_reg),
.ctl_tx_send_lfi(cmac_ctl_tx_send_lfi_reg), .ctl_tx_send_lfi(cmac_ctl_tx_send_lfi_reg),
@ -1666,6 +1720,32 @@ cmac_usplus cmac_inst (
.tx_clk(tx_clk), .tx_clk(tx_clk),
.stat_tx_pause_valid(),
.stat_tx_pause(),
.stat_tx_user_pause(),
.ctl_tx_pause_enable({tx_lfc_en, tx_pfc_en}),
.ctl_tx_pause_quanta0(16'hffff),
.ctl_tx_pause_quanta1(16'hffff),
.ctl_tx_pause_quanta2(16'hffff),
.ctl_tx_pause_quanta3(16'hffff),
.ctl_tx_pause_quanta4(16'hffff),
.ctl_tx_pause_quanta5(16'hffff),
.ctl_tx_pause_quanta6(16'hffff),
.ctl_tx_pause_quanta7(16'hffff),
.ctl_tx_pause_quanta8(16'hffff),
.ctl_tx_pause_refresh_timer0(16'h7fff),
.ctl_tx_pause_refresh_timer1(16'h7fff),
.ctl_tx_pause_refresh_timer2(16'h7fff),
.ctl_tx_pause_refresh_timer3(16'h7fff),
.ctl_tx_pause_refresh_timer4(16'h7fff),
.ctl_tx_pause_refresh_timer5(16'h7fff),
.ctl_tx_pause_refresh_timer6(16'h7fff),
.ctl_tx_pause_refresh_timer7(16'h7fff),
.ctl_tx_pause_refresh_timer8(16'h7fff),
.ctl_tx_pause_req({tx_lfc_req, tx_pfc_req}),
.ctl_tx_resend_pause(1'b0),
.tx_axis_tready(cmac_tx_axis_tready), .tx_axis_tready(cmac_tx_axis_tready),
.tx_axis_tvalid(cmac_tx_axis_tvalid), .tx_axis_tvalid(cmac_tx_axis_tvalid),
.tx_axis_tdata(cmac_tx_axis_tdata), .tx_axis_tdata(cmac_tx_axis_tdata),

34
fpga/common/rtl/mqnic_core.v
View File

@ -80,6 +80,9 @@ module mqnic_core #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter MAC_CTRL_ENABLE = 0,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -410,7 +413,13 @@ module mqnic_core #
input wire [PORT_COUNT-1:0] s_axis_tx_cpl_valid, input wire [PORT_COUNT-1:0] s_axis_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_cpl_ready, output wire [PORT_COUNT-1:0] s_axis_tx_cpl_ready,
output wire [PORT_COUNT-1:0] tx_enable,
input wire [PORT_COUNT-1:0] tx_status, input wire [PORT_COUNT-1:0] tx_status,
output wire [PORT_COUNT-1:0] tx_lfc_en,
output wire [PORT_COUNT-1:0] tx_lfc_req,
output wire [PORT_COUNT*8-1:0] tx_pfc_en,
output wire [PORT_COUNT*8-1:0] tx_pfc_req,
input wire [PORT_COUNT-1:0] tx_fc_quanta_clk_en,
input wire [PORT_COUNT-1:0] rx_clk, input wire [PORT_COUNT-1:0] rx_clk,
input wire [PORT_COUNT-1:0] rx_rst, input wire [PORT_COUNT-1:0] rx_rst,
@ -427,7 +436,15 @@ module mqnic_core #
input wire [PORT_COUNT-1:0] s_axis_rx_tlast, input wire [PORT_COUNT-1:0] s_axis_rx_tlast,
input wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser, input wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
output wire [PORT_COUNT-1:0] rx_enable,
input wire [PORT_COUNT-1:0] rx_status, input wire [PORT_COUNT-1:0] rx_status,
output wire [PORT_COUNT-1:0] rx_lfc_en,
input wire [PORT_COUNT-1:0] rx_lfc_req,
output wire [PORT_COUNT-1:0] rx_lfc_ack,
output wire [PORT_COUNT*8-1:0] rx_pfc_en,
input wire [PORT_COUNT*8-1:0] rx_pfc_req,
output wire [PORT_COUNT*8-1:0] rx_pfc_ack,
input wire [PORT_COUNT-1:0] rx_fc_quanta_clk_en,
/* /*
* DDR * DDR
@ -3060,6 +3077,9 @@ generate
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(MAC_CTRL_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -3433,7 +3453,13 @@ generate
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid[n*PORTS_PER_IF +: PORTS_PER_IF]), .s_axis_tx_cpl_valid(s_axis_tx_cpl_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready[n*PORTS_PER_IF +: PORTS_PER_IF]), .s_axis_tx_cpl_ready(s_axis_tx_cpl_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
.tx_enable(tx_enable[n*PORTS_PER_IF +: PORTS_PER_IF]),
.tx_status(tx_status[n*PORTS_PER_IF +: PORTS_PER_IF]), .tx_status(tx_status[n*PORTS_PER_IF +: PORTS_PER_IF]),
.tx_lfc_en(tx_lfc_en[n*PORTS_PER_IF +: PORTS_PER_IF]),
.tx_lfc_req(tx_lfc_req[n*PORTS_PER_IF +: PORTS_PER_IF]),
.tx_pfc_en(tx_pfc_en[n*PORTS_PER_IF*8 +: PORTS_PER_IF*8]),
.tx_pfc_req(tx_pfc_req[n*PORTS_PER_IF*8 +: PORTS_PER_IF*8]),
.tx_fc_quanta_clk_en(tx_fc_quanta_clk_en[n*PORTS_PER_IF +: PORTS_PER_IF]),
/* /*
* Receive data input * Receive data input
@ -3448,7 +3474,15 @@ generate
.s_axis_rx_tlast(s_axis_rx_tlast[n*PORTS_PER_IF +: PORTS_PER_IF]), .s_axis_rx_tlast(s_axis_rx_tlast[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_rx_tuser(s_axis_rx_tuser[n*PORTS_PER_IF*AXIS_RX_USER_WIDTH +: PORTS_PER_IF*AXIS_RX_USER_WIDTH]), .s_axis_rx_tuser(s_axis_rx_tuser[n*PORTS_PER_IF*AXIS_RX_USER_WIDTH +: PORTS_PER_IF*AXIS_RX_USER_WIDTH]),
.rx_enable(rx_enable[n*PORTS_PER_IF +: PORTS_PER_IF]),
.rx_status(rx_status[n*PORTS_PER_IF +: PORTS_PER_IF]), .rx_status(rx_status[n*PORTS_PER_IF +: PORTS_PER_IF]),
.rx_lfc_en(rx_lfc_en[n*PORTS_PER_IF +: PORTS_PER_IF]),
.rx_lfc_req(rx_lfc_req[n*PORTS_PER_IF +: PORTS_PER_IF]),
.rx_lfc_ack(rx_lfc_ack[n*PORTS_PER_IF +: PORTS_PER_IF]),
.rx_pfc_en(rx_pfc_en[n*PORTS_PER_IF*8 +: PORTS_PER_IF*8]),
.rx_pfc_req(rx_pfc_req[n*PORTS_PER_IF*8 +: PORTS_PER_IF*8]),
.rx_pfc_ack(rx_pfc_ack[n*PORTS_PER_IF*8 +: PORTS_PER_IF*8]),
.rx_fc_quanta_clk_en(rx_fc_quanta_clk_en[n*PORTS_PER_IF +: PORTS_PER_IF]),
/* /*
* PTP clock * PTP clock

34
fpga/common/rtl/mqnic_core_axi.v
View File

@ -80,6 +80,9 @@ module mqnic_core_axi #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter MAC_CTRL_ENABLE = 0,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -372,7 +375,13 @@ module mqnic_core_axi #
input wire [PORT_COUNT-1:0] s_axis_tx_cpl_valid, input wire [PORT_COUNT-1:0] s_axis_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_cpl_ready, output wire [PORT_COUNT-1:0] s_axis_tx_cpl_ready,
output wire [PORT_COUNT-1:0] tx_enable,
input wire [PORT_COUNT-1:0] tx_status, input wire [PORT_COUNT-1:0] tx_status,
output wire [PORT_COUNT-1:0] tx_lfc_en,
output wire [PORT_COUNT-1:0] tx_lfc_req,
output wire [PORT_COUNT*8-1:0] tx_pfc_en,
output wire [PORT_COUNT*8-1:0] tx_pfc_req,
input wire [PORT_COUNT-1:0] tx_fc_quanta_clk_en,
input wire [PORT_COUNT-1:0] rx_clk, input wire [PORT_COUNT-1:0] rx_clk,
input wire [PORT_COUNT-1:0] rx_rst, input wire [PORT_COUNT-1:0] rx_rst,
@ -389,7 +398,15 @@ module mqnic_core_axi #
input wire [PORT_COUNT-1:0] s_axis_rx_tlast, input wire [PORT_COUNT-1:0] s_axis_rx_tlast,
input wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser, input wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
output wire [PORT_COUNT-1:0] rx_enable,
input wire [PORT_COUNT-1:0] rx_status, input wire [PORT_COUNT-1:0] rx_status,
output wire [PORT_COUNT-1:0] rx_lfc_en,
input wire [PORT_COUNT-1:0] rx_lfc_req,
output wire [PORT_COUNT-1:0] rx_lfc_ack,
output wire [PORT_COUNT*8-1:0] rx_pfc_en,
input wire [PORT_COUNT*8-1:0] rx_pfc_req,
output wire [PORT_COUNT*8-1:0] rx_pfc_ack,
input wire [PORT_COUNT-1:0] rx_fc_quanta_clk_en,
/* /*
* DDR * DDR
@ -994,6 +1011,9 @@ mqnic_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(MAC_CTRL_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1298,7 +1318,13 @@ core_inst (
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid), .s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready), .s_axis_tx_cpl_ready(s_axis_tx_cpl_ready),
.tx_enable(tx_enable),
.tx_status(tx_status), .tx_status(tx_status),
.tx_lfc_en(tx_lfc_en),
.tx_lfc_req(tx_lfc_req),
.tx_pfc_en(tx_pfc_en),
.tx_pfc_req(tx_pfc_req),
.tx_fc_quanta_clk_en(tx_fc_quanta_clk_en),
.rx_clk(rx_clk), .rx_clk(rx_clk),
.rx_rst(rx_rst), .rx_rst(rx_rst),
@ -1315,7 +1341,15 @@ core_inst (
.s_axis_rx_tlast(s_axis_rx_tlast), .s_axis_rx_tlast(s_axis_rx_tlast),
.s_axis_rx_tuser(s_axis_rx_tuser), .s_axis_rx_tuser(s_axis_rx_tuser),
.rx_enable(rx_enable),
.rx_status(rx_status), .rx_status(rx_status),
.rx_lfc_en(rx_lfc_en),
.rx_lfc_req(rx_lfc_req),
.rx_lfc_ack(rx_lfc_ack),
.rx_pfc_en(rx_pfc_en),
.rx_pfc_req(rx_pfc_req),
.rx_pfc_ack(rx_pfc_ack),
.rx_fc_quanta_clk_en(rx_fc_quanta_clk_en),
/* /*
* DDR * DDR

34
fpga/common/rtl/mqnic_core_pcie.v
View File

@ -80,6 +80,9 @@ module mqnic_core_pcie #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter MAC_CTRL_ENABLE = 0,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -389,7 +392,13 @@ module mqnic_core_pcie #
input wire [PORT_COUNT-1:0] s_axis_tx_cpl_valid, input wire [PORT_COUNT-1:0] s_axis_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_cpl_ready, output wire [PORT_COUNT-1:0] s_axis_tx_cpl_ready,
output wire [PORT_COUNT-1:0] tx_enable,
input wire [PORT_COUNT-1:0] tx_status, input wire [PORT_COUNT-1:0] tx_status,
output wire [PORT_COUNT-1:0] tx_lfc_en,
output wire [PORT_COUNT-1:0] tx_lfc_req,
output wire [PORT_COUNT*8-1:0] tx_pfc_en,
output wire [PORT_COUNT*8-1:0] tx_pfc_req,
input wire [PORT_COUNT-1:0] tx_fc_quanta_clk_en,
input wire [PORT_COUNT-1:0] rx_clk, input wire [PORT_COUNT-1:0] rx_clk,
input wire [PORT_COUNT-1:0] rx_rst, input wire [PORT_COUNT-1:0] rx_rst,
@ -406,7 +415,15 @@ module mqnic_core_pcie #
input wire [PORT_COUNT-1:0] s_axis_rx_tlast, input wire [PORT_COUNT-1:0] s_axis_rx_tlast,
input wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser, input wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
output wire [PORT_COUNT-1:0] rx_enable,
input wire [PORT_COUNT-1:0] rx_status, input wire [PORT_COUNT-1:0] rx_status,
output wire [PORT_COUNT-1:0] rx_lfc_en,
input wire [PORT_COUNT-1:0] rx_lfc_req,
output wire [PORT_COUNT-1:0] rx_lfc_ack,
output wire [PORT_COUNT*8-1:0] rx_pfc_en,
input wire [PORT_COUNT*8-1:0] rx_pfc_req,
output wire [PORT_COUNT*8-1:0] rx_pfc_ack,
input wire [PORT_COUNT-1:0] rx_fc_quanta_clk_en,
/* /*
* DDR * DDR
@ -1626,6 +1643,9 @@ mqnic_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(MAC_CTRL_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1954,7 +1974,13 @@ core_inst (
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid), .s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready), .s_axis_tx_cpl_ready(s_axis_tx_cpl_ready),
.tx_enable(tx_enable),
.tx_status(tx_status), .tx_status(tx_status),
.tx_lfc_en(tx_lfc_en),
.tx_lfc_req(tx_lfc_req),
.tx_pfc_en(tx_pfc_en),
.tx_pfc_req(tx_pfc_req),
.tx_fc_quanta_clk_en(tx_fc_quanta_clk_en),
.rx_clk(rx_clk), .rx_clk(rx_clk),
.rx_rst(rx_rst), .rx_rst(rx_rst),
@ -1971,7 +1997,15 @@ core_inst (
.s_axis_rx_tlast(s_axis_rx_tlast), .s_axis_rx_tlast(s_axis_rx_tlast),
.s_axis_rx_tuser(s_axis_rx_tuser), .s_axis_rx_tuser(s_axis_rx_tuser),
.rx_enable(rx_enable),
.rx_status(rx_status), .rx_status(rx_status),
.rx_lfc_en(rx_lfc_en),
.rx_lfc_req(rx_lfc_req),
.rx_lfc_ack(rx_lfc_ack),
.rx_pfc_en(rx_pfc_en),
.rx_pfc_req(rx_pfc_req),
.rx_pfc_ack(rx_pfc_ack),
.rx_fc_quanta_clk_en(rx_fc_quanta_clk_en),
/* /*
* DDR * DDR

34
fpga/common/rtl/mqnic_core_pcie_ptile.v
View File

@ -80,6 +80,9 @@ module mqnic_core_pcie_ptile #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter MAC_CTRL_ENABLE = 0,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -337,7 +340,13 @@ module mqnic_core_pcie_ptile #
input wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_valid, input wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_ready, output wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_ready,
output wire [PORT_COUNT-1:0] eth_tx_enable,
input wire [PORT_COUNT-1:0] eth_tx_status, input wire [PORT_COUNT-1:0] eth_tx_status,
output wire [PORT_COUNT-1:0] eth_tx_lfc_en,
output wire [PORT_COUNT-1:0] eth_tx_lfc_req,
output wire [PORT_COUNT*8-1:0] eth_tx_pfc_en,
output wire [PORT_COUNT*8-1:0] eth_tx_pfc_req,
input wire [PORT_COUNT-1:0] eth_tx_fc_quanta_clk_en,
input wire [PORT_COUNT-1:0] eth_rx_clk, input wire [PORT_COUNT-1:0] eth_rx_clk,
input wire [PORT_COUNT-1:0] eth_rx_rst, input wire [PORT_COUNT-1:0] eth_rx_rst,
@ -354,7 +363,15 @@ module mqnic_core_pcie_ptile #
input wire [PORT_COUNT-1:0] s_axis_eth_rx_tlast, input wire [PORT_COUNT-1:0] s_axis_eth_rx_tlast,
input wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] s_axis_eth_rx_tuser, input wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] s_axis_eth_rx_tuser,
output wire [PORT_COUNT-1:0] eth_rx_enable,
input wire [PORT_COUNT-1:0] eth_rx_status, input wire [PORT_COUNT-1:0] eth_rx_status,
output wire [PORT_COUNT-1:0] eth_rx_lfc_en,
input wire [PORT_COUNT-1:0] eth_rx_lfc_req,
output wire [PORT_COUNT-1:0] eth_rx_lfc_ack,
output wire [PORT_COUNT*8-1:0] eth_rx_pfc_en,
input wire [PORT_COUNT*8-1:0] eth_rx_pfc_req,
output wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack,
input wire [PORT_COUNT-1:0] eth_rx_fc_quanta_clk_en,
/* /*
* DDR * DDR
@ -788,6 +805,9 @@ mqnic_core_pcie #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(MAC_CTRL_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1095,7 +1115,13 @@ core_pcie_inst (
.s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid), .s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready), .s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready),
.tx_enable(eth_tx_enable),
.tx_status(eth_tx_status), .tx_status(eth_tx_status),
.tx_lfc_en(eth_tx_lfc_en),
.tx_lfc_req(eth_tx_lfc_req),
.tx_pfc_en(eth_tx_pfc_en),
.tx_pfc_req(eth_tx_pfc_req),
.tx_fc_quanta_clk_en(eth_tx_fc_quanta_clk_en),
.rx_clk(eth_rx_clk), .rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst), .rx_rst(eth_rx_rst),
@ -1112,7 +1138,15 @@ core_pcie_inst (
.s_axis_rx_tlast(s_axis_eth_rx_tlast), .s_axis_rx_tlast(s_axis_eth_rx_tlast),
.s_axis_rx_tuser(s_axis_eth_rx_tuser), .s_axis_rx_tuser(s_axis_eth_rx_tuser),
.rx_enable(eth_rx_enable),
.rx_status(eth_rx_status), .rx_status(eth_rx_status),
.rx_lfc_en(eth_rx_lfc_en),
.rx_lfc_req(eth_rx_lfc_req),
.rx_lfc_ack(eth_rx_lfc_ack),
.rx_pfc_en(eth_rx_pfc_en),
.rx_pfc_req(eth_rx_pfc_req),
.rx_pfc_ack(eth_rx_pfc_ack),
.rx_fc_quanta_clk_en(eth_rx_fc_quanta_clk_en),
/* /*
* DDR * DDR

34
fpga/common/rtl/mqnic_core_pcie_s10.v
View File

@ -80,6 +80,9 @@ module mqnic_core_pcie_s10 #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter MAC_CTRL_ENABLE = 0,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -333,7 +336,13 @@ module mqnic_core_pcie_s10 #
input wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_valid, input wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_ready, output wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_ready,
output wire [PORT_COUNT-1:0] eth_tx_enable,
input wire [PORT_COUNT-1:0] eth_tx_status, input wire [PORT_COUNT-1:0] eth_tx_status,
output wire [PORT_COUNT-1:0] eth_tx_lfc_en,
output wire [PORT_COUNT-1:0] eth_tx_lfc_req,
output wire [PORT_COUNT*8-1:0] eth_tx_pfc_en,
output wire [PORT_COUNT*8-1:0] eth_tx_pfc_req,
input wire [PORT_COUNT-1:0] eth_tx_fc_quanta_clk_en,
input wire [PORT_COUNT-1:0] eth_rx_clk, input wire [PORT_COUNT-1:0] eth_rx_clk,
input wire [PORT_COUNT-1:0] eth_rx_rst, input wire [PORT_COUNT-1:0] eth_rx_rst,
@ -350,7 +359,15 @@ module mqnic_core_pcie_s10 #
input wire [PORT_COUNT-1:0] s_axis_eth_rx_tlast, input wire [PORT_COUNT-1:0] s_axis_eth_rx_tlast,
input wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] s_axis_eth_rx_tuser, input wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] s_axis_eth_rx_tuser,
output wire [PORT_COUNT-1:0] eth_rx_enable,
input wire [PORT_COUNT-1:0] eth_rx_status, input wire [PORT_COUNT-1:0] eth_rx_status,
output wire [PORT_COUNT-1:0] eth_rx_lfc_en,
input wire [PORT_COUNT-1:0] eth_rx_lfc_req,
output wire [PORT_COUNT-1:0] eth_rx_lfc_ack,
output wire [PORT_COUNT*8-1:0] eth_rx_pfc_en,
input wire [PORT_COUNT*8-1:0] eth_rx_pfc_req,
output wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack,
input wire [PORT_COUNT-1:0] eth_rx_fc_quanta_clk_en,
/* /*
* DDR * DDR
@ -797,6 +814,9 @@ mqnic_core_pcie #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(MAC_CTRL_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1104,7 +1124,13 @@ core_pcie_inst (
.s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid), .s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready), .s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready),
.tx_enable(eth_tx_enable),
.tx_status(eth_tx_status), .tx_status(eth_tx_status),
.tx_lfc_en(eth_tx_lfc_en),
.tx_lfc_req(eth_tx_lfc_req),
.tx_pfc_en(eth_tx_pfc_en),
.tx_pfc_req(eth_tx_pfc_req),
.tx_fc_quanta_clk_en(eth_tx_fc_quanta_clk_en),
.rx_clk(eth_rx_clk), .rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst), .rx_rst(eth_rx_rst),
@ -1121,7 +1147,15 @@ core_pcie_inst (
.s_axis_rx_tlast(s_axis_eth_rx_tlast), .s_axis_rx_tlast(s_axis_eth_rx_tlast),
.s_axis_rx_tuser(s_axis_eth_rx_tuser), .s_axis_rx_tuser(s_axis_eth_rx_tuser),
.rx_enable(eth_rx_enable),
.rx_status(eth_rx_status), .rx_status(eth_rx_status),
.rx_lfc_en(eth_rx_lfc_en),
.rx_lfc_req(eth_rx_lfc_req),
.rx_lfc_ack(eth_rx_lfc_ack),
.rx_pfc_en(eth_rx_pfc_en),
.rx_pfc_req(eth_rx_pfc_req),
.rx_pfc_ack(eth_rx_pfc_ack),
.rx_fc_quanta_clk_en(eth_rx_fc_quanta_clk_en),
/* /*
* DDR * DDR

34
fpga/common/rtl/mqnic_core_pcie_us.v
View File

@ -80,6 +80,9 @@ module mqnic_core_pcie_us #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter MAC_CTRL_ENABLE = 0,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -393,7 +396,13 @@ module mqnic_core_pcie_us #
input wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_valid, input wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_ready, output wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_ready,
output wire [PORT_COUNT-1:0] eth_tx_enable,
input wire [PORT_COUNT-1:0] eth_tx_status, input wire [PORT_COUNT-1:0] eth_tx_status,
output wire [PORT_COUNT-1:0] eth_tx_lfc_en,
output wire [PORT_COUNT-1:0] eth_tx_lfc_req,
output wire [PORT_COUNT*8-1:0] eth_tx_pfc_en,
output wire [PORT_COUNT*8-1:0] eth_tx_pfc_req,
input wire [PORT_COUNT-1:0] eth_tx_fc_quanta_clk_en,
input wire [PORT_COUNT-1:0] eth_rx_clk, input wire [PORT_COUNT-1:0] eth_rx_clk,
input wire [PORT_COUNT-1:0] eth_rx_rst, input wire [PORT_COUNT-1:0] eth_rx_rst,
@ -410,7 +419,15 @@ module mqnic_core_pcie_us #
input wire [PORT_COUNT-1:0] s_axis_eth_rx_tlast, input wire [PORT_COUNT-1:0] s_axis_eth_rx_tlast,
input wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] s_axis_eth_rx_tuser, input wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] s_axis_eth_rx_tuser,
output wire [PORT_COUNT-1:0] eth_rx_enable,
input wire [PORT_COUNT-1:0] eth_rx_status, input wire [PORT_COUNT-1:0] eth_rx_status,
output wire [PORT_COUNT-1:0] eth_rx_lfc_en,
input wire [PORT_COUNT-1:0] eth_rx_lfc_req,
output wire [PORT_COUNT-1:0] eth_rx_lfc_ack,
output wire [PORT_COUNT*8-1:0] eth_rx_pfc_en,
input wire [PORT_COUNT*8-1:0] eth_rx_pfc_req,
output wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack,
input wire [PORT_COUNT-1:0] eth_rx_fc_quanta_clk_en,
/* /*
* DDR * DDR
@ -917,6 +934,9 @@ mqnic_core_pcie #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(MAC_CTRL_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1224,7 +1244,13 @@ core_pcie_inst (
.s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid), .s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready), .s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready),
.tx_enable(eth_tx_enable),
.tx_status(eth_tx_status), .tx_status(eth_tx_status),
.tx_lfc_en(eth_tx_lfc_en),
.tx_lfc_req(eth_tx_lfc_req),
.tx_pfc_en(eth_tx_pfc_en),
.tx_pfc_req(eth_tx_pfc_req),
.tx_fc_quanta_clk_en(eth_tx_fc_quanta_clk_en),
.rx_clk(eth_rx_clk), .rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst), .rx_rst(eth_rx_rst),
@ -1241,7 +1267,15 @@ core_pcie_inst (
.s_axis_rx_tlast(s_axis_eth_rx_tlast), .s_axis_rx_tlast(s_axis_eth_rx_tlast),
.s_axis_rx_tuser(s_axis_eth_rx_tuser), .s_axis_rx_tuser(s_axis_eth_rx_tuser),
.rx_enable(eth_rx_enable),
.rx_status(eth_rx_status), .rx_status(eth_rx_status),
.rx_lfc_en(eth_rx_lfc_en),
.rx_lfc_req(eth_rx_lfc_req),
.rx_lfc_ack(eth_rx_lfc_ack),
.rx_pfc_en(eth_rx_pfc_en),
.rx_pfc_req(eth_rx_pfc_req),
.rx_pfc_ack(eth_rx_pfc_ack),
.rx_fc_quanta_clk_en(eth_rx_fc_quanta_clk_en),
/* /*
* DDR * DDR

38
fpga/common/rtl/mqnic_interface.v
View File

@ -62,6 +62,9 @@ module mqnic_interface #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 0,
parameter LFC_ENABLE = PFC_ENABLE,
parameter MAC_CTRL_ENABLE = 0,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -435,7 +438,13 @@ module mqnic_interface #
input wire [PORTS-1:0] s_axis_tx_cpl_valid, input wire [PORTS-1:0] s_axis_tx_cpl_valid,
output wire [PORTS-1:0] s_axis_tx_cpl_ready, output wire [PORTS-1:0] s_axis_tx_cpl_ready,
output wire [PORTS-1:0] tx_enable,
input wire [PORTS-1:0] tx_status, input wire [PORTS-1:0] tx_status,
output wire [PORTS-1:0] tx_lfc_en,
output wire [PORTS-1:0] tx_lfc_req,
output wire [PORTS*8-1:0] tx_pfc_en,
output wire [PORTS*8-1:0] tx_pfc_req,
input wire [PORTS-1:0] tx_fc_quanta_clk_en,
/* /*
* Receive data input * Receive data input
@ -450,7 +459,15 @@ module mqnic_interface #
input wire [PORTS-1:0] s_axis_rx_tlast, input wire [PORTS-1:0] s_axis_rx_tlast,
input wire [PORTS*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser, input wire [PORTS*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
output wire [PORTS-1:0] rx_enable,
input wire [PORTS-1:0] rx_status, input wire [PORTS-1:0] rx_status,
output wire [PORTS-1:0] rx_lfc_en,
input wire [PORTS-1:0] rx_lfc_req,
output wire [PORTS-1:0] rx_lfc_ack,
output wire [PORTS*8-1:0] rx_pfc_en,
input wire [PORTS*8-1:0] rx_pfc_req,
output wire [PORTS*8-1:0] rx_pfc_ack,
input wire [PORTS-1:0] rx_fc_quanta_clk_en,
/* /*
* PTP clock * PTP clock
@ -1084,6 +1101,8 @@ always @(posedge clk) begin
ctrl_reg_rd_data_reg[8] <= TX_CHECKSUM_ENABLE; ctrl_reg_rd_data_reg[8] <= TX_CHECKSUM_ENABLE;
ctrl_reg_rd_data_reg[9] <= RX_CHECKSUM_ENABLE; ctrl_reg_rd_data_reg[9] <= RX_CHECKSUM_ENABLE;
ctrl_reg_rd_data_reg[10] <= RX_HASH_ENABLE; ctrl_reg_rd_data_reg[10] <= RX_HASH_ENABLE;
ctrl_reg_rd_data_reg[11] <= LFC_ENABLE;
ctrl_reg_rd_data_reg[12] <= PFC_ENABLE;
end end
RBB+8'h10: ctrl_reg_rd_data_reg <= PORTS; // IF ctrl: Port count RBB+8'h10: ctrl_reg_rd_data_reg <= PORTS; // IF ctrl: Port count
RBB+8'h14: ctrl_reg_rd_data_reg <= SCHEDULERS; // IF ctrl: Scheduler count RBB+8'h14: ctrl_reg_rd_data_reg <= SCHEDULERS; // IF ctrl: Scheduler count
@ -3101,6 +3120,9 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.TX_CPL_ENABLE(TX_CPL_ENABLE), .TX_CPL_ENABLE(TX_CPL_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_TAG_WIDTH(TX_TAG_WIDTH),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(MAC_CTRL_ENABLE),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE), .MAX_RX_SIZE(MAX_RX_SIZE),
@ -3275,7 +3297,13 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid[n +: 1]), .s_axis_tx_cpl_valid(s_axis_tx_cpl_valid[n +: 1]),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready[n +: 1]), .s_axis_tx_cpl_ready(s_axis_tx_cpl_ready[n +: 1]),
.tx_enable(tx_enable[n +: 1]),
.tx_status(tx_status[n +: 1]), .tx_status(tx_status[n +: 1]),
.tx_lfc_en(tx_lfc_en[n +: 1]),
.tx_lfc_req(tx_lfc_req[n +: 1]),
.tx_pfc_en(tx_pfc_en[n*8 +: 8]),
.tx_pfc_req(tx_pfc_req[n*8 +: 8]),
.tx_fc_quanta_clk_en(tx_fc_quanta_clk_en[n +: 1]),
/* /*
* Receive data input * Receive data input
@ -3290,7 +3318,15 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.s_axis_rx_tlast(s_axis_rx_tlast[n +: 1]), .s_axis_rx_tlast(s_axis_rx_tlast[n +: 1]),
.s_axis_rx_tuser(s_axis_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]), .s_axis_rx_tuser(s_axis_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]),
.rx_status(rx_status[n +: 1]) .rx_enable(rx_enable[n +: 1]),
.rx_status(rx_status[n +: 1]),
.rx_lfc_en(rx_lfc_en[n +: 1]),
.rx_lfc_req(rx_lfc_req[n +: 1]),
.rx_lfc_ack(rx_lfc_ack[n +: 1]),
.rx_pfc_en(rx_pfc_en[n*8 +: 8]),
.rx_pfc_req(rx_pfc_req[n*8 +: 8]),
.rx_pfc_ack(rx_pfc_ack[n*8 +: 8]),
.rx_fc_quanta_clk_en(rx_fc_quanta_clk_en[n +: 1])
); );
end end

182
fpga/common/rtl/mqnic_l2_egress.v
View File

@ -14,11 +14,14 @@
*/ */
module mqnic_l2_egress # module mqnic_l2_egress #
( (
// Width of AXI stream interfaces in bits // Interface configuration
parameter PFC_ENABLE = 0,
parameter LFC_ENABLE = PFC_ENABLE,
parameter MAC_CTRL_ENABLE = 0,
// Streaming interface configuration
parameter AXIS_DATA_WIDTH = 256, parameter AXIS_DATA_WIDTH = 256,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
// AXI stream tuser signal width
parameter AXIS_USER_WIDTH = 1 parameter AXIS_USER_WIDTH = 1
) )
( (
@ -43,16 +46,173 @@ module mqnic_l2_egress #
output wire m_axis_tvalid, output wire m_axis_tvalid,
input wire m_axis_tready, input wire m_axis_tready,
output wire m_axis_tlast, output wire m_axis_tlast,
output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser,
/*
* Flow control
*/
input wire tx_lfc_en,
input wire tx_lfc_req,
input wire [7:0] tx_pfc_en,
input wire [7:0] tx_pfc_req,
input wire tx_pause_req,
output wire tx_pause_ack,
input wire [9:0] tx_fc_quanta_step,
input wire tx_fc_quanta_clk_en
); );
// placeholder if ((LFC_ENABLE || PFC_ENABLE) && MAC_CTRL_ENABLE) begin : mac_ctrl
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep; localparam MCF_PARAMS_SIZE = PFC_ENABLE ? 18 : 2;
assign m_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_tready; wire tx_mcf_valid;
assign m_axis_tlast = s_axis_tlast; wire tx_mcf_ready;
assign m_axis_tuser = s_axis_tuser; wire [47:0] tx_mcf_eth_dst;
wire [47:0] tx_mcf_eth_src;
wire [15:0] tx_mcf_eth_type;
wire [15:0] tx_mcf_opcode;
wire [MCF_PARAMS_SIZE*8-1:0] tx_mcf_params;
mac_ctrl_tx #(
.DATA_WIDTH(AXIS_DATA_WIDTH),
.KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_USER_WIDTH),
.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE)
)
mac_ctrl_tx_inst (
.clk(clk),
.rst(rst),
/*
* AXI stream input
*/
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_tuser),
/*
* AXI stream output
*/
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(m_axis_tuser),
/*
* MAC control frame interface
*/
.mcf_valid(tx_mcf_valid),
.mcf_ready(tx_mcf_ready),
.mcf_eth_dst(tx_mcf_eth_dst),
.mcf_eth_src(tx_mcf_eth_src),
.mcf_eth_type(tx_mcf_eth_type),
.mcf_opcode(tx_mcf_opcode),
.mcf_params(tx_mcf_params),
.mcf_id(0),
.mcf_dest(0),
.mcf_user(0),
/*
* Pause interface
*/
.tx_pause_req(tx_pause_req),
.tx_pause_ack(tx_pause_ack),
/*
* Status
*/
.stat_tx_mcf()
);
mac_pause_ctrl_tx #(
.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE),
.PFC_ENABLE(PFC_ENABLE)
)
mac_pause_ctrl_tx_inst (
.clk(clk),
.rst(rst),
/*
* MAC control frame interface
*/
.mcf_valid(tx_mcf_valid),
.mcf_ready(tx_mcf_ready),
.mcf_eth_dst(tx_mcf_eth_dst),
.mcf_eth_src(tx_mcf_eth_src),
.mcf_eth_type(tx_mcf_eth_type),
.mcf_opcode(tx_mcf_opcode),
.mcf_params(tx_mcf_params),
/*
* Pause (IEEE 802.3 annex 31B)
*/
.tx_lfc_req(tx_lfc_req),
.tx_lfc_resend(1'b0),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D)
*/
.tx_pfc_req(tx_pfc_req),
.tx_pfc_resend(1'b0),
/*
* Configuration
*/
.cfg_tx_lfc_eth_dst(48'h01_80_C2_00_00_01),
.cfg_tx_lfc_eth_src(48'h80_23_31_43_54_4C),
.cfg_tx_lfc_eth_type(16'h8808),
.cfg_tx_lfc_opcode(16'h0001),
.cfg_tx_lfc_en(tx_lfc_en),
.cfg_tx_lfc_quanta(16'hffff),
.cfg_tx_lfc_refresh(16'h7fff),
.cfg_tx_pfc_eth_dst(48'h01_80_C2_00_00_01),
.cfg_tx_pfc_eth_src(48'h80_23_31_43_54_4C),
.cfg_tx_pfc_eth_type(16'h8808),
.cfg_tx_pfc_opcode(16'h0101),
.cfg_tx_pfc_en(tx_pfc_en),
.cfg_tx_pfc_quanta({8{16'hffff}}),
.cfg_tx_pfc_refresh({8{16'h7fff}}),
.cfg_quanta_step(tx_fc_quanta_step),
.cfg_quanta_clk_en(tx_fc_quanta_clk_en),
/*
* Status
*/
.stat_tx_lfc_pkt(),
.stat_tx_lfc_xon(),
.stat_tx_lfc_xoff(),
.stat_tx_lfc_paused(),
.stat_tx_pfc_pkt(),
.stat_tx_pfc_xon(),
.stat_tx_pfc_xoff(),
.stat_tx_pfc_paused()
);
end else begin
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_tready;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tuser = s_axis_tuser;
assign tx_pause_ack = 1'b0;
end
endmodule endmodule

211
fpga/common/rtl/mqnic_l2_ingress.v
View File

@ -14,47 +14,208 @@
*/ */
module mqnic_l2_ingress # module mqnic_l2_ingress #
( (
// Width of AXI stream interfaces in bits // Interface configuration
parameter PFC_ENABLE = 0,
parameter LFC_ENABLE = PFC_ENABLE,
parameter MAC_CTRL_ENABLE = 0,
// Streaming interface configuration
parameter AXIS_DATA_WIDTH = 256, parameter AXIS_DATA_WIDTH = 256,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
// AXI stream tuser signal width
parameter AXIS_USER_WIDTH = 1, parameter AXIS_USER_WIDTH = 1,
// Can apply backpressure with tready
parameter AXIS_USE_READY = 0 parameter AXIS_USE_READY = 0
) )
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* Receive data input * Receive data input
*/ */
input wire [AXIS_DATA_WIDTH-1:0] s_axis_tdata, input wire [AXIS_DATA_WIDTH-1:0] s_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_tkeep, input wire [AXIS_KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid, input wire s_axis_tvalid,
output wire s_axis_tready, output wire s_axis_tready,
input wire s_axis_tlast, input wire s_axis_tlast,
input wire [AXIS_USER_WIDTH-1:0] s_axis_tuser, input wire [AXIS_USER_WIDTH-1:0] s_axis_tuser,
/* /*
* Receive data output * Receive data output
*/ */
output wire [AXIS_DATA_WIDTH-1:0] m_axis_tdata, output wire [AXIS_DATA_WIDTH-1:0] m_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep, output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid, output wire m_axis_tvalid,
input wire m_axis_tready, input wire m_axis_tready,
output wire m_axis_tlast, output wire m_axis_tlast,
output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser,
/*
* Flow control
*/
input wire rx_lfc_en,
output wire rx_lfc_req,
input wire rx_lfc_ack,
input wire [7:0] rx_pfc_en,
output wire [7:0] rx_pfc_req,
input wire [7:0] rx_pfc_ack,
input wire [9:0] rx_fc_quanta_step,
input wire rx_fc_quanta_clk_en
); );
// placeholder if ((LFC_ENABLE || PFC_ENABLE) && MAC_CTRL_ENABLE) begin : mac_ctrl
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep; localparam MCF_PARAMS_SIZE = PFC_ENABLE ? 18 : 2;
assign m_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_tready; wire rx_mcf_valid;
assign m_axis_tlast = s_axis_tlast; wire [47:0] rx_mcf_eth_dst;
assign m_axis_tuser = s_axis_tuser; wire [47:0] rx_mcf_eth_src;
wire [15:0] rx_mcf_eth_type;
wire [15:0] rx_mcf_opcode;
wire [MCF_PARAMS_SIZE*8-1:0] rx_mcf_params;
mac_ctrl_rx #(
.DATA_WIDTH(AXIS_DATA_WIDTH),
.KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_USER_WIDTH),
.USE_READY(AXIS_USE_READY),
.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE)
)
mac_ctrl_rx_inst (
.clk(clk),
.rst(rst),
/*
* AXI stream input
*/
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_tuser),
/*
* AXI stream output
*/
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(m_axis_tuser),
/*
* MAC control frame interface
*/
.mcf_valid(rx_mcf_valid),
.mcf_eth_dst(rx_mcf_eth_dst),
.mcf_eth_src(rx_mcf_eth_src),
.mcf_eth_type(rx_mcf_eth_type),
.mcf_opcode(rx_mcf_opcode),
.mcf_params(rx_mcf_params),
.mcf_id(),
.mcf_dest(),
.mcf_user(),
/*
* Configuration
*/
.cfg_mcf_rx_eth_dst_mcast(48'h01_80_C2_00_00_01),
.cfg_mcf_rx_check_eth_dst_mcast(1'b1),
.cfg_mcf_rx_eth_dst_ucast(48'd0),
.cfg_mcf_rx_check_eth_dst_ucast(1'b0),
.cfg_mcf_rx_eth_src(48'd0),
.cfg_mcf_rx_check_eth_src(1'b0),
.cfg_mcf_rx_eth_type(16'h8808),
.cfg_mcf_rx_opcode_lfc(16'h0001),
.cfg_mcf_rx_check_opcode_lfc(rx_lfc_en),
.cfg_mcf_rx_opcode_pfc(16'h0101),
.cfg_mcf_rx_check_opcode_pfc(rx_pfc_en != 0),
.cfg_mcf_rx_forward(1'b0),
.cfg_mcf_rx_enable(rx_lfc_en || rx_pfc_en),
/*
* Status
*/
.stat_rx_mcf()
);
mac_pause_ctrl_rx #(
.MCF_PARAMS_SIZE(18),
.PFC_ENABLE(PFC_ENABLE)
)
mac_pause_ctrl_rx_inst (
.clk(clk),
.rst(rst),
/*
* MAC control frame interface
*/
.mcf_valid(rx_mcf_valid),
.mcf_eth_dst(rx_mcf_eth_dst),
.mcf_eth_src(rx_mcf_eth_src),
.mcf_eth_type(rx_mcf_eth_type),
.mcf_opcode(rx_mcf_opcode),
.mcf_params(rx_mcf_params),
/*
* Pause (IEEE 802.3 annex 31B)
*/
.rx_lfc_en(rx_lfc_en),
.rx_lfc_req(rx_lfc_req),
.rx_lfc_ack(rx_lfc_ack),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D)
*/
.rx_pfc_en(rx_pfc_en),
.rx_pfc_req(rx_pfc_req),
.rx_pfc_ack(rx_pfc_ack),
/*
* Configuration
*/
.cfg_rx_lfc_opcode(16'h0001),
.cfg_rx_lfc_en(rx_lfc_en),
.cfg_rx_pfc_opcode(16'h0101),
.cfg_rx_pfc_en(rx_pfc_en),
.cfg_quanta_step(rx_fc_quanta_step),
.cfg_quanta_clk_en(rx_fc_quanta_clk_en),
/*
* Status
*/
.stat_rx_lfc_pkt(),
.stat_rx_lfc_xon(),
.stat_rx_lfc_xoff(),
.stat_rx_lfc_paused(),
.stat_rx_pfc_pkt(),
.stat_rx_pfc_xon(),
.stat_rx_pfc_xoff(),
.stat_rx_pfc_paused()
);
end else begin
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_tready;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tuser = s_axis_tuser;
assign rx_lfc_req = 1'b0;
assign rx_pfc_req = 8'd0;
end
endmodule endmodule

283
fpga/common/rtl/mqnic_port.v
View File

@ -22,6 +22,9 @@ module mqnic_port #
parameter TX_CPL_ENABLE = 1, parameter TX_CPL_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16, parameter TX_TAG_WIDTH = 16,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter MAC_CTRL_ENABLE = 0,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214, parameter MAX_RX_SIZE = 9214,
@ -196,7 +199,13 @@ module mqnic_port #
input wire s_axis_tx_cpl_valid, input wire s_axis_tx_cpl_valid,
output wire s_axis_tx_cpl_ready, output wire s_axis_tx_cpl_ready,
output wire tx_enable,
input wire tx_status, input wire tx_status,
output wire tx_lfc_en,
output wire tx_lfc_req,
output wire [7:0] tx_pfc_en,
output wire [7:0] tx_pfc_req,
input wire tx_fc_quanta_clk_en,
/* /*
* Receive data input * Receive data input
@ -211,7 +220,15 @@ module mqnic_port #
input wire s_axis_rx_tlast, input wire s_axis_rx_tlast,
input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser, input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
input wire rx_status output wire rx_enable,
input wire rx_status,
output wire rx_lfc_en,
input wire rx_lfc_req,
output wire rx_lfc_ack,
output wire [7:0] rx_pfc_en,
input wire [7:0] rx_pfc_req,
output wire [7:0] rx_pfc_ack,
input wire rx_fc_quanta_clk_en
); );
localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}}; localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}};
@ -239,6 +256,52 @@ initial begin
end end
end end
wire rx_lfc_req_int;
wire [7:0] rx_pfc_req_int;
// TX control
reg tx_enable_reg = 1'b0;
reg tx_pause_reg = 1'b0;
reg tx_lfc_en_reg = 1'b0;
reg tx_lfc_req_reg = 1'b0;
reg [7:0] tx_pfc_en_reg = 8'd0;
reg [7:0] tx_pfc_req_reg = 8'd0;
reg [9:0] tx_fc_quanta_step_reg = (AXIS_DATA_WIDTH*256)/512;
reg tx_enable_sync_1_reg = 1'b0;
reg tx_enable_sync_2_reg = 1'b0;
reg tx_lfc_en_sync_1_reg = 1'b0;
reg tx_lfc_en_sync_2_reg = 1'b0;
reg tx_lfc_req_sync_1_reg = 1'b0;
reg tx_lfc_req_sync_2_reg = 1'b0;
reg [7:0] tx_pfc_en_sync_1_reg = 8'd0;
reg [7:0] tx_pfc_en_sync_2_reg = 8'd0;
reg [7:0] tx_pfc_req_sync_1_reg = 8'd0;
reg [7:0] tx_pfc_req_sync_2_reg = 8'd0;
reg [9:0] tx_fc_quanta_step_sync_1_reg = 10'd0;
reg [9:0] tx_fc_quanta_step_sync_2_reg = 10'd0;
assign tx_enable = tx_enable_sync_2_reg;
assign tx_lfc_en = LFC_ENABLE ? tx_lfc_en_sync_2_reg : 1'b0;
assign tx_lfc_req = LFC_ENABLE ? tx_lfc_req_sync_2_reg : 1'b0;
assign tx_pfc_en = PFC_ENABLE ? tx_pfc_en_sync_2_reg : 8'd0;
assign tx_pfc_req = PFC_ENABLE ? tx_pfc_req_sync_2_reg : 8'd0;
always @(posedge tx_clk) begin
tx_enable_sync_1_reg <= tx_enable_reg;
tx_enable_sync_2_reg <= tx_enable_sync_1_reg;
tx_lfc_en_sync_1_reg <= tx_lfc_en_reg;
tx_lfc_en_sync_2_reg <= tx_lfc_en_sync_1_reg;
tx_lfc_req_sync_1_reg <= tx_lfc_req_reg;
tx_lfc_req_sync_2_reg <= tx_lfc_req_sync_1_reg;
tx_pfc_en_sync_1_reg <= tx_pfc_en_reg;
tx_pfc_en_sync_2_reg <= tx_pfc_en_sync_1_reg;
tx_pfc_req_sync_1_reg <= tx_pfc_req_reg;
tx_pfc_req_sync_2_reg <= tx_pfc_req_sync_1_reg;
tx_fc_quanta_step_sync_1_reg <= tx_fc_quanta_step_reg;
tx_fc_quanta_step_sync_2_reg <= tx_fc_quanta_step_sync_1_reg;
end
// TX status // TX status
reg tx_rst_sync_1_reg = 1'b0; reg tx_rst_sync_1_reg = 1'b0;
reg tx_rst_sync_2_reg = 1'b0; reg tx_rst_sync_2_reg = 1'b0;
@ -264,6 +327,49 @@ always @(posedge clk) begin
tx_status_sync_3_reg <= tx_status_sync_2_reg; tx_status_sync_3_reg <= tx_status_sync_2_reg;
end end
// RX control
reg rx_enable_reg = 1'b0;
reg rx_pause_reg = 1'b0;
reg rx_lfc_en_reg = 1'b0;
reg rx_lfc_ack_reg = 1'b0;
reg [7:0] rx_pfc_en_reg = 8'd0;
reg [7:0] rx_pfc_ack_reg = 8'd0;
reg [9:0] rx_fc_quanta_step_reg = (AXIS_DATA_WIDTH*256)/512;
reg rx_enable_sync_1_reg = 1'b0;
reg rx_enable_sync_2_reg = 1'b0;
reg rx_lfc_en_sync_1_reg = 1'b0;
reg rx_lfc_en_sync_2_reg = 1'b0;
reg rx_lfc_ack_sync_1_reg = 1'b0;
reg rx_lfc_ack_sync_2_reg = 1'b0;
reg [7:0] rx_pfc_en_sync_1_reg = 8'd0;
reg [7:0] rx_pfc_en_sync_2_reg = 8'd0;
reg [7:0] rx_pfc_ack_sync_1_reg = 8'd0;
reg [7:0] rx_pfc_ack_sync_2_reg = 8'd0;
reg [9:0] rx_fc_quanta_step_sync_1_reg = 10'd0;
reg [9:0] rx_fc_quanta_step_sync_2_reg = 10'd0;
assign rx_enable = rx_enable_sync_2_reg;
assign rx_lfc_en = LFC_ENABLE ? rx_lfc_en_sync_2_reg : 1'b0;
assign rx_lfc_ack = LFC_ENABLE ? rx_lfc_ack_sync_2_reg : 1'b0;
assign rx_pfc_en = PFC_ENABLE ? rx_pfc_en_sync_2_reg : 8'd0;
assign rx_pfc_ack = PFC_ENABLE ? rx_pfc_ack_sync_2_reg : 8'd0;
always @(posedge rx_clk) begin
rx_enable_sync_1_reg <= rx_enable_reg;
rx_enable_sync_2_reg <= rx_enable_sync_1_reg;
rx_lfc_en_sync_1_reg <= rx_lfc_en_reg;
rx_lfc_en_sync_2_reg <= rx_lfc_en_sync_1_reg;
rx_lfc_ack_sync_1_reg <= rx_lfc_ack_reg;
rx_lfc_ack_sync_2_reg <= rx_lfc_ack_sync_1_reg;
rx_pfc_en_sync_1_reg <= rx_pfc_en_reg;
rx_pfc_en_sync_2_reg <= rx_pfc_en_sync_1_reg;
rx_pfc_ack_sync_1_reg <= rx_pfc_ack_reg;
rx_pfc_ack_sync_2_reg <= rx_pfc_ack_sync_1_reg;
rx_fc_quanta_step_sync_1_reg <= rx_fc_quanta_step_reg;
rx_fc_quanta_step_sync_2_reg <= rx_fc_quanta_step_sync_1_reg;
end
// RX status // RX status
reg rx_rst_sync_1_reg = 1'b0; reg rx_rst_sync_1_reg = 1'b0;
reg rx_rst_sync_2_reg = 1'b0; reg rx_rst_sync_2_reg = 1'b0;
@ -271,14 +377,24 @@ reg rx_rst_sync_3_reg = 1'b0;
reg rx_status_sync_1_reg = 1'b0; reg rx_status_sync_1_reg = 1'b0;
reg rx_status_sync_2_reg = 1'b0; reg rx_status_sync_2_reg = 1'b0;
reg rx_status_sync_3_reg = 1'b0; reg rx_status_sync_3_reg = 1'b0;
reg rx_lfc_req_sync_1_reg = 1'b0;
reg rx_lfc_req_sync_2_reg = 1'b0;
reg rx_lfc_req_sync_3_reg = 1'b0;
reg [7:0] rx_pfc_req_sync_1_reg = 8'd0;
reg [7:0] rx_pfc_req_sync_2_reg = 8'd0;
reg [7:0] rx_pfc_req_sync_3_reg = 8'd0;
always @(posedge rx_clk or posedge rx_rst) begin always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin if (rx_rst) begin
rx_rst_sync_1_reg <= 1'b1; rx_rst_sync_1_reg <= 1'b1;
rx_status_sync_1_reg <= 1'b0; rx_status_sync_1_reg <= 1'b0;
rx_lfc_req_sync_1_reg <= 1'b0;
rx_pfc_req_sync_1_reg <= 8'd0;
end else begin end else begin
rx_rst_sync_1_reg <= 1'b0; rx_rst_sync_1_reg <= 1'b0;
rx_status_sync_1_reg <= rx_status; rx_status_sync_1_reg <= rx_status;
rx_lfc_req_sync_1_reg <= MAC_CTRL_ENABLE ? rx_lfc_req_int : rx_lfc_req;
rx_pfc_req_sync_1_reg <= MAC_CTRL_ENABLE ? rx_pfc_req_int : rx_pfc_req;
end end
end end
@ -287,6 +403,10 @@ always @(posedge clk) begin
rx_rst_sync_3_reg <= rx_rst_sync_2_reg; rx_rst_sync_3_reg <= rx_rst_sync_2_reg;
rx_status_sync_2_reg <= rx_status_sync_1_reg; rx_status_sync_2_reg <= rx_status_sync_1_reg;
rx_status_sync_3_reg <= rx_status_sync_2_reg; rx_status_sync_3_reg <= rx_status_sync_2_reg;
rx_lfc_req_sync_2_reg <= rx_lfc_req_sync_1_reg;
rx_lfc_req_sync_3_reg <= rx_lfc_req_sync_2_reg;
rx_pfc_req_sync_2_reg <= rx_pfc_req_sync_1_reg;
rx_pfc_req_sync_3_reg <= rx_pfc_req_sync_2_reg;
end end
// control registers // control registers
@ -294,24 +414,76 @@ reg ctrl_reg_wr_ack_reg = 1'b0;
reg [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {REG_DATA_WIDTH{1'b0}}; reg [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {REG_DATA_WIDTH{1'b0}};
reg ctrl_reg_rd_ack_reg = 1'b0; reg ctrl_reg_rd_ack_reg = 1'b0;
wire tx_pause_status;
wire rx_pause_status;
wire tx_fifo_pause_req = !tx_enable_reg || tx_pause_reg || (LFC_ENABLE && rx_lfc_en_reg && rx_lfc_req_sync_3_reg);
wire tx_fifo_pause_ack;
wire rx_fifo_pause_req = !rx_enable_reg || rx_pause_reg;
wire rx_fifo_pause_ack;
assign ctrl_reg_wr_wait = 1'b0; assign ctrl_reg_wr_wait = 1'b0;
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg; assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg;
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg; assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg;
assign ctrl_reg_rd_wait = 1'b0; assign ctrl_reg_rd_wait = 1'b0;
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg; assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg;
integer i;
always @(posedge clk) begin always @(posedge clk) begin
ctrl_reg_wr_ack_reg <= 1'b0; ctrl_reg_wr_ack_reg <= 1'b0;
ctrl_reg_rd_data_reg <= {REG_DATA_WIDTH{1'b0}}; ctrl_reg_rd_data_reg <= {REG_DATA_WIDTH{1'b0}};
ctrl_reg_rd_ack_reg <= 1'b0; ctrl_reg_rd_ack_reg <= 1'b0;
tx_lfc_req_reg <= 1'b0;
tx_pfc_req_reg <= 8'd0;
rx_lfc_ack_reg <= tx_fifo_pause_ack;
rx_pfc_ack_reg <= 8'd0;
if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin
// write operation // write operation
ctrl_reg_wr_ack_reg <= 1'b1; ctrl_reg_wr_ack_reg <= 1'b1;
case ({ctrl_reg_wr_addr >> 2, 2'b00}) case ({ctrl_reg_wr_addr >> 2, 2'b00})
// Port control // Port control
RBB+8'h20: begin
// Port ctrl: TX control/status
tx_enable_reg <= ctrl_reg_wr_data[0];
tx_pause_reg <= ctrl_reg_wr_data[8];
end
RBB+8'h24: begin
// Port ctrl: RX control/status
rx_enable_reg <= ctrl_reg_wr_data[0];
rx_pause_reg <= ctrl_reg_wr_data[8];
end
default: ctrl_reg_wr_ack_reg <= 1'b0; default: ctrl_reg_wr_ack_reg <= 1'b0;
endcase endcase
if (MAC_CTRL_ENABLE) begin
if ({ctrl_reg_wr_addr >> 2, 2'b00} == RBB+8'h28) begin
// Port ctrl: FC control
tx_fc_quanta_step_reg <= ctrl_reg_wr_data[15:0];
rx_fc_quanta_step_reg <= ctrl_reg_wr_data[31:16];
ctrl_reg_wr_ack_reg <= 1'b1;
end
end
if (LFC_ENABLE) begin
if ({ctrl_reg_wr_addr >> 2, 2'b00} == RBB+8'h2C) begin
// Port ctrl: LFC control
tx_lfc_en_reg <= ctrl_reg_wr_data[24];
rx_lfc_en_reg <= ctrl_reg_wr_data[25];
ctrl_reg_wr_ack_reg <= 1'b1;
end
end
if (PFC_ENABLE) begin
for (i = 0; i < 8; i = i + 1) begin
if ({ctrl_reg_wr_addr >> 2, 2'b00} == RBB+8'h30+i*4) begin
// Port ctrl: PFC control N
tx_pfc_en_reg[i] <= ctrl_reg_wr_data[24];
rx_pfc_en_reg[i] <= ctrl_reg_wr_data[25];
ctrl_reg_wr_ack_reg <= 1'b1;
end
end
end
end end
if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin
@ -325,28 +497,85 @@ always @(posedge clk) begin
RBB+8'h0C: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // Port: Offset RBB+8'h0C: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // Port: Offset
// Port control // Port control
RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C003; // Port ctrl: Type RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C003; // Port ctrl: Type
RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000200; // Port ctrl: Version RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000300; // Port ctrl: Version
RBB+8'h18: ctrl_reg_rd_data_reg <= 0; // Port ctrl: Next header RBB+8'h18: ctrl_reg_rd_data_reg <= 0; // Port ctrl: Next header
RBB+8'h1C: begin RBB+8'h1C: begin
// Port ctrl: features // Port ctrl: features
ctrl_reg_rd_data_reg[0] <= LFC_ENABLE;
ctrl_reg_rd_data_reg[1] <= PFC_ENABLE;
ctrl_reg_rd_data_reg[2] <= MAC_CTRL_ENABLE;
end end
RBB+8'h20: begin RBB+8'h20: begin
// Port ctrl: TX status // Port ctrl: TX control/status
ctrl_reg_rd_data_reg[0] <= tx_status_sync_3_reg; ctrl_reg_rd_data_reg[0] <= tx_enable_reg;
ctrl_reg_rd_data_reg[1] <= tx_rst_sync_3_reg; ctrl_reg_rd_data_reg[8] <= tx_pause_reg;
ctrl_reg_rd_data_reg[16] <= tx_status_sync_3_reg;
ctrl_reg_rd_data_reg[17] <= tx_rst_sync_3_reg;
ctrl_reg_rd_data_reg[24] <= tx_fifo_pause_req;
ctrl_reg_rd_data_reg[25] <= tx_fifo_pause_ack;
end end
RBB+8'h24: begin RBB+8'h24: begin
// Port ctrl: RX status // Port ctrl: RX control/status
ctrl_reg_rd_data_reg[0] <= rx_status_sync_3_reg; ctrl_reg_rd_data_reg[0] <= rx_enable_reg;
ctrl_reg_rd_data_reg[1] <= rx_rst_sync_3_reg; ctrl_reg_rd_data_reg[8] <= rx_pause_reg;
ctrl_reg_rd_data_reg[16] <= rx_status_sync_3_reg;
ctrl_reg_rd_data_reg[17] <= rx_rst_sync_3_reg;
ctrl_reg_rd_data_reg[24] <= rx_fifo_pause_req;
ctrl_reg_rd_data_reg[25] <= rx_fifo_pause_ack;
end end
default: ctrl_reg_rd_ack_reg <= 1'b0; default: ctrl_reg_rd_ack_reg <= 1'b0;
endcase endcase
if (MAC_CTRL_ENABLE) begin
if ({ctrl_reg_rd_addr >> 2, 2'b00} == RBB+8'h28) begin
// Port ctrl: FC control
ctrl_reg_rd_data_reg[15:0] <= tx_fc_quanta_step_reg;
ctrl_reg_rd_data_reg[31:16] <= rx_fc_quanta_step_reg;
ctrl_reg_rd_ack_reg <= 1'b1;
end
end
if (LFC_ENABLE) begin
if ({ctrl_reg_rd_addr >> 2, 2'b00} == RBB+8'h2C) begin
// Port ctrl: LFC control
ctrl_reg_rd_data_reg[24] <= tx_lfc_en_reg;
ctrl_reg_rd_data_reg[25] <= rx_lfc_en_reg;
ctrl_reg_rd_data_reg[28] <= tx_lfc_req_reg;
ctrl_reg_rd_data_reg[29] <= rx_lfc_req_sync_3_reg;
ctrl_reg_rd_ack_reg <= 1'b1;
end
end
if (PFC_ENABLE) begin
for (i = 0; i < 8; i = i + 1) begin
if ({ctrl_reg_rd_addr >> 2, 2'b00} == RBB+8'h30+i*4) begin
// Port ctrl: PFC control N
ctrl_reg_rd_data_reg[24] <= tx_pfc_en_reg[i];
ctrl_reg_rd_data_reg[25] <= rx_pfc_en_reg[i];
ctrl_reg_rd_data_reg[28] <= tx_pfc_req_reg[i];
ctrl_reg_rd_data_reg[29] <= rx_pfc_req_sync_3_reg[i];
ctrl_reg_rd_ack_reg <= 1'b1;
end
end
end
end end
if (rst) begin if (rst) begin
ctrl_reg_wr_ack_reg <= 1'b0; ctrl_reg_wr_ack_reg <= 1'b0;
ctrl_reg_rd_ack_reg <= 1'b0; ctrl_reg_rd_ack_reg <= 1'b0;
tx_enable_reg <= 1'b0;
tx_pause_reg <= 1'b0;
tx_lfc_en_reg <= 1'b0;
tx_lfc_req_reg <= 1'b0;
tx_pfc_en_reg <= 8'd0;
tx_pfc_req_reg <= 8'd0;
tx_fc_quanta_step_reg <= (AXIS_DATA_WIDTH*256)/512;
rx_enable_reg <= 1'b0;
rx_pause_reg <= 1'b0;
rx_lfc_en_reg <= 1'b0;
rx_lfc_ack_reg <= 1'b0;
rx_pfc_en_reg <= 8'd0;
rx_pfc_ack_reg <= 8'd0;
rx_fc_quanta_step_reg <= (AXIS_DATA_WIDTH*256)/512;
end end
end end
@ -359,6 +588,9 @@ mqnic_port_tx #(
.TX_CPL_ENABLE(TX_CPL_ENABLE), .TX_CPL_ENABLE(TX_CPL_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_TAG_WIDTH(TX_TAG_WIDTH),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(MAC_CTRL_ENABLE),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
// Application block configuration // Application block configuration
@ -465,7 +697,21 @@ port_tx_inst (
.s_axis_tx_cpl_ts(s_axis_tx_cpl_ts), .s_axis_tx_cpl_ts(s_axis_tx_cpl_ts),
.s_axis_tx_cpl_tag(s_axis_tx_cpl_tag), .s_axis_tx_cpl_tag(s_axis_tx_cpl_tag),
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid), .s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready) .s_axis_tx_cpl_ready(s_axis_tx_cpl_ready),
/*
* Flow control
*/
.tx_lfc_en(tx_lfc_en),
.tx_lfc_req(tx_lfc_req),
.tx_pfc_en(tx_pfc_en),
.tx_pfc_req(tx_pfc_req),
.tx_pause_req(1'b0),
.tx_pause_ack(),
.tx_fc_quanta_step(tx_fc_quanta_step_reg),
.tx_fc_quanta_clk_en(tx_fc_quanta_clk_en),
.fifo_pause_req(tx_fifo_pause_req),
.fifo_pause_ack(tx_fifo_pause_ack)
); );
mqnic_port_rx #( mqnic_port_rx #(
@ -474,6 +720,9 @@ mqnic_port_rx #(
// Interface configuration // Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE), .PTP_TS_ENABLE(PTP_TS_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(MAC_CTRL_ENABLE),
.MAX_RX_SIZE(MAX_RX_SIZE), .MAX_RX_SIZE(MAX_RX_SIZE),
// Application block configuration // Application block configuration
@ -550,7 +799,21 @@ port_rx_inst (
.s_axis_rx_tvalid(s_axis_rx_tvalid), .s_axis_rx_tvalid(s_axis_rx_tvalid),
.s_axis_rx_tready(s_axis_rx_tready), .s_axis_rx_tready(s_axis_rx_tready),
.s_axis_rx_tlast(s_axis_rx_tlast), .s_axis_rx_tlast(s_axis_rx_tlast),
.s_axis_rx_tuser(s_axis_rx_tuser) .s_axis_rx_tuser(s_axis_rx_tuser),
/*
* Flow control
*/
.rx_lfc_en(rx_lfc_en),
.rx_lfc_req(rx_lfc_req_int),
.rx_lfc_ack(rx_lfc_ack),
.rx_pfc_en(rx_pfc_en),
.rx_pfc_req(rx_pfc_req_int),
.rx_pfc_ack(rx_pfc_ack),
.rx_fc_quanta_step(rx_fc_quanta_step_reg),
.rx_fc_quanta_clk_en(rx_fc_quanta_clk_en),
.fifo_pause_req(rx_fifo_pause_req),
.fifo_pause_ack(rx_fifo_pause_ack)
); );
endmodule endmodule

50
fpga/common/rtl/mqnic_port_map_mac_axis.v
View File

@ -52,7 +52,12 @@ module mqnic_port_map_mac_axis #
input wire [MAC_COUNT-1:0] s_axis_mac_tx_ptp_ts_valid, input wire [MAC_COUNT-1:0] s_axis_mac_tx_ptp_ts_valid,
output wire [MAC_COUNT-1:0] s_axis_mac_tx_ptp_ts_ready, output wire [MAC_COUNT-1:0] s_axis_mac_tx_ptp_ts_ready,
output wire [MAC_COUNT-1:0] mac_tx_enable,
input wire [MAC_COUNT-1:0] mac_tx_status, input wire [MAC_COUNT-1:0] mac_tx_status,
output wire [MAC_COUNT-1:0] mac_tx_lfc_en,
output wire [MAC_COUNT-1:0] mac_tx_lfc_req,
output wire [MAC_COUNT*8-1:0] mac_tx_pfc_en,
output wire [MAC_COUNT*8-1:0] mac_tx_pfc_req,
input wire [MAC_COUNT-1:0] mac_rx_clk, input wire [MAC_COUNT-1:0] mac_rx_clk,
input wire [MAC_COUNT-1:0] mac_rx_rst, input wire [MAC_COUNT-1:0] mac_rx_rst,
@ -69,7 +74,14 @@ module mqnic_port_map_mac_axis #
input wire [MAC_COUNT-1:0] s_axis_mac_rx_tlast, input wire [MAC_COUNT-1:0] s_axis_mac_rx_tlast,
input wire [MAC_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_mac_rx_tuser, input wire [MAC_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_mac_rx_tuser,
output wire [MAC_COUNT-1:0] mac_rx_enable,
input wire [MAC_COUNT-1:0] mac_rx_status, input wire [MAC_COUNT-1:0] mac_rx_status,
output wire [MAC_COUNT-1:0] mac_rx_lfc_en,
input wire [MAC_COUNT-1:0] mac_rx_lfc_req,
output wire [MAC_COUNT-1:0] mac_rx_lfc_ack,
output wire [MAC_COUNT*8-1:0] mac_rx_pfc_en,
input wire [MAC_COUNT*8-1:0] mac_rx_pfc_req,
output wire [MAC_COUNT*8-1:0] mac_rx_pfc_ack,
// towards datapath // towards datapath
output wire [PORT_COUNT-1:0] tx_clk, output wire [PORT_COUNT-1:0] tx_clk,
@ -92,7 +104,12 @@ module mqnic_port_map_mac_axis #
output wire [PORT_COUNT-1:0] m_axis_tx_ptp_ts_valid, output wire [PORT_COUNT-1:0] m_axis_tx_ptp_ts_valid,
input wire [PORT_COUNT-1:0] m_axis_tx_ptp_ts_ready, input wire [PORT_COUNT-1:0] m_axis_tx_ptp_ts_ready,
input wire [PORT_COUNT-1:0] tx_enable,
output wire [PORT_COUNT-1:0] tx_status, output wire [PORT_COUNT-1:0] tx_status,
input wire [PORT_COUNT-1:0] tx_lfc_en,
input wire [PORT_COUNT-1:0] tx_lfc_req,
input wire [PORT_COUNT*8-1:0] tx_pfc_en,
input wire [PORT_COUNT*8-1:0] tx_pfc_req,
output wire [PORT_COUNT-1:0] rx_clk, output wire [PORT_COUNT-1:0] rx_clk,
output wire [PORT_COUNT-1:0] rx_rst, output wire [PORT_COUNT-1:0] rx_rst,
@ -109,7 +126,14 @@ module mqnic_port_map_mac_axis #
output wire [PORT_COUNT-1:0] m_axis_rx_tlast, output wire [PORT_COUNT-1:0] m_axis_rx_tlast,
output wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] m_axis_rx_tuser, output wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] m_axis_rx_tuser,
output wire [PORT_COUNT-1:0] rx_status input wire [PORT_COUNT-1:0] rx_enable,
output wire [PORT_COUNT-1:0] rx_status,
input wire [PORT_COUNT-1:0] rx_lfc_en,
output wire [PORT_COUNT-1:0] rx_lfc_req,
input wire [PORT_COUNT-1:0] rx_lfc_ack,
input wire [PORT_COUNT*8-1:0] rx_pfc_en,
output wire [PORT_COUNT*8-1:0] rx_pfc_req,
input wire [PORT_COUNT*8-1:0] rx_pfc_ack
); );
initial begin initial begin
@ -205,7 +229,12 @@ generate
assign mac_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = tx_ptp_ts_96[IND[n*8 +: 8]*PTP_TS_WIDTH +: PTP_TS_WIDTH]; assign mac_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = tx_ptp_ts_96[IND[n*8 +: 8]*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign mac_tx_ptp_ts_step[n] = tx_ptp_ts_step[IND[n*8 +: 8]]; assign mac_tx_ptp_ts_step[n] = tx_ptp_ts_step[IND[n*8 +: 8]];
assign mac_tx_enable[n] = tx_enable[IND[n*8 +: 8]];
assign tx_status[IND[n*8 +: 8]] = mac_tx_status[n]; assign tx_status[IND[n*8 +: 8]] = mac_tx_status[n];
assign mac_tx_lfc_en[n] = tx_lfc_en[IND[n*8 +: 8]];
assign mac_tx_lfc_req[n] = tx_lfc_req[IND[n*8 +: 8]];
assign mac_tx_pfc_en[n*8 +: 8] = tx_pfc_en[IND[n*8 +: 8]*8 +: 8];
assign mac_tx_pfc_req[n*8 +: 8] = tx_pfc_req[IND[n*8 +: 8]*8 +: 8];
assign rx_clk[IND[n*8 +: 8]] = mac_rx_clk[n]; assign rx_clk[IND[n*8 +: 8]] = mac_rx_clk[n];
assign rx_rst[IND[n*8 +: 8]] = mac_rx_rst[n]; assign rx_rst[IND[n*8 +: 8]] = mac_rx_rst[n];
@ -223,7 +252,14 @@ generate
assign mac_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = rx_ptp_ts_96[IND[n*8 +: 8]*PTP_TS_WIDTH +: PTP_TS_WIDTH]; assign mac_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = rx_ptp_ts_96[IND[n*8 +: 8]*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign mac_rx_ptp_ts_step[n] = rx_ptp_ts_step[IND[n*8 +: 8]]; assign mac_rx_ptp_ts_step[n] = rx_ptp_ts_step[IND[n*8 +: 8]];
assign mac_rx_enable[n] = rx_enable[IND[n*8 +: 8]];
assign rx_status[IND[n*8 +: 8]] = mac_rx_status[n]; assign rx_status[IND[n*8 +: 8]] = mac_rx_status[n];
assign mac_rx_lfc_en[n] = rx_lfc_en[IND[n*8 +: 8]];
assign rx_lfc_req[IND[n*8 +: 8]] = mac_rx_lfc_req[n];
assign mac_rx_lfc_ack[n] = rx_lfc_ack[IND[n*8 +: 8]];
assign mac_rx_pfc_en[n*8 +: 8] = rx_pfc_en[IND[n*8 +: 8]*8 +: 8];
assign rx_pfc_req[IND[n*8 +: 8]*8 +: 8] = mac_rx_pfc_req[n*8 +: 8];
assign mac_rx_pfc_ack[n*8 +: 8] = rx_pfc_ack[IND[n*8 +: 8]*8 +: 8];
end else begin end else begin
assign m_axis_mac_tx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH] = {AXIS_DATA_WIDTH{1'b0}}; assign m_axis_mac_tx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH] = {AXIS_DATA_WIDTH{1'b0}};
assign m_axis_mac_tx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH] = {AXIS_KEEP_WIDTH{1'b0}}; assign m_axis_mac_tx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH] = {AXIS_KEEP_WIDTH{1'b0}};
@ -234,8 +270,20 @@ generate
assign mac_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = {PTP_TS_WIDTH{1'b0}}; assign mac_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = {PTP_TS_WIDTH{1'b0}};
assign mac_tx_ptp_ts_step[n] = 1'b0; assign mac_tx_ptp_ts_step[n] = 1'b0;
assign mac_tx_enable[n] = 1'b0;
assign mac_tx_lfc_en[n] = 1'b0;
assign mac_tx_lfc_req[n] = 1'b0;
assign mac_tx_pfc_en[n*8 +: 8] = 8'd0;
assign mac_tx_pfc_req[n*8 +: 8] = 8'd0;
assign mac_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = {PTP_TS_WIDTH{1'b0}}; assign mac_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = {PTP_TS_WIDTH{1'b0}};
assign mac_rx_ptp_ts_step[n] = 1'b0; assign mac_rx_ptp_ts_step[n] = 1'b0;
assign mac_rx_enable[n] = 1'b0;
assign mac_rx_lfc_en[n] = 1'b0;
assign mac_rx_lfc_ack[n] = 1'b0;
assign mac_rx_pfc_en[n*8 +: 8] = 8'd0;
assign mac_rx_pfc_ack[n*8 +: 8] = 8'd0;
end end
end end
endgenerate endgenerate

43
fpga/common/rtl/mqnic_port_rx.v
View File

@ -19,6 +19,9 @@ module mqnic_port_rx #
// Interface configuration // Interface configuration
parameter PTP_TS_ENABLE = 1, parameter PTP_TS_ENABLE = 1,
parameter PFC_ENABLE = 0,
parameter LFC_ENABLE = PFC_ENABLE,
parameter MAC_CTRL_ENABLE = 0,
parameter MAX_RX_SIZE = 9214, parameter MAX_RX_SIZE = 9214,
// Application block configuration // Application block configuration
@ -95,7 +98,21 @@ module mqnic_port_rx #
input wire s_axis_rx_tvalid, input wire s_axis_rx_tvalid,
output wire s_axis_rx_tready, output wire s_axis_rx_tready,
input wire s_axis_rx_tlast, input wire s_axis_rx_tlast,
input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
/*
* Flow control
*/
input wire rx_lfc_en,
output wire rx_lfc_req,
input wire rx_lfc_ack,
input wire [7:0] rx_pfc_en,
output wire [7:0] rx_pfc_req,
input wire [7:0] rx_pfc_ack,
input wire [9:0] rx_fc_quanta_step,
input wire rx_fc_quanta_clk_en,
input wire fifo_pause_req,
output wire fifo_pause_ack
); );
generate generate
@ -137,6 +154,12 @@ wire axis_if_rx_tlast;
wire [AXIS_RX_USER_WIDTH-1:0] axis_if_rx_tuser; wire [AXIS_RX_USER_WIDTH-1:0] axis_if_rx_tuser;
mqnic_l2_ingress #( mqnic_l2_ingress #(
// Interface configuration
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(MAC_CTRL_ENABLE),
// Streaming interface configuration
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_USER_WIDTH(AXIS_RX_USER_WIDTH), .AXIS_USER_WIDTH(AXIS_RX_USER_WIDTH),
@ -164,7 +187,19 @@ mqnic_l2_ingress_inst (
.m_axis_tvalid(axis_rx_l2_tvalid), .m_axis_tvalid(axis_rx_l2_tvalid),
.m_axis_tready(axis_rx_l2_tready), .m_axis_tready(axis_rx_l2_tready),
.m_axis_tlast(axis_rx_l2_tlast), .m_axis_tlast(axis_rx_l2_tlast),
.m_axis_tuser(axis_rx_l2_tuser) .m_axis_tuser(axis_rx_l2_tuser),
/*
* Flow control
*/
.rx_lfc_en(rx_lfc_en),
.rx_lfc_req(rx_lfc_req),
.rx_lfc_ack(rx_lfc_ack),
.rx_pfc_en(rx_pfc_en),
.rx_pfc_req(rx_pfc_req),
.rx_pfc_ack(rx_pfc_ack),
.rx_fc_quanta_step(rx_fc_quanta_step),
.rx_fc_quanta_clk_en(rx_fc_quanta_clk_en)
); );
if (APP_AXIS_DIRECT_ENABLE) begin if (APP_AXIS_DIRECT_ENABLE) begin
@ -253,8 +288,8 @@ rx_async_fifo_inst (
// Pause // Pause
.s_pause_req(1'b0), .s_pause_req(1'b0),
.s_pause_ack(), .s_pause_ack(),
.m_pause_req(1'b0), .m_pause_req(fifo_pause_req),
.m_pause_ack(), .m_pause_ack(fifo_pause_ack),
// Status // Status
.s_status_depth(), .s_status_depth(),

43
fpga/common/rtl/mqnic_port_tx.v
View File

@ -22,6 +22,9 @@ module mqnic_port_tx #
parameter TX_CPL_ENABLE = 1, parameter TX_CPL_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16, parameter TX_TAG_WIDTH = 16,
parameter PFC_ENABLE = 0,
parameter LFC_ENABLE = PFC_ENABLE,
parameter MAC_CTRL_ENABLE = 0,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
// Application block configuration // Application block configuration
@ -128,7 +131,21 @@ module mqnic_port_tx #
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_cpl_ts, input wire [PTP_TS_WIDTH-1:0] s_axis_tx_cpl_ts,
input wire [TX_TAG_WIDTH-1:0] s_axis_tx_cpl_tag, input wire [TX_TAG_WIDTH-1:0] s_axis_tx_cpl_tag,
input wire s_axis_tx_cpl_valid, input wire s_axis_tx_cpl_valid,
output wire s_axis_tx_cpl_ready output wire s_axis_tx_cpl_ready,
/*
* Flow control
*/
input wire tx_lfc_en,
input wire tx_lfc_req,
input wire [7:0] tx_pfc_en,
input wire [7:0] tx_pfc_req,
input wire tx_pause_req,
output wire tx_pause_ack,
input wire [9:0] tx_fc_quanta_step,
input wire tx_fc_quanta_clk_en,
input wire fifo_pause_req,
output wire fifo_pause_ack
); );
initial begin initial begin
@ -463,8 +480,8 @@ tx_async_fifo_inst (
.m_axis_tuser(axis_tx_out_tuser), .m_axis_tuser(axis_tx_out_tuser),
// Pause // Pause
.s_pause_req(1'b0), .s_pause_req(fifo_pause_req),
.s_pause_ack(), .s_pause_ack(fifo_pause_ack),
.m_pause_req(1'b0), .m_pause_req(1'b0),
.m_pause_ack(), .m_pause_ack(),
@ -517,6 +534,12 @@ end else begin
end end
mqnic_l2_egress #( mqnic_l2_egress #(
// Interface configuration
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(MAC_CTRL_ENABLE),
// Streaming interface configuration
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_USER_WIDTH(AXIS_TX_USER_WIDTH) .AXIS_USER_WIDTH(AXIS_TX_USER_WIDTH)
@ -543,7 +566,19 @@ mqnic_l2_egress_inst (
.m_axis_tvalid(m_axis_tx_tvalid), .m_axis_tvalid(m_axis_tx_tvalid),
.m_axis_tready(m_axis_tx_tready), .m_axis_tready(m_axis_tx_tready),
.m_axis_tlast(m_axis_tx_tlast), .m_axis_tlast(m_axis_tx_tlast),
.m_axis_tuser(m_axis_tx_tuser) .m_axis_tuser(m_axis_tx_tuser),
/*
* Flow control
*/
.tx_lfc_en(tx_lfc_en),
.tx_lfc_req(tx_lfc_req),
.tx_pfc_en(tx_pfc_en),
.tx_pfc_req(tx_pfc_req),
.tx_pause_req(tx_pause_req),
.tx_pause_ack(tx_pause_ack),
.tx_fc_quanta_step(tx_fc_quanta_step),
.tx_fc_quanta_clk_en(tx_fc_quanta_clk_en)
); );
endgenerate endgenerate

31
fpga/common/syn/vivado/mqnic_port.tcl
View File

@ -6,18 +6,35 @@
foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_port || REF_NAME == mqnic_port)}] { foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_port || REF_NAME == mqnic_port)}] {
puts "Inserting timing constraints for mqnic_port instance $inst" puts "Inserting timing constraints for mqnic_port instance $inst"
proc constrain_slow_sync {inst driver args} { proc constrain_sync_chain_async {inst driver args} {
set sync_ffs [get_cells -hier $args -filter "PARENT == $inst"] set sync_ffs [get_cells -hier [concat $driver $args] -filter "PARENT == $inst"]
if {[llength $sync_ffs]} { if {[llength $sync_ffs]} {
set_property ASYNC_REG TRUE $sync_ffs set_property ASYNC_REG TRUE $sync_ffs
set_false_path -from [get_cells "$inst/$driver"] -to [get_cells "$inst/[lindex $args 0]"] set_false_path -to [get_pins "$inst/$driver/D"]
} }
} }
constrain_slow_sync $inst "rx_rst_sync_1_reg_reg" "rx_rst_sync_2_reg_reg" "rx_rst_sync_3_reg_reg" constrain_sync_chain_async $inst "tx_enable_sync_1_reg_reg" "tx_enable_sync_2_reg_reg"
constrain_slow_sync $inst "rx_status_sync_1_reg_reg" "rx_status_sync_2_reg_reg" "rx_status_sync_3_reg_reg" constrain_sync_chain_async $inst "tx_lfc_en_sync_1_reg_reg" "tx_lfc_en_sync_2_reg_reg"
constrain_slow_sync $inst "tx_rst_sync_1_reg_reg" "tx_rst_sync_2_reg_reg" "tx_rst_sync_3_reg_reg" constrain_sync_chain_async $inst "tx_lfc_req_sync_1_reg_reg" "tx_lfc_req_sync_2_reg_reg"
constrain_slow_sync $inst "tx_status_sync_1_reg_reg" "tx_status_sync_2_reg_reg" "tx_status_sync_3_reg_reg" constrain_sync_chain_async $inst "tx_pfc_en_sync_1_reg_reg[*]" "tx_pfc_en_sync_2_reg_reg[*]"
constrain_sync_chain_async $inst "tx_pfc_req_sync_1_reg_reg[*]" "tx_pfc_req_sync_2_reg_reg[*]"
constrain_sync_chain_async $inst "tx_fc_quanta_step_sync_1_reg_reg[*]" "tx_fc_quanta_step_sync_2_reg_reg[*]"
constrain_sync_chain_async $inst "tx_rst_sync_2_reg_reg" "tx_rst_sync_3_reg_reg"
constrain_sync_chain_async $inst "tx_status_sync_2_reg_reg" "tx_status_sync_3_reg_reg"
constrain_sync_chain_async $inst "rx_enable_sync_1_reg_reg" "rx_enable_sync_2_reg_reg"
constrain_sync_chain_async $inst "rx_lfc_en_sync_1_reg_reg" "rx_lfc_en_sync_2_reg_reg"
constrain_sync_chain_async $inst "rx_lfc_ack_sync_1_reg_reg" "rx_lfc_ack_sync_2_reg_reg"
constrain_sync_chain_async $inst "rx_pfc_en_sync_1_reg_reg[*]" "rx_pfc_en_sync_2_reg_reg[*]"
constrain_sync_chain_async $inst "rx_pfc_ack_sync_1_reg_reg[*]" "rx_pfc_ack_sync_2_reg_reg[*]"
constrain_sync_chain_async $inst "rx_rst_sync_2_reg_reg" "rx_rst_sync_3_reg_reg"
constrain_sync_chain_async $inst "rx_status_sync_2_reg_reg" "rx_status_sync_3_reg_reg"
constrain_sync_chain_async $inst "rx_lfc_req_sync_2_reg_reg" "rx_lfc_req_sync_3_reg_reg"
constrain_sync_chain_async $inst "rx_pfc_req_sync_2_reg_reg[*]" "rx_pfc_req_sync_3_reg_reg[*]"
constrain_sync_chain_async $inst "rx_fc_quanta_step_sync_1_reg_reg[*]" "rx_fc_quanta_step_sync_2_reg_reg[*]"
} }

93
fpga/common/tb/mqnic.py
View File

@ -147,6 +147,8 @@ MQNIC_IF_FEATURE_PTP_TS = (1 << 4)
MQNIC_IF_FEATURE_TX_CSUM = (1 << 8) MQNIC_IF_FEATURE_TX_CSUM = (1 << 8)
MQNIC_IF_FEATURE_RX_CSUM = (1 << 9) MQNIC_IF_FEATURE_RX_CSUM = (1 << 9)
MQNIC_IF_FEATURE_RX_HASH = (1 << 10) MQNIC_IF_FEATURE_RX_HASH = (1 << 10)
MQNIC_IF_FEATURE_LFC = (1 << 11)
MQNIC_IF_FEATURE_PFC = (1 << 12)
MQNIC_RB_RX_QUEUE_MAP_TYPE = 0x0000C090 MQNIC_RB_RX_QUEUE_MAP_TYPE = 0x0000C090
MQNIC_RB_RX_QUEUE_MAP_VER = 0x00000200 MQNIC_RB_RX_QUEUE_MAP_VER = 0x00000200
@ -186,10 +188,47 @@ MQNIC_RB_PORT_VER = 0x00000200
MQNIC_RB_PORT_REG_OFFSET = 0x0C MQNIC_RB_PORT_REG_OFFSET = 0x0C
MQNIC_RB_PORT_CTRL_TYPE = 0x0000C003 MQNIC_RB_PORT_CTRL_TYPE = 0x0000C003
MQNIC_RB_PORT_CTRL_VER = 0x00000200 MQNIC_RB_PORT_CTRL_VER = 0x00000300
MQNIC_RB_PORT_CTRL_REG_FEATURES = 0x0C MQNIC_RB_PORT_CTRL_REG_FEATURES = 0x0C
MQNIC_RB_PORT_CTRL_REG_TX_STATUS = 0x10 MQNIC_RB_PORT_CTRL_REG_TX_CTRL = 0x10
MQNIC_RB_PORT_CTRL_REG_RX_STATUS = 0x14 MQNIC_RB_PORT_CTRL_REG_RX_CTRL = 0x14
MQNIC_RB_PORT_CTRL_REG_LFC_CTRL = 0x1C
MQNIC_RB_PORT_CTRL_REG_PFC_CTRL0 = 0x20
MQNIC_RB_PORT_CTRL_REG_PFC_CTRL1 = 0x24
MQNIC_RB_PORT_CTRL_REG_PFC_CTRL2 = 0x28
MQNIC_RB_PORT_CTRL_REG_PFC_CTRL3 = 0x2C
MQNIC_RB_PORT_CTRL_REG_PFC_CTRL4 = 0x30
MQNIC_RB_PORT_CTRL_REG_PFC_CTRL5 = 0x34
MQNIC_RB_PORT_CTRL_REG_PFC_CTRL6 = 0x38
MQNIC_RB_PORT_CTRL_REG_PFC_CTRL7 = 0x3C
MQNIC_PORT_FEATURE_LFC = (1 << 0)
MQNIC_PORT_FEATURE_PFC = (1 << 1)
MQNIC_PORT_FEATURE_INT_MAC_CTRL = (1 << 2)
MQNIC_PORT_TX_CTRL_EN = (1 << 0)
MQNIC_PORT_TX_CTRL_PAUSE = (1 << 8)
MQNIC_PORT_TX_CTRL_STATUS = (1 << 16)
MQNIC_PORT_TX_CTRL_RESET = (1 << 17)
MQNIC_PORT_TX_CTRL_PAUSE_REQ = (1 << 24)
MQNIC_PORT_TX_CTRL_PAUSE_ACK = (1 << 25)
MQNIC_PORT_RX_CTRL_EN = (1 << 0)
MQNIC_PORT_RX_CTRL_PAUSE = (1 << 8)
MQNIC_PORT_RX_CTRL_STATUS = (1 << 16)
MQNIC_PORT_RX_CTRL_RESET = (1 << 17)
MQNIC_PORT_RX_CTRL_PAUSE_REQ = (1 << 24)
MQNIC_PORT_RX_CTRL_PAUSE_ACK = (1 << 25)
MQNIC_PORT_LFC_CTRL_TX_LFC_EN = (1 << 24)
MQNIC_PORT_LFC_CTRL_RX_LFC_EN = (1 << 25)
MQNIC_PORT_LFC_CTRL_TX_LFC_REQ = (1 << 28)
MQNIC_PORT_LFC_CTRL_RX_LFC_REQ = (1 << 29)
MQNIC_PORT_PFC_CTRL_TX_PFC_EN = (1 << 24)
MQNIC_PORT_PFC_CTRL_RX_PFC_EN = (1 << 25)
MQNIC_PORT_PFC_CTRL_TX_PFC_REQ = (1 << 28)
MQNIC_PORT_PFC_CTRL_RX_PFC_REQ = (1 << 29)
MQNIC_RB_SCHED_BLOCK_TYPE = 0x0000C004 MQNIC_RB_SCHED_BLOCK_TYPE = 0x0000C004
MQNIC_RB_SCHED_BLOCK_VER = 0x00000300 MQNIC_RB_SCHED_BLOCK_VER = 0x00000300
@ -1119,6 +1158,9 @@ class Port:
self.port_ctrl_rb = None self.port_ctrl_rb = None
self.port_features = None self.port_features = None
self.port_feature_lfc = None
self.port_feature_pfc = None
self.port_feature_int_mac_ctrl = None
async def init(self): async def init(self):
# Read ID registers # Read ID registers
@ -1129,14 +1171,42 @@ class Port:
self.port_ctrl_rb = self.reg_blocks.find(MQNIC_RB_PORT_CTRL_TYPE, MQNIC_RB_PORT_CTRL_VER) self.port_ctrl_rb = self.reg_blocks.find(MQNIC_RB_PORT_CTRL_TYPE, MQNIC_RB_PORT_CTRL_VER)
self.port_features = await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_FEATURES) self.port_features = await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_FEATURES)
self.port_feature_lfc = bool(self.port_features & MQNIC_PORT_FEATURE_LFC)
self.port_feature_pfc = bool(self.port_features & MQNIC_PORT_FEATURE_PFC)
self.port_feature_int_mac_ctrl = bool(self.port_features & MQNIC_PORT_FEATURE_INT_MAC_CTRL)
self.log.info("Port features: 0x%08x", self.port_features) self.log.info("Port features: 0x%08x", self.port_features)
async def get_tx_status(self, port): await self.set_tx_ctrl(0)
return await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_TX_STATUS) await self.set_rx_ctrl(0)
await self.set_lfc_ctrl(0)
async def get_rx_status(self, port): for k in range(8):
return await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_RX_STATUS) await self.set_pfc_ctrl(k, 0)
async def get_tx_ctrl(self):
return await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_TX_CTRL)
async def set_tx_ctrl(self, val):
await self.port_ctrl_rb.write_dword(MQNIC_RB_PORT_CTRL_REG_TX_CTRL, val)
async def get_rx_ctrl(self):
return await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_RX_CTRL)
async def set_rx_ctrl(self, val):
await self.port_ctrl_rb.write_dword(MQNIC_RB_PORT_CTRL_REG_RX_CTRL, val)
async def get_lfc_ctrl(self):
return await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_LFC_CTRL)
async def set_lfc_ctrl(self, val):
await self.port_ctrl_rb.write_dword(MQNIC_RB_PORT_CTRL_REG_LFC_CTRL, val)
async def get_pfc_ctrl(self, index):
return await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_PFC_CTRL0 + 4*index)
async def set_pfc_ctrl(self, index, val):
await self.port_ctrl_rb.write_dword(MQNIC_RB_PORT_CTRL_REG_PFC_CTRL0 + 4*index, val)
class Interface: class Interface:
@ -1209,6 +1279,8 @@ class Interface:
self.if_feature_tx_csum = bool(self.if_features & MQNIC_IF_FEATURE_TX_CSUM) self.if_feature_tx_csum = bool(self.if_features & MQNIC_IF_FEATURE_TX_CSUM)
self.if_feature_rx_csum = bool(self.if_features & MQNIC_IF_FEATURE_RX_CSUM) self.if_feature_rx_csum = bool(self.if_features & MQNIC_IF_FEATURE_RX_CSUM)
self.if_feature_rx_hash = bool(self.if_features & MQNIC_IF_FEATURE_RX_HASH) self.if_feature_rx_hash = bool(self.if_features & MQNIC_IF_FEATURE_RX_HASH)
self.if_feature_lfc = bool(self.if_features & MQNIC_IF_FEATURE_LFC)
self.if_feature_pfc = bool(self.if_features & MQNIC_IF_FEATURE_PFC)
self.log.info("IF features: 0x%08x", self.if_features) self.log.info("IF features: 0x%08x", self.if_features)
self.log.info("Port count: %d", self.port_count) self.log.info("Port count: %d", self.port_count)
@ -1357,11 +1429,16 @@ class Interface:
# wait for all writes to complete # wait for all writes to complete
await self.hw_regs.read_dword(0) await self.hw_regs.read_dword(0)
await self.ports[0].set_tx_ctrl(MQNIC_PORT_TX_CTRL_EN)
await self.ports[0].set_rx_ctrl(MQNIC_PORT_RX_CTRL_EN)
self.port_up = True self.port_up = True
async def close(self): async def close(self):
self.port_up = False self.port_up = False
await self.ports[0].set_rx_ctrl(0)
for q in self.txq: for q in self.txq:
q.disable() q.disable()
@ -1386,6 +1463,8 @@ class Interface:
self.txq = [] self.txq = []
self.rxq = [] self.rxq = []
await self.ports[0].set_tx_ctrl(0)
async def start_xmit(self, skb, tx_ring=None, csum_start=None, csum_offset=None): async def start_xmit(self, skb, tx_ring=None, csum_start=None, csum_offset=None):
if not self.port_up: if not self.port_up:
return return

7
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -52,6 +52,10 @@ VERILOG_SOURCES += ../../rtl/stats_dma_if_axi.v
VERILOG_SOURCES += ../../rtl/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
@ -145,6 +149,9 @@ export PARAM_TX_TAG_WIDTH := 16
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_MAC_CTRL_ENABLE := 1
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 131072 export PARAM_RX_FIFO_DEPTH := 131072
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

48
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -3,6 +3,7 @@
import logging import logging
import os import os
import struct
import sys import sys
import scapy.utils import scapy.utils
@ -103,7 +104,11 @@ class TB(object):
self.port_mac.append(mac) self.port_mac.append(mac)
dut.tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.tx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.rx_lfc_req.setimmediatevalue(0)
dut.rx_pfc_req.setimmediatevalue(0)
dut.rx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
# DDR # DDR
self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value
@ -445,13 +450,16 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) await block.interface.set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(len(block.interface.txq)): for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(block.interface.sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else: else:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000)
await block.interface.ports[block.index].set_tx_ctrl(mqnic.MQNIC_PORT_TX_CTRL_EN)
await block.interface.ports[block.index].set_rx_ctrl(mqnic.MQNIC_PORT_RX_CTRL_EN)
count = 64 count = 64
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
@ -481,6 +489,35 @@ async def run_test_nic(dut):
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
if tb.driver.interfaces[0].if_feature_lfc:
tb.log.info("Test LFC pause frame RX")
await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN)
await tb.driver.hw_regs.read_dword(0)
lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000)
await tb.port_mac[0].rx.send(bytes(lfc_xoff))
count = 16
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
if tb.driver.interfaces[0].if_feature_rx_csum:
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
tb.log.info("Read statistics counters") tb.log.info("Read statistics counters")
await Timer(2000, 'ns') await Timer(2000, 'ns')
@ -562,6 +599,10 @@ def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width,
os.path.join(rtl_dir, "stats_dma_latency.v"), os.path.join(rtl_dir, "stats_dma_latency.v"),
os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "tx_scheduler_rr.v"), os.path.join(rtl_dir, "tx_scheduler_rr.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"),
@ -656,6 +697,9 @@ def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width,
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['MAC_CTRL_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072 parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

7
fpga/common/tb/mqnic_core_pcie_ptile/Makefile
View File

@ -53,6 +53,10 @@ VERILOG_SOURCES += ../../rtl/stats_dma_if_pcie.v
VERILOG_SOURCES += ../../rtl/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
@ -160,6 +164,9 @@ export PARAM_TX_TAG_WIDTH := 16
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_MAC_CTRL_ENABLE := 1
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 131072 export PARAM_RX_FIFO_DEPTH := 131072
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

48
fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py
View File

@ -3,6 +3,7 @@
import logging import logging
import os import os
import struct
import sys import sys
import scapy.utils import scapy.utils
@ -299,7 +300,11 @@ class TB(object):
self.port_mac.append(mac) self.port_mac.append(mac)
dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_tx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_lfc_req.setimmediatevalue(0)
dut.eth_rx_pfc_req.setimmediatevalue(0)
dut.eth_rx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
# DDR # DDR
self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value
@ -643,13 +648,16 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) await block.interface.set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(len(block.interface.txq)): for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(block.interface.sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else: else:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000)
await block.interface.ports[block.index].set_tx_ctrl(mqnic.MQNIC_PORT_TX_CTRL_EN)
await block.interface.ports[block.index].set_rx_ctrl(mqnic.MQNIC_PORT_RX_CTRL_EN)
count = 64 count = 64
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
@ -679,6 +687,35 @@ async def run_test_nic(dut):
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
if tb.driver.interfaces[0].if_feature_lfc:
tb.log.info("Test LFC pause frame RX")
await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN)
await tb.driver.hw_regs.read_dword(0)
lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000)
await tb.port_mac[0].rx.send(bytes(lfc_xoff))
count = 16
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
if tb.driver.interfaces[0].if_feature_rx_csum:
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
tb.log.info("Read statistics counters") tb.log.info("Read statistics counters")
await Timer(2000, 'ns') await Timer(2000, 'ns')
@ -764,6 +801,10 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
os.path.join(rtl_dir, "stats_dma_latency.v"), os.path.join(rtl_dir, "stats_dma_latency.v"),
os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "tx_scheduler_rr.v"), os.path.join(rtl_dir, "tx_scheduler_rr.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"),
@ -872,6 +913,9 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['MAC_CTRL_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072 parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

7
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -53,6 +53,10 @@ VERILOG_SOURCES += ../../rtl/stats_dma_if_pcie.v
VERILOG_SOURCES += ../../rtl/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
@ -159,6 +163,9 @@ export PARAM_TX_TAG_WIDTH := 16
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_MAC_CTRL_ENABLE := 1
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 131072 export PARAM_RX_FIFO_DEPTH := 131072
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

48
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -3,6 +3,7 @@
import logging import logging
import os import os
import struct
import sys import sys
import scapy.utils import scapy.utils
@ -247,7 +248,11 @@ class TB(object):
self.port_mac.append(mac) self.port_mac.append(mac)
dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_tx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_lfc_req.setimmediatevalue(0)
dut.eth_rx_pfc_req.setimmediatevalue(0)
dut.eth_rx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
# DDR # DDR
self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value
@ -591,13 +596,16 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) await block.interface.set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(len(block.interface.txq)): for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(block.interface.sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else: else:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000)
await block.interface.ports[block.index].set_tx_ctrl(mqnic.MQNIC_PORT_TX_CTRL_EN)
await block.interface.ports[block.index].set_rx_ctrl(mqnic.MQNIC_PORT_RX_CTRL_EN)
count = 64 count = 64
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
@ -627,6 +635,35 @@ async def run_test_nic(dut):
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
if tb.driver.interfaces[0].if_feature_lfc:
tb.log.info("Test LFC pause frame RX")
await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN)
await tb.driver.hw_regs.read_dword(0)
lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000)
await tb.port_mac[0].rx.send(bytes(lfc_xoff))
count = 16
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
if tb.driver.interfaces[0].if_feature_rx_csum:
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
tb.log.info("Read statistics counters") tb.log.info("Read statistics counters")
await Timer(2000, 'ns') await Timer(2000, 'ns')
@ -712,6 +749,10 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
os.path.join(rtl_dir, "stats_dma_latency.v"), os.path.join(rtl_dir, "stats_dma_latency.v"),
os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "tx_scheduler_rr.v"), os.path.join(rtl_dir, "tx_scheduler_rr.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"),
@ -819,6 +860,9 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['MAC_CTRL_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072 parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

7
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -53,6 +53,10 @@ VERILOG_SOURCES += ../../rtl/stats_dma_if_pcie.v
VERILOG_SOURCES += ../../rtl/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
@ -159,6 +163,9 @@ export PARAM_TX_TAG_WIDTH := 16
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_MAC_CTRL_ENABLE := 1
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 131072 export PARAM_RX_FIFO_DEPTH := 131072
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

48
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -3,6 +3,7 @@
import logging import logging
import os import os
import struct
import sys import sys
import scapy.utils import scapy.utils
@ -321,7 +322,11 @@ class TB(object):
self.port_mac.append(mac) self.port_mac.append(mac)
dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_tx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_lfc_req.setimmediatevalue(0)
dut.eth_rx_pfc_req.setimmediatevalue(0)
dut.eth_rx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
# DDR # DDR
self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value
@ -665,13 +670,16 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) await block.interface.set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(len(block.interface.txq)): for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(block.interface.sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else: else:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000)
await block.interface.ports[block.index].set_tx_ctrl(mqnic.MQNIC_PORT_TX_CTRL_EN)
await block.interface.ports[block.index].set_rx_ctrl(mqnic.MQNIC_PORT_RX_CTRL_EN)
count = 64 count = 64
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
@ -701,6 +709,35 @@ async def run_test_nic(dut):
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
if tb.driver.interfaces[0].if_feature_lfc:
tb.log.info("Test LFC pause frame RX")
await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN)
await tb.driver.hw_regs.read_dword(0)
lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000)
await tb.port_mac[0].rx.send(bytes(lfc_xoff))
count = 16
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
if tb.driver.interfaces[0].if_feature_rx_csum:
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
tb.log.info("Read statistics counters") tb.log.info("Read statistics counters")
await Timer(2000, 'ns') await Timer(2000, 'ns')
@ -786,6 +823,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "stats_dma_latency.v"), os.path.join(rtl_dir, "stats_dma_latency.v"),
os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "tx_scheduler_rr.v"), os.path.join(rtl_dir, "tx_scheduler_rr.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"),
@ -893,6 +934,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['MAC_CTRL_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072 parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

7
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -55,6 +55,10 @@ VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr_tdma.v
VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v
VERILOG_SOURCES += ../../rtl/tx_scheduler_ctrl_tdma.v VERILOG_SOURCES += ../../rtl/tx_scheduler_ctrl_tdma.v
VERILOG_SOURCES += ../../rtl/tdma_scheduler.v VERILOG_SOURCES += ../../rtl/tdma_scheduler.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
@ -161,6 +165,9 @@ export PARAM_TX_TAG_WIDTH := 16
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_MAC_CTRL_ENABLE := 1
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 131072 export PARAM_RX_FIFO_DEPTH := 131072
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

48
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -3,6 +3,7 @@
import logging import logging
import os import os
import struct
import sys import sys
import scapy.utils import scapy.utils
@ -321,7 +322,11 @@ class TB(object):
self.port_mac.append(mac) self.port_mac.append(mac)
dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_tx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_lfc_req.setimmediatevalue(0)
dut.eth_rx_pfc_req.setimmediatevalue(0)
dut.eth_rx_fc_quanta_clk_en.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1)
# DDR # DDR
self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value
@ -665,13 +670,16 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) await block.interface.set_rx_queue_map_indir_table(block.index, 0, block.index)
for k in range(len(block.interface.txq)): for k in range(len(block.interface.txq)):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(block.interface.sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
else: else:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000)
await block.interface.ports[block.index].set_tx_ctrl(mqnic.MQNIC_PORT_TX_CTRL_EN)
await block.interface.ports[block.index].set_rx_ctrl(mqnic.MQNIC_PORT_RX_CTRL_EN)
count = 64 count = 64
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
@ -701,6 +709,35 @@ async def run_test_nic(dut):
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
if tb.driver.interfaces[0].if_feature_lfc:
tb.log.info("Test LFC pause frame RX")
await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN)
await tb.driver.hw_regs.read_dword(0)
lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000)
await tb.port_mac[0].rx.send(bytes(lfc_xoff))
count = 16
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
if tb.driver.interfaces[0].if_feature_rx_csum:
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
await Timer(1000, 'ns') await Timer(1000, 'ns')
tb.log.info("TDMA") tb.log.info("TDMA")
@ -841,6 +878,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "tx_scheduler_rr.v"), os.path.join(rtl_dir, "tx_scheduler_rr.v"),
os.path.join(rtl_dir, "tx_scheduler_ctrl_tdma.v"), os.path.join(rtl_dir, "tx_scheduler_ctrl_tdma.v"),
os.path.join(rtl_dir, "tdma_scheduler.v"), os.path.join(rtl_dir, "tdma_scheduler.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"),
@ -948,6 +989,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['MAC_CTRL_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072 parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

2
fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl
View File

@ -101,6 +101,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params TX_FIFO_DEPTH "32768" dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "131072" dict set params RX_FIFO_DEPTH "131072"
dict set params MAX_TX_SIZE "9214" dict set params MAX_TX_SIZE "9214"

2
fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -101,6 +101,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params TX_FIFO_DEPTH "32768" dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "131072" dict set params RX_FIFO_DEPTH "131072"
dict set params MAX_TX_SIZE "9214" dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/250_SoC/fpga_100g/ip/cmac_usplus.tcl
View File

@ -7,8 +7,10 @@ set_property -dict [list \
CONFIG.USER_INTERFACE {AXIS} \ CONFIG.USER_INTERFACE {AXIS} \
CONFIG.GT_DRP_CLK {125} \ CONFIG.GT_DRP_CLK {125} \
CONFIG.GT_LOCATION {0} \ CONFIG.GT_LOCATION {0} \
CONFIG.TX_FLOW_CONTROL {0} \ CONFIG.TX_FLOW_CONTROL {1} \
CONFIG.RX_FLOW_CONTROL {0} \ CONFIG.RX_FLOW_CONTROL {1} \
CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \
CONFIG.RX_CHECK_ACK {1} \
CONFIG.INCLUDE_RS_FEC {1} \ CONFIG.INCLUDE_RS_FEC {1} \
CONFIG.ENABLE_TIME_STAMPING {1} CONFIG.ENABLE_TIME_STAMPING {1}
] [get_ips cmac_usplus] ] [get_ips cmac_usplus]

90
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
View File

@ -71,6 +71,8 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072, parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -720,7 +722,20 @@ wire qsfp0_drp_we;
wire [15:0] qsfp0_drp_do; wire [15:0] qsfp0_drp_do;
wire qsfp0_drp_rdy; wire qsfp0_drp_rdy;
wire qsfp0_rx_status; wire qsfp0_tx_enable;
wire qsfp0_tx_lfc_en;
wire qsfp0_tx_lfc_req;
wire [7:0] qsfp0_tx_pfc_en;
wire [7:0] qsfp0_tx_pfc_req;
wire qsfp0_rx_enable;
wire qsfp0_rx_status;
wire qsfp0_rx_lfc_en;
wire qsfp0_rx_lfc_req;
wire qsfp0_rx_lfc_ack;
wire [7:0] qsfp0_rx_pfc_en;
wire [7:0] qsfp0_rx_pfc_req;
wire [7:0] qsfp0_rx_pfc_ack;
wire qsfp0_gtpowergood; wire qsfp0_gtpowergood;
@ -813,6 +828,12 @@ qsfp0_cmac_inst (
.tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int), .tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int),
.tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int), .tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int),
.tx_enable(qsfp0_tx_enable),
.tx_lfc_en(qsfp0_tx_lfc_en),
.tx_lfc_req(qsfp0_tx_lfc_req),
.tx_pfc_en(qsfp0_tx_pfc_en),
.tx_pfc_req(qsfp0_tx_pfc_req),
.rx_clk(qsfp0_rx_clk_int), .rx_clk(qsfp0_rx_clk_int),
.rx_rst(qsfp0_rx_rst_int), .rx_rst(qsfp0_rx_rst_int),
@ -826,7 +847,14 @@ qsfp0_cmac_inst (
.rx_ptp_rst(qsfp0_rx_ptp_rst_int), .rx_ptp_rst(qsfp0_rx_ptp_rst_int),
.rx_ptp_time(qsfp0_rx_ptp_time_int), .rx_ptp_time(qsfp0_rx_ptp_time_int),
.rx_status(qsfp0_rx_status) .rx_enable(qsfp0_rx_enable),
.rx_status(qsfp0_rx_status),
.rx_lfc_en(qsfp0_rx_lfc_en),
.rx_lfc_req(qsfp0_rx_lfc_req),
.rx_lfc_ack(qsfp0_rx_lfc_ack),
.rx_pfc_en(qsfp0_rx_pfc_en),
.rx_pfc_req(qsfp0_rx_pfc_req),
.rx_pfc_ack(qsfp0_rx_pfc_ack)
); );
// QSFP1 CMAC // QSFP1 CMAC
@ -867,7 +895,20 @@ wire qsfp1_drp_we;
wire [15:0] qsfp1_drp_do; wire [15:0] qsfp1_drp_do;
wire qsfp1_drp_rdy; wire qsfp1_drp_rdy;
wire qsfp1_rx_status; wire qsfp1_tx_enable;
wire qsfp1_tx_lfc_en;
wire qsfp1_tx_lfc_req;
wire [7:0] qsfp1_tx_pfc_en;
wire [7:0] qsfp1_tx_pfc_req;
wire qsfp1_rx_enable;
wire qsfp1_rx_status;
wire qsfp1_rx_lfc_en;
wire qsfp1_rx_lfc_req;
wire qsfp1_rx_lfc_ack;
wire [7:0] qsfp1_rx_pfc_en;
wire [7:0] qsfp1_rx_pfc_req;
wire [7:0] qsfp1_rx_pfc_ack;
wire qsfp1_gtpowergood; wire qsfp1_gtpowergood;
@ -960,6 +1001,12 @@ qsfp1_cmac_inst (
.tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int), .tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int),
.tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int), .tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int),
.tx_enable(qsfp1_tx_enable),
.tx_lfc_en(qsfp1_tx_lfc_en),
.tx_lfc_req(qsfp1_tx_lfc_req),
.tx_pfc_en(qsfp1_tx_pfc_en),
.tx_pfc_req(qsfp1_tx_pfc_req),
.rx_clk(qsfp1_rx_clk_int), .rx_clk(qsfp1_rx_clk_int),
.rx_rst(qsfp1_rx_rst_int), .rx_rst(qsfp1_rx_rst_int),
@ -973,7 +1020,14 @@ qsfp1_cmac_inst (
.rx_ptp_rst(qsfp1_rx_ptp_rst_int), .rx_ptp_rst(qsfp1_rx_ptp_rst_int),
.rx_ptp_time(qsfp1_rx_ptp_time_int), .rx_ptp_time(qsfp1_rx_ptp_time_int),
.rx_status(qsfp1_rx_status) .rx_enable(qsfp1_rx_enable),
.rx_status(qsfp1_rx_status),
.rx_lfc_en(qsfp1_rx_lfc_en),
.rx_lfc_req(qsfp1_rx_lfc_req),
.rx_lfc_ack(qsfp1_rx_lfc_ack),
.rx_pfc_en(qsfp1_rx_pfc_en),
.rx_pfc_req(qsfp1_rx_pfc_req),
.rx_pfc_ack(qsfp1_rx_pfc_ack)
); );
wire ptp_clk; wire ptp_clk;
@ -1241,6 +1295,8 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1458,6 +1514,12 @@ core_inst (
.qsfp0_tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int), .qsfp0_tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int),
.qsfp0_tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int), .qsfp0_tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int),
.qsfp0_tx_enable(qsfp0_tx_enable),
.qsfp0_tx_lfc_en(qsfp0_tx_lfc_en),
.qsfp0_tx_lfc_req(qsfp0_tx_lfc_req),
.qsfp0_tx_pfc_en(qsfp0_tx_pfc_en),
.qsfp0_tx_pfc_req(qsfp0_tx_pfc_req),
.qsfp0_rx_clk(qsfp0_rx_clk_int), .qsfp0_rx_clk(qsfp0_rx_clk_int),
.qsfp0_rx_rst(qsfp0_rx_rst_int), .qsfp0_rx_rst(qsfp0_rx_rst_int),
.qsfp0_rx_axis_tdata(qsfp0_rx_axis_tdata_int), .qsfp0_rx_axis_tdata(qsfp0_rx_axis_tdata_int),
@ -1469,7 +1531,14 @@ core_inst (
.qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int), .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
.qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int), .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
.qsfp0_rx_enable(qsfp0_rx_enable),
.qsfp0_rx_status(qsfp0_rx_status), .qsfp0_rx_status(qsfp0_rx_status),
.qsfp0_rx_lfc_en(qsfp0_rx_lfc_en),
.qsfp0_rx_lfc_req(qsfp0_rx_lfc_req),
.qsfp0_rx_lfc_ack(qsfp0_rx_lfc_ack),
.qsfp0_rx_pfc_en(qsfp0_rx_pfc_en),
.qsfp0_rx_pfc_req(qsfp0_rx_pfc_req),
.qsfp0_rx_pfc_ack(qsfp0_rx_pfc_ack),
.qsfp0_drp_clk(qsfp0_drp_clk), .qsfp0_drp_clk(qsfp0_drp_clk),
.qsfp0_drp_rst(qsfp0_drp_rst), .qsfp0_drp_rst(qsfp0_drp_rst),
@ -1498,6 +1567,12 @@ core_inst (
.qsfp1_tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int), .qsfp1_tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int),
.qsfp1_tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int), .qsfp1_tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int),
.qsfp1_tx_enable(qsfp1_tx_enable),
.qsfp1_tx_lfc_en(qsfp1_tx_lfc_en),
.qsfp1_tx_lfc_req(qsfp1_tx_lfc_req),
.qsfp1_tx_pfc_en(qsfp1_tx_pfc_en),
.qsfp1_tx_pfc_req(qsfp1_tx_pfc_req),
.qsfp1_rx_clk(qsfp1_rx_clk_int), .qsfp1_rx_clk(qsfp1_rx_clk_int),
.qsfp1_rx_rst(qsfp1_rx_rst_int), .qsfp1_rx_rst(qsfp1_rx_rst_int),
.qsfp1_rx_axis_tdata(qsfp1_rx_axis_tdata_int), .qsfp1_rx_axis_tdata(qsfp1_rx_axis_tdata_int),
@ -1509,7 +1584,14 @@ core_inst (
.qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int), .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
.qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int), .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
.qsfp1_rx_enable(qsfp1_rx_enable),
.qsfp1_rx_status(qsfp1_rx_status), .qsfp1_rx_status(qsfp1_rx_status),
.qsfp1_rx_lfc_en(qsfp1_rx_lfc_en),
.qsfp1_rx_lfc_req(qsfp1_rx_lfc_req),
.qsfp1_rx_lfc_ack(qsfp1_rx_lfc_ack),
.qsfp1_rx_pfc_en(qsfp1_rx_pfc_en),
.qsfp1_rx_pfc_req(qsfp1_rx_pfc_req),
.qsfp1_rx_pfc_ack(qsfp1_rx_pfc_ack),
.qsfp1_drp_clk(qsfp1_drp_clk), .qsfp1_drp_clk(qsfp1_drp_clk),
.qsfp1_drp_rst(qsfp1_drp_rst), .qsfp1_drp_rst(qsfp1_drp_rst),

83
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v
View File

@ -77,6 +77,8 @@ module fpga_core #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072, parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -296,6 +298,12 @@ module fpga_core #
input wire [15:0] qsfp0_tx_ptp_ts_tag, input wire [15:0] qsfp0_tx_ptp_ts_tag,
input wire qsfp0_tx_ptp_ts_valid, input wire qsfp0_tx_ptp_ts_valid,
output wire qsfp0_tx_enable,
output wire qsfp0_tx_lfc_en,
output wire qsfp0_tx_lfc_req,
output wire [7:0] qsfp0_tx_pfc_en,
output wire [7:0] qsfp0_tx_pfc_req,
input wire qsfp0_rx_clk, input wire qsfp0_rx_clk,
input wire qsfp0_rx_rst, input wire qsfp0_rx_rst,
@ -309,7 +317,14 @@ module fpga_core #
input wire qsfp0_rx_ptp_rst, input wire qsfp0_rx_ptp_rst,
output wire [79:0] qsfp0_rx_ptp_time, output wire [79:0] qsfp0_rx_ptp_time,
output wire qsfp0_rx_enable,
input wire qsfp0_rx_status, input wire qsfp0_rx_status,
output wire qsfp0_rx_lfc_en,
input wire qsfp0_rx_lfc_req,
output wire qsfp0_rx_lfc_ack,
output wire [7:0] qsfp0_rx_pfc_en,
input wire [7:0] qsfp0_rx_pfc_req,
output wire [7:0] qsfp0_rx_pfc_ack,
input wire qsfp0_drp_clk, input wire qsfp0_drp_clk,
input wire qsfp0_drp_rst, input wire qsfp0_drp_rst,
@ -340,6 +355,12 @@ module fpga_core #
input wire [15:0] qsfp1_tx_ptp_ts_tag, input wire [15:0] qsfp1_tx_ptp_ts_tag,
input wire qsfp1_tx_ptp_ts_valid, input wire qsfp1_tx_ptp_ts_valid,
output wire qsfp1_tx_enable,
output wire qsfp1_tx_lfc_en,
output wire qsfp1_tx_lfc_req,
output wire [7:0] qsfp1_tx_pfc_en,
output wire [7:0] qsfp1_tx_pfc_req,
input wire qsfp1_rx_clk, input wire qsfp1_rx_clk,
input wire qsfp1_rx_rst, input wire qsfp1_rx_rst,
@ -353,7 +374,14 @@ module fpga_core #
input wire qsfp1_rx_ptp_rst, input wire qsfp1_rx_ptp_rst,
output wire [79:0] qsfp1_rx_ptp_time, output wire [79:0] qsfp1_rx_ptp_time,
output wire qsfp1_rx_enable,
input wire qsfp1_rx_status, input wire qsfp1_rx_status,
output wire qsfp1_rx_lfc_en,
input wire qsfp1_rx_lfc_req,
output wire qsfp1_rx_lfc_ack,
output wire [7:0] qsfp1_rx_pfc_en,
input wire [7:0] qsfp1_rx_pfc_req,
output wire [7:0] qsfp1_rx_pfc_ack,
input wire qsfp1_drp_clk, input wire qsfp1_drp_clk,
input wire qsfp1_drp_rst, input wire qsfp1_drp_rst,
@ -760,7 +788,12 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_enable;
wire [PORT_COUNT-1:0] eth_tx_status; wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_tx_lfc_en;
wire [PORT_COUNT-1:0] eth_tx_lfc_req;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_rst;
@ -777,7 +810,14 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast; wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_enable;
wire [PORT_COUNT-1:0] eth_rx_status; wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] eth_rx_lfc_en;
wire [PORT_COUNT-1:0] eth_rx_lfc_req;
wire [PORT_COUNT-1:0] eth_rx_lfc_ack;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_req;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack;
wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int; wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int; wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
@ -828,7 +868,12 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}), .s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts_ready(), .s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_enable({qsfp1_tx_enable, qsfp0_tx_enable}),
.mac_tx_status(2'b11), .mac_tx_status(2'b11),
.mac_tx_lfc_en({qsfp1_tx_lfc_en, qsfp0_tx_lfc_en}),
.mac_tx_lfc_req({qsfp1_tx_lfc_req, qsfp0_tx_lfc_req}),
.mac_tx_pfc_en({qsfp1_tx_pfc_en, qsfp0_tx_pfc_en}),
.mac_tx_pfc_req({qsfp1_tx_pfc_req, qsfp0_tx_pfc_req}),
.mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}), .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}),
.mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}), .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}),
@ -845,7 +890,14 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}), .s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
.s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}), .s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
.mac_rx_enable({qsfp1_rx_enable, qsfp0_rx_enable}),
.mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}), .mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}),
.mac_rx_lfc_en({qsfp1_rx_lfc_en, qsfp0_rx_lfc_en}),
.mac_rx_lfc_req({qsfp1_rx_lfc_req, qsfp0_rx_lfc_req}),
.mac_rx_lfc_ack({qsfp1_rx_lfc_ack, qsfp0_rx_lfc_ack}),
.mac_rx_pfc_en({qsfp1_rx_pfc_en, qsfp0_rx_pfc_en}),
.mac_rx_pfc_req({qsfp1_rx_pfc_req, qsfp0_rx_pfc_req}),
.mac_rx_pfc_ack({qsfp1_rx_pfc_ack, qsfp0_rx_pfc_ack}),
// towards datapath // towards datapath
.tx_clk(eth_tx_clk), .tx_clk(eth_tx_clk),
@ -868,7 +920,12 @@ mqnic_port_map_mac_axis_inst (
.m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid), .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready), .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.tx_enable(eth_tx_enable),
.tx_status(eth_tx_status), .tx_status(eth_tx_status),
.tx_lfc_en(eth_tx_lfc_en),
.tx_lfc_req(eth_tx_lfc_req),
.tx_pfc_en(eth_tx_pfc_en),
.tx_pfc_req(eth_tx_pfc_req),
.rx_clk(eth_rx_clk), .rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst), .rx_rst(eth_rx_rst),
@ -885,7 +942,14 @@ mqnic_port_map_mac_axis_inst (
.m_axis_rx_tlast(axis_eth_rx_tlast), .m_axis_rx_tlast(axis_eth_rx_tlast),
.m_axis_rx_tuser(axis_eth_rx_tuser), .m_axis_rx_tuser(axis_eth_rx_tuser),
.rx_status(eth_rx_status) .rx_enable(eth_rx_enable),
.rx_status(eth_rx_status),
.rx_lfc_en(eth_rx_lfc_en),
.rx_lfc_req(eth_rx_lfc_req),
.rx_lfc_ack(eth_rx_lfc_ack),
.rx_pfc_en(eth_rx_pfc_en),
.rx_pfc_req(eth_rx_pfc_req),
.rx_pfc_ack(eth_rx_pfc_ack)
); );
mqnic_core_pcie_us #( mqnic_core_pcie_us #(
@ -955,6 +1019,9 @@ mqnic_core_pcie_us #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(0),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1236,7 +1303,13 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_enable(eth_tx_enable),
.eth_tx_status(eth_tx_status), .eth_tx_status(eth_tx_status),
.eth_tx_lfc_en(eth_tx_lfc_en),
.eth_tx_lfc_req(eth_tx_lfc_req),
.eth_tx_pfc_en(eth_tx_pfc_en),
.eth_tx_pfc_req(eth_tx_pfc_req),
.eth_tx_fc_quanta_clk_en(0),
.eth_rx_clk(eth_rx_clk), .eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst), .eth_rx_rst(eth_rx_rst),
@ -1253,7 +1326,15 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast), .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser), .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_enable(eth_rx_enable),
.eth_rx_status(eth_rx_status), .eth_rx_status(eth_rx_status),
.eth_rx_lfc_en(eth_rx_lfc_en),
.eth_rx_lfc_req(eth_rx_lfc_req),
.eth_rx_lfc_ack(eth_rx_lfc_ack),
.eth_rx_pfc_en(eth_rx_pfc_en),
.eth_rx_pfc_req(eth_rx_pfc_req),
.eth_rx_pfc_ack(eth_rx_pfc_ack),
.eth_rx_fc_quanta_clk_en(0),
/* /*
* DDR * DDR

2
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile
View File

@ -161,6 +161,8 @@ export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 131072 export PARAM_RX_FIFO_DEPTH := 131072
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

4
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -300,6 +300,8 @@ class TB(object):
self.qsfp_mac.append(mac) self.qsfp_mac.append(mac)
getattr(dut, f"qsfp{k}_rx_status").setimmediatevalue(1) getattr(dut, f"qsfp{k}_rx_status").setimmediatevalue(1)
getattr(dut, f"qsfp{k}_rx_lfc_req").setimmediatevalue(0)
getattr(dut, f"qsfp{k}_rx_pfc_req").setimmediatevalue(0)
cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_drp_clk"), 8, units="ns").start()) cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_drp_clk"), 8, units="ns").start())
getattr(dut, f"qsfp{k}_drp_rst").setimmediatevalue(0) getattr(dut, f"qsfp{k}_drp_rst").setimmediatevalue(0)
@ -723,6 +725,8 @@ def test_fpga_core(request):
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072 parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

4
fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile
View File

@ -61,6 +61,10 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/mac_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_ctrl_tx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v

2
fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params ENABLE_PADDING "1" dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1" dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64" dict set params MIN_FRAME_LENGTH "64"

4
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile
View File

@ -61,6 +61,10 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/mac_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_ctrl_tx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v

2
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params ENABLE_PADDING "1" dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1" dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64" dict set params MIN_FRAME_LENGTH "64"

4
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,8 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter ENABLE_PADDING = 1, parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1, parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64, parameter MIN_FRAME_LENGTH = 64,
@ -1376,6 +1378,8 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING), .ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC), .ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),

134
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v
View File

@ -81,6 +81,8 @@ module fpga_core #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter ENABLE_PADDING = 1, parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1, parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64, parameter MIN_FRAME_LENGTH = 64,
@ -902,7 +904,12 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_enable;
wire [PORT_COUNT-1:0] eth_tx_status; wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_tx_lfc_en;
wire [PORT_COUNT-1:0] eth_tx_lfc_req;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_rst;
@ -917,7 +924,14 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast; wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_enable;
wire [PORT_COUNT-1:0] eth_rx_status; wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] eth_rx_lfc_en;
wire [PORT_COUNT-1:0] eth_rx_lfc_req;
wire [PORT_COUNT-1:0] eth_rx_lfc_ack;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_req;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack;
wire [PORT_COUNT-1:0] port_xgmii_tx_clk; wire [PORT_COUNT-1:0] port_xgmii_tx_clk;
wire [PORT_COUNT-1:0] port_xgmii_tx_rst; wire [PORT_COUNT-1:0] port_xgmii_tx_rst;
@ -990,12 +1004,15 @@ generate
.PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE), .TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH), .TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TS_CTRL_IN_TUSER(0),
.TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE), .RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH), .RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
.PFC_ENABLE(PFC_ENABLE),
.PAUSE_ENABLE(LFC_ENABLE)
) )
eth_mac_inst ( eth_mac_inst (
.tx_clk(port_xgmii_tx_clk[n]), .tx_clk(port_xgmii_tx_clk[n]),
@ -1003,6 +1020,9 @@ generate
.rx_clk(port_xgmii_rx_clk[n]), .rx_clk(port_xgmii_rx_clk[n]),
.rx_rst(port_xgmii_rx_rst[n]), .rx_rst(port_xgmii_rx_rst[n]),
/*
* AXI input
*/
.tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
.tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]),
.tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]),
@ -1010,30 +1030,121 @@ generate
.tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]),
.tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]),
/*
* AXI output
*/
.rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
.rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]),
.rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]),
.rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]),
.rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]),
/*
* XGMII interface
*/
.xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]),
.xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]),
.xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]),
.xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]),
/*
* PTP
*/
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req(eth_tx_lfc_req[n +: 1]),
.tx_lfc_resend(1'b0),
.rx_lfc_en(eth_rx_lfc_en[n +: 1]),
.rx_lfc_req(eth_rx_lfc_req[n +: 1]),
.rx_lfc_ack(eth_rx_lfc_ack[n +: 1]),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req(eth_tx_pfc_req[n*8 +: 8]),
.tx_pfc_resend(1'b0),
.rx_pfc_en(eth_rx_pfc_en[n*8 +: 8]),
.rx_pfc_req(eth_rx_pfc_req[n*8 +: 8]),
.rx_pfc_ack(eth_rx_pfc_ack[n*8 +: 8]),
/*
* Pause interface
*/
.tx_lfc_pause_en(1'b1),
.tx_pause_req(1'b0),
.tx_pause_ack(),
/*
* Status
*/
.tx_start_packet(),
.tx_error_underflow(), .tx_error_underflow(),
.rx_start_packet(),
.rx_error_bad_frame(), .rx_error_bad_frame(),
.rx_error_bad_fcs(), .rx_error_bad_fcs(),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
.stat_tx_lfc_xon(),
.stat_tx_lfc_xoff(),
.stat_tx_lfc_paused(),
.stat_tx_pfc_pkt(),
.stat_tx_pfc_xon(),
.stat_tx_pfc_xoff(),
.stat_tx_pfc_paused(),
.stat_rx_lfc_pkt(),
.stat_rx_lfc_xon(),
.stat_rx_lfc_xoff(),
.stat_rx_lfc_paused(),
.stat_rx_pfc_pkt(),
.stat_rx_pfc_xon(),
.stat_rx_pfc_xoff(),
.stat_rx_pfc_paused(),
/*
* Configuration
*/
.cfg_ifg(8'd12), .cfg_ifg(8'd12),
.cfg_tx_enable(1'b1), .cfg_tx_enable(eth_tx_enable[n +: 1]),
.cfg_rx_enable(1'b1) .cfg_rx_enable(eth_rx_enable[n +: 1]),
.cfg_mcf_rx_eth_dst_mcast(48'h01_80_C2_00_00_01),
.cfg_mcf_rx_check_eth_dst_mcast(1'b1),
.cfg_mcf_rx_eth_dst_ucast(48'd0),
.cfg_mcf_rx_check_eth_dst_ucast(1'b0),
.cfg_mcf_rx_eth_src(48'd0),
.cfg_mcf_rx_check_eth_src(1'b0),
.cfg_mcf_rx_eth_type(16'h8808),
.cfg_mcf_rx_opcode_lfc(16'h0001),
.cfg_mcf_rx_check_opcode_lfc(eth_rx_lfc_en[n +: 1]),
.cfg_mcf_rx_opcode_pfc(16'h0101),
.cfg_mcf_rx_check_opcode_pfc(eth_rx_pfc_en[n*8 +: 8] != 0),
.cfg_mcf_rx_forward(1'b0),
.cfg_mcf_rx_enable(eth_rx_lfc_en[n +: 1] || eth_rx_pfc_en[n*8 +: 8]),
.cfg_tx_lfc_eth_dst(48'h01_80_C2_00_00_01),
.cfg_tx_lfc_eth_src(48'h80_23_31_43_54_4C),
.cfg_tx_lfc_eth_type(16'h8808),
.cfg_tx_lfc_opcode(16'h0001),
.cfg_tx_lfc_en(eth_tx_lfc_en[n +: 1]),
.cfg_tx_lfc_quanta(16'hffff),
.cfg_tx_lfc_refresh(16'h7fff),
.cfg_tx_pfc_eth_dst(48'h01_80_C2_00_00_01),
.cfg_tx_pfc_eth_src(48'h80_23_31_43_54_4C),
.cfg_tx_pfc_eth_type(16'h8808),
.cfg_tx_pfc_opcode(16'h0101),
.cfg_tx_pfc_en(eth_tx_pfc_en[n*8 +: 8] != 0),
.cfg_tx_pfc_quanta({8{16'hffff}}),
.cfg_tx_pfc_refresh({8{16'h7fff}}),
.cfg_rx_lfc_opcode(16'h0001),
.cfg_rx_lfc_en(eth_rx_lfc_en[n +: 1]),
.cfg_rx_pfc_opcode(16'h0101),
.cfg_rx_pfc_en(eth_rx_pfc_en[n*8 +: 8] != 0)
); );
end end
@ -1107,6 +1218,9 @@ mqnic_core_pcie_us #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(0),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1388,7 +1502,13 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_enable(eth_tx_enable),
.eth_tx_status(eth_tx_status), .eth_tx_status(eth_tx_status),
.eth_tx_lfc_en(eth_tx_lfc_en),
.eth_tx_lfc_req(eth_tx_lfc_req),
.eth_tx_pfc_en(eth_tx_pfc_en),
.eth_tx_pfc_req(eth_tx_pfc_req),
.eth_tx_fc_quanta_clk_en(0),
.eth_rx_clk(eth_rx_clk), .eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst), .eth_rx_rst(eth_rx_rst),
@ -1405,7 +1525,15 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast), .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser), .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_enable(eth_rx_enable),
.eth_rx_status(eth_rx_status), .eth_rx_status(eth_rx_status),
.eth_rx_lfc_en(eth_rx_lfc_en),
.eth_rx_lfc_req(eth_rx_lfc_req),
.eth_rx_lfc_ack(eth_rx_lfc_ack),
.eth_rx_pfc_en(eth_rx_pfc_en),
.eth_rx_pfc_req(eth_rx_pfc_req),
.eth_rx_pfc_ack(eth_rx_pfc_ack),
.eth_rx_fc_quanta_clk_en(0),
/* /*
* DDR * DDR

6
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile
View File

@ -62,6 +62,10 @@ VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
@ -167,6 +171,8 @@ export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 32768 export PARAM_RX_FIFO_DEPTH := 32768
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

40
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -3,6 +3,7 @@
import logging import logging
import os import os
import struct
import sys import sys
import scapy.utils import scapy.utils
@ -17,7 +18,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.triggers import RisingEdge, FallingEdge, Timer
from cocotbext.axi import AxiStreamBus from cocotbext.axi import AxiStreamBus
from cocotbext.eth import XgmiiSource, XgmiiSink from cocotbext.eth import XgmiiSource, XgmiiSink, XgmiiFrame
from cocotbext.pcie.core import RootComplex from cocotbext.pcie.core import RootComplex
from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
@ -396,7 +397,7 @@ async def run_test_nic(dut):
# await tb.driver.interfaces[1].start_xmit(data, 0) # await tb.driver.interfaces[1].start_xmit(data, 0)
# pkt = await tb.qsfp_sink.r[1][0]ecv() # pkt = await tb.qsfp_sink[1][0].recv()
# tb.log.info("Packet: %s", pkt) # tb.log.info("Packet: %s", pkt)
# await tb.qsfp_source[1][0].send(pkt) # await tb.qsfp_source[1][0].send(pkt)
@ -528,6 +529,35 @@ async def run_test_nic(dut):
tb.loopback_enable = False tb.loopback_enable = False
if tb.driver.interfaces[0].if_feature_lfc:
tb.log.info("Test LFC pause frame RX")
await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN)
await tb.driver.hw_regs.read_dword(0)
lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000)
await tb.qsfp_source[0][0].send(XgmiiFrame.from_payload(bytes(lfc_xoff)))
count = 16
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
if tb.driver.interfaces[0].if_feature_rx_csum:
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
await RisingEdge(dut.clk_250mhz) await RisingEdge(dut.clk_250mhz)
await RisingEdge(dut.clk_250mhz) await RisingEdge(dut.clk_250mhz)
@ -600,6 +630,10 @@ def test_fpga_core(request):
os.path.join(eth_rtl_dir, "eth_mac_10g.v"), os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "lfsr.v"), os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
@ -706,6 +740,8 @@ def test_fpga_core(request):
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 32768 parameters['RX_FIFO_DEPTH'] = 32768
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

4
fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile
View File

@ -59,6 +59,10 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/mac_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_ctrl_tx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v

2
fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl
View File

@ -104,6 +104,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params ENABLE_PADDING "1" dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1" dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64" dict set params MIN_FRAME_LENGTH "64"

4
fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile
View File

@ -59,6 +59,10 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/mac_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_ctrl_tx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v

2
fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl
View File

@ -104,6 +104,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params ENABLE_PADDING "1" dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1" dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64" dict set params MIN_FRAME_LENGTH "64"

4
fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,8 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter ENABLE_PADDING = 1, parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1, parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64, parameter MIN_FRAME_LENGTH = 64,
@ -1321,6 +1323,8 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING), .ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC), .ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),

134
fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v
View File

@ -81,6 +81,8 @@ module fpga_core #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter ENABLE_PADDING = 1, parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1, parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64, parameter MIN_FRAME_LENGTH = 64,
@ -676,7 +678,12 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_enable;
wire [PORT_COUNT-1:0] eth_tx_status; wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_tx_lfc_en;
wire [PORT_COUNT-1:0] eth_tx_lfc_req;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_rst;
@ -691,7 +698,14 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast; wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_enable;
wire [PORT_COUNT-1:0] eth_rx_status; wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] eth_rx_lfc_en;
wire [PORT_COUNT-1:0] eth_rx_lfc_req;
wire [PORT_COUNT-1:0] eth_rx_lfc_ack;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_req;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack;
wire [PORT_COUNT-1:0] port_xgmii_tx_clk; wire [PORT_COUNT-1:0] port_xgmii_tx_clk;
wire [PORT_COUNT-1:0] port_xgmii_tx_rst; wire [PORT_COUNT-1:0] port_xgmii_tx_rst;
@ -764,12 +778,15 @@ generate
.PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE), .TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH), .TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TS_CTRL_IN_TUSER(0),
.TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE), .RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH), .RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
.PFC_ENABLE(PFC_ENABLE),
.PAUSE_ENABLE(LFC_ENABLE)
) )
eth_mac_inst ( eth_mac_inst (
.tx_clk(port_xgmii_tx_clk[n]), .tx_clk(port_xgmii_tx_clk[n]),
@ -777,6 +794,9 @@ generate
.rx_clk(port_xgmii_rx_clk[n]), .rx_clk(port_xgmii_rx_clk[n]),
.rx_rst(port_xgmii_rx_rst[n]), .rx_rst(port_xgmii_rx_rst[n]),
/*
* AXI input
*/
.tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
.tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]),
.tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]),
@ -784,30 +804,121 @@ generate
.tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]),
.tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]),
/*
* AXI output
*/
.rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
.rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]),
.rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]),
.rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]),
.rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]),
/*
* XGMII interface
*/
.xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]),
.xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]),
.xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]),
.xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]),
/*
* PTP
*/
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req(eth_tx_lfc_req[n +: 1]),
.tx_lfc_resend(1'b0),
.rx_lfc_en(eth_rx_lfc_en[n +: 1]),
.rx_lfc_req(eth_rx_lfc_req[n +: 1]),
.rx_lfc_ack(eth_rx_lfc_ack[n +: 1]),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req(eth_tx_pfc_req[n*8 +: 8]),
.tx_pfc_resend(1'b0),
.rx_pfc_en(eth_rx_pfc_en[n*8 +: 8]),
.rx_pfc_req(eth_rx_pfc_req[n*8 +: 8]),
.rx_pfc_ack(eth_rx_pfc_ack[n*8 +: 8]),
/*
* Pause interface
*/
.tx_lfc_pause_en(1'b1),
.tx_pause_req(1'b0),
.tx_pause_ack(),
/*
* Status
*/
.tx_start_packet(),
.tx_error_underflow(), .tx_error_underflow(),
.rx_start_packet(),
.rx_error_bad_frame(), .rx_error_bad_frame(),
.rx_error_bad_fcs(), .rx_error_bad_fcs(),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
.stat_tx_lfc_xon(),
.stat_tx_lfc_xoff(),
.stat_tx_lfc_paused(),
.stat_tx_pfc_pkt(),
.stat_tx_pfc_xon(),
.stat_tx_pfc_xoff(),
.stat_tx_pfc_paused(),
.stat_rx_lfc_pkt(),
.stat_rx_lfc_xon(),
.stat_rx_lfc_xoff(),
.stat_rx_lfc_paused(),
.stat_rx_pfc_pkt(),
.stat_rx_pfc_xon(),
.stat_rx_pfc_xoff(),
.stat_rx_pfc_paused(),
/*
* Configuration
*/
.cfg_ifg(8'd12), .cfg_ifg(8'd12),
.cfg_tx_enable(1'b1), .cfg_tx_enable(eth_tx_enable[n +: 1]),
.cfg_rx_enable(1'b1) .cfg_rx_enable(eth_rx_enable[n +: 1]),
.cfg_mcf_rx_eth_dst_mcast(48'h01_80_C2_00_00_01),
.cfg_mcf_rx_check_eth_dst_mcast(1'b1),
.cfg_mcf_rx_eth_dst_ucast(48'd0),
.cfg_mcf_rx_check_eth_dst_ucast(1'b0),
.cfg_mcf_rx_eth_src(48'd0),
.cfg_mcf_rx_check_eth_src(1'b0),
.cfg_mcf_rx_eth_type(16'h8808),
.cfg_mcf_rx_opcode_lfc(16'h0001),
.cfg_mcf_rx_check_opcode_lfc(eth_rx_lfc_en[n +: 1]),
.cfg_mcf_rx_opcode_pfc(16'h0101),
.cfg_mcf_rx_check_opcode_pfc(eth_rx_pfc_en[n*8 +: 8] != 0),
.cfg_mcf_rx_forward(1'b0),
.cfg_mcf_rx_enable(eth_rx_lfc_en[n +: 1] || eth_rx_pfc_en[n*8 +: 8]),
.cfg_tx_lfc_eth_dst(48'h01_80_C2_00_00_01),
.cfg_tx_lfc_eth_src(48'h80_23_31_43_54_4C),
.cfg_tx_lfc_eth_type(16'h8808),
.cfg_tx_lfc_opcode(16'h0001),
.cfg_tx_lfc_en(eth_tx_lfc_en[n +: 1]),
.cfg_tx_lfc_quanta(16'hffff),
.cfg_tx_lfc_refresh(16'h7fff),
.cfg_tx_pfc_eth_dst(48'h01_80_C2_00_00_01),
.cfg_tx_pfc_eth_src(48'h80_23_31_43_54_4C),
.cfg_tx_pfc_eth_type(16'h8808),
.cfg_tx_pfc_opcode(16'h0101),
.cfg_tx_pfc_en(eth_tx_pfc_en[n*8 +: 8] != 0),
.cfg_tx_pfc_quanta({8{16'hffff}}),
.cfg_tx_pfc_refresh({8{16'h7fff}}),
.cfg_rx_lfc_opcode(16'h0001),
.cfg_rx_lfc_en(eth_rx_lfc_en[n +: 1]),
.cfg_rx_pfc_opcode(16'h0101),
.cfg_rx_pfc_en(eth_rx_pfc_en[n*8 +: 8] != 0)
); );
end end
@ -881,6 +992,9 @@ mqnic_core_pcie_s10 #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(0),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1087,7 +1201,13 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_enable(eth_tx_enable),
.eth_tx_status(eth_tx_status), .eth_tx_status(eth_tx_status),
.eth_tx_lfc_en(eth_tx_lfc_en),
.eth_tx_lfc_req(eth_tx_lfc_req),
.eth_tx_pfc_en(eth_tx_pfc_en),
.eth_tx_pfc_req(eth_tx_pfc_req),
.eth_tx_fc_quanta_clk_en(0),
.eth_rx_clk(eth_rx_clk), .eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst), .eth_rx_rst(eth_rx_rst),
@ -1104,7 +1224,15 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast), .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser), .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_enable(eth_rx_enable),
.eth_rx_status(eth_rx_status), .eth_rx_status(eth_rx_status),
.eth_rx_lfc_en(eth_rx_lfc_en),
.eth_rx_lfc_req(eth_rx_lfc_req),
.eth_rx_lfc_ack(eth_rx_lfc_ack),
.eth_rx_pfc_en(eth_rx_pfc_en),
.eth_rx_pfc_req(eth_rx_pfc_req),
.eth_rx_pfc_ack(eth_rx_pfc_ack),
.eth_rx_fc_quanta_clk_en(0),
/* /*
* DDR * DDR

6
fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile
View File

@ -60,6 +60,10 @@ VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
@ -165,6 +169,8 @@ export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 32768 export PARAM_RX_FIFO_DEPTH := 32768
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

38
fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -3,6 +3,7 @@
import logging import logging
import os import os
import struct
import sys import sys
import scapy.utils import scapy.utils
@ -16,7 +17,7 @@ from cocotb.log import SimLog
from cocotb.clock import Clock from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.triggers import RisingEdge, FallingEdge, Timer
from cocotbext.eth import XgmiiSource, XgmiiSink from cocotbext.eth import XgmiiSource, XgmiiSink, XgmiiFrame
from cocotbext.pcie.core import RootComplex from cocotbext.pcie.core import RootComplex
from cocotbext.pcie.intel.s10 import S10PcieDevice, S10RxBus, S10TxBus from cocotbext.pcie.intel.s10 import S10PcieDevice, S10RxBus, S10TxBus
@ -438,6 +439,35 @@ async def run_test_nic(dut):
tb.loopback_enable = False tb.loopback_enable = False
if tb.driver.interfaces[0].if_feature_lfc:
tb.log.info("Test LFC pause frame RX")
await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN)
await tb.driver.hw_regs.read_dword(0)
lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000)
await tb.qsfp_source[0][0].send(XgmiiFrame.from_payload(bytes(lfc_xoff)))
count = 16
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
if tb.driver.interfaces[0].if_feature_rx_csum:
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
await RisingEdge(dut.clk_250mhz) await RisingEdge(dut.clk_250mhz)
await RisingEdge(dut.clk_250mhz) await RisingEdge(dut.clk_250mhz)
@ -508,6 +538,10 @@ def test_fpga_core(request):
os.path.join(eth_rtl_dir, "eth_mac_10g.v"), os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "lfsr.v"), os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
@ -614,6 +648,8 @@ def test_fpga_core(request):
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 32768 parameters['RX_FIFO_DEPTH'] = 32768
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
View File

@ -101,6 +101,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params TX_FIFO_DEPTH "32768" dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "131072" dict set params RX_FIFO_DEPTH "131072"
dict set params MAX_TX_SIZE "9214" dict set params MAX_TX_SIZE "9214"

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -101,6 +101,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params TX_FIFO_DEPTH "32768" dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "131072" dict set params RX_FIFO_DEPTH "131072"
dict set params MAX_TX_SIZE "9214" dict set params MAX_TX_SIZE "9214"

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
View File

@ -101,6 +101,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params TX_FIFO_DEPTH "32768" dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "131072" dict set params RX_FIFO_DEPTH "131072"
dict set params MAX_TX_SIZE "9214" dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/cmac_usplus.tcl
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@ -7,8 +7,10 @@ set_property -dict [list \
CONFIG.USER_INTERFACE {AXIS} \ CONFIG.USER_INTERFACE {AXIS} \
CONFIG.GT_DRP_CLK {125} \ CONFIG.GT_DRP_CLK {125} \
CONFIG.GT_LOCATION {0} \ CONFIG.GT_LOCATION {0} \
CONFIG.TX_FLOW_CONTROL {0} \ CONFIG.TX_FLOW_CONTROL {1} \
CONFIG.RX_FLOW_CONTROL {0} \ CONFIG.RX_FLOW_CONTROL {1} \
CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \
CONFIG.RX_CHECK_ACK {1} \
CONFIG.INCLUDE_RS_FEC {1} \ CONFIG.INCLUDE_RS_FEC {1} \
CONFIG.ENABLE_TIME_STAMPING {1} CONFIG.ENABLE_TIME_STAMPING {1}
] [get_ips cmac_usplus] ] [get_ips cmac_usplus]

90
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -71,6 +71,8 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072, parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -955,7 +957,20 @@ wire qsfp_0_drp_we;
wire [15:0] qsfp_0_drp_do; wire [15:0] qsfp_0_drp_do;
wire qsfp_0_drp_rdy; wire qsfp_0_drp_rdy;
wire qsfp_0_rx_status; wire qsfp_0_tx_enable;
wire qsfp_0_tx_lfc_en;
wire qsfp_0_tx_lfc_req;
wire [7:0] qsfp_0_tx_pfc_en;
wire [7:0] qsfp_0_tx_pfc_req;
wire qsfp_0_rx_enable;
wire qsfp_0_rx_status;
wire qsfp_0_rx_lfc_en;
wire qsfp_0_rx_lfc_req;
wire qsfp_0_rx_lfc_ack;
wire [7:0] qsfp_0_rx_pfc_en;
wire [7:0] qsfp_0_rx_pfc_req;
wire [7:0] qsfp_0_rx_pfc_ack;
wire qsfp_0_gtpowergood; wire qsfp_0_gtpowergood;
@ -1048,6 +1063,12 @@ qsfp_0_cmac_inst (
.tx_ptp_ts_tag(qsfp_0_tx_ptp_ts_tag_int), .tx_ptp_ts_tag(qsfp_0_tx_ptp_ts_tag_int),
.tx_ptp_ts_valid(qsfp_0_tx_ptp_ts_valid_int), .tx_ptp_ts_valid(qsfp_0_tx_ptp_ts_valid_int),
.tx_enable(qsfp_0_tx_enable),
.tx_lfc_en(qsfp_0_tx_lfc_en),
.tx_lfc_req(qsfp_0_tx_lfc_req),
.tx_pfc_en(qsfp_0_tx_pfc_en),
.tx_pfc_req(qsfp_0_tx_pfc_req),
.rx_clk(qsfp_0_rx_clk_int), .rx_clk(qsfp_0_rx_clk_int),
.rx_rst(qsfp_0_rx_rst_int), .rx_rst(qsfp_0_rx_rst_int),
@ -1061,7 +1082,14 @@ qsfp_0_cmac_inst (
.rx_ptp_rst(qsfp_0_rx_ptp_rst_int), .rx_ptp_rst(qsfp_0_rx_ptp_rst_int),
.rx_ptp_time(qsfp_0_rx_ptp_time_int), .rx_ptp_time(qsfp_0_rx_ptp_time_int),
.rx_status(qsfp_0_rx_status) .rx_enable(qsfp_0_rx_enable),
.rx_status(qsfp_0_rx_status),
.rx_lfc_en(qsfp_0_rx_lfc_en),
.rx_lfc_req(qsfp_0_rx_lfc_req),
.rx_lfc_ack(qsfp_0_rx_lfc_ack),
.rx_pfc_en(qsfp_0_rx_pfc_en),
.rx_pfc_req(qsfp_0_rx_pfc_req),
.rx_pfc_ack(qsfp_0_rx_pfc_ack)
); );
// QSFP1 CMAC // QSFP1 CMAC
@ -1102,7 +1130,20 @@ wire qsfp_1_drp_we;
wire [15:0] qsfp_1_drp_do; wire [15:0] qsfp_1_drp_do;
wire qsfp_1_drp_rdy; wire qsfp_1_drp_rdy;
wire qsfp_1_rx_status; wire qsfp_1_tx_enable;
wire qsfp_1_tx_lfc_en;
wire qsfp_1_tx_lfc_req;
wire [7:0] qsfp_1_tx_pfc_en;
wire [7:0] qsfp_1_tx_pfc_req;
wire qsfp_1_rx_enable;
wire qsfp_1_rx_status;
wire qsfp_1_rx_lfc_en;
wire qsfp_1_rx_lfc_req;
wire qsfp_1_rx_lfc_ack;
wire [7:0] qsfp_1_rx_pfc_en;
wire [7:0] qsfp_1_rx_pfc_req;
wire [7:0] qsfp_1_rx_pfc_ack;
wire qsfp_1_gtpowergood; wire qsfp_1_gtpowergood;
@ -1195,6 +1236,12 @@ qsfp_1_cmac_inst (
.tx_ptp_ts_tag(qsfp_1_tx_ptp_ts_tag_int), .tx_ptp_ts_tag(qsfp_1_tx_ptp_ts_tag_int),
.tx_ptp_ts_valid(qsfp_1_tx_ptp_ts_valid_int), .tx_ptp_ts_valid(qsfp_1_tx_ptp_ts_valid_int),
.tx_enable(qsfp_1_tx_enable),
.tx_lfc_en(qsfp_1_tx_lfc_en),
.tx_lfc_req(qsfp_1_tx_lfc_req),
.tx_pfc_en(qsfp_1_tx_pfc_en),
.tx_pfc_req(qsfp_1_tx_pfc_req),
.rx_clk(qsfp_1_rx_clk_int), .rx_clk(qsfp_1_rx_clk_int),
.rx_rst(qsfp_1_rx_rst_int), .rx_rst(qsfp_1_rx_rst_int),
@ -1208,7 +1255,14 @@ qsfp_1_cmac_inst (
.rx_ptp_rst(qsfp_1_rx_ptp_rst_int), .rx_ptp_rst(qsfp_1_rx_ptp_rst_int),
.rx_ptp_time(qsfp_1_rx_ptp_time_int), .rx_ptp_time(qsfp_1_rx_ptp_time_int),
.rx_status(qsfp_1_rx_status) .rx_enable(qsfp_1_rx_enable),
.rx_status(qsfp_1_rx_status),
.rx_lfc_en(qsfp_1_rx_lfc_en),
.rx_lfc_req(qsfp_1_rx_lfc_req),
.rx_lfc_ack(qsfp_1_rx_lfc_ack),
.rx_pfc_en(qsfp_1_rx_pfc_en),
.rx_pfc_req(qsfp_1_rx_pfc_req),
.rx_pfc_ack(qsfp_1_rx_pfc_ack)
); );
wire ptp_clk; wire ptp_clk;
@ -1601,6 +1655,8 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1797,6 +1853,12 @@ core_inst (
.qsfp_0_tx_ptp_ts_tag(qsfp_0_tx_ptp_ts_tag_int), .qsfp_0_tx_ptp_ts_tag(qsfp_0_tx_ptp_ts_tag_int),
.qsfp_0_tx_ptp_ts_valid(qsfp_0_tx_ptp_ts_valid_int), .qsfp_0_tx_ptp_ts_valid(qsfp_0_tx_ptp_ts_valid_int),
.qsfp_0_tx_enable(qsfp_0_tx_enable),
.qsfp_0_tx_lfc_en(qsfp_0_tx_lfc_en),
.qsfp_0_tx_lfc_req(qsfp_0_tx_lfc_req),
.qsfp_0_tx_pfc_en(qsfp_0_tx_pfc_en),
.qsfp_0_tx_pfc_req(qsfp_0_tx_pfc_req),
.qsfp_0_rx_clk(qsfp_0_rx_clk_int), .qsfp_0_rx_clk(qsfp_0_rx_clk_int),
.qsfp_0_rx_rst(qsfp_0_rx_rst_int), .qsfp_0_rx_rst(qsfp_0_rx_rst_int),
.qsfp_0_rx_axis_tdata(qsfp_0_rx_axis_tdata_int), .qsfp_0_rx_axis_tdata(qsfp_0_rx_axis_tdata_int),
@ -1808,7 +1870,14 @@ core_inst (
.qsfp_0_rx_ptp_rst(qsfp_0_rx_ptp_rst_int), .qsfp_0_rx_ptp_rst(qsfp_0_rx_ptp_rst_int),
.qsfp_0_rx_ptp_time(qsfp_0_rx_ptp_time_int), .qsfp_0_rx_ptp_time(qsfp_0_rx_ptp_time_int),
.qsfp_0_rx_enable(qsfp_0_rx_enable),
.qsfp_0_rx_status(qsfp_0_rx_status), .qsfp_0_rx_status(qsfp_0_rx_status),
.qsfp_0_rx_lfc_en(qsfp_0_rx_lfc_en),
.qsfp_0_rx_lfc_req(qsfp_0_rx_lfc_req),
.qsfp_0_rx_lfc_ack(qsfp_0_rx_lfc_ack),
.qsfp_0_rx_pfc_en(qsfp_0_rx_pfc_en),
.qsfp_0_rx_pfc_req(qsfp_0_rx_pfc_req),
.qsfp_0_rx_pfc_ack(qsfp_0_rx_pfc_ack),
.qsfp_0_drp_clk(qsfp_0_drp_clk), .qsfp_0_drp_clk(qsfp_0_drp_clk),
.qsfp_0_drp_rst(qsfp_0_drp_rst), .qsfp_0_drp_rst(qsfp_0_drp_rst),
@ -1835,6 +1904,12 @@ core_inst (
.qsfp_1_tx_ptp_ts_tag(qsfp_1_tx_ptp_ts_tag_int), .qsfp_1_tx_ptp_ts_tag(qsfp_1_tx_ptp_ts_tag_int),
.qsfp_1_tx_ptp_ts_valid(qsfp_1_tx_ptp_ts_valid_int), .qsfp_1_tx_ptp_ts_valid(qsfp_1_tx_ptp_ts_valid_int),
.qsfp_1_tx_enable(qsfp_1_tx_enable),
.qsfp_1_tx_lfc_en(qsfp_1_tx_lfc_en),
.qsfp_1_tx_lfc_req(qsfp_1_tx_lfc_req),
.qsfp_1_tx_pfc_en(qsfp_1_tx_pfc_en),
.qsfp_1_tx_pfc_req(qsfp_1_tx_pfc_req),
.qsfp_1_rx_clk(qsfp_1_rx_clk_int), .qsfp_1_rx_clk(qsfp_1_rx_clk_int),
.qsfp_1_rx_rst(qsfp_1_rx_rst_int), .qsfp_1_rx_rst(qsfp_1_rx_rst_int),
.qsfp_1_rx_axis_tdata(qsfp_1_rx_axis_tdata_int), .qsfp_1_rx_axis_tdata(qsfp_1_rx_axis_tdata_int),
@ -1846,7 +1921,14 @@ core_inst (
.qsfp_1_rx_ptp_rst(qsfp_1_rx_ptp_rst_int), .qsfp_1_rx_ptp_rst(qsfp_1_rx_ptp_rst_int),
.qsfp_1_rx_ptp_time(qsfp_1_rx_ptp_time_int), .qsfp_1_rx_ptp_time(qsfp_1_rx_ptp_time_int),
.qsfp_1_rx_enable(qsfp_1_rx_enable),
.qsfp_1_rx_status(qsfp_1_rx_status), .qsfp_1_rx_status(qsfp_1_rx_status),
.qsfp_1_rx_lfc_en(qsfp_1_rx_lfc_en),
.qsfp_1_rx_lfc_req(qsfp_1_rx_lfc_req),
.qsfp_1_rx_lfc_ack(qsfp_1_rx_lfc_ack),
.qsfp_1_rx_pfc_en(qsfp_1_rx_pfc_en),
.qsfp_1_rx_pfc_req(qsfp_1_rx_pfc_req),
.qsfp_1_rx_pfc_ack(qsfp_1_rx_pfc_ack),
.qsfp_1_drp_clk(qsfp_1_drp_clk), .qsfp_1_drp_clk(qsfp_1_drp_clk),
.qsfp_1_drp_rst(qsfp_1_drp_rst), .qsfp_1_drp_rst(qsfp_1_drp_rst),

87
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
View File

@ -77,6 +77,8 @@ module fpga_core #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072, parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -275,6 +277,12 @@ module fpga_core #
input wire [15:0] qsfp_0_tx_ptp_ts_tag, input wire [15:0] qsfp_0_tx_ptp_ts_tag,
input wire qsfp_0_tx_ptp_ts_valid, input wire qsfp_0_tx_ptp_ts_valid,
output wire qsfp_0_tx_enable,
output wire qsfp_0_tx_lfc_en,
output wire qsfp_0_tx_lfc_req,
output wire [7:0] qsfp_0_tx_pfc_en,
output wire [7:0] qsfp_0_tx_pfc_req,
input wire qsfp_0_rx_clk, input wire qsfp_0_rx_clk,
input wire qsfp_0_rx_rst, input wire qsfp_0_rx_rst,
@ -288,7 +296,14 @@ module fpga_core #
input wire qsfp_0_rx_ptp_rst, input wire qsfp_0_rx_ptp_rst,
output wire [79:0] qsfp_0_rx_ptp_time, output wire [79:0] qsfp_0_rx_ptp_time,
output wire qsfp_0_rx_enable,
input wire qsfp_0_rx_status, input wire qsfp_0_rx_status,
output wire qsfp_0_rx_lfc_en,
input wire qsfp_0_rx_lfc_req,
output wire qsfp_0_rx_lfc_ack,
output wire [7:0] qsfp_0_rx_pfc_en,
input wire [7:0] qsfp_0_rx_pfc_req,
output wire [7:0] qsfp_0_rx_pfc_ack,
input wire qsfp_0_drp_clk, input wire qsfp_0_drp_clk,
input wire qsfp_0_drp_rst, input wire qsfp_0_drp_rst,
@ -317,8 +332,12 @@ module fpga_core #
input wire [15:0] qsfp_1_tx_ptp_ts_tag, input wire [15:0] qsfp_1_tx_ptp_ts_tag,
input wire qsfp_1_tx_ptp_ts_valid, input wire qsfp_1_tx_ptp_ts_valid,
input wire qsfp_1_rx_ptp_clk, output wire qsfp_1_tx_enable,
input wire qsfp_1_rx_ptp_rst, output wire qsfp_1_tx_lfc_en,
output wire qsfp_1_tx_lfc_req,
output wire [7:0] qsfp_1_tx_pfc_en,
output wire [7:0] qsfp_1_tx_pfc_req,
input wire qsfp_1_rx_clk, input wire qsfp_1_rx_clk,
input wire qsfp_1_rx_rst, input wire qsfp_1_rx_rst,
@ -328,9 +347,18 @@ module fpga_core #
input wire qsfp_1_rx_axis_tlast, input wire qsfp_1_rx_axis_tlast,
input wire [80+1-1:0] qsfp_1_rx_axis_tuser, input wire [80+1-1:0] qsfp_1_rx_axis_tuser,
input wire qsfp_1_rx_ptp_clk,
input wire qsfp_1_rx_ptp_rst,
output wire [79:0] qsfp_1_rx_ptp_time, output wire [79:0] qsfp_1_rx_ptp_time,
output wire qsfp_1_rx_enable,
input wire qsfp_1_rx_status, input wire qsfp_1_rx_status,
output wire qsfp_1_rx_lfc_en,
input wire qsfp_1_rx_lfc_req,
output wire qsfp_1_rx_lfc_ack,
output wire [7:0] qsfp_1_rx_pfc_en,
input wire [7:0] qsfp_1_rx_pfc_req,
output wire [7:0] qsfp_1_rx_pfc_ack,
input wire qsfp_1_drp_clk, input wire qsfp_1_drp_clk,
input wire qsfp_1_drp_rst, input wire qsfp_1_drp_rst,
@ -850,7 +878,12 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_enable;
wire [PORT_COUNT-1:0] eth_tx_status; wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_tx_lfc_en;
wire [PORT_COUNT-1:0] eth_tx_lfc_req;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_rst;
@ -867,7 +900,14 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast; wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_enable;
wire [PORT_COUNT-1:0] eth_rx_status; wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] eth_rx_lfc_en;
wire [PORT_COUNT-1:0] eth_rx_lfc_req;
wire [PORT_COUNT-1:0] eth_rx_lfc_ack;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_req;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack;
wire [PTP_TS_WIDTH-1:0] qsfp_0_tx_ptp_time_int; wire [PTP_TS_WIDTH-1:0] qsfp_0_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp_1_tx_ptp_time_int; wire [PTP_TS_WIDTH-1:0] qsfp_1_tx_ptp_time_int;
@ -918,7 +958,12 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_tx_ptp_ts_valid({qsfp_1_tx_ptp_ts_valid, qsfp_0_tx_ptp_ts_valid}), .s_axis_mac_tx_ptp_ts_valid({qsfp_1_tx_ptp_ts_valid, qsfp_0_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts_ready(), .s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_enable({qsfp_1_tx_enable, qsfp_0_tx_enable}),
.mac_tx_status(2'b11), .mac_tx_status(2'b11),
.mac_tx_lfc_en({qsfp_1_tx_lfc_en, qsfp_0_tx_lfc_en}),
.mac_tx_lfc_req({qsfp_1_tx_lfc_req, qsfp_0_tx_lfc_req}),
.mac_tx_pfc_en({qsfp_1_tx_pfc_en, qsfp_0_tx_pfc_en}),
.mac_tx_pfc_req({qsfp_1_tx_pfc_req, qsfp_0_tx_pfc_req}),
.mac_rx_clk({qsfp_1_rx_clk, qsfp_0_rx_clk}), .mac_rx_clk({qsfp_1_rx_clk, qsfp_0_rx_clk}),
.mac_rx_rst({qsfp_1_rx_rst, qsfp_0_rx_rst}), .mac_rx_rst({qsfp_1_rx_rst, qsfp_0_rx_rst}),
@ -935,7 +980,14 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_rx_tlast({qsfp_1_rx_axis_tlast, qsfp_0_rx_axis_tlast}), .s_axis_mac_rx_tlast({qsfp_1_rx_axis_tlast, qsfp_0_rx_axis_tlast}),
.s_axis_mac_rx_tuser({{qsfp_1_rx_axis_tuser[80:1], 16'd0, qsfp_1_rx_axis_tuser[0]}, {qsfp_0_rx_axis_tuser[80:1], 16'd0, qsfp_0_rx_axis_tuser[0]}}), .s_axis_mac_rx_tuser({{qsfp_1_rx_axis_tuser[80:1], 16'd0, qsfp_1_rx_axis_tuser[0]}, {qsfp_0_rx_axis_tuser[80:1], 16'd0, qsfp_0_rx_axis_tuser[0]}}),
.mac_rx_enable({qsfp_1_rx_enable, qsfp_0_rx_enable}),
.mac_rx_status({qsfp_1_rx_status, qsfp_0_rx_status}), .mac_rx_status({qsfp_1_rx_status, qsfp_0_rx_status}),
.mac_rx_lfc_en({qsfp_1_rx_lfc_en, qsfp_0_rx_lfc_en}),
.mac_rx_lfc_req({qsfp_1_rx_lfc_req, qsfp_0_rx_lfc_req}),
.mac_rx_lfc_ack({qsfp_1_rx_lfc_ack, qsfp_0_rx_lfc_ack}),
.mac_rx_pfc_en({qsfp_1_rx_pfc_en, qsfp_0_rx_pfc_en}),
.mac_rx_pfc_req({qsfp_1_rx_pfc_req, qsfp_0_rx_pfc_req}),
.mac_rx_pfc_ack({qsfp_1_rx_pfc_ack, qsfp_0_rx_pfc_ack}),
// towards datapath // towards datapath
.tx_clk(eth_tx_clk), .tx_clk(eth_tx_clk),
@ -958,7 +1010,12 @@ mqnic_port_map_mac_axis_inst (
.m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid), .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready), .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.tx_enable(eth_tx_enable),
.tx_status(eth_tx_status), .tx_status(eth_tx_status),
.tx_lfc_en(eth_tx_lfc_en),
.tx_lfc_req(eth_tx_lfc_req),
.tx_pfc_en(eth_tx_pfc_en),
.tx_pfc_req(eth_tx_pfc_req),
.rx_clk(eth_rx_clk), .rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst), .rx_rst(eth_rx_rst),
@ -975,7 +1032,14 @@ mqnic_port_map_mac_axis_inst (
.m_axis_rx_tlast(axis_eth_rx_tlast), .m_axis_rx_tlast(axis_eth_rx_tlast),
.m_axis_rx_tuser(axis_eth_rx_tuser), .m_axis_rx_tuser(axis_eth_rx_tuser),
.rx_status(eth_rx_status) .rx_enable(eth_rx_enable),
.rx_status(eth_rx_status),
.rx_lfc_en(eth_rx_lfc_en),
.rx_lfc_req(eth_rx_lfc_req),
.rx_lfc_ack(eth_rx_lfc_ack),
.rx_pfc_en(eth_rx_pfc_en),
.rx_pfc_req(eth_rx_pfc_req),
.rx_pfc_ack(eth_rx_pfc_ack)
); );
mqnic_core_pcie_us #( mqnic_core_pcie_us #(
@ -1045,6 +1109,9 @@ mqnic_core_pcie_us #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(0),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1326,7 +1393,13 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_enable(eth_tx_enable),
.eth_tx_status(eth_tx_status), .eth_tx_status(eth_tx_status),
.eth_tx_lfc_en(eth_tx_lfc_en),
.eth_tx_lfc_req(eth_tx_lfc_req),
.eth_tx_pfc_en(eth_tx_pfc_en),
.eth_tx_pfc_req(eth_tx_pfc_req),
.eth_tx_fc_quanta_clk_en(0),
.eth_rx_clk(eth_rx_clk), .eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst), .eth_rx_rst(eth_rx_rst),
@ -1343,7 +1416,15 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast), .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser), .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_enable(eth_rx_enable),
.eth_rx_status(eth_rx_status), .eth_rx_status(eth_rx_status),
.eth_rx_lfc_en(eth_rx_lfc_en),
.eth_rx_lfc_req(eth_rx_lfc_req),
.eth_rx_lfc_ack(eth_rx_lfc_ack),
.eth_rx_pfc_en(eth_rx_pfc_en),
.eth_rx_pfc_req(eth_rx_pfc_req),
.eth_rx_pfc_ack(eth_rx_pfc_ack),
.eth_rx_fc_quanta_clk_en(0),
/* /*
* DDR * DDR

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -162,6 +162,8 @@ export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 131072 export PARAM_RX_FIFO_DEPTH := 131072
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

4
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -300,6 +300,8 @@ class TB(object):
self.qsfp_mac.append(mac) self.qsfp_mac.append(mac)
getattr(dut, f"qsfp_{k}_rx_status").setimmediatevalue(1) getattr(dut, f"qsfp_{k}_rx_status").setimmediatevalue(1)
getattr(dut, f"qsfp_{k}_rx_lfc_req").setimmediatevalue(0)
getattr(dut, f"qsfp_{k}_rx_pfc_req").setimmediatevalue(0)
cocotb.start_soon(Clock(getattr(dut, f"qsfp_{k}_drp_clk"), 8, units="ns").start()) cocotb.start_soon(Clock(getattr(dut, f"qsfp_{k}_drp_clk"), 8, units="ns").start())
getattr(dut, f"qsfp_{k}_drp_rst").setimmediatevalue(0) getattr(dut, f"qsfp_{k}_drp_rst").setimmediatevalue(0)
@ -726,6 +728,8 @@ def test_fpga_core(request):
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072 parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

4
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -63,6 +63,10 @@ SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/mac_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_ctrl_tx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params ENABLE_PADDING "1" dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1" dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64" dict set params MIN_FRAME_LENGTH "64"

4
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
View File

@ -63,6 +63,10 @@ SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/mac_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_ctrl_tx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params ENABLE_PADDING "1" dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1" dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64" dict set params MIN_FRAME_LENGTH "64"

6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
View File

@ -60,10 +60,14 @@ SYN_FILES += rtl/common/tx_scheduler_ctrl_tdma.v
SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/tdma_ber.v SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/mac_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_ctrl_tx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
View File

@ -113,6 +113,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params ENABLE_PADDING "1" dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1" dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64" dict set params MIN_FRAME_LENGTH "64"

4
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,8 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter ENABLE_PADDING = 1, parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1, parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64, parameter MIN_FRAME_LENGTH = 64,
@ -1740,6 +1742,8 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING), .ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC), .ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),

134
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -81,6 +81,8 @@ module fpga_core #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter ENABLE_PADDING = 1, parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1, parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64, parameter MIN_FRAME_LENGTH = 64,
@ -997,7 +999,12 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_enable;
wire [PORT_COUNT-1:0] eth_tx_status; wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_tx_lfc_en;
wire [PORT_COUNT-1:0] eth_tx_lfc_req;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_rst;
@ -1012,7 +1019,14 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast; wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_enable;
wire [PORT_COUNT-1:0] eth_rx_status; wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] eth_rx_lfc_en;
wire [PORT_COUNT-1:0] eth_rx_lfc_req;
wire [PORT_COUNT-1:0] eth_rx_lfc_ack;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_req;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack;
wire [PORT_COUNT-1:0] port_xgmii_tx_clk; wire [PORT_COUNT-1:0] port_xgmii_tx_clk;
wire [PORT_COUNT-1:0] port_xgmii_tx_rst; wire [PORT_COUNT-1:0] port_xgmii_tx_rst;
@ -1085,12 +1099,15 @@ generate
.PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE), .TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH), .TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TS_CTRL_IN_TUSER(0),
.TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE), .RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH), .RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
.PFC_ENABLE(PFC_ENABLE),
.PAUSE_ENABLE(LFC_ENABLE)
) )
eth_mac_inst ( eth_mac_inst (
.tx_clk(port_xgmii_tx_clk[n]), .tx_clk(port_xgmii_tx_clk[n]),
@ -1098,6 +1115,9 @@ generate
.rx_clk(port_xgmii_rx_clk[n]), .rx_clk(port_xgmii_rx_clk[n]),
.rx_rst(port_xgmii_rx_rst[n]), .rx_rst(port_xgmii_rx_rst[n]),
/*
* AXI input
*/
.tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
.tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]),
.tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]),
@ -1105,30 +1125,121 @@ generate
.tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]),
.tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]),
/*
* AXI output
*/
.rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
.rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]),
.rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]),
.rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]),
.rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]),
/*
* XGMII interface
*/
.xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]),
.xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]),
.xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]),
.xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]),
/*
* PTP
*/
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req(eth_tx_lfc_req[n +: 1]),
.tx_lfc_resend(1'b0),
.rx_lfc_en(eth_rx_lfc_en[n +: 1]),
.rx_lfc_req(eth_rx_lfc_req[n +: 1]),
.rx_lfc_ack(eth_rx_lfc_ack[n +: 1]),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req(eth_tx_pfc_req[n*8 +: 8]),
.tx_pfc_resend(1'b0),
.rx_pfc_en(eth_rx_pfc_en[n*8 +: 8]),
.rx_pfc_req(eth_rx_pfc_req[n*8 +: 8]),
.rx_pfc_ack(eth_rx_pfc_ack[n*8 +: 8]),
/*
* Pause interface
*/
.tx_lfc_pause_en(1'b1),
.tx_pause_req(1'b0),
.tx_pause_ack(),
/*
* Status
*/
.tx_start_packet(),
.tx_error_underflow(), .tx_error_underflow(),
.rx_start_packet(),
.rx_error_bad_frame(), .rx_error_bad_frame(),
.rx_error_bad_fcs(), .rx_error_bad_fcs(),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
.stat_tx_lfc_xon(),
.stat_tx_lfc_xoff(),
.stat_tx_lfc_paused(),
.stat_tx_pfc_pkt(),
.stat_tx_pfc_xon(),
.stat_tx_pfc_xoff(),
.stat_tx_pfc_paused(),
.stat_rx_lfc_pkt(),
.stat_rx_lfc_xon(),
.stat_rx_lfc_xoff(),
.stat_rx_lfc_paused(),
.stat_rx_pfc_pkt(),
.stat_rx_pfc_xon(),
.stat_rx_pfc_xoff(),
.stat_rx_pfc_paused(),
/*
* Configuration
*/
.cfg_ifg(8'd12), .cfg_ifg(8'd12),
.cfg_tx_enable(1'b1), .cfg_tx_enable(eth_tx_enable[n +: 1]),
.cfg_rx_enable(1'b1) .cfg_rx_enable(eth_rx_enable[n +: 1]),
.cfg_mcf_rx_eth_dst_mcast(48'h01_80_C2_00_00_01),
.cfg_mcf_rx_check_eth_dst_mcast(1'b1),
.cfg_mcf_rx_eth_dst_ucast(48'd0),
.cfg_mcf_rx_check_eth_dst_ucast(1'b0),
.cfg_mcf_rx_eth_src(48'd0),
.cfg_mcf_rx_check_eth_src(1'b0),
.cfg_mcf_rx_eth_type(16'h8808),
.cfg_mcf_rx_opcode_lfc(16'h0001),
.cfg_mcf_rx_check_opcode_lfc(eth_rx_lfc_en[n +: 1]),
.cfg_mcf_rx_opcode_pfc(16'h0101),
.cfg_mcf_rx_check_opcode_pfc(eth_rx_pfc_en[n*8 +: 8] != 0),
.cfg_mcf_rx_forward(1'b0),
.cfg_mcf_rx_enable(eth_rx_lfc_en[n +: 1] || eth_rx_pfc_en[n*8 +: 8]),
.cfg_tx_lfc_eth_dst(48'h01_80_C2_00_00_01),
.cfg_tx_lfc_eth_src(48'h80_23_31_43_54_4C),
.cfg_tx_lfc_eth_type(16'h8808),
.cfg_tx_lfc_opcode(16'h0001),
.cfg_tx_lfc_en(eth_tx_lfc_en[n +: 1]),
.cfg_tx_lfc_quanta(16'hffff),
.cfg_tx_lfc_refresh(16'h7fff),
.cfg_tx_pfc_eth_dst(48'h01_80_C2_00_00_01),
.cfg_tx_pfc_eth_src(48'h80_23_31_43_54_4C),
.cfg_tx_pfc_eth_type(16'h8808),
.cfg_tx_pfc_opcode(16'h0101),
.cfg_tx_pfc_en(eth_tx_pfc_en[n*8 +: 8] != 0),
.cfg_tx_pfc_quanta({8{16'hffff}}),
.cfg_tx_pfc_refresh({8{16'h7fff}}),
.cfg_rx_lfc_opcode(16'h0001),
.cfg_rx_lfc_en(eth_rx_lfc_en[n +: 1]),
.cfg_rx_pfc_opcode(16'h0101),
.cfg_rx_pfc_en(eth_rx_pfc_en[n*8 +: 8] != 0)
); );
end end
@ -1202,6 +1313,9 @@ mqnic_core_pcie_us #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(0),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1483,7 +1597,13 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_enable(eth_tx_enable),
.eth_tx_status(eth_tx_status), .eth_tx_status(eth_tx_status),
.eth_tx_lfc_en(eth_tx_lfc_en),
.eth_tx_lfc_req(eth_tx_lfc_req),
.eth_tx_pfc_en(eth_tx_pfc_en),
.eth_tx_pfc_req(eth_tx_pfc_req),
.eth_tx_fc_quanta_clk_en(0),
.eth_rx_clk(eth_rx_clk), .eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst), .eth_rx_rst(eth_rx_rst),
@ -1500,7 +1620,15 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast), .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser), .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_enable(eth_rx_enable),
.eth_rx_status(eth_rx_status), .eth_rx_status(eth_rx_status),
.eth_rx_lfc_en(eth_rx_lfc_en),
.eth_rx_lfc_req(eth_rx_lfc_req),
.eth_rx_lfc_ack(eth_rx_lfc_ack),
.eth_rx_pfc_en(eth_rx_pfc_en),
.eth_rx_pfc_req(eth_rx_pfc_req),
.eth_rx_pfc_ack(eth_rx_pfc_ack),
.eth_rx_fc_quanta_clk_en(0),
/* /*
* DDR * DDR

6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -63,6 +63,10 @@ VERILOG_SOURCES += ../../rtl/common/i2c_single_reg.v
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
@ -168,6 +172,8 @@ export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 32768 export PARAM_RX_FIFO_DEPTH := 32768
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

38
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -3,6 +3,7 @@
import logging import logging
import os import os
import struct
import sys import sys
import scapy.utils import scapy.utils
@ -17,7 +18,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.triggers import RisingEdge, FallingEdge, Timer
from cocotbext.axi import AxiStreamBus from cocotbext.axi import AxiStreamBus
from cocotbext.eth import XgmiiSource, XgmiiSink from cocotbext.eth import XgmiiSource, XgmiiSink, XgmiiFrame
from cocotbext.pcie.core import RootComplex from cocotbext.pcie.core import RootComplex
from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
@ -530,6 +531,35 @@ async def run_test_nic(dut):
tb.loopback_enable = False tb.loopback_enable = False
if tb.driver.interfaces[0].if_feature_lfc:
tb.log.info("Test LFC pause frame RX")
await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN)
await tb.driver.hw_regs.read_dword(0)
lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000)
await tb.qsfp_source[0][0].send(XgmiiFrame.from_payload(bytes(lfc_xoff)))
count = 16
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
if tb.driver.interfaces[0].if_feature_rx_csum:
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
await RisingEdge(dut.clk_250mhz) await RisingEdge(dut.clk_250mhz)
await RisingEdge(dut.clk_250mhz) await RisingEdge(dut.clk_250mhz)
@ -603,6 +633,10 @@ def test_fpga_core(request):
os.path.join(eth_rtl_dir, "eth_mac_10g.v"), os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "lfsr.v"), os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
@ -709,6 +743,8 @@ def test_fpga_core(request):
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 32768 parameters['RX_FIFO_DEPTH'] = 32768
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

2
fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
View File

@ -101,6 +101,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params TX_FIFO_DEPTH "32768" dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "131072" dict set params RX_FIFO_DEPTH "131072"
dict set params MAX_TX_SIZE "9214" dict set params MAX_TX_SIZE "9214"

2
fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -101,6 +101,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params TX_FIFO_DEPTH "32768" dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "131072" dict set params RX_FIFO_DEPTH "131072"
dict set params MAX_TX_SIZE "9214" dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/AU200/fpga_100g/ip/cmac_usplus.tcl
View File

@ -7,8 +7,10 @@ set_property -dict [list \
CONFIG.USER_INTERFACE {AXIS} \ CONFIG.USER_INTERFACE {AXIS} \
CONFIG.GT_DRP_CLK {125} \ CONFIG.GT_DRP_CLK {125} \
CONFIG.GT_LOCATION {0} \ CONFIG.GT_LOCATION {0} \
CONFIG.TX_FLOW_CONTROL {0} \ CONFIG.TX_FLOW_CONTROL {1} \
CONFIG.RX_FLOW_CONTROL {0} \ CONFIG.RX_FLOW_CONTROL {1} \
CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \
CONFIG.RX_CHECK_ACK {1} \
CONFIG.INCLUDE_RS_FEC {1} \ CONFIG.INCLUDE_RS_FEC {1} \
CONFIG.ENABLE_TIME_STAMPING {1} CONFIG.ENABLE_TIME_STAMPING {1}
] [get_ips cmac_usplus] ] [get_ips cmac_usplus]

90
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -71,6 +71,8 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072, parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -1109,7 +1111,20 @@ wire qsfp0_drp_we;
wire [15:0] qsfp0_drp_do; wire [15:0] qsfp0_drp_do;
wire qsfp0_drp_rdy; wire qsfp0_drp_rdy;
wire qsfp0_rx_status; wire qsfp0_tx_enable;
wire qsfp0_tx_lfc_en;
wire qsfp0_tx_lfc_req;
wire [7:0] qsfp0_tx_pfc_en;
wire [7:0] qsfp0_tx_pfc_req;
wire qsfp0_rx_enable;
wire qsfp0_rx_status;
wire qsfp0_rx_lfc_en;
wire qsfp0_rx_lfc_req;
wire qsfp0_rx_lfc_ack;
wire [7:0] qsfp0_rx_pfc_en;
wire [7:0] qsfp0_rx_pfc_req;
wire [7:0] qsfp0_rx_pfc_ack;
wire qsfp0_gtpowergood; wire qsfp0_gtpowergood;
@ -1204,6 +1219,12 @@ qsfp0_cmac_inst (
.tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int), .tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int),
.tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int), .tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int),
.tx_enable(qsfp0_tx_enable),
.tx_lfc_en(qsfp0_tx_lfc_en),
.tx_lfc_req(qsfp0_tx_lfc_req),
.tx_pfc_en(qsfp0_tx_pfc_en),
.tx_pfc_req(qsfp0_tx_pfc_req),
.rx_clk(qsfp0_rx_clk_int), .rx_clk(qsfp0_rx_clk_int),
.rx_rst(qsfp0_rx_rst_int), .rx_rst(qsfp0_rx_rst_int),
@ -1217,7 +1238,14 @@ qsfp0_cmac_inst (
.rx_ptp_rst(qsfp0_rx_ptp_rst_int), .rx_ptp_rst(qsfp0_rx_ptp_rst_int),
.rx_ptp_time(qsfp0_rx_ptp_time_int), .rx_ptp_time(qsfp0_rx_ptp_time_int),
.rx_status(qsfp0_rx_status) .rx_enable(qsfp0_rx_enable),
.rx_status(qsfp0_rx_status),
.rx_lfc_en(qsfp0_rx_lfc_en),
.rx_lfc_req(qsfp0_rx_lfc_req),
.rx_lfc_ack(qsfp0_rx_lfc_ack),
.rx_pfc_en(qsfp0_rx_pfc_en),
.rx_pfc_req(qsfp0_rx_pfc_req),
.rx_pfc_ack(qsfp0_rx_pfc_ack)
); );
// QSFP1 CMAC // QSFP1 CMAC
@ -1261,7 +1289,20 @@ wire qsfp1_drp_we;
wire [15:0] qsfp1_drp_do; wire [15:0] qsfp1_drp_do;
wire qsfp1_drp_rdy; wire qsfp1_drp_rdy;
wire qsfp1_rx_status; wire qsfp1_tx_enable;
wire qsfp1_tx_lfc_en;
wire qsfp1_tx_lfc_req;
wire [7:0] qsfp1_tx_pfc_en;
wire [7:0] qsfp1_tx_pfc_req;
wire qsfp1_rx_enable;
wire qsfp1_rx_status;
wire qsfp1_rx_lfc_en;
wire qsfp1_rx_lfc_req;
wire qsfp1_rx_lfc_ack;
wire [7:0] qsfp1_rx_pfc_en;
wire [7:0] qsfp1_rx_pfc_req;
wire [7:0] qsfp1_rx_pfc_ack;
wire qsfp1_gtpowergood; wire qsfp1_gtpowergood;
@ -1354,6 +1395,12 @@ qsfp1_cmac_inst (
.tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int), .tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int),
.tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int), .tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int),
.tx_enable(qsfp1_tx_enable),
.tx_lfc_en(qsfp1_tx_lfc_en),
.tx_lfc_req(qsfp1_tx_lfc_req),
.tx_pfc_en(qsfp1_tx_pfc_en),
.tx_pfc_req(qsfp1_tx_pfc_req),
.rx_clk(qsfp1_rx_clk_int), .rx_clk(qsfp1_rx_clk_int),
.rx_rst(qsfp1_rx_rst_int), .rx_rst(qsfp1_rx_rst_int),
@ -1367,7 +1414,14 @@ qsfp1_cmac_inst (
.rx_ptp_rst(qsfp1_rx_ptp_rst_int), .rx_ptp_rst(qsfp1_rx_ptp_rst_int),
.rx_ptp_time(qsfp1_rx_ptp_time_int), .rx_ptp_time(qsfp1_rx_ptp_time_int),
.rx_status(qsfp1_rx_status) .rx_enable(qsfp1_rx_enable),
.rx_status(qsfp1_rx_status),
.rx_lfc_en(qsfp1_rx_lfc_en),
.rx_lfc_req(qsfp1_rx_lfc_req),
.rx_lfc_ack(qsfp1_rx_lfc_ack),
.rx_pfc_en(qsfp1_rx_pfc_en),
.rx_pfc_req(qsfp1_rx_pfc_req),
.rx_pfc_ack(qsfp1_rx_pfc_ack)
); );
wire ptp_clk; wire ptp_clk;
@ -2001,6 +2055,8 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -2205,6 +2261,12 @@ core_inst (
.qsfp0_tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int), .qsfp0_tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int),
.qsfp0_tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int), .qsfp0_tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int),
.qsfp0_tx_enable(qsfp0_tx_enable),
.qsfp0_tx_lfc_en(qsfp0_tx_lfc_en),
.qsfp0_tx_lfc_req(qsfp0_tx_lfc_req),
.qsfp0_tx_pfc_en(qsfp0_tx_pfc_en),
.qsfp0_tx_pfc_req(qsfp0_tx_pfc_req),
.qsfp0_rx_clk(qsfp0_rx_clk_int), .qsfp0_rx_clk(qsfp0_rx_clk_int),
.qsfp0_rx_rst(qsfp0_rx_rst_int), .qsfp0_rx_rst(qsfp0_rx_rst_int),
.qsfp0_rx_axis_tdata(qsfp0_rx_axis_tdata_int), .qsfp0_rx_axis_tdata(qsfp0_rx_axis_tdata_int),
@ -2216,7 +2278,14 @@ core_inst (
.qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int), .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
.qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int), .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
.qsfp0_rx_enable(qsfp0_rx_enable),
.qsfp0_rx_status(qsfp0_rx_status), .qsfp0_rx_status(qsfp0_rx_status),
.qsfp0_rx_lfc_en(qsfp0_rx_lfc_en),
.qsfp0_rx_lfc_req(qsfp0_rx_lfc_req),
.qsfp0_rx_lfc_ack(qsfp0_rx_lfc_ack),
.qsfp0_rx_pfc_en(qsfp0_rx_pfc_en),
.qsfp0_rx_pfc_req(qsfp0_rx_pfc_req),
.qsfp0_rx_pfc_ack(qsfp0_rx_pfc_ack),
.qsfp0_drp_clk(qsfp0_drp_clk), .qsfp0_drp_clk(qsfp0_drp_clk),
.qsfp0_drp_rst(qsfp0_drp_rst), .qsfp0_drp_rst(qsfp0_drp_rst),
@ -2246,6 +2315,12 @@ core_inst (
.qsfp1_tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int), .qsfp1_tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int),
.qsfp1_tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int), .qsfp1_tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int),
.qsfp1_tx_enable(qsfp1_tx_enable),
.qsfp1_tx_lfc_en(qsfp1_tx_lfc_en),
.qsfp1_tx_lfc_req(qsfp1_tx_lfc_req),
.qsfp1_tx_pfc_en(qsfp1_tx_pfc_en),
.qsfp1_tx_pfc_req(qsfp1_tx_pfc_req),
.qsfp1_rx_clk(qsfp1_rx_clk_int), .qsfp1_rx_clk(qsfp1_rx_clk_int),
.qsfp1_rx_rst(qsfp1_rx_rst_int), .qsfp1_rx_rst(qsfp1_rx_rst_int),
.qsfp1_rx_axis_tdata(qsfp1_rx_axis_tdata_int), .qsfp1_rx_axis_tdata(qsfp1_rx_axis_tdata_int),
@ -2257,7 +2332,14 @@ core_inst (
.qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int), .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
.qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int), .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
.qsfp1_rx_enable(qsfp1_rx_enable),
.qsfp1_rx_status(qsfp1_rx_status), .qsfp1_rx_status(qsfp1_rx_status),
.qsfp1_rx_lfc_en(qsfp1_rx_lfc_en),
.qsfp1_rx_lfc_req(qsfp1_rx_lfc_req),
.qsfp1_rx_lfc_ack(qsfp1_rx_lfc_ack),
.qsfp1_rx_pfc_en(qsfp1_rx_pfc_en),
.qsfp1_rx_pfc_req(qsfp1_rx_pfc_req),
.qsfp1_rx_pfc_ack(qsfp1_rx_pfc_ack),
.qsfp1_drp_clk(qsfp1_drp_clk), .qsfp1_drp_clk(qsfp1_drp_clk),
.qsfp1_drp_rst(qsfp1_drp_rst), .qsfp1_drp_rst(qsfp1_drp_rst),

83
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -77,6 +77,8 @@ module fpga_core #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072, parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -283,6 +285,12 @@ module fpga_core #
input wire [15:0] qsfp0_tx_ptp_ts_tag, input wire [15:0] qsfp0_tx_ptp_ts_tag,
input wire qsfp0_tx_ptp_ts_valid, input wire qsfp0_tx_ptp_ts_valid,
output wire qsfp0_tx_enable,
output wire qsfp0_tx_lfc_en,
output wire qsfp0_tx_lfc_req,
output wire [7:0] qsfp0_tx_pfc_en,
output wire [7:0] qsfp0_tx_pfc_req,
input wire qsfp0_rx_clk, input wire qsfp0_rx_clk,
input wire qsfp0_rx_rst, input wire qsfp0_rx_rst,
@ -296,7 +304,14 @@ module fpga_core #
input wire qsfp0_rx_ptp_rst, input wire qsfp0_rx_ptp_rst,
output wire [79:0] qsfp0_rx_ptp_time, output wire [79:0] qsfp0_rx_ptp_time,
output wire qsfp0_rx_enable,
input wire qsfp0_rx_status, input wire qsfp0_rx_status,
output wire qsfp0_rx_lfc_en,
input wire qsfp0_rx_lfc_req,
output wire qsfp0_rx_lfc_ack,
output wire [7:0] qsfp0_rx_pfc_en,
input wire [7:0] qsfp0_rx_pfc_req,
output wire [7:0] qsfp0_rx_pfc_ack,
input wire qsfp0_drp_clk, input wire qsfp0_drp_clk,
input wire qsfp0_drp_rst, input wire qsfp0_drp_rst,
@ -328,6 +343,12 @@ module fpga_core #
input wire [15:0] qsfp1_tx_ptp_ts_tag, input wire [15:0] qsfp1_tx_ptp_ts_tag,
input wire qsfp1_tx_ptp_ts_valid, input wire qsfp1_tx_ptp_ts_valid,
output wire qsfp1_tx_enable,
output wire qsfp1_tx_lfc_en,
output wire qsfp1_tx_lfc_req,
output wire [7:0] qsfp1_tx_pfc_en,
output wire [7:0] qsfp1_tx_pfc_req,
input wire qsfp1_rx_clk, input wire qsfp1_rx_clk,
input wire qsfp1_rx_rst, input wire qsfp1_rx_rst,
@ -341,7 +362,14 @@ module fpga_core #
input wire qsfp1_rx_ptp_rst, input wire qsfp1_rx_ptp_rst,
output wire [79:0] qsfp1_rx_ptp_time, output wire [79:0] qsfp1_rx_ptp_time,
output wire qsfp1_rx_enable,
input wire qsfp1_rx_status, input wire qsfp1_rx_status,
output wire qsfp1_rx_lfc_en,
input wire qsfp1_rx_lfc_req,
output wire qsfp1_rx_lfc_ack,
output wire [7:0] qsfp1_rx_pfc_en,
input wire [7:0] qsfp1_rx_pfc_req,
output wire [7:0] qsfp1_rx_pfc_ack,
input wire qsfp1_drp_clk, input wire qsfp1_drp_clk,
input wire qsfp1_drp_rst, input wire qsfp1_drp_rst,
@ -837,7 +865,12 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_enable;
wire [PORT_COUNT-1:0] eth_tx_status; wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_tx_lfc_en;
wire [PORT_COUNT-1:0] eth_tx_lfc_req;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_rst;
@ -854,7 +887,14 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast; wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_enable;
wire [PORT_COUNT-1:0] eth_rx_status; wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] eth_rx_lfc_en;
wire [PORT_COUNT-1:0] eth_rx_lfc_req;
wire [PORT_COUNT-1:0] eth_rx_lfc_ack;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_req;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack;
wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int; wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int; wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
@ -905,7 +945,12 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}), .s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts_ready(), .s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_enable({qsfp1_tx_enable, qsfp0_tx_enable}),
.mac_tx_status(2'b11), .mac_tx_status(2'b11),
.mac_tx_lfc_en({qsfp1_tx_lfc_en, qsfp0_tx_lfc_en}),
.mac_tx_lfc_req({qsfp1_tx_lfc_req, qsfp0_tx_lfc_req}),
.mac_tx_pfc_en({qsfp1_tx_pfc_en, qsfp0_tx_pfc_en}),
.mac_tx_pfc_req({qsfp1_tx_pfc_req, qsfp0_tx_pfc_req}),
.mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}), .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}),
.mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}), .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}),
@ -922,7 +967,14 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}), .s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
.s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}), .s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
.mac_rx_enable({qsfp1_rx_enable, qsfp0_rx_enable}),
.mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}), .mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}),
.mac_rx_lfc_en({qsfp1_rx_lfc_en, qsfp0_rx_lfc_en}),
.mac_rx_lfc_req({qsfp1_rx_lfc_req, qsfp0_rx_lfc_req}),
.mac_rx_lfc_ack({qsfp1_rx_lfc_ack, qsfp0_rx_lfc_ack}),
.mac_rx_pfc_en({qsfp1_rx_pfc_en, qsfp0_rx_pfc_en}),
.mac_rx_pfc_req({qsfp1_rx_pfc_req, qsfp0_rx_pfc_req}),
.mac_rx_pfc_ack({qsfp1_rx_pfc_ack, qsfp0_rx_pfc_ack}),
// towards datapath // towards datapath
.tx_clk(eth_tx_clk), .tx_clk(eth_tx_clk),
@ -945,7 +997,12 @@ mqnic_port_map_mac_axis_inst (
.m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid), .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready), .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.tx_enable(eth_tx_enable),
.tx_status(eth_tx_status), .tx_status(eth_tx_status),
.tx_lfc_en(eth_tx_lfc_en),
.tx_lfc_req(eth_tx_lfc_req),
.tx_pfc_en(eth_tx_pfc_en),
.tx_pfc_req(eth_tx_pfc_req),
.rx_clk(eth_rx_clk), .rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst), .rx_rst(eth_rx_rst),
@ -962,7 +1019,14 @@ mqnic_port_map_mac_axis_inst (
.m_axis_rx_tlast(axis_eth_rx_tlast), .m_axis_rx_tlast(axis_eth_rx_tlast),
.m_axis_rx_tuser(axis_eth_rx_tuser), .m_axis_rx_tuser(axis_eth_rx_tuser),
.rx_status(eth_rx_status) .rx_enable(eth_rx_enable),
.rx_status(eth_rx_status),
.rx_lfc_en(eth_rx_lfc_en),
.rx_lfc_req(eth_rx_lfc_req),
.rx_lfc_ack(eth_rx_lfc_ack),
.rx_pfc_en(eth_rx_pfc_en),
.rx_pfc_req(eth_rx_pfc_req),
.rx_pfc_ack(eth_rx_pfc_ack)
); );
mqnic_core_pcie_us #( mqnic_core_pcie_us #(
@ -1032,6 +1096,9 @@ mqnic_core_pcie_us #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(0),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1313,7 +1380,13 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_enable(eth_tx_enable),
.eth_tx_status(eth_tx_status), .eth_tx_status(eth_tx_status),
.eth_tx_lfc_en(eth_tx_lfc_en),
.eth_tx_lfc_req(eth_tx_lfc_req),
.eth_tx_pfc_en(eth_tx_pfc_en),
.eth_tx_pfc_req(eth_tx_pfc_req),
.eth_tx_fc_quanta_clk_en(0),
.eth_rx_clk(eth_rx_clk), .eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst), .eth_rx_rst(eth_rx_rst),
@ -1330,7 +1403,15 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast), .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser), .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_enable(eth_rx_enable),
.eth_rx_status(eth_rx_status), .eth_rx_status(eth_rx_status),
.eth_rx_lfc_en(eth_rx_lfc_en),
.eth_rx_lfc_req(eth_rx_lfc_req),
.eth_rx_lfc_ack(eth_rx_lfc_ack),
.eth_rx_pfc_en(eth_rx_pfc_en),
.eth_rx_pfc_req(eth_rx_pfc_req),
.eth_rx_pfc_ack(eth_rx_pfc_ack),
.eth_rx_fc_quanta_clk_en(0),
/* /*
* DDR * DDR

2
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -161,6 +161,8 @@ export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 131072 export PARAM_RX_FIFO_DEPTH := 131072
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

6
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -300,6 +300,8 @@ class TB(object):
self.qsfp_mac.append(mac) self.qsfp_mac.append(mac)
getattr(dut, f"qsfp{k}_rx_status").setimmediatevalue(1) getattr(dut, f"qsfp{k}_rx_status").setimmediatevalue(1)
getattr(dut, f"qsfp{k}_rx_lfc_req").setimmediatevalue(0)
getattr(dut, f"qsfp{k}_rx_pfc_req").setimmediatevalue(0)
cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_drp_clk"), 8, units="ns").start()) cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_drp_clk"), 8, units="ns").start())
getattr(dut, f"qsfp{k}_drp_rst").setimmediatevalue(0) getattr(dut, f"qsfp{k}_drp_rst").setimmediatevalue(0)
@ -307,7 +309,7 @@ class TB(object):
getattr(dut, f"qsfp{k}_drp_rdy").setimmediatevalue(0) getattr(dut, f"qsfp{k}_drp_rdy").setimmediatevalue(0)
getattr(dut, f"qsfp{k}_modprsl").setimmediatevalue(0) getattr(dut, f"qsfp{k}_modprsl").setimmediatevalue(0)
getattr(dut, f"qsfp{k}_intl").setimmediatevalue(0) getattr(dut, f"qsfp{k}_intl").setimmediatevalue(1)
dut.sw.setimmediatevalue(0) dut.sw.setimmediatevalue(0)
@ -723,6 +725,8 @@ def test_fpga_core(request):
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072 parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

4
fpga/mqnic/AU200/fpga_25g/fpga/Makefile
View File

@ -62,6 +62,10 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/mac_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_ctrl_tx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v

2
fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params ENABLE_PADDING "1" dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1" dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64" dict set params MIN_FRAME_LENGTH "64"

4
fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
View File

@ -62,6 +62,10 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/mac_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_ctrl_tx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v

2
fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params ENABLE_PADDING "1" dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1" dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64" dict set params MIN_FRAME_LENGTH "64"

4
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,8 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter ENABLE_PADDING = 1, parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1, parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64, parameter MIN_FRAME_LENGTH = 64,
@ -2137,6 +2139,8 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING), .ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC), .ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),

134
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -81,6 +81,8 @@ module fpga_core #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter ENABLE_PADDING = 1, parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1, parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64, parameter MIN_FRAME_LENGTH = 64,
@ -979,7 +981,12 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_enable;
wire [PORT_COUNT-1:0] eth_tx_status; wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_tx_lfc_en;
wire [PORT_COUNT-1:0] eth_tx_lfc_req;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_rst;
@ -994,7 +1001,14 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast; wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_enable;
wire [PORT_COUNT-1:0] eth_rx_status; wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] eth_rx_lfc_en;
wire [PORT_COUNT-1:0] eth_rx_lfc_req;
wire [PORT_COUNT-1:0] eth_rx_lfc_ack;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_req;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack;
wire [PORT_COUNT-1:0] port_xgmii_tx_clk; wire [PORT_COUNT-1:0] port_xgmii_tx_clk;
wire [PORT_COUNT-1:0] port_xgmii_tx_rst; wire [PORT_COUNT-1:0] port_xgmii_tx_rst;
@ -1067,12 +1081,15 @@ generate
.PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE), .TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH), .TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TS_CTRL_IN_TUSER(0),
.TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE), .RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH), .RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
.PFC_ENABLE(PFC_ENABLE),
.PAUSE_ENABLE(LFC_ENABLE)
) )
eth_mac_inst ( eth_mac_inst (
.tx_clk(port_xgmii_tx_clk[n]), .tx_clk(port_xgmii_tx_clk[n]),
@ -1080,6 +1097,9 @@ generate
.rx_clk(port_xgmii_rx_clk[n]), .rx_clk(port_xgmii_rx_clk[n]),
.rx_rst(port_xgmii_rx_rst[n]), .rx_rst(port_xgmii_rx_rst[n]),
/*
* AXI input
*/
.tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
.tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]),
.tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]),
@ -1087,30 +1107,121 @@ generate
.tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]),
.tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]),
/*
* AXI output
*/
.rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
.rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]),
.rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]),
.rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]),
.rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]),
/*
* XGMII interface
*/
.xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]),
.xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]),
.xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]),
.xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]),
/*
* PTP
*/
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req(eth_tx_lfc_req[n +: 1]),
.tx_lfc_resend(1'b0),
.rx_lfc_en(eth_rx_lfc_en[n +: 1]),
.rx_lfc_req(eth_rx_lfc_req[n +: 1]),
.rx_lfc_ack(eth_rx_lfc_ack[n +: 1]),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req(eth_tx_pfc_req[n*8 +: 8]),
.tx_pfc_resend(1'b0),
.rx_pfc_en(eth_rx_pfc_en[n*8 +: 8]),
.rx_pfc_req(eth_rx_pfc_req[n*8 +: 8]),
.rx_pfc_ack(eth_rx_pfc_ack[n*8 +: 8]),
/*
* Pause interface
*/
.tx_lfc_pause_en(1'b1),
.tx_pause_req(1'b0),
.tx_pause_ack(),
/*
* Status
*/
.tx_start_packet(),
.tx_error_underflow(), .tx_error_underflow(),
.rx_start_packet(),
.rx_error_bad_frame(), .rx_error_bad_frame(),
.rx_error_bad_fcs(), .rx_error_bad_fcs(),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
.stat_tx_lfc_xon(),
.stat_tx_lfc_xoff(),
.stat_tx_lfc_paused(),
.stat_tx_pfc_pkt(),
.stat_tx_pfc_xon(),
.stat_tx_pfc_xoff(),
.stat_tx_pfc_paused(),
.stat_rx_lfc_pkt(),
.stat_rx_lfc_xon(),
.stat_rx_lfc_xoff(),
.stat_rx_lfc_paused(),
.stat_rx_pfc_pkt(),
.stat_rx_pfc_xon(),
.stat_rx_pfc_xoff(),
.stat_rx_pfc_paused(),
/*
* Configuration
*/
.cfg_ifg(8'd12), .cfg_ifg(8'd12),
.cfg_tx_enable(1'b1), .cfg_tx_enable(eth_tx_enable[n +: 1]),
.cfg_rx_enable(1'b1) .cfg_rx_enable(eth_rx_enable[n +: 1]),
.cfg_mcf_rx_eth_dst_mcast(48'h01_80_C2_00_00_01),
.cfg_mcf_rx_check_eth_dst_mcast(1'b1),
.cfg_mcf_rx_eth_dst_ucast(48'd0),
.cfg_mcf_rx_check_eth_dst_ucast(1'b0),
.cfg_mcf_rx_eth_src(48'd0),
.cfg_mcf_rx_check_eth_src(1'b0),
.cfg_mcf_rx_eth_type(16'h8808),
.cfg_mcf_rx_opcode_lfc(16'h0001),
.cfg_mcf_rx_check_opcode_lfc(eth_rx_lfc_en[n +: 1]),
.cfg_mcf_rx_opcode_pfc(16'h0101),
.cfg_mcf_rx_check_opcode_pfc(eth_rx_pfc_en[n*8 +: 8] != 0),
.cfg_mcf_rx_forward(1'b0),
.cfg_mcf_rx_enable(eth_rx_lfc_en[n +: 1] || eth_rx_pfc_en[n*8 +: 8]),
.cfg_tx_lfc_eth_dst(48'h01_80_C2_00_00_01),
.cfg_tx_lfc_eth_src(48'h80_23_31_43_54_4C),
.cfg_tx_lfc_eth_type(16'h8808),
.cfg_tx_lfc_opcode(16'h0001),
.cfg_tx_lfc_en(eth_tx_lfc_en[n +: 1]),
.cfg_tx_lfc_quanta(16'hffff),
.cfg_tx_lfc_refresh(16'h7fff),
.cfg_tx_pfc_eth_dst(48'h01_80_C2_00_00_01),
.cfg_tx_pfc_eth_src(48'h80_23_31_43_54_4C),
.cfg_tx_pfc_eth_type(16'h8808),
.cfg_tx_pfc_opcode(16'h0101),
.cfg_tx_pfc_en(eth_tx_pfc_en[n*8 +: 8] != 0),
.cfg_tx_pfc_quanta({8{16'hffff}}),
.cfg_tx_pfc_refresh({8{16'h7fff}}),
.cfg_rx_lfc_opcode(16'h0001),
.cfg_rx_lfc_en(eth_rx_lfc_en[n +: 1]),
.cfg_rx_pfc_opcode(16'h0101),
.cfg_rx_pfc_en(eth_rx_pfc_en[n*8 +: 8] != 0)
); );
end end
@ -1184,6 +1295,9 @@ mqnic_core_pcie_us #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(0),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1465,7 +1579,13 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_enable(eth_tx_enable),
.eth_tx_status(eth_tx_status), .eth_tx_status(eth_tx_status),
.eth_tx_lfc_en(eth_tx_lfc_en),
.eth_tx_lfc_req(eth_tx_lfc_req),
.eth_tx_pfc_en(eth_tx_pfc_en),
.eth_tx_pfc_req(eth_tx_pfc_req),
.eth_tx_fc_quanta_clk_en(0),
.eth_rx_clk(eth_rx_clk), .eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst), .eth_rx_rst(eth_rx_rst),
@ -1482,7 +1602,15 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast), .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser), .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_enable(eth_rx_enable),
.eth_rx_status(eth_rx_status), .eth_rx_status(eth_rx_status),
.eth_rx_lfc_en(eth_rx_lfc_en),
.eth_rx_lfc_req(eth_rx_lfc_req),
.eth_rx_lfc_ack(eth_rx_lfc_ack),
.eth_rx_pfc_en(eth_rx_pfc_en),
.eth_rx_pfc_req(eth_rx_pfc_req),
.eth_rx_pfc_ack(eth_rx_pfc_ack),
.eth_rx_fc_quanta_clk_en(0),
/* /*
* DDR * DDR

6
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -62,6 +62,10 @@ VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
@ -167,6 +171,8 @@ export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 32768 export PARAM_RX_FIFO_DEPTH := 32768
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

38
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -3,6 +3,7 @@
import logging import logging
import os import os
import struct
import sys import sys
import scapy.utils import scapy.utils
@ -17,7 +18,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.triggers import RisingEdge, FallingEdge, Timer
from cocotbext.axi import AxiStreamBus, AxiLiteBus, AxiLiteRam from cocotbext.axi import AxiStreamBus, AxiLiteBus, AxiLiteRam
from cocotbext.eth import XgmiiSource, XgmiiSink from cocotbext.eth import XgmiiSource, XgmiiSink, XgmiiFrame
from cocotbext.pcie.core import RootComplex from cocotbext.pcie.core import RootComplex
from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
@ -528,6 +529,35 @@ async def run_test_nic(dut):
tb.loopback_enable = False tb.loopback_enable = False
if tb.driver.interfaces[0].if_feature_lfc:
tb.log.info("Test LFC pause frame RX")
await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN)
await tb.driver.hw_regs.read_dword(0)
lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000)
await tb.qsfp_source[0][0].send(XgmiiFrame.from_payload(bytes(lfc_xoff)))
count = 16
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
if tb.driver.interfaces[0].if_feature_rx_csum:
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
await RisingEdge(dut.clk_250mhz) await RisingEdge(dut.clk_250mhz)
await RisingEdge(dut.clk_250mhz) await RisingEdge(dut.clk_250mhz)
@ -600,6 +630,10 @@ def test_fpga_core(request):
os.path.join(eth_rtl_dir, "eth_mac_10g.v"), os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "lfsr.v"), os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
@ -706,6 +740,8 @@ def test_fpga_core(request):
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 32768 parameters['RX_FIFO_DEPTH'] = 32768
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

2
fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
View File

@ -101,6 +101,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params TX_FIFO_DEPTH "32768" dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "131072" dict set params RX_FIFO_DEPTH "131072"
dict set params MAX_TX_SIZE "9214" dict set params MAX_TX_SIZE "9214"

2
fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -101,6 +101,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params TX_FIFO_DEPTH "32768" dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "131072" dict set params RX_FIFO_DEPTH "131072"
dict set params MAX_TX_SIZE "9214" dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/AU250/fpga_100g/ip/cmac_usplus.tcl
View File

@ -7,8 +7,10 @@ set_property -dict [list \
CONFIG.USER_INTERFACE {AXIS} \ CONFIG.USER_INTERFACE {AXIS} \
CONFIG.GT_DRP_CLK {125} \ CONFIG.GT_DRP_CLK {125} \
CONFIG.GT_LOCATION {0} \ CONFIG.GT_LOCATION {0} \
CONFIG.TX_FLOW_CONTROL {0} \ CONFIG.TX_FLOW_CONTROL {1} \
CONFIG.RX_FLOW_CONTROL {0} \ CONFIG.RX_FLOW_CONTROL {1} \
CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \
CONFIG.RX_CHECK_ACK {1} \
CONFIG.INCLUDE_RS_FEC {1} \ CONFIG.INCLUDE_RS_FEC {1} \
CONFIG.ENABLE_TIME_STAMPING {1} CONFIG.ENABLE_TIME_STAMPING {1}
] [get_ips cmac_usplus] ] [get_ips cmac_usplus]

90
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -71,6 +71,8 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072, parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -1109,7 +1111,20 @@ wire qsfp0_drp_we;
wire [15:0] qsfp0_drp_do; wire [15:0] qsfp0_drp_do;
wire qsfp0_drp_rdy; wire qsfp0_drp_rdy;
wire qsfp0_rx_status; wire qsfp0_tx_enable;
wire qsfp0_tx_lfc_en;
wire qsfp0_tx_lfc_req;
wire [7:0] qsfp0_tx_pfc_en;
wire [7:0] qsfp0_tx_pfc_req;
wire qsfp0_rx_enable;
wire qsfp0_rx_status;
wire qsfp0_rx_lfc_en;
wire qsfp0_rx_lfc_req;
wire qsfp0_rx_lfc_ack;
wire [7:0] qsfp0_rx_pfc_en;
wire [7:0] qsfp0_rx_pfc_req;
wire [7:0] qsfp0_rx_pfc_ack;
wire qsfp0_gtpowergood; wire qsfp0_gtpowergood;
@ -1204,6 +1219,12 @@ qsfp0_cmac_inst (
.tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int), .tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int),
.tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int), .tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int),
.tx_enable(qsfp0_tx_enable),
.tx_lfc_en(qsfp0_tx_lfc_en),
.tx_lfc_req(qsfp0_tx_lfc_req),
.tx_pfc_en(qsfp0_tx_pfc_en),
.tx_pfc_req(qsfp0_tx_pfc_req),
.rx_clk(qsfp0_rx_clk_int), .rx_clk(qsfp0_rx_clk_int),
.rx_rst(qsfp0_rx_rst_int), .rx_rst(qsfp0_rx_rst_int),
@ -1217,7 +1238,14 @@ qsfp0_cmac_inst (
.rx_ptp_rst(qsfp0_rx_ptp_rst_int), .rx_ptp_rst(qsfp0_rx_ptp_rst_int),
.rx_ptp_time(qsfp0_rx_ptp_time_int), .rx_ptp_time(qsfp0_rx_ptp_time_int),
.rx_status(qsfp0_rx_status) .rx_enable(qsfp0_rx_enable),
.rx_status(qsfp0_rx_status),
.rx_lfc_en(qsfp0_rx_lfc_en),
.rx_lfc_req(qsfp0_rx_lfc_req),
.rx_lfc_ack(qsfp0_rx_lfc_ack),
.rx_pfc_en(qsfp0_rx_pfc_en),
.rx_pfc_req(qsfp0_rx_pfc_req),
.rx_pfc_ack(qsfp0_rx_pfc_ack)
); );
// QSFP1 CMAC // QSFP1 CMAC
@ -1261,7 +1289,20 @@ wire qsfp1_drp_we;
wire [15:0] qsfp1_drp_do; wire [15:0] qsfp1_drp_do;
wire qsfp1_drp_rdy; wire qsfp1_drp_rdy;
wire qsfp1_rx_status; wire qsfp1_tx_enable;
wire qsfp1_tx_lfc_en;
wire qsfp1_tx_lfc_req;
wire [7:0] qsfp1_tx_pfc_en;
wire [7:0] qsfp1_tx_pfc_req;
wire qsfp1_rx_enable;
wire qsfp1_rx_status;
wire qsfp1_rx_lfc_en;
wire qsfp1_rx_lfc_req;
wire qsfp1_rx_lfc_ack;
wire [7:0] qsfp1_rx_pfc_en;
wire [7:0] qsfp1_rx_pfc_req;
wire [7:0] qsfp1_rx_pfc_ack;
wire qsfp1_gtpowergood; wire qsfp1_gtpowergood;
@ -1354,6 +1395,12 @@ qsfp1_cmac_inst (
.tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int), .tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int),
.tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int), .tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int),
.tx_enable(qsfp1_tx_enable),
.tx_lfc_en(qsfp1_tx_lfc_en),
.tx_lfc_req(qsfp1_tx_lfc_req),
.tx_pfc_en(qsfp1_tx_pfc_en),
.tx_pfc_req(qsfp1_tx_pfc_req),
.rx_clk(qsfp1_rx_clk_int), .rx_clk(qsfp1_rx_clk_int),
.rx_rst(qsfp1_rx_rst_int), .rx_rst(qsfp1_rx_rst_int),
@ -1367,7 +1414,14 @@ qsfp1_cmac_inst (
.rx_ptp_rst(qsfp1_rx_ptp_rst_int), .rx_ptp_rst(qsfp1_rx_ptp_rst_int),
.rx_ptp_time(qsfp1_rx_ptp_time_int), .rx_ptp_time(qsfp1_rx_ptp_time_int),
.rx_status(qsfp1_rx_status) .rx_enable(qsfp1_rx_enable),
.rx_status(qsfp1_rx_status),
.rx_lfc_en(qsfp1_rx_lfc_en),
.rx_lfc_req(qsfp1_rx_lfc_req),
.rx_lfc_ack(qsfp1_rx_lfc_ack),
.rx_pfc_en(qsfp1_rx_pfc_en),
.rx_pfc_req(qsfp1_rx_pfc_req),
.rx_pfc_ack(qsfp1_rx_pfc_ack)
); );
wire ptp_clk; wire ptp_clk;
@ -2001,6 +2055,8 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -2205,6 +2261,12 @@ core_inst (
.qsfp0_tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int), .qsfp0_tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int),
.qsfp0_tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int), .qsfp0_tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int),
.qsfp0_tx_enable(qsfp0_tx_enable),
.qsfp0_tx_lfc_en(qsfp0_tx_lfc_en),
.qsfp0_tx_lfc_req(qsfp0_tx_lfc_req),
.qsfp0_tx_pfc_en(qsfp0_tx_pfc_en),
.qsfp0_tx_pfc_req(qsfp0_tx_pfc_req),
.qsfp0_rx_clk(qsfp0_rx_clk_int), .qsfp0_rx_clk(qsfp0_rx_clk_int),
.qsfp0_rx_rst(qsfp0_rx_rst_int), .qsfp0_rx_rst(qsfp0_rx_rst_int),
.qsfp0_rx_axis_tdata(qsfp0_rx_axis_tdata_int), .qsfp0_rx_axis_tdata(qsfp0_rx_axis_tdata_int),
@ -2216,7 +2278,14 @@ core_inst (
.qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int), .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
.qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int), .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
.qsfp0_rx_enable(qsfp0_rx_enable),
.qsfp0_rx_status(qsfp0_rx_status), .qsfp0_rx_status(qsfp0_rx_status),
.qsfp0_rx_lfc_en(qsfp0_rx_lfc_en),
.qsfp0_rx_lfc_req(qsfp0_rx_lfc_req),
.qsfp0_rx_lfc_ack(qsfp0_rx_lfc_ack),
.qsfp0_rx_pfc_en(qsfp0_rx_pfc_en),
.qsfp0_rx_pfc_req(qsfp0_rx_pfc_req),
.qsfp0_rx_pfc_ack(qsfp0_rx_pfc_ack),
.qsfp0_drp_clk(qsfp0_drp_clk), .qsfp0_drp_clk(qsfp0_drp_clk),
.qsfp0_drp_rst(qsfp0_drp_rst), .qsfp0_drp_rst(qsfp0_drp_rst),
@ -2246,6 +2315,12 @@ core_inst (
.qsfp1_tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int), .qsfp1_tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int),
.qsfp1_tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int), .qsfp1_tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int),
.qsfp1_tx_enable(qsfp1_tx_enable),
.qsfp1_tx_lfc_en(qsfp1_tx_lfc_en),
.qsfp1_tx_lfc_req(qsfp1_tx_lfc_req),
.qsfp1_tx_pfc_en(qsfp1_tx_pfc_en),
.qsfp1_tx_pfc_req(qsfp1_tx_pfc_req),
.qsfp1_rx_clk(qsfp1_rx_clk_int), .qsfp1_rx_clk(qsfp1_rx_clk_int),
.qsfp1_rx_rst(qsfp1_rx_rst_int), .qsfp1_rx_rst(qsfp1_rx_rst_int),
.qsfp1_rx_axis_tdata(qsfp1_rx_axis_tdata_int), .qsfp1_rx_axis_tdata(qsfp1_rx_axis_tdata_int),
@ -2257,7 +2332,14 @@ core_inst (
.qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int), .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
.qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int), .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
.qsfp1_rx_enable(qsfp1_rx_enable),
.qsfp1_rx_status(qsfp1_rx_status), .qsfp1_rx_status(qsfp1_rx_status),
.qsfp1_rx_lfc_en(qsfp1_rx_lfc_en),
.qsfp1_rx_lfc_req(qsfp1_rx_lfc_req),
.qsfp1_rx_lfc_ack(qsfp1_rx_lfc_ack),
.qsfp1_rx_pfc_en(qsfp1_rx_pfc_en),
.qsfp1_rx_pfc_req(qsfp1_rx_pfc_req),
.qsfp1_rx_pfc_ack(qsfp1_rx_pfc_ack),
.qsfp1_drp_clk(qsfp1_drp_clk), .qsfp1_drp_clk(qsfp1_drp_clk),
.qsfp1_drp_rst(qsfp1_drp_rst), .qsfp1_drp_rst(qsfp1_drp_rst),

83
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -77,6 +77,8 @@ module fpga_core #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter TX_FIFO_DEPTH = 32768, parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072, parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214, parameter MAX_TX_SIZE = 9214,
@ -283,6 +285,12 @@ module fpga_core #
input wire [15:0] qsfp0_tx_ptp_ts_tag, input wire [15:0] qsfp0_tx_ptp_ts_tag,
input wire qsfp0_tx_ptp_ts_valid, input wire qsfp0_tx_ptp_ts_valid,
output wire qsfp0_tx_enable,
output wire qsfp0_tx_lfc_en,
output wire qsfp0_tx_lfc_req,
output wire [7:0] qsfp0_tx_pfc_en,
output wire [7:0] qsfp0_tx_pfc_req,
input wire qsfp0_rx_clk, input wire qsfp0_rx_clk,
input wire qsfp0_rx_rst, input wire qsfp0_rx_rst,
@ -296,7 +304,14 @@ module fpga_core #
input wire qsfp0_rx_ptp_rst, input wire qsfp0_rx_ptp_rst,
output wire [79:0] qsfp0_rx_ptp_time, output wire [79:0] qsfp0_rx_ptp_time,
output wire qsfp0_rx_enable,
input wire qsfp0_rx_status, input wire qsfp0_rx_status,
output wire qsfp0_rx_lfc_en,
input wire qsfp0_rx_lfc_req,
output wire qsfp0_rx_lfc_ack,
output wire [7:0] qsfp0_rx_pfc_en,
input wire [7:0] qsfp0_rx_pfc_req,
output wire [7:0] qsfp0_rx_pfc_ack,
input wire qsfp0_drp_clk, input wire qsfp0_drp_clk,
input wire qsfp0_drp_rst, input wire qsfp0_drp_rst,
@ -328,6 +343,12 @@ module fpga_core #
input wire [15:0] qsfp1_tx_ptp_ts_tag, input wire [15:0] qsfp1_tx_ptp_ts_tag,
input wire qsfp1_tx_ptp_ts_valid, input wire qsfp1_tx_ptp_ts_valid,
output wire qsfp1_tx_enable,
output wire qsfp1_tx_lfc_en,
output wire qsfp1_tx_lfc_req,
output wire [7:0] qsfp1_tx_pfc_en,
output wire [7:0] qsfp1_tx_pfc_req,
input wire qsfp1_rx_clk, input wire qsfp1_rx_clk,
input wire qsfp1_rx_rst, input wire qsfp1_rx_rst,
@ -341,7 +362,14 @@ module fpga_core #
input wire qsfp1_rx_ptp_rst, input wire qsfp1_rx_ptp_rst,
output wire [79:0] qsfp1_rx_ptp_time, output wire [79:0] qsfp1_rx_ptp_time,
output wire qsfp1_rx_enable,
input wire qsfp1_rx_status, input wire qsfp1_rx_status,
output wire qsfp1_rx_lfc_en,
input wire qsfp1_rx_lfc_req,
output wire qsfp1_rx_lfc_ack,
output wire [7:0] qsfp1_rx_pfc_en,
input wire [7:0] qsfp1_rx_pfc_req,
output wire [7:0] qsfp1_rx_pfc_ack,
input wire qsfp1_drp_clk, input wire qsfp1_drp_clk,
input wire qsfp1_drp_rst, input wire qsfp1_drp_rst,
@ -837,7 +865,12 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_enable;
wire [PORT_COUNT-1:0] eth_tx_status; wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_tx_lfc_en;
wire [PORT_COUNT-1:0] eth_tx_lfc_req;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_rst;
@ -854,7 +887,14 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast; wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_enable;
wire [PORT_COUNT-1:0] eth_rx_status; wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] eth_rx_lfc_en;
wire [PORT_COUNT-1:0] eth_rx_lfc_req;
wire [PORT_COUNT-1:0] eth_rx_lfc_ack;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_en;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_req;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack;
wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int; wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int; wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
@ -905,7 +945,12 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}), .s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts_ready(), .s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_enable({qsfp1_tx_enable, qsfp0_tx_enable}),
.mac_tx_status(2'b11), .mac_tx_status(2'b11),
.mac_tx_lfc_en({qsfp1_tx_lfc_en, qsfp0_tx_lfc_en}),
.mac_tx_lfc_req({qsfp1_tx_lfc_req, qsfp0_tx_lfc_req}),
.mac_tx_pfc_en({qsfp1_tx_pfc_en, qsfp0_tx_pfc_en}),
.mac_tx_pfc_req({qsfp1_tx_pfc_req, qsfp0_tx_pfc_req}),
.mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}), .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}),
.mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}), .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}),
@ -922,7 +967,14 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}), .s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
.s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}), .s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
.mac_rx_enable({qsfp1_rx_enable, qsfp0_rx_enable}),
.mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}), .mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}),
.mac_rx_lfc_en({qsfp1_rx_lfc_en, qsfp0_rx_lfc_en}),
.mac_rx_lfc_req({qsfp1_rx_lfc_req, qsfp0_rx_lfc_req}),
.mac_rx_lfc_ack({qsfp1_rx_lfc_ack, qsfp0_rx_lfc_ack}),
.mac_rx_pfc_en({qsfp1_rx_pfc_en, qsfp0_rx_pfc_en}),
.mac_rx_pfc_req({qsfp1_rx_pfc_req, qsfp0_rx_pfc_req}),
.mac_rx_pfc_ack({qsfp1_rx_pfc_ack, qsfp0_rx_pfc_ack}),
// towards datapath // towards datapath
.tx_clk(eth_tx_clk), .tx_clk(eth_tx_clk),
@ -945,7 +997,12 @@ mqnic_port_map_mac_axis_inst (
.m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid), .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready), .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.tx_enable(eth_tx_enable),
.tx_status(eth_tx_status), .tx_status(eth_tx_status),
.tx_lfc_en(eth_tx_lfc_en),
.tx_lfc_req(eth_tx_lfc_req),
.tx_pfc_en(eth_tx_pfc_en),
.tx_pfc_req(eth_tx_pfc_req),
.rx_clk(eth_rx_clk), .rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst), .rx_rst(eth_rx_rst),
@ -962,7 +1019,14 @@ mqnic_port_map_mac_axis_inst (
.m_axis_rx_tlast(axis_eth_rx_tlast), .m_axis_rx_tlast(axis_eth_rx_tlast),
.m_axis_rx_tuser(axis_eth_rx_tuser), .m_axis_rx_tuser(axis_eth_rx_tuser),
.rx_status(eth_rx_status) .rx_enable(eth_rx_enable),
.rx_status(eth_rx_status),
.rx_lfc_en(eth_rx_lfc_en),
.rx_lfc_req(eth_rx_lfc_req),
.rx_lfc_ack(eth_rx_lfc_ack),
.rx_pfc_en(eth_rx_pfc_en),
.rx_pfc_req(eth_rx_pfc_req),
.rx_pfc_ack(eth_rx_pfc_ack)
); );
mqnic_core_pcie_us #( mqnic_core_pcie_us #(
@ -1032,6 +1096,9 @@ mqnic_core_pcie_us #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.MAC_CTRL_ENABLE(0),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
@ -1313,7 +1380,13 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_enable(eth_tx_enable),
.eth_tx_status(eth_tx_status), .eth_tx_status(eth_tx_status),
.eth_tx_lfc_en(eth_tx_lfc_en),
.eth_tx_lfc_req(eth_tx_lfc_req),
.eth_tx_pfc_en(eth_tx_pfc_en),
.eth_tx_pfc_req(eth_tx_pfc_req),
.eth_tx_fc_quanta_clk_en(0),
.eth_rx_clk(eth_rx_clk), .eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst), .eth_rx_rst(eth_rx_rst),
@ -1330,7 +1403,15 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast), .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser), .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_enable(eth_rx_enable),
.eth_rx_status(eth_rx_status), .eth_rx_status(eth_rx_status),
.eth_rx_lfc_en(eth_rx_lfc_en),
.eth_rx_lfc_req(eth_rx_lfc_req),
.eth_rx_lfc_ack(eth_rx_lfc_ack),
.eth_rx_pfc_en(eth_rx_pfc_en),
.eth_rx_pfc_req(eth_rx_pfc_req),
.eth_rx_pfc_ack(eth_rx_pfc_ack),
.eth_rx_fc_quanta_clk_en(0),
/* /*
* DDR * DDR

2
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -161,6 +161,8 @@ export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_CHECKSUM_ENABLE := 1 export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_LFC_ENABLE := 1
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
export PARAM_TX_FIFO_DEPTH := 32768 export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 131072 export PARAM_RX_FIFO_DEPTH := 131072
export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_TX_SIZE := 9214

6
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -300,6 +300,8 @@ class TB(object):
self.qsfp_mac.append(mac) self.qsfp_mac.append(mac)
getattr(dut, f"qsfp{k}_rx_status").setimmediatevalue(1) getattr(dut, f"qsfp{k}_rx_status").setimmediatevalue(1)
getattr(dut, f"qsfp{k}_rx_lfc_req").setimmediatevalue(0)
getattr(dut, f"qsfp{k}_rx_pfc_req").setimmediatevalue(0)
cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_drp_clk"), 8, units="ns").start()) cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_drp_clk"), 8, units="ns").start())
getattr(dut, f"qsfp{k}_drp_rst").setimmediatevalue(0) getattr(dut, f"qsfp{k}_drp_rst").setimmediatevalue(0)
@ -307,7 +309,7 @@ class TB(object):
getattr(dut, f"qsfp{k}_drp_rdy").setimmediatevalue(0) getattr(dut, f"qsfp{k}_drp_rdy").setimmediatevalue(0)
getattr(dut, f"qsfp{k}_modprsl").setimmediatevalue(0) getattr(dut, f"qsfp{k}_modprsl").setimmediatevalue(0)
getattr(dut, f"qsfp{k}_intl").setimmediatevalue(0) getattr(dut, f"qsfp{k}_intl").setimmediatevalue(1)
dut.sw.setimmediatevalue(0) dut.sw.setimmediatevalue(0)
@ -723,6 +725,8 @@ def test_fpga_core(request):
parameters['TX_CHECKSUM_ENABLE'] = 1 parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['LFC_ENABLE'] = 1
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
parameters['TX_FIFO_DEPTH'] = 32768 parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072 parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_TX_SIZE'] = 9214

4
fpga/mqnic/AU250/fpga_25g/fpga/Makefile
View File

@ -62,6 +62,10 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/mac_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_ctrl_tx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v

2
fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params ENABLE_PADDING "1" dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1" dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64" dict set params MIN_FRAME_LENGTH "64"

4
fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
View File

@ -62,6 +62,10 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/mac_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_ctrl_tx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_rx.v
SYN_FILES += lib/eth/rtl/mac_pause_ctrl_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v

2
fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,8 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1" dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1" dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1"
dict set params PFC_ENABLE "1"
dict set params LFC_ENABLE [dict get $params PFC_ENABLE]
dict set params ENABLE_PADDING "1" dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1" dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64" dict set params MIN_FRAME_LENGTH "64"

4
fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,8 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1, parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1, parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter ENABLE_PADDING = 1, parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1, parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64, parameter MIN_FRAME_LENGTH = 64,
@ -2137,6 +2139,8 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING), .ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC), .ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),

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