diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
index 8bfad341a..672420fee 100644
--- a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
@@ -143,9 +143,8 @@ dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
 dict set params HBM_CH "32"
 dict set params HBM_ENABLE "0"
-dict set params HBM_GROUP_SIZE "32"
-dict set params AXI_HBM_ADDR_WIDTH "33"
-dict set params AXI_HBM_MAX_BURST_LEN "256"
+dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+dict set params AXI_HBM_MAX_BURST_LEN "16"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"
@@ -203,6 +202,24 @@ if {[dict get $params DDR_ENABLE]} {
     dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
 }
 
+# HBM settings
+if {[dict get $params HBM_ENABLE]} {
+    set hbm [get_ips hbm_0]
+
+    # switch configuration
+    if {[dict get $params HBM_GROUP_SIZE] == 1} {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
+        dict set params HBM_GROUP_SIZE "1"
+        dict set params AXI_HBM_ADDR_WIDTH "28"
+    } else {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
+        dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+        dict set params AXI_HBM_ADDR_WIDTH "33"
+    }
+}
+
 # PCIe IP core settings
 set pcie [get_ips pcie4c_uscale_plus_0]
 
diff --git a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl
index fd98a1ece..4b7856247 100644
--- a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -143,9 +143,8 @@ dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
 dict set params HBM_CH "32"
 dict set params HBM_ENABLE "1"
-dict set params HBM_GROUP_SIZE "32"
-dict set params AXI_HBM_ADDR_WIDTH "33"
-dict set params AXI_HBM_MAX_BURST_LEN "256"
+dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+dict set params AXI_HBM_MAX_BURST_LEN "16"
 
 # Application block configuration
 dict set params APP_ID "32'h12348001"
@@ -203,6 +202,24 @@ if {[dict get $params DDR_ENABLE]} {
     dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
 }
 
+# HBM settings
+if {[dict get $params HBM_ENABLE]} {
+    set hbm [get_ips hbm_0]
+
+    # switch configuration
+    if {[dict get $params HBM_GROUP_SIZE] == 1} {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
+        dict set params HBM_GROUP_SIZE "1"
+        dict set params AXI_HBM_ADDR_WIDTH "28"
+    } else {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
+        dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+        dict set params AXI_HBM_ADDR_WIDTH "33"
+    }
+}
+
 # PCIe IP core settings
 set pcie [get_ips pcie4c_uscale_plus_0]
 
diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
index c129e6764..198d9da91 100644
--- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
@@ -118,9 +118,9 @@ module fpga #
     parameter AXI_DDR_NARROW_BURST = 0,
     parameter HBM_CH = 32,
     parameter HBM_ENABLE = 0,
-    parameter HBM_GROUP_SIZE = 32,
+    parameter HBM_GROUP_SIZE = HBM_CH,
     parameter AXI_HBM_ADDR_WIDTH = 33,
-    parameter AXI_HBM_MAX_BURST_LEN = 256,
+    parameter AXI_HBM_MAX_BURST_LEN = 16,
 
     // Application block configuration
     parameter APP_ID = 32'h00000000,
diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
index e26b575cc..a64145d0c 100644
--- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
@@ -125,12 +125,12 @@ module fpga_core #
     parameter AXI_DDR_NARROW_BURST = 0,
     parameter HBM_CH = 32,
     parameter HBM_ENABLE = 0,
-    parameter HBM_GROUP_SIZE = 32,
+    parameter HBM_GROUP_SIZE = HBM_CH,
     parameter AXI_HBM_DATA_WIDTH = 256,
     parameter AXI_HBM_ADDR_WIDTH = 33,
     parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
     parameter AXI_HBM_ID_WIDTH = 6,
-    parameter AXI_HBM_MAX_BURST_LEN = 256,
+    parameter AXI_HBM_MAX_BURST_LEN = 16,
 
     // Application block configuration
     parameter APP_ID = 32'h00000000,
diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
index e581a5f36..979102071 100644
--- a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
@@ -155,9 +155,8 @@ dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
 dict set params HBM_CH "32"
 dict set params HBM_ENABLE "0"
-dict set params HBM_GROUP_SIZE "32"
-dict set params AXI_HBM_ADDR_WIDTH "33"
-dict set params AXI_HBM_MAX_BURST_LEN "256"
+dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+dict set params AXI_HBM_MAX_BURST_LEN "16"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"
@@ -216,6 +215,24 @@ if {[dict get $params DDR_ENABLE]} {
     dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
 }
 
+# HBM settings
+if {[dict get $params HBM_ENABLE]} {
+    set hbm [get_ips hbm_0]
+
+    # switch configuration
+    if {[dict get $params HBM_GROUP_SIZE] == 1} {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
+        dict set params HBM_GROUP_SIZE "1"
+        dict set params AXI_HBM_ADDR_WIDTH "28"
+    } else {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
+        dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+        dict set params AXI_HBM_ADDR_WIDTH "33"
+    }
+}
+
 # PCIe IP core settings
 set pcie [get_ips pcie4c_uscale_plus_0]
 
diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
index 8155cfd31..863cb561b 100644
--- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
@@ -155,9 +155,8 @@ dict set params AXI_DDR_ID_WIDTH "8"
 dict set params AXI_DDR_MAX_BURST_LEN "256"
 dict set params HBM_CH "32"
 dict set params HBM_ENABLE "0"
-dict set params HBM_GROUP_SIZE "32"
-dict set params AXI_HBM_ADDR_WIDTH "33"
-dict set params AXI_HBM_MAX_BURST_LEN "256"
+dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+dict set params AXI_HBM_MAX_BURST_LEN "16"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"
@@ -216,6 +215,24 @@ if {[dict get $params DDR_ENABLE]} {
     dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
 }
 
+# HBM settings
+if {[dict get $params HBM_ENABLE]} {
+    set hbm [get_ips hbm_0]
+
+    # switch configuration
+    if {[dict get $params HBM_GROUP_SIZE] == 1} {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
+        dict set params HBM_GROUP_SIZE "1"
+        dict set params AXI_HBM_ADDR_WIDTH "28"
+    } else {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
+        dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+        dict set params AXI_HBM_ADDR_WIDTH "33"
+    }
+}
+
 # PCIe IP core settings
 set pcie [get_ips pcie4c_uscale_plus_0]
 
diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
index 7eb7754fc..37ccd89e4 100644
--- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
@@ -121,9 +121,9 @@ module fpga #
     parameter AXI_DDR_NARROW_BURST = 0,
     parameter HBM_CH = 32,
     parameter HBM_ENABLE = 0,
-    parameter HBM_GROUP_SIZE = 32,
+    parameter HBM_GROUP_SIZE = HBM_CH,
     parameter AXI_HBM_ADDR_WIDTH = 33,
-    parameter AXI_HBM_MAX_BURST_LEN = 256,
+    parameter AXI_HBM_MAX_BURST_LEN = 16,
 
     // Application block configuration
     parameter APP_ID = 32'h00000000,
diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
index b226b72ed..694f45343 100644
--- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
@@ -132,12 +132,12 @@ module fpga_core #
     parameter AXI_DDR_NARROW_BURST = 0,
     parameter HBM_CH = 32,
     parameter HBM_ENABLE = 0,
-    parameter HBM_GROUP_SIZE = 32,
+    parameter HBM_GROUP_SIZE = HBM_CH,
     parameter AXI_HBM_DATA_WIDTH = 256,
     parameter AXI_HBM_ADDR_WIDTH = 33,
     parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
     parameter AXI_HBM_ID_WIDTH = 6,
-    parameter AXI_HBM_MAX_BURST_LEN = 256,
+    parameter AXI_HBM_MAX_BURST_LEN = 16,
 
     // Application block configuration
     parameter APP_ID = 32'h00000000,
diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
index 3f5039871..973b9516e 100644
--- a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
@@ -139,9 +139,8 @@ dict set params RX_RAM_SIZE "131072"
 # RAM configuration
 dict set params HBM_CH "32"
 dict set params HBM_ENABLE "0"
-dict set params HBM_GROUP_SIZE "32"
-dict set params AXI_HBM_ADDR_WIDTH "33"
-dict set params AXI_HBM_MAX_BURST_LEN "256"
+dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+dict set params AXI_HBM_MAX_BURST_LEN "16"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"
@@ -186,6 +185,24 @@ dict set params STAT_PCIE_ENABLE "1"
 dict set params STAT_INC_WIDTH "24"
 dict set params STAT_ID_WIDTH "12"
 
+# HBM settings
+if {[dict get $params HBM_ENABLE]} {
+    set hbm [get_ips hbm_0]
+
+    # switch configuration
+    if {[dict get $params HBM_GROUP_SIZE] == 1} {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
+        dict set params HBM_GROUP_SIZE "1"
+        dict set params AXI_HBM_ADDR_WIDTH "28"
+    } else {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
+        dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+        dict set params AXI_HBM_ADDR_WIDTH "33"
+    }
+}
+
 # PCIe IP core settings
 set pcie [get_ips pcie4c_uscale_plus_0]
 
diff --git a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl
index 7f4515a56..14efa4878 100644
--- a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -139,9 +139,8 @@ dict set params RX_RAM_SIZE "131072"
 # RAM configuration
 dict set params HBM_CH "32"
 dict set params HBM_ENABLE "1"
-dict set params HBM_GROUP_SIZE "32"
-dict set params AXI_HBM_ADDR_WIDTH "33"
-dict set params AXI_HBM_MAX_BURST_LEN "256"
+dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+dict set params AXI_HBM_MAX_BURST_LEN "16"
 
 # Application block configuration
 dict set params APP_ID "32'h12348001"
@@ -186,6 +185,24 @@ dict set params STAT_PCIE_ENABLE "1"
 dict set params STAT_INC_WIDTH "24"
 dict set params STAT_ID_WIDTH "12"
 
+# HBM settings
+if {[dict get $params HBM_ENABLE]} {
+    set hbm [get_ips hbm_0]
+
+    # switch configuration
+    if {[dict get $params HBM_GROUP_SIZE] == 1} {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
+        dict set params HBM_GROUP_SIZE "1"
+        dict set params AXI_HBM_ADDR_WIDTH "28"
+    } else {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
+        dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+        dict set params AXI_HBM_ADDR_WIDTH "33"
+    }
+}
+
 # PCIe IP core settings
 set pcie [get_ips pcie4c_uscale_plus_0]
 
diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
index 944800067..c96581804 100644
--- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
@@ -111,9 +111,9 @@ module fpga #
     // RAM configuration
     parameter HBM_CH = 32,
     parameter HBM_ENABLE = 0,
-    parameter HBM_GROUP_SIZE = 32,
+    parameter HBM_GROUP_SIZE = HBM_CH,
     parameter AXI_HBM_ADDR_WIDTH = 33,
-    parameter AXI_HBM_MAX_BURST_LEN = 256,
+    parameter AXI_HBM_MAX_BURST_LEN = 16,
 
     // Application block configuration
     parameter APP_ID = 32'h00000000,
diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
index 9c4fda6af..69985b138 100644
--- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
@@ -117,12 +117,12 @@ module fpga_core #
     // RAM configuration
     parameter HBM_CH = 32,
     parameter HBM_ENABLE = 0,
-    parameter HBM_GROUP_SIZE = 32,
+    parameter HBM_GROUP_SIZE = HBM_CH,
     parameter AXI_HBM_DATA_WIDTH = 256,
     parameter AXI_HBM_ADDR_WIDTH = 33,
     parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
     parameter AXI_HBM_ID_WIDTH = 6,
-    parameter AXI_HBM_MAX_BURST_LEN = 256,
+    parameter AXI_HBM_MAX_BURST_LEN = 16,
 
     // Application block configuration
     parameter APP_ID = 32'h00000000,
diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
index 23d5f44df..5e9a2c5ac 100644
--- a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
@@ -151,9 +151,8 @@ dict set params RX_RAM_SIZE "131072"
 # RAM configuration
 dict set params HBM_CH "32"
 dict set params HBM_ENABLE "0"
-dict set params HBM_GROUP_SIZE "32"
-dict set params AXI_HBM_ADDR_WIDTH "33"
-dict set params AXI_HBM_MAX_BURST_LEN "256"
+dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+dict set params AXI_HBM_MAX_BURST_LEN "16"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"
@@ -199,6 +198,24 @@ dict set params STAT_PCIE_ENABLE "1"
 dict set params STAT_INC_WIDTH "24"
 dict set params STAT_ID_WIDTH "12"
 
+# HBM settings
+if {[dict get $params HBM_ENABLE]} {
+    set hbm [get_ips hbm_0]
+
+    # switch configuration
+    if {[dict get $params HBM_GROUP_SIZE] == 1} {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
+        dict set params HBM_GROUP_SIZE "1"
+        dict set params AXI_HBM_ADDR_WIDTH "28"
+    } else {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
+        dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+        dict set params AXI_HBM_ADDR_WIDTH "33"
+    }
+}
+
 # PCIe IP core settings
 set pcie [get_ips pcie4c_uscale_plus_0]
 
diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
index bd309dc8d..73cac740a 100644
--- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
@@ -151,9 +151,8 @@ dict set params RX_RAM_SIZE "32768"
 # RAM configuration
 dict set params HBM_CH "32"
 dict set params HBM_ENABLE "0"
-dict set params HBM_GROUP_SIZE "32"
-dict set params AXI_HBM_ADDR_WIDTH "33"
-dict set params AXI_HBM_MAX_BURST_LEN "256"
+dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+dict set params AXI_HBM_MAX_BURST_LEN "16"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"
@@ -199,6 +198,24 @@ dict set params STAT_PCIE_ENABLE "1"
 dict set params STAT_INC_WIDTH "24"
 dict set params STAT_ID_WIDTH "12"
 
+# HBM settings
+if {[dict get $params HBM_ENABLE]} {
+    set hbm [get_ips hbm_0]
+
+    # switch configuration
+    if {[dict get $params HBM_GROUP_SIZE] == 1} {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
+        dict set params HBM_GROUP_SIZE "1"
+        dict set params AXI_HBM_ADDR_WIDTH "28"
+    } else {
+        set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
+        set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
+        dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
+        dict set params AXI_HBM_ADDR_WIDTH "33"
+    }
+}
+
 # PCIe IP core settings
 set pcie [get_ips pcie4c_uscale_plus_0]
 
diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
index 2765d520e..aa034cfd1 100644
--- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
@@ -117,9 +117,9 @@ module fpga #
     // RAM configuration
     parameter HBM_CH = 32,
     parameter HBM_ENABLE = 0,
-    parameter HBM_GROUP_SIZE = 32,
+    parameter HBM_GROUP_SIZE = HBM_CH,
     parameter AXI_HBM_ADDR_WIDTH = 33,
-    parameter AXI_HBM_MAX_BURST_LEN = 256,
+    parameter AXI_HBM_MAX_BURST_LEN = 16,
 
     // Application block configuration
     parameter APP_ID = 32'h00000000,
diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
index bc13ad5fb..ee0c3e843 100644
--- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
@@ -124,12 +124,12 @@ module fpga_core #
     // RAM configuration
     parameter HBM_CH = 32,
     parameter HBM_ENABLE = 0,
-    parameter HBM_GROUP_SIZE = 32,
+    parameter HBM_GROUP_SIZE = HBM_CH,
     parameter AXI_HBM_DATA_WIDTH = 256,
     parameter AXI_HBM_ADDR_WIDTH = 33,
     parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
     parameter AXI_HBM_ID_WIDTH = 6,
-    parameter AXI_HBM_MAX_BURST_LEN = 256,
+    parameter AXI_HBM_MAX_BURST_LEN = 16,
 
     // Application block configuration
     parameter APP_ID = 32'h00000000,