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fpga/mqnic: Clean up HBM configuration

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-12-17 22:56:12 -08:00
parent 8672edfdb3
commit 9969b957d5
16 changed files with 176 additions and 40 deletions
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23
fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
View File

@ -143,9 +143,8 @@ dict set params AXI_DDR_ID_WIDTH "8"
dict set params AXI_DDR_MAX_BURST_LEN "256"
dict set params HBM_CH "32"
dict set params HBM_ENABLE "0"
dict set params HBM_GROUP_SIZE "32"
dict set params AXI_HBM_ADDR_WIDTH "33"
dict set params AXI_HBM_MAX_BURST_LEN "256"
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_MAX_BURST_LEN "16"
# Application block configuration
dict set params APP_ID "32'h00000000"
@ -203,6 +202,24 @@ if {[dict get $params DDR_ENABLE]} {
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
}
# HBM settings
if {[dict get $params HBM_ENABLE]} {
set hbm [get_ips hbm_0]
# switch configuration
if {[dict get $params HBM_GROUP_SIZE] == 1} {
set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
dict set params HBM_GROUP_SIZE "1"
dict set params AXI_HBM_ADDR_WIDTH "28"
} else {
set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_ADDR_WIDTH "33"
}
}
# PCIe IP core settings
set pcie [get_ips pcie4c_uscale_plus_0]

23
fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -143,9 +143,8 @@ dict set params AXI_DDR_ID_WIDTH "8"
dict set params AXI_DDR_MAX_BURST_LEN "256"
dict set params HBM_CH "32"
dict set params HBM_ENABLE "1"
dict set params HBM_GROUP_SIZE "32"
dict set params AXI_HBM_ADDR_WIDTH "33"
dict set params AXI_HBM_MAX_BURST_LEN "256"
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_MAX_BURST_LEN "16"
# Application block configuration
dict set params APP_ID "32'h12348001"
@ -203,6 +202,24 @@ if {[dict get $params DDR_ENABLE]} {
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
}
# HBM settings
if {[dict get $params HBM_ENABLE]} {
set hbm [get_ips hbm_0]
# switch configuration
if {[dict get $params HBM_GROUP_SIZE] == 1} {
set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
dict set params HBM_GROUP_SIZE "1"
dict set params AXI_HBM_ADDR_WIDTH "28"
} else {
set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_ADDR_WIDTH "33"
}
}
# PCIe IP core settings
set pcie [get_ips pcie4c_uscale_plus_0]

4
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
View File

@ -118,9 +118,9 @@ module fpga #
parameter AXI_DDR_NARROW_BURST = 0,
parameter HBM_CH = 32,
parameter HBM_ENABLE = 0,
parameter HBM_GROUP_SIZE = 32,
parameter HBM_GROUP_SIZE = HBM_CH,
parameter AXI_HBM_ADDR_WIDTH = 33,
parameter AXI_HBM_MAX_BURST_LEN = 256,
parameter AXI_HBM_MAX_BURST_LEN = 16,
// Application block configuration
parameter APP_ID = 32'h00000000,

4
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -125,12 +125,12 @@ module fpga_core #
parameter AXI_DDR_NARROW_BURST = 0,
parameter HBM_CH = 32,
parameter HBM_ENABLE = 0,
parameter HBM_GROUP_SIZE = 32,
parameter HBM_GROUP_SIZE = HBM_CH,
parameter AXI_HBM_DATA_WIDTH = 256,
parameter AXI_HBM_ADDR_WIDTH = 33,
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
parameter AXI_HBM_ID_WIDTH = 6,
parameter AXI_HBM_MAX_BURST_LEN = 256,
parameter AXI_HBM_MAX_BURST_LEN = 16,
// Application block configuration
parameter APP_ID = 32'h00000000,

23
fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
View File

@ -155,9 +155,8 @@ dict set params AXI_DDR_ID_WIDTH "8"
dict set params AXI_DDR_MAX_BURST_LEN "256"
dict set params HBM_CH "32"
dict set params HBM_ENABLE "0"
dict set params HBM_GROUP_SIZE "32"
dict set params AXI_HBM_ADDR_WIDTH "33"
dict set params AXI_HBM_MAX_BURST_LEN "256"
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_MAX_BURST_LEN "16"
# Application block configuration
dict set params APP_ID "32'h00000000"
@ -216,6 +215,24 @@ if {[dict get $params DDR_ENABLE]} {
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
}
# HBM settings
if {[dict get $params HBM_ENABLE]} {
set hbm [get_ips hbm_0]
# switch configuration
if {[dict get $params HBM_GROUP_SIZE] == 1} {
set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
dict set params HBM_GROUP_SIZE "1"
dict set params AXI_HBM_ADDR_WIDTH "28"
} else {
set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_ADDR_WIDTH "33"
}
}
# PCIe IP core settings
set pcie [get_ips pcie4c_uscale_plus_0]

23
fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
View File

@ -155,9 +155,8 @@ dict set params AXI_DDR_ID_WIDTH "8"
dict set params AXI_DDR_MAX_BURST_LEN "256"
dict set params HBM_CH "32"
dict set params HBM_ENABLE "0"
dict set params HBM_GROUP_SIZE "32"
dict set params AXI_HBM_ADDR_WIDTH "33"
dict set params AXI_HBM_MAX_BURST_LEN "256"
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_MAX_BURST_LEN "16"
# Application block configuration
dict set params APP_ID "32'h00000000"
@ -216,6 +215,24 @@ if {[dict get $params DDR_ENABLE]} {
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
}
# HBM settings
if {[dict get $params HBM_ENABLE]} {
set hbm [get_ips hbm_0]
# switch configuration
if {[dict get $params HBM_GROUP_SIZE] == 1} {
set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
dict set params HBM_GROUP_SIZE "1"
dict set params AXI_HBM_ADDR_WIDTH "28"
} else {
set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_ADDR_WIDTH "33"
}
}
# PCIe IP core settings
set pcie [get_ips pcie4c_uscale_plus_0]

4
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -121,9 +121,9 @@ module fpga #
parameter AXI_DDR_NARROW_BURST = 0,
parameter HBM_CH = 32,
parameter HBM_ENABLE = 0,
parameter HBM_GROUP_SIZE = 32,
parameter HBM_GROUP_SIZE = HBM_CH,
parameter AXI_HBM_ADDR_WIDTH = 33,
parameter AXI_HBM_MAX_BURST_LEN = 256,
parameter AXI_HBM_MAX_BURST_LEN = 16,
// Application block configuration
parameter APP_ID = 32'h00000000,

4
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -132,12 +132,12 @@ module fpga_core #
parameter AXI_DDR_NARROW_BURST = 0,
parameter HBM_CH = 32,
parameter HBM_ENABLE = 0,
parameter HBM_GROUP_SIZE = 32,
parameter HBM_GROUP_SIZE = HBM_CH,
parameter AXI_HBM_DATA_WIDTH = 256,
parameter AXI_HBM_ADDR_WIDTH = 33,
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
parameter AXI_HBM_ID_WIDTH = 6,
parameter AXI_HBM_MAX_BURST_LEN = 256,
parameter AXI_HBM_MAX_BURST_LEN = 16,
// Application block configuration
parameter APP_ID = 32'h00000000,

23
fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
View File

@ -139,9 +139,8 @@ dict set params RX_RAM_SIZE "131072"
# RAM configuration
dict set params HBM_CH "32"
dict set params HBM_ENABLE "0"
dict set params HBM_GROUP_SIZE "32"
dict set params AXI_HBM_ADDR_WIDTH "33"
dict set params AXI_HBM_MAX_BURST_LEN "256"
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_MAX_BURST_LEN "16"
# Application block configuration
dict set params APP_ID "32'h00000000"
@ -186,6 +185,24 @@ dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"
dict set params STAT_ID_WIDTH "12"
# HBM settings
if {[dict get $params HBM_ENABLE]} {
set hbm [get_ips hbm_0]
# switch configuration
if {[dict get $params HBM_GROUP_SIZE] == 1} {
set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
dict set params HBM_GROUP_SIZE "1"
dict set params AXI_HBM_ADDR_WIDTH "28"
} else {
set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_ADDR_WIDTH "33"
}
}
# PCIe IP core settings
set pcie [get_ips pcie4c_uscale_plus_0]

23
fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -139,9 +139,8 @@ dict set params RX_RAM_SIZE "131072"
# RAM configuration
dict set params HBM_CH "32"
dict set params HBM_ENABLE "1"
dict set params HBM_GROUP_SIZE "32"
dict set params AXI_HBM_ADDR_WIDTH "33"
dict set params AXI_HBM_MAX_BURST_LEN "256"
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_MAX_BURST_LEN "16"
# Application block configuration
dict set params APP_ID "32'h12348001"
@ -186,6 +185,24 @@ dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"
dict set params STAT_ID_WIDTH "12"
# HBM settings
if {[dict get $params HBM_ENABLE]} {
set hbm [get_ips hbm_0]
# switch configuration
if {[dict get $params HBM_GROUP_SIZE] == 1} {
set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
dict set params HBM_GROUP_SIZE "1"
dict set params AXI_HBM_ADDR_WIDTH "28"
} else {
set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_ADDR_WIDTH "33"
}
}
# PCIe IP core settings
set pcie [get_ips pcie4c_uscale_plus_0]

4
fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
View File

@ -111,9 +111,9 @@ module fpga #
// RAM configuration
parameter HBM_CH = 32,
parameter HBM_ENABLE = 0,
parameter HBM_GROUP_SIZE = 32,
parameter HBM_GROUP_SIZE = HBM_CH,
parameter AXI_HBM_ADDR_WIDTH = 33,
parameter AXI_HBM_MAX_BURST_LEN = 256,
parameter AXI_HBM_MAX_BURST_LEN = 16,
// Application block configuration
parameter APP_ID = 32'h00000000,

4
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -117,12 +117,12 @@ module fpga_core #
// RAM configuration
parameter HBM_CH = 32,
parameter HBM_ENABLE = 0,
parameter HBM_GROUP_SIZE = 32,
parameter HBM_GROUP_SIZE = HBM_CH,
parameter AXI_HBM_DATA_WIDTH = 256,
parameter AXI_HBM_ADDR_WIDTH = 33,
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
parameter AXI_HBM_ID_WIDTH = 6,
parameter AXI_HBM_MAX_BURST_LEN = 256,
parameter AXI_HBM_MAX_BURST_LEN = 16,
// Application block configuration
parameter APP_ID = 32'h00000000,

23
fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
View File

@ -151,9 +151,8 @@ dict set params RX_RAM_SIZE "131072"
# RAM configuration
dict set params HBM_CH "32"
dict set params HBM_ENABLE "0"
dict set params HBM_GROUP_SIZE "32"
dict set params AXI_HBM_ADDR_WIDTH "33"
dict set params AXI_HBM_MAX_BURST_LEN "256"
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_MAX_BURST_LEN "16"
# Application block configuration
dict set params APP_ID "32'h00000000"
@ -199,6 +198,24 @@ dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"
dict set params STAT_ID_WIDTH "12"
# HBM settings
if {[dict get $params HBM_ENABLE]} {
set hbm [get_ips hbm_0]
# switch configuration
if {[dict get $params HBM_GROUP_SIZE] == 1} {
set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
dict set params HBM_GROUP_SIZE "1"
dict set params AXI_HBM_ADDR_WIDTH "28"
} else {
set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_ADDR_WIDTH "33"
}
}
# PCIe IP core settings
set pcie [get_ips pcie4c_uscale_plus_0]

23
fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
View File

@ -151,9 +151,8 @@ dict set params RX_RAM_SIZE "32768"
# RAM configuration
dict set params HBM_CH "32"
dict set params HBM_ENABLE "0"
dict set params HBM_GROUP_SIZE "32"
dict set params AXI_HBM_ADDR_WIDTH "33"
dict set params AXI_HBM_MAX_BURST_LEN "256"
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_MAX_BURST_LEN "16"
# Application block configuration
dict set params APP_ID "32'h00000000"
@ -199,6 +198,24 @@ dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"
dict set params STAT_ID_WIDTH "12"
# HBM settings
if {[dict get $params HBM_ENABLE]} {
set hbm [get_ips hbm_0]
# switch configuration
if {[dict get $params HBM_GROUP_SIZE] == 1} {
set_property CONFIG.USER_SWITCH_ENABLE_00 "FALSE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "FALSE" $hbm
dict set params HBM_GROUP_SIZE "1"
dict set params AXI_HBM_ADDR_WIDTH "28"
} else {
set_property CONFIG.USER_SWITCH_ENABLE_00 "TRUE" $hbm
set_property CONFIG.USER_SWITCH_ENABLE_01 "TRUE" $hbm
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_ADDR_WIDTH "33"
}
}
# PCIe IP core settings
set pcie [get_ips pcie4c_uscale_plus_0]

4
fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
View File

@ -117,9 +117,9 @@ module fpga #
// RAM configuration
parameter HBM_CH = 32,
parameter HBM_ENABLE = 0,
parameter HBM_GROUP_SIZE = 32,
parameter HBM_GROUP_SIZE = HBM_CH,
parameter AXI_HBM_ADDR_WIDTH = 33,
parameter AXI_HBM_MAX_BURST_LEN = 256,
parameter AXI_HBM_MAX_BURST_LEN = 16,
// Application block configuration
parameter APP_ID = 32'h00000000,

4
fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -124,12 +124,12 @@ module fpga_core #
// RAM configuration
parameter HBM_CH = 32,
parameter HBM_ENABLE = 0,
parameter HBM_GROUP_SIZE = 32,
parameter HBM_GROUP_SIZE = HBM_CH,
parameter AXI_HBM_DATA_WIDTH = 256,
parameter AXI_HBM_ADDR_WIDTH = 33,
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
parameter AXI_HBM_ID_WIDTH = 6,
parameter AXI_HBM_MAX_BURST_LEN = 256,
parameter AXI_HBM_MAX_BURST_LEN = 16,
// Application block configuration
parameter APP_ID = 32'h00000000,