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fpga/mqnic: Clean up readmes

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich 2023-06-26 00:08:49 -07:00
parent 7d9528a6ae
commit 9a93cfb5ad
37 changed files with 321 additions and 310 deletions
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16
fpga/mqnic/250_SoC/fpga_100g/README.md
View File

@ -9,18 +9,16 @@ This design targets the BittWare 250-SoC FPGA board.
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
* RAM: 4 GB DDR4 2666 (512M x72)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the 250-SoC board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/250_SoC/fpga_25g/README.md
View File

@ -8,18 +8,16 @@ This design targets the BittWare 250-SoC FPGA board.
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* RAM: 4 GB DDR4 2666 (512M x72)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the 250-SoC board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

18
fpga/mqnic/520N_MX/fpga_25g/README.md
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@ -4,15 +4,19 @@
This design targets the BittWare 520N-MX FPGA development board.
* FPGA: 1SM21CHU2F53E2VG
* PHY: Transceiver in 10G BASE-R native mode
* FPGA: 1SM21CHU2F53E2VG
* PHY: Transceiver in 10G BASE-R native mode
## How to build
## Quick start
Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Intel Quartus Pro toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Quartus. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/README.md
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@ -9,18 +9,16 @@ This design targets the Alpha Data ADM-PCIE-9V3 FPGA board.
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
* RAM: 16 GB DDR4 2400 (2x 1G x72)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the ADM-PCIE-9V3 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/README.md
View File

@ -8,18 +8,16 @@ This design targets the Alpha Data ADM-PCIE-9V3 FPGA board.
* PHY: 25G BASE-R PHY IP core and internal GTY transceiver
* RAM: 16 GB DDR4 2400 (2x 1G x72)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the ADM-PCIE-9V3 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/AU200/fpga_100g/README.md
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@ -9,18 +9,16 @@ This design targets the Xilinx Alveo U200 FPGA board.
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the Alveo U200 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/AU200/fpga_25g/README.md
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@ -8,18 +8,16 @@ This design targets the Xilinx Alveo U200 FPGA board.
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the Alveo U200 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/AU250/fpga_100g/README.md
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@ -9,18 +9,16 @@ This design targets the Xilinx Alveo U250 FPGA board.
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the Alveo U250 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/AU250/fpga_25g/README.md
View File

@ -8,18 +8,16 @@ This design targets the Xilinx Alveo U250 FPGA board.
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the Alveo U250 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/AU280/fpga_100g/README.md
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@ -10,18 +10,16 @@ This design targets the Xilinx Alveo U280 FPGA board.
* RAM: 32 GB DDR4 2400 (2x 2G x72 DIMM)
* HBM: 8GB HBM2
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the Alveo U280 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/AU280/fpga_25g/README.md
View File

@ -9,18 +9,16 @@ This design targets the Xilinx Alveo U280 FPGA board.
* RAM: 32 GB DDR4 2400 (2x 2G x72 DIMM)
* HBM: 8GB HBM2
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the Alveo U280 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/AU50/fpga_100g/README.md
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@ -9,18 +9,16 @@ This design targets the Xilinx Alveo U50 FPGA board.
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
* RAM: 8GB HBM2
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the Alveo U50 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/AU50/fpga_25g/README.md
View File

@ -8,18 +8,16 @@ This design targets the Xilinx Alveo U50 FPGA board.
* PHY: 10G BASE-R PHY IP core and internal GTY transceivers
* RAM: 8GB HBM2
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the Alveo U50 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

18
fpga/mqnic/DE10_Agilex/fpga_100g/README.md
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@ -4,15 +4,19 @@
This design targets the Terasic DE10-Agilex FPGA development board.
* FPGA: AGFB014R24B2E2V
* PHY: E-Tile
* FPGA: AGFB014R24B2E2V
* PHY: E-Tile
## How to build
## Quick start
Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Intel Quartus Pro toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the DE10-Agilex board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Quartus. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

18
fpga/mqnic/DE10_Agilex/fpga_25g/README.md
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@ -4,15 +4,19 @@
This design targets the Terasic DE10-Agilex FPGA development board.
* FPGA: AGFB014R24B2E2V
* PHY: E-Tile
* FPGA: AGFB014R24B2E2V
* PHY: E-Tile
## How to build
## Quick start
Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Intel Quartus Pro toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the DE10-Agilex board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Quartus. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

18
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/README.md
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@ -4,15 +4,19 @@
This design targets the Intel DK-DEV-1SDX-P-A FPGA development board.
* FPGA: 1SD280PT2F55E1VG
* PHY: E-Tile
* FPGA: 1SD280PT2F55E1VG
* PHY: E-Tile
## How to build
## Quick start
Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Intel Quartus Pro toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Quartus. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

18
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/README.md
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@ -4,15 +4,19 @@
This design targets the Intel DK-DEV-1SDX-P-A FPGA development board.
* FPGA: 1SD280PT2F55E1VG
* PHY: E-Tile
* FPGA: 1SD280PT2F55E1VG
* PHY: E-Tile
## How to build
## Quick start
Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Intel Quartus Pro toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Quartus. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

20
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/README.md
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@ -4,16 +4,20 @@
This design targets the Intel DK-DEV-1SMX-H-A FPGA development board.
* FPGA (DK-DEV-1SMX-H-A): 1SM21BHU2F53E1VG (8 GB HBM2)
* FPGA (DK-DEV-1SMC-H-A): 1SM21CHU1F53E1VG (16 GB HBM2)
* PHY: Transceiver in 10G BASE-R native mode
* FPGA (DK-DEV-1SMX-H-A): 1SM21BHU2F53E1VG (8 GB HBM2)
* FPGA (DK-DEV-1SMC-H-A): 1SM21CHU1F53E1VG (16 GB HBM2)
* PHY: Transceiver in 10G BASE-R native mode
## How to build
## Quick start
Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Intel Quartus Pro toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Quartus. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

30
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/README.md
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@ -4,24 +4,28 @@
This design targets the Intel DK-DEV-AGF014EA FPGA development board.
* FPGA: AGFB014R24B2E2V
* PHY: E-Tile
* FPGA: AGFB014R24B2E2V
* PHY: E-Tile
## How to build
## Quick start
Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Intel Quartus Pro toolchain components are in PATH.
## How to test
### Build driver and userspace tools
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Configure DIP switches:
* SW1: off, on, on, off (AS_NORMAL)
* SW2: all off (UART, Si52202, Si5341 all enable, select USB JTAG)
* SW3: all off (enable all I2C interfaces)
* SW4: off, on, on, off (select USB JTAG, bypass MAX10 JTAG, bypass MICTOR JTAG, enable FPGA JTAG)
* SW6: 1 on, rest off (select x16)
* SW7: off (PCIe reference clock from edge connector)
* SW1: off, on, on, off (AS_NORMAL)
* SW2: all off (UART, Si52202, Si5341 all enable, select USB JTAG)
* SW3: all off (enable all I2C interfaces)
* SW4: off, on, on, off (select USB JTAG, bypass MAX10 JTAG, bypass MICTOR JTAG, enable FPGA JTAG)
* SW6: 1 on, rest off (select x16)
* SW7: off (PCIe reference clock from edge connector)
Run make program to program the DK-DEV-AGF014EA board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
Run `make program` to program the board with Quartus. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

30
fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/README.md
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@ -4,24 +4,28 @@
This design targets the Intel DK-DEV-AGF014EA FPGA development board.
* FPGA: AGFB014R24B2E2V
* PHY: E-Tile
* FPGA: AGFB014R24B2E2V
* PHY: E-Tile
## How to build
## Quick start
Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Intel Quartus Pro toolchain components are in PATH.
## How to test
### Build driver and userspace tools
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Configure DIP switches:
* SW1: off, on, on, off (AS_NORMAL)
* SW2: all off (UART, Si52202, Si5341 all enable, select USB JTAG)
* SW3: all off (enable all I2C interfaces)
* SW4: off, on, on, off (select USB JTAG, bypass MAX10 JTAG, bypass MICTOR JTAG, enable FPGA JTAG)
* SW6: 1 on, rest off (select x16)
* SW7: off (PCIe reference clock from edge connector)
* SW1: off, on, on, off (AS_NORMAL)
* SW2: all off (UART, Si52202, Si5341 all enable, select USB JTAG)
* SW3: all off (enable all I2C interfaces)
* SW4: off, on, on, off (select USB JTAG, bypass MAX10 JTAG, bypass MICTOR JTAG, enable FPGA JTAG)
* SW6: 1 on, rest off (select x16)
* SW7: off (PCIe reference clock from edge connector)
Run make program to program the DK-DEV-AGF014EA board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
Run `make program` to program the board with Quartus. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

12
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/README.md
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@ -8,14 +8,16 @@ This design targets the Dini Group DNPCIe_40G_KU_LL_2QSFP FPGA board.
* PHY: 10G BASE-R PHY IP core and internal GTH transceiver
* RAM: 4 GB DDR4 2400 (512M x72)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the DNPCIe_40G_KU_LL_2QSFP board with Vivado. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

20
fpga/mqnic/NetFPGA_SUME/fpga/README.md
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@ -4,21 +4,19 @@
This design targets the NetFPGA SUME FPGA board.
FPGA: XC7VX690T-3FFG1761I
PHY: 10G BASE-R PHY IP core and internal GTH transceiver
* FPGA: XC7VX690T-3FFG1761I
* PHY: 10G BASE-R PHY IP core and internal GTH transceiver
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the NetFPGA SUME board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

12
fpga/mqnic/Nexus_K35_S/fpga/README.md
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@ -7,14 +7,16 @@ This design targets the Cisco Nexus K35-S FPGA board.
* FPGA: xcku035-fbva676-2-e
* PHY: 10G BASE-R PHY IP core and internal GTH transceiver
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the Nexus K35-S board with Vivado. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

14
fpga/mqnic/Nexus_K3P_Q/fpga_25g/README.md
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@ -8,12 +8,16 @@ This design targets the Cisco Nexus K3P-Q FPGA board.
* PHY: 25G BASE-R PHY IP core and internal GTY transceiver
* RAM: 8 GB DDR4 (1G x72)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the Nexus K3P-Q board with Vivado. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

14
fpga/mqnic/Nexus_K3P_S/fpga_25g/README.md
View File

@ -7,12 +7,16 @@ This design targets the Cisco Nexus K3P-S FPGA board.
* FPGA: xcku3p-ffvb676-2-e
* PHY: 25G BASE-R PHY IP core and internal GTY transceiver
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the Nexus K3P-S board with Vivado. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/VCU108/fpga_25g/README.md
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@ -8,18 +8,16 @@ This design targets the Xilinx VCU108 FPGA board.
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* RAM: 4 GB DDR4 2400 (2x 256M x80)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the VCU108 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/VCU118/fpga_100g/README.md
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@ -9,18 +9,16 @@ This design targets the Xilinx VCU118 FPGA board.
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
* RAM: 4 GB DDR4 2666 (2x 256M x80)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the VCU118 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/VCU118/fpga_25g/README.md
View File

@ -8,18 +8,16 @@ This design targets the Xilinx VCU118 FPGA board.
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* RAM: 4 GB DDR4 2666 (2x 256M x80)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the VCU118 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/VCU1525/fpga_100g/README.md
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@ -9,18 +9,16 @@ This design targets the Xilinx VCU1525 FPGA board.
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the VCU1525 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/VCU1525/fpga_25g/README.md
View File

@ -8,18 +8,16 @@ This design targets the Xilinx VCU1525 FPGA board.
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the VCU1525 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

18
fpga/mqnic/XUPP3R/fpga_100g/README.md
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@ -9,16 +9,16 @@ This design targets the BittWare XUP-P3R FPGA board.
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
* RAM: 4x DDR4 DIMM
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the XUP-P3R board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

18
fpga/mqnic/XUPP3R/fpga_25g/README.md
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@ -8,16 +8,16 @@ This design targets the BittWare XUP-P3R FPGA board.
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* RAM: 4x DDR4 DIMM
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the XUP-P3R board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

21
fpga/mqnic/ZCU106/fpga_pcie/README.md
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@ -1,25 +1,24 @@
# Corundum mqnic for ZCU106
# Corundum mqnic for ZCU106 (PCIe host)
## Introduction
This design targets the Xilinx ZCU106 FPGA board.
This design targets the Xilinx ZCU106 FPGA board. The host system of the NIC is
an external host computer connected via PCIe.
* FPGA: xczu7ev-ffvc1156-2-e
* PHY: 10G BASE-R PHY IP core and internal GTH transceiver
* RAM: 2 GB DDR4 2400 (256M x64)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the ZCU106 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/fb2CG/fpga_100g/README.md
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@ -9,18 +9,16 @@ This design targets the Silicom fb2CG@KU15P FPGA board.
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
* RAM: 16GB DDR4 2666 (4x 512M x72)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the fb2CG@KU15P board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

16
fpga/mqnic/fb2CG/fpga_25g/README.md
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@ -8,18 +8,16 @@ This design targets the Silicom fb2CG@KU15P FPGA board.
* PHY: 25G BASE-R PHY IP core and internal GTY transceiver
* RAM: 16GB DDR4 2666 (4x 512M x72)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the fb2CG@KU15P board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

14
fpga/mqnic/fb4CGg3/fpga_100g/README.md
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@ -9,12 +9,16 @@ This design targets the Silicom fb4CGg3@VU09P FPGA board.
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
* RAM: 8GB DDR4 2666 (2x 512M x64) + 2x SODIMM
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the fb4CGg3@VU09P board with Vivado. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

14
fpga/mqnic/fb4CGg3/fpga_25g/README.md
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@ -8,12 +8,16 @@ This design targets the Silicom fb4CGg3@VU09P FPGA board.
* PHY: 25G BASE-R PHY IP core and internal GTY transceiver
* RAM: 16GB DDR4 2666 (4x 512M x72)
## How to build
## Quick start
Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH.
### Build FPGA bitstream
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
### Build driver and userspace tools
Run make program to program the fb4CGg3@VU09P board with Vivado. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
### Testing
Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.