FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-02-06 08:38:23 +08:00
Code Issues Projects Releases Wiki Activity

Fix backpressure bug

Browse Source
This commit is contained in:
Alex Forencich 2020-04-12 23:33:15 -07:00
parent 8ff77c8ae7
commit 9b03dfdb1a
1 changed files with 12 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
rtl/axi_dp_ram.v
View File

@ -152,7 +152,7 @@ wire [STRB_WIDTH-1:0] ram_a_cmd_wr_strb;
wire ram_a_cmd_wr_en; wire ram_a_cmd_wr_en;
wire ram_a_cmd_rd_en; wire ram_a_cmd_rd_en;
wire ram_a_cmd_last; wire ram_a_cmd_last;
reg ram_a_cmd_ready_reg = 1'b1; wire ram_a_cmd_ready;
reg [ID_WIDTH-1:0] ram_a_rd_resp_id_reg = {ID_WIDTH{1'b0}}; reg [ID_WIDTH-1:0] ram_a_rd_resp_id_reg = {ID_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] ram_a_rd_resp_data_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] ram_a_rd_resp_data_reg = {DATA_WIDTH{1'b0}};
reg ram_a_rd_resp_last_reg = 1'b0; reg ram_a_rd_resp_last_reg = 1'b0;
@ -166,7 +166,7 @@ wire [STRB_WIDTH-1:0] ram_b_cmd_wr_strb;
wire ram_b_cmd_wr_en; wire ram_b_cmd_wr_en;
wire ram_b_cmd_rd_en; wire ram_b_cmd_rd_en;
wire ram_b_cmd_last; wire ram_b_cmd_last;
reg ram_b_cmd_ready_reg = 1'b1; wire ram_b_cmd_ready;
reg [ID_WIDTH-1:0] ram_b_rd_resp_id_reg = {ID_WIDTH{1'b0}}; reg [ID_WIDTH-1:0] ram_b_rd_resp_id_reg = {ID_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] ram_b_rd_resp_data_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] ram_b_rd_resp_data_reg = {DATA_WIDTH{1'b0}};
reg ram_b_rd_resp_last_reg = 1'b0; reg ram_b_rd_resp_last_reg = 1'b0;
@ -255,7 +255,7 @@ a_if (
.ram_cmd_wr_en(ram_a_cmd_wr_en), .ram_cmd_wr_en(ram_a_cmd_wr_en),
.ram_cmd_rd_en(ram_a_cmd_rd_en), .ram_cmd_rd_en(ram_a_cmd_rd_en),
.ram_cmd_last(ram_a_cmd_last), .ram_cmd_last(ram_a_cmd_last),
.ram_cmd_ready(ram_a_cmd_ready_reg), .ram_cmd_ready(ram_a_cmd_ready),
.ram_rd_resp_id(ram_a_rd_resp_id_reg), .ram_rd_resp_id(ram_a_rd_resp_id_reg),
.ram_rd_resp_data(ram_a_rd_resp_data_reg), .ram_rd_resp_data(ram_a_rd_resp_data_reg),
.ram_rd_resp_last(ram_a_rd_resp_last_reg), .ram_rd_resp_last(ram_a_rd_resp_last_reg),
@ -346,7 +346,7 @@ b_if (
.ram_cmd_wr_en(ram_b_cmd_wr_en), .ram_cmd_wr_en(ram_b_cmd_wr_en),
.ram_cmd_rd_en(ram_b_cmd_rd_en), .ram_cmd_rd_en(ram_b_cmd_rd_en),
.ram_cmd_last(ram_b_cmd_last), .ram_cmd_last(ram_b_cmd_last),
.ram_cmd_ready(ram_b_cmd_ready_reg), .ram_cmd_ready(ram_b_cmd_ready),
.ram_rd_resp_id(ram_b_rd_resp_id_reg), .ram_rd_resp_id(ram_b_rd_resp_id_reg),
.ram_rd_resp_data(ram_b_rd_resp_data_reg), .ram_rd_resp_data(ram_b_rd_resp_data_reg),
.ram_rd_resp_last(ram_b_rd_resp_last_reg), .ram_rd_resp_last(ram_b_rd_resp_last_reg),
@ -373,17 +373,17 @@ initial begin
end end
end end
assign ram_a_cmd_ready = !ram_a_rd_resp_valid_reg || ram_a_rd_resp_ready;
always @(posedge a_clk) begin always @(posedge a_clk) begin
ram_a_rd_resp_valid_reg <= ram_a_rd_resp_valid_reg && !ram_a_rd_resp_ready; ram_a_rd_resp_valid_reg <= ram_a_rd_resp_valid_reg && !ram_a_rd_resp_ready;
ram_a_cmd_ready_reg <= !ram_a_rd_resp_valid_reg || ram_a_rd_resp_ready;
if (ram_a_cmd_ready_reg && ram_a_cmd_rd_en) begin if (ram_a_cmd_rd_en && ram_a_cmd_ready) begin
ram_a_rd_resp_id_reg <= ram_a_cmd_id; ram_a_rd_resp_id_reg <= ram_a_cmd_id;
ram_a_rd_resp_data_reg <= mem[addr_a_valid]; ram_a_rd_resp_data_reg <= mem[addr_a_valid];
ram_a_rd_resp_last_reg <= ram_a_cmd_last; ram_a_rd_resp_last_reg <= ram_a_cmd_last;
ram_a_rd_resp_valid_reg <= 1'b1; ram_a_rd_resp_valid_reg <= 1'b1;
ram_a_cmd_ready_reg <= ram_a_rd_resp_ready; end else if (ram_a_cmd_wr_en && ram_a_cmd_ready) begin
end else if (ram_a_cmd_ready_reg && ram_a_cmd_wr_en) begin
for (i = 0; i < WORD_WIDTH; i = i + 1) begin for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (ram_a_cmd_wr_strb[i]) begin if (ram_a_cmd_wr_strb[i]) begin
mem[addr_a_valid][WORD_SIZE*i +: WORD_SIZE] <= ram_a_cmd_wr_data[WORD_SIZE*i +: WORD_SIZE]; mem[addr_a_valid][WORD_SIZE*i +: WORD_SIZE] <= ram_a_cmd_wr_data[WORD_SIZE*i +: WORD_SIZE];
@ -392,22 +392,21 @@ always @(posedge a_clk) begin
end end
if (a_rst) begin if (a_rst) begin
ram_a_cmd_ready_reg <= 1'b1;
ram_a_rd_resp_valid_reg <= 1'b0; ram_a_rd_resp_valid_reg <= 1'b0;
end end
end end
assign ram_b_cmd_ready = !ram_b_rd_resp_valid_reg || ram_b_rd_resp_ready;
always @(posedge b_clk) begin always @(posedge b_clk) begin
ram_b_rd_resp_valid_reg <= ram_b_rd_resp_valid_reg && !ram_b_rd_resp_ready; ram_b_rd_resp_valid_reg <= ram_b_rd_resp_valid_reg && !ram_b_rd_resp_ready;
ram_b_cmd_ready_reg <= !ram_b_rd_resp_valid_reg || ram_b_rd_resp_ready;
if (ram_b_cmd_ready_reg && ram_b_cmd_rd_en) begin if (ram_b_cmd_rd_en && ram_b_cmd_ready) begin
ram_b_rd_resp_id_reg <= ram_b_cmd_id; ram_b_rd_resp_id_reg <= ram_b_cmd_id;
ram_b_rd_resp_data_reg <= mem[addr_b_valid]; ram_b_rd_resp_data_reg <= mem[addr_b_valid];
ram_b_rd_resp_last_reg <= ram_b_cmd_last; ram_b_rd_resp_last_reg <= ram_b_cmd_last;
ram_b_rd_resp_valid_reg <= 1'b1; ram_b_rd_resp_valid_reg <= 1'b1;
ram_b_cmd_ready_reg <= ram_b_rd_resp_ready; end else if (ram_b_cmd_wr_en && ram_b_cmd_ready) begin
end else if (ram_b_cmd_ready_reg && ram_b_cmd_wr_en) begin
for (i = 0; i < WORD_WIDTH; i = i + 1) begin for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (ram_b_cmd_wr_strb[i]) begin if (ram_b_cmd_wr_strb[i]) begin
mem[addr_b_valid][WORD_SIZE*i +: WORD_SIZE] <= ram_b_cmd_wr_data[WORD_SIZE*i +: WORD_SIZE]; mem[addr_b_valid][WORD_SIZE*i +: WORD_SIZE] <= ram_b_cmd_wr_data[WORD_SIZE*i +: WORD_SIZE];
@ -416,7 +415,6 @@ always @(posedge b_clk) begin
end end
if (b_rst) begin if (b_rst) begin
ram_b_cmd_ready_reg <= 1'b1;
ram_b_rd_resp_valid_reg <= 1'b0; ram_b_rd_resp_valid_reg <= 1'b0;
end end
end end