diff --git a/fpga/mqnic/AU280/fpga_100g/Makefile b/fpga/mqnic/AU280/fpga_100g/Makefile new file mode 100644 index 000000000..f504bd06f --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/Makefile @@ -0,0 +1,25 @@ +# Targets +TARGETS:= + +# Subdirectories +SUBDIRS = fpga +SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) + +# Rules +.PHONY: all +all: $(SUBDIRS) $(TARGETS) + +.PHONY: $(SUBDIRS) +$(SUBDIRS): + cd $@ && $(MAKE) + +.PHONY: $(SUBDIRS_CLEAN) +$(SUBDIRS_CLEAN): + cd $(@:.clean=) && $(MAKE) clean + +.PHONY: clean +clean: $(SUBDIRS_CLEAN) + -rm -rf $(TARGETS) + +program: + #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/fpga/mqnic/AU280/fpga_100g/README.md b/fpga/mqnic/AU280/fpga_100g/README.md new file mode 100644 index 000000000..8154d21d6 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/README.md @@ -0,0 +1,25 @@ +# Corundum mqnic for Alveo U280 + +## Introduction + +This design targets the Xilinx Alveo U280 FPGA board. + +* FPGA: xcu280-fsvh2892-2L-e +* MAC: Xilinx 100G CMAC +* PHY: 100G CAUI-4 CMAC and internal GTY transceivers + +## How to build + +Run make to build. Ensure that the Xilinx Vivado toolchain components are +in PATH. + +Run make to build the driver. Ensure the headers for the running kernel are +installed, otherwise the driver cannot be compiled. + +## How to test + +Run make program to program the Alveo U280 board with Vivado. Then load the +driver with insmod mqnic.ko. Check dmesg for output from driver +initialization. + + diff --git a/fpga/mqnic/AU280/fpga_100g/common/vivado.mk b/fpga/mqnic/AU280/fpga_100g/common/vivado.mk new file mode 100644 index 000000000..b84025221 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/common/vivado.mk @@ -0,0 +1,120 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: clean fpga + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) +INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) +XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) + +ifdef XDC_FILES + XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) +else + XDC_FILES_REL = $(FPGA_TOP).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(FPGA_TOP).bit + +tmpclean: + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean: tmpclean + -rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + +distclean: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +%.xpr: Makefile $(XCI_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl + echo "add_files -fileset sources_1 defines.v" >> create_project.tcl + for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done + for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done + echo "exit" >> create_project.tcl + vivado -nojournal -nolog -mode batch -source create_project.tcl + +# synthesis run +%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project $*.xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + echo "exit" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp + echo "open_project $*.xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "exit" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +%.bit: %.runs/impl_1/%_routed.dcp + echo "open_project $*.xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $*.bit" >> generate_bit.tcl + echo "exit" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + mkdir -p rev + EXT=bit; COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp $@ rev/$*_rev$$COUNT.$$EXT; \ + echo "Output: rev/$*_rev$$COUNT.$$EXT"; diff --git a/fpga/mqnic/AU280/fpga_100g/fpga.xdc b/fpga/mqnic/AU280/fpga_100g/fpga.xdc new file mode 100644 index 000000000..dbd1105ff --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/fpga.xdc @@ -0,0 +1,212 @@ +# XDC constraints for the Xilinx Alveo U280 board +# part: xcu280-fsvh2892-2L-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] + +# System clocks +# 100 MHz (DDR4) +#set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p] +#set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n] +#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p] + +# 100 MHz (DDR4) +#set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p] +#set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n] +#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p] + +# 100 MHz +#set_property -dict {LOC G31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_p] +#set_property -dict {LOC F31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_n] +#create_clock -period 10 -name clk_100mhz_2 [get_ports clk_100mhz_2_p] + +# SI570 user clock +#set_property -dict {LOC G30 IOSTANDARD LVDS} [get_ports clk_si570_p] +#set_property -dict {LOC F30 IOSTANDARD LVDS} [get_ports clk_si570_n] +#create_clock -period 6.4 -name clk_si570 [get_ports clk_si570_p] + +# Reset button +#set_property -dict {LOC L30 IOSTANDARD LVCMOS18} [get_ports reset] + +# UART +#set_property -dict {LOC A28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports usb_uart_txd] +#set_property -dict {LOC B33 IOSTANDARD LVCMOS18} [get_ports usb_uart_rxd] + +# HBM overtemp +set_property -dict {LOC D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip] + +# QSFP28 Interfaces +set_property -dict {LOC L48 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_134 GTYE3_CHANNEL_X1Y40 / GTYE3_COMMON_X1Y10 +#set_property -dict {LOC L49 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_134 GTYE3_CHANNEL_X1Y40 / GTYE3_COMMON_X1Y10 +set_property -dict {LOC L53 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_134 GTYE3_CHANNEL_X1Y40 / GTYE3_COMMON_X1Y10 +#set_property -dict {LOC L54 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_134 GTYE3_CHANNEL_X1Y40 / GTYE3_COMMON_X1Y10 +set_property -dict {LOC L44 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_134 GTYE3_CHANNEL_X1Y41 / GTYE3_COMMON_X1Y10 +#set_property -dict {LOC L45 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_134 GTYE3_CHANNEL_X1Y41 / GTYE3_COMMON_X1Y10 +set_property -dict {LOC K51 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_134 GTYE3_CHANNEL_X1Y41 / GTYE3_COMMON_X1Y10 +#set_property -dict {LOC K52 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_134 GTYE3_CHANNEL_X1Y41 / GTYE3_COMMON_X1Y10 +set_property -dict {LOC K46 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_134 GTYE3_CHANNEL_X1Y42 / GTYE3_COMMON_X1Y10 +#set_property -dict {LOC K47 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_134 GTYE3_CHANNEL_X1Y42 / GTYE3_COMMON_X1Y10 +set_property -dict {LOC J53 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_134 GTYE3_CHANNEL_X1Y42 / GTYE3_COMMON_X1Y10 +#set_property -dict {LOC J54 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_134 GTYE3_CHANNEL_X1Y42 / GTYE3_COMMON_X1Y10 +set_property -dict {LOC J48 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_134 GTYE3_CHANNEL_X1Y43 / GTYE3_COMMON_X1Y10 +#set_property -dict {LOC J49 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_134 GTYE3_CHANNEL_X1Y43 / GTYE3_COMMON_X1Y10 +set_property -dict {LOC H51 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_134 GTYE3_CHANNEL_X1Y43 / GTYE3_COMMON_X1Y10 +#set_property -dict {LOC H52 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_134 GTYE3_CHANNEL_X1Y43 / GTYE3_COMMON_X1Y10 +#set_property -dict {LOC T42 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_134 from SI570 +#set_property -dict {LOC T43 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_134 from SI570 +set_property -dict {LOC R40 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_134 from SI546 +#set_property -dict {LOC R41 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_134 from SI546 +set_property -dict {LOC H32 IOSTANDARD LVCMOS18} [get_ports qsfp0_refclk_oe_b] +set_property -dict {LOC G32 IOSTANDARD LVCMOS18} [get_ports qsfp0_refclk_fs] + +# 156.25 MHz MGT reference clock (from SI570) +#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] + +# 156.25 MHz MGT reference clock (from SI546, fs = 0) +#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] + +# 161.1328125 MHz MGT reference clock (from SI546, fs = 1) +#create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] + +set_property -dict {LOC G48 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_135 GTYE3_CHANNEL_X1Y44 / GTYE3_COMMON_X1Y11 +#set_property -dict {LOC G49 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_135 GTYE3_CHANNEL_X1Y44 / GTYE3_COMMON_X1Y11 +set_property -dict {LOC G53 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_135 GTYE3_CHANNEL_X1Y44 / GTYE3_COMMON_X1Y11 +#set_property -dict {LOC G54 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_135 GTYE3_CHANNEL_X1Y44 / GTYE3_COMMON_X1Y11 +set_property -dict {LOC E48 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_135 GTYE3_CHANNEL_X1Y45 / GTYE3_COMMON_X1Y11 +#set_property -dict {LOC E49 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_135 GTYE3_CHANNEL_X1Y45 / GTYE3_COMMON_X1Y11 +set_property -dict {LOC F51 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_135 GTYE3_CHANNEL_X1Y45 / GTYE3_COMMON_X1Y11 +#set_property -dict {LOC F52 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_135 GTYE3_CHANNEL_X1Y45 / GTYE3_COMMON_X1Y11 +set_property -dict {LOC C48 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_135 GTYE3_CHANNEL_X1Y46 / GTYE3_COMMON_X1Y11 +#set_property -dict {LOC C49 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_135 GTYE3_CHANNEL_X1Y46 / GTYE3_COMMON_X1Y11 +set_property -dict {LOC E53 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_135 GTYE3_CHANNEL_X1Y46 / GTYE3_COMMON_X1Y11 +#set_property -dict {LOC E54 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_135 GTYE3_CHANNEL_X1Y46 / GTYE3_COMMON_X1Y11 +set_property -dict {LOC A49 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_135 GTYE3_CHANNEL_X1Y47 / GTYE3_COMMON_X1Y11 +#set_property -dict {LOC A50 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_135 GTYE3_CHANNEL_X1Y47 / GTYE3_COMMON_X1Y11 +set_property -dict {LOC D51 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_135 GTYE3_CHANNEL_X1Y47 / GTYE3_COMMON_X1Y11 +#set_property -dict {LOC D52 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_135 GTYE3_CHANNEL_X1Y47 / GTYE3_COMMON_X1Y11 +#set_property -dict {LOC P42 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_135 from SI570 +#set_property -dict {LOC P43 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_135 from SI570 +set_property -dict {LOC M42 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_135 from SI546 +#set_property -dict {LOC M43 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_135 from SI546 +set_property -dict {LOC H30 IOSTANDARD LVCMOS18} [get_ports qsfp1_refclk_oe_b] +set_property -dict {LOC G33 IOSTANDARD LVCMOS18} [get_ports qsfp1_refclk_fs] + +# 156.25 MHz MGT reference clock (from SI570) +#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] + +# 156.25 MHz MGT reference clock (from SI546, fs = 0) +#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] + +# 161.1328125 MHz MGT reference clock (from SI546, fs = 1) +#create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] + +# PCIe Interface +set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 +set_property -dict {LOC AL11} [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AL10} [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 +set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 +set_property -dict {LOC AM9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AM8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 +set_property -dict {LOC AN6 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AN5 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 +set_property -dict {LOC AN11} [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AN10} [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 +set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 +set_property -dict {LOC AP9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AP8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 +set_property -dict {LOC AP4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AP3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 +set_property -dict {LOC AR11} [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AR10} [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 +set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 +set_property -dict {LOC AR7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AR6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 +set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 +set_property -dict {LOC AT9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AT8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 +set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 +set_property -dict {LOC AU11} [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AU10} [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 +set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AW6 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AW5 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AV9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AV8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AW2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AW1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AW11} [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AW10} [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AY4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AY3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AY9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AY8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC BA6 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BA5 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC BA11} [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BA10} [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC BB9 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BB8 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC BB4 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BB3 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC BC11} [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BC10} [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC BC7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BC6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC AL15} [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_227 (for x8 bifurcated lanes 0-7) +#set_property -dict {LOC AL14} [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_227 (for x8 bifurcated lanes 0-7) +#set_property -dict {LOC AK13} [get_ports pcie_refclk_2_p] ;# MGTREFCLK1P_227 (for async x8 bifurcated lanes 0-7) +#set_property -dict {LOC AK12} [get_ports pcie_refclk_2_n] ;# MGTREFCLK1N_227 (for async x8 bifurcated lanes 0-7) +set_property -dict {LOC AR15} [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_225 (for x16 or x8 bifurcated lanes 8-16) +#set_property -dict {LOC AR14} [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_225 (for x16 or x8 bifurcated lanes 8-16) +#set_property -dict {LOC AP13} [get_ports pcie_refclk_3_p] ;# MGTREFCLK1P_225 (for async x16 or x8 bifurcated lanes 8-16) +#set_property -dict {LOC AP12} [get_ports pcie_refclk_3_n] ;# MGTREFCLK1N_225 (for async x16 or x8 bifurcated lanes 8-16) +set_property -dict {LOC BH26 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n] + +# 100 MHz MGT reference clock +#create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p] +create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p] +#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p] +#create_clock -period 10 -name pcie_mgt_refclk_3 [get_ports pcie_refclk_3_p] + + + +# Floorplanning constraints +create_pblock pblock_slr0 +add_cells_to_pblock [get_pblocks pblock_slr0] [get_cells -quiet [list pcie4c_uscale_plus_inst]] +add_cells_to_pblock [get_pblocks pblock_slr0] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]] +resize_pblock [get_pblocks pblock_slr0] -add {SLR0} + +#create_pblock pblock_slr1 +#add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list ]] +#resize_pblock [get_pblocks pblock_slr1] -add {SLR1} + +create_pblock pblock_slr2 +add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list qsfp0_cmac_inst qsfp0_cmac_pad_inst]] +add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list core_inst/iface[0].mac[0].mac_tx_fifo_inst core_inst/iface[0].mac[0].mac_rx_fifo_inst]] +add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list qsfp1_cmac_inst qsfp1_cmac_pad_inst]] +add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list core_inst/iface[1].mac[0].mac_tx_fifo_inst core_inst/iface[1].mac[0].mac_rx_fifo_inst]] +resize_pblock [get_pblocks pblock_slr2] -add {SLR2} + diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile new file mode 100644 index 000000000..272fa660f --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile @@ -0,0 +1,79 @@ + +# FPGA settings +FPGA_PART = xcu280-fsvh2892-2L-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/common/interface.v +SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/cpl_write.v +SYN_FILES += rtl/common/cpl_op_mux.v +SYN_FILES += rtl/common/desc_fetch.v +SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/queue_manager.v +SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/event_mux.v +SYN_FILES += rtl/common/tx_scheduler_rr.v +SYN_FILES += rtl/common/tdma_scheduler.v +SYN_FILES += rtl/common/tx_engine.v +SYN_FILES += rtl/common/rx_engine.v +SYN_FILES += rtl/common/tx_checksum.v +SYN_FILES += rtl/common/rx_hash.v +SYN_FILES += rtl/common/rx_checksum.v +SYN_FILES += rtl/common/cmac_pad.v +SYN_FILES += lib/eth/rtl/ptp_clock.v +SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_ts_extract.v +SYN_FILES += lib/axi/rtl/axil_interconnect.v +SYN_FILES += lib/axi/rtl/arbiter.v +SYN_FILES += lib/axi/rtl/priority_encoder.v +SYN_FILES += lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_pipeline_register.v +SYN_FILES += lib/axis/rtl/axis_register.v +SYN_FILES += lib/axis/rtl/sync_reset.v +SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_mux.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v +SYN_FILES += lib/pcie/rtl/dma_psdpram.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v +SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v +SYN_FILES += lib/pcie/rtl/pcie_us_msi.v +SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v +SYN_FILES += lib/pcie/rtl/pulse_merge.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/axis/syn/axis_async_fifo.tcl +XDC_FILES += lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/ptp_clock_cdc.tcl +XDC_FILES += ../../../common/syn/tdma_ber_ch.tcl + +# IP +IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl +IP_TCL_FILES += ip/cmac_usplus_0.tcl +IP_TCL_FILES += ip/cmac_usplus_1.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + diff --git a/fpga/mqnic/AU280/fpga_100g/ip/cmac_usplus_0.tcl b/fpga/mqnic/AU280/fpga_100g/ip/cmac_usplus_0.tcl new file mode 100644 index 000000000..97f080775 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/ip/cmac_usplus_0.tcl @@ -0,0 +1,20 @@ + +create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus_0 + +set_property -dict [list \ + CONFIG.CMAC_CAUI4_MODE {1} \ + CONFIG.NUM_LANES {4x25} \ + CONFIG.GT_REF_CLK_FREQ {161.1328125} \ + CONFIG.USER_INTERFACE {AXIS} \ + CONFIG.GT_DRP_CLK {125} \ + CONFIG.TX_FLOW_CONTROL {0} \ + CONFIG.RX_FLOW_CONTROL {0} \ + CONFIG.INCLUDE_RS_FEC {1} \ + CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y6} \ + CONFIG.GT_GROUP_SELECT {X0Y40~X0Y43} \ + CONFIG.LANE1_GT_LOC {X0Y40} \ + CONFIG.LANE2_GT_LOC {X0Y41} \ + CONFIG.LANE3_GT_LOC {X0Y42} \ + CONFIG.LANE4_GT_LOC {X0Y43} \ + CONFIG.ENABLE_PIPELINE_REG {1} +] [get_ips cmac_usplus_0] diff --git a/fpga/mqnic/AU280/fpga_100g/ip/cmac_usplus_1.tcl b/fpga/mqnic/AU280/fpga_100g/ip/cmac_usplus_1.tcl new file mode 100644 index 000000000..38c60b921 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/ip/cmac_usplus_1.tcl @@ -0,0 +1,20 @@ + +create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus_1 + +set_property -dict [list \ + CONFIG.CMAC_CAUI4_MODE {1} \ + CONFIG.NUM_LANES {4x25} \ + CONFIG.GT_REF_CLK_FREQ {161.1328125} \ + CONFIG.USER_INTERFACE {AXIS} \ + CONFIG.GT_DRP_CLK {125} \ + CONFIG.TX_FLOW_CONTROL {0} \ + CONFIG.RX_FLOW_CONTROL {0} \ + CONFIG.INCLUDE_RS_FEC {1} \ + CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y7} \ + CONFIG.GT_GROUP_SELECT {X0Y44~X0Y47} \ + CONFIG.LANE1_GT_LOC {X0Y44} \ + CONFIG.LANE2_GT_LOC {X0Y45} \ + CONFIG.LANE3_GT_LOC {X0Y46} \ + CONFIG.LANE4_GT_LOC {X0Y47} \ + CONFIG.ENABLE_PIPELINE_REG {1} +] [get_ips cmac_usplus_1] diff --git a/fpga/mqnic/AU280/fpga_100g/ip/pcie4c_uscale_plus_0.tcl b/fpga/mqnic/AU280/fpga_100g/ip/pcie4c_uscale_plus_0.tcl new file mode 100644 index 000000000..ac813ac25 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/ip/pcie4c_uscale_plus_0.tcl @@ -0,0 +1,24 @@ + +create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name pcie4c_uscale_plus_0 + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ + CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ + CONFIG.axisten_if_enable_client_tag {true} \ + CONFIG.axisten_if_width {512_bit} \ + CONFIG.axisten_freq {250} \ + CONFIG.PF0_CLASS_CODE {020000} \ + CONFIG.PF0_DEVICE_ID {1001} \ + CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ + CONFIG.PF0_SUBSYSTEM_ID {1001} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1234} \ + CONFIG.PF0_Use_Class_Code_Lookup_Assistant {true} \ + CONFIG.pf0_class_code_sub {00} \ + CONFIG.pf0_base_class_menu {Network_controller} \ + CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {16} \ + CONFIG.vendor_id {1234} \ + CONFIG.en_msi_per_vec_masking {true} \ +] [get_ips pcie4c_uscale_plus_0] diff --git a/fpga/mqnic/AU280/fpga_100g/lib b/fpga/mqnic/AU280/fpga_100g/lib new file mode 120000 index 000000000..9512b3d5e --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/lib @@ -0,0 +1 @@ +../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/common b/fpga/mqnic/AU280/fpga_100g/rtl/common new file mode 120000 index 000000000..449c9409c --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/rtl/common @@ -0,0 +1 @@ +../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v new file mode 100644 index 000000000..157d70ed8 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v @@ -0,0 +1,1255 @@ +/* + +Copyright 2019, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * FPGA top-level module + */ +module fpga ( + /* + * GPIO + */ + output wire hbm_cattrip, + + /* + * PCI express + */ + input wire [15:0] pcie_rx_p, + input wire [15:0] pcie_rx_n, + output wire [15:0] pcie_tx_p, + output wire [15:0] pcie_tx_n, + input wire pcie_refclk_1_p, + input wire pcie_refclk_1_n, + input wire pcie_reset_n, + + /* + * Ethernet: QSFP28 + */ + output wire qsfp0_tx1_p, + output wire qsfp0_tx1_n, + input wire qsfp0_rx1_p, + input wire qsfp0_rx1_n, + output wire qsfp0_tx2_p, + output wire qsfp0_tx2_n, + input wire qsfp0_rx2_p, + input wire qsfp0_rx2_n, + output wire qsfp0_tx3_p, + output wire qsfp0_tx3_n, + input wire qsfp0_rx3_p, + input wire qsfp0_rx3_n, + output wire qsfp0_tx4_p, + output wire qsfp0_tx4_n, + input wire qsfp0_rx4_p, + input wire qsfp0_rx4_n, + // input wire qsfp0_mgt_refclk_0_p, + // input wire qsfp0_mgt_refclk_0_n, + input wire qsfp0_mgt_refclk_1_p, + input wire qsfp0_mgt_refclk_1_n, + output wire qsfp0_refclk_oe_b, + output wire qsfp0_refclk_fs, + + output wire qsfp1_tx1_p, + output wire qsfp1_tx1_n, + input wire qsfp1_rx1_p, + input wire qsfp1_rx1_n, + output wire qsfp1_tx2_p, + output wire qsfp1_tx2_n, + input wire qsfp1_rx2_p, + input wire qsfp1_rx2_n, + output wire qsfp1_tx3_p, + output wire qsfp1_tx3_n, + input wire qsfp1_rx3_p, + input wire qsfp1_rx3_n, + output wire qsfp1_tx4_p, + output wire qsfp1_tx4_n, + input wire qsfp1_rx4_p, + input wire qsfp1_rx4_n, + // input wire qsfp1_mgt_refclk_0_p, + // input wire qsfp1_mgt_refclk_0_n, + input wire qsfp1_mgt_refclk_1_p, + input wire qsfp1_mgt_refclk_1_n, + output wire qsfp1_refclk_oe_b, + output wire qsfp1_refclk_fs +); + +parameter AXIS_PCIE_DATA_WIDTH = 512; +parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RC_USER_WIDTH = 161; +parameter AXIS_PCIE_RQ_USER_WIDTH = 137; +parameter AXIS_PCIE_CQ_USER_WIDTH = 183; +parameter AXIS_PCIE_CC_USER_WIDTH = 81; +parameter RQ_SEQ_NUM_WIDTH = 6; +parameter BAR0_APERTURE = 24; + +parameter AXIS_ETH_DATA_WIDTH = 512; +parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; + +// Clock and reset +wire pcie_user_clk; +wire pcie_user_reset; + +wire cfgmclk_int; + +wire clk_161mhz_ref_int; + +wire clk_125mhz_mmcm_out; + +// Internal 125 MHz clock +wire clk_125mhz_int; +wire rst_125mhz_int; + +wire mmcm_rst = pcie_user_reset; +wire mmcm_locked; +wire mmcm_clkfb; + +// MMCM instance +// 161.13 MHz in, 125 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 64, D = 11 sets Fvco = 937.5 MHz (in range) +// Divide by 7.5 to get output frequency of 125 MHz +MMCME4_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(7.5), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(64), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(11), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(6.206), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +clk_mmcm_inst ( + .CLKIN1(clk_161mhz_ref_int), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// GPIO +assign hbm_cattrip = 1'b0; + +// PCIe +wire pcie_sys_clk; +wire pcie_sys_clk_gt; + +IBUFDS_GTE4 #( + .REFCLK_HROW_CK_SEL(2'b00) +) +ibufds_gte4_pcie_mgt_refclk_inst ( + .I (pcie_refclk_1_p), + .IB (pcie_refclk_1_n), + .CEB (1'b0), + .O (pcie_sys_clk_gt), + .ODIV2 (pcie_sys_clk) +); + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; +wire axis_rq_tlast; +wire axis_rq_tready; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; +wire axis_rq_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; +wire axis_rc_tlast; +wire axis_rc_tready; +wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; +wire axis_rc_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; +wire axis_cq_tlast; +wire axis_cq_tready; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; +wire axis_cq_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; +wire axis_cc_tlast; +wire axis_cc_tready; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; +wire axis_cc_tvalid; + +wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0; +wire pcie_rq_seq_num_vld0; +wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1; +wire pcie_rq_seq_num_vld1; + +wire [3:0] pcie_tfc_nph_av; +wire [3:0] pcie_tfc_npd_av; + +wire [2:0] cfg_max_payload; +wire [2:0] cfg_max_read_req; + +wire [9:0] cfg_mgmt_addr; +wire [7:0] cfg_mgmt_function_number; +wire cfg_mgmt_write; +wire [31:0] cfg_mgmt_write_data; +wire [3:0] cfg_mgmt_byte_enable; +wire cfg_mgmt_read; +wire [31:0] cfg_mgmt_read_data; +wire cfg_mgmt_read_write_done; + +wire [7:0] cfg_fc_ph; +wire [11:0] cfg_fc_pd; +wire [7:0] cfg_fc_nph; +wire [11:0] cfg_fc_npd; +wire [7:0] cfg_fc_cplh; +wire [11:0] cfg_fc_cpld; +wire [2:0] cfg_fc_sel; + +wire [3:0] cfg_interrupt_msi_enable; +wire [11:0] cfg_interrupt_msi_mmenable; +wire cfg_interrupt_msi_mask_update; +wire [31:0] cfg_interrupt_msi_data; +wire [3:0] cfg_interrupt_msi_select; +wire [31:0] cfg_interrupt_msi_int; +wire [31:0] cfg_interrupt_msi_pending_status; +wire cfg_interrupt_msi_pending_status_data_enable; +wire [3:0] cfg_interrupt_msi_pending_status_function_num; +wire cfg_interrupt_msi_sent; +wire cfg_interrupt_msi_fail; +wire [2:0] cfg_interrupt_msi_attr; +wire cfg_interrupt_msi_tph_present; +wire [1:0] cfg_interrupt_msi_tph_type; +wire [8:0] cfg_interrupt_msi_tph_st_tag; +wire [3:0] cfg_interrupt_msi_function_number; + +wire status_error_cor; +wire status_error_uncor; + +pcie4c_uscale_plus_0 +pcie4c_uscale_plus_inst ( + .pci_exp_txn(pcie_tx_n), + .pci_exp_txp(pcie_tx_p), + .pci_exp_rxn(pcie_rx_n), + .pci_exp_rxp(pcie_rx_p), + .user_clk(pcie_user_clk), + .user_reset(pcie_user_reset), + .user_lnk_up(), + + .s_axis_rq_tdata(axis_rq_tdata), + .s_axis_rq_tkeep(axis_rq_tkeep), + .s_axis_rq_tlast(axis_rq_tlast), + .s_axis_rq_tready(axis_rq_tready), + .s_axis_rq_tuser(axis_rq_tuser), + .s_axis_rq_tvalid(axis_rq_tvalid), + + .m_axis_rc_tdata(axis_rc_tdata), + .m_axis_rc_tkeep(axis_rc_tkeep), + .m_axis_rc_tlast(axis_rc_tlast), + .m_axis_rc_tready(axis_rc_tready), + .m_axis_rc_tuser(axis_rc_tuser), + .m_axis_rc_tvalid(axis_rc_tvalid), + + .m_axis_cq_tdata(axis_cq_tdata), + .m_axis_cq_tkeep(axis_cq_tkeep), + .m_axis_cq_tlast(axis_cq_tlast), + .m_axis_cq_tready(axis_cq_tready), + .m_axis_cq_tuser(axis_cq_tuser), + .m_axis_cq_tvalid(axis_cq_tvalid), + + .s_axis_cc_tdata(axis_cc_tdata), + .s_axis_cc_tkeep(axis_cc_tkeep), + .s_axis_cc_tlast(axis_cc_tlast), + .s_axis_cc_tready(axis_cc_tready), + .s_axis_cc_tuser(axis_cc_tuser), + .s_axis_cc_tvalid(axis_cc_tvalid), + + .pcie_rq_seq_num0(pcie_rq_seq_num0), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), + .pcie_rq_seq_num1(pcie_rq_seq_num1), + .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), + .pcie_rq_tag0(), + .pcie_rq_tag1(), + .pcie_rq_tag_av(), + .pcie_rq_tag_vld0(), + .pcie_rq_tag_vld1(), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .pcie_cq_np_req(1'b1), + .pcie_cq_np_req_count(), + + .cfg_phy_link_down(), + .cfg_phy_link_status(), + .cfg_negotiated_width(), + .cfg_current_speed(), + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_function_status(), + .cfg_function_power_state(), + .cfg_vf_status(), + .cfg_vf_power_state(), + .cfg_link_power_state(), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + .cfg_mgmt_debug_access(1'b0), + + .cfg_err_cor_out(), + .cfg_err_nonfatal_out(), + .cfg_err_fatal_out(), + .cfg_local_error_valid(), + .cfg_local_error_out(), + .cfg_ltssm_state(), + .cfg_rx_pm_state(), + .cfg_tx_pm_state(), + .cfg_rcb_status(), + .cfg_obff_enable(), + .cfg_pl_status_change(), + .cfg_tph_requester_enable(), + .cfg_tph_st_mode(), + .cfg_vf_tph_requester_enable(), + .cfg_vf_tph_st_mode(), + + .cfg_msg_received(), + .cfg_msg_received_data(), + .cfg_msg_received_type(), + .cfg_msg_transmit(1'b0), + .cfg_msg_transmit_type(3'd0), + .cfg_msg_transmit_data(32'd0), + .cfg_msg_transmit_done(), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_dsn(64'd0), + + .cfg_power_state_change_ack(1'b1), + .cfg_power_state_change_interrupt(), + + .cfg_err_cor_in(status_error_cor), + .cfg_err_uncor_in(status_error_uncor), + .cfg_flr_in_process(), + .cfg_flr_done(4'd0), + .cfg_vf_flr_in_process(), + .cfg_vf_flr_func_num(8'd0), + .cfg_vf_flr_done(8'd0), + + .cfg_link_training_enable(1'b1), + + .cfg_interrupt_int(4'd0), + .cfg_interrupt_pending(4'd0), + .cfg_interrupt_sent(), + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .cfg_pm_aspm_l1_entry_reject(1'b0), + .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), + + .cfg_hot_reset_out(), + + .cfg_config_space_enable(1'b1), + .cfg_req_pm_transition_l23_ready(1'b0), + .cfg_hot_reset_in(1'b0), + + .cfg_ds_port_number(8'd0), + .cfg_ds_bus_number(8'd0), + .cfg_ds_device_number(5'd0), + + .sys_clk(pcie_sys_clk), + .sys_clk_gt(pcie_sys_clk_gt), + .sys_reset(pcie_reset_n), + + .phy_rdy_out() +); + +reg [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0_reg; +reg pcie_rq_seq_num_vld0_reg; +reg [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1_reg; +reg pcie_rq_seq_num_vld1_reg; + +always @(posedge pcie_user_clk) begin + pcie_rq_seq_num0_reg <= pcie_rq_seq_num0; + pcie_rq_seq_num_vld0_reg <= pcie_rq_seq_num_vld0; + pcie_rq_seq_num1_reg <= pcie_rq_seq_num1; + pcie_rq_seq_num_vld1_reg <= pcie_rq_seq_num_vld1; + + if (pcie_user_reset) begin + pcie_rq_seq_num_vld0_reg <= 1'b0; + pcie_rq_seq_num_vld1_reg <= 1'b0; + end +end + +// CMAC +assign qsfp0_refclk_oe_b = 1'b0; +assign qsfp0_refclk_fs = 1'b1; + +wire qsfp0_tx_clk_int; +wire qsfp0_tx_rst_int; + +wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_tx_axis_tdata_int; +wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_tx_axis_tkeep_int; +wire qsfp0_tx_axis_tvalid_int; +wire qsfp0_tx_axis_tready_int; +wire qsfp0_tx_axis_tlast_int; +wire qsfp0_tx_axis_tuser_int; + +wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_mac_tx_axis_tdata; +wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_mac_tx_axis_tkeep; +wire qsfp0_mac_tx_axis_tvalid; +wire qsfp0_mac_tx_axis_tready; +wire qsfp0_mac_tx_axis_tlast; +wire qsfp0_mac_tx_axis_tuser; + +wire qsfp0_rx_clk_int; +wire qsfp0_rx_rst_int; + +wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_rx_axis_tdata_int; +wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_rx_axis_tkeep_int; +wire qsfp0_rx_axis_tvalid_int; +wire qsfp0_rx_axis_tlast_int; +wire qsfp0_rx_axis_tuser_int; + +assign qsfp1_refclk_oe_b = 1'b0; +assign qsfp1_refclk_fs = 1'b1; + +wire qsfp1_tx_clk_int; +wire qsfp1_tx_rst_int; + +wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_tx_axis_tdata_int; +wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_tx_axis_tkeep_int; +wire qsfp1_tx_axis_tvalid_int; +wire qsfp1_tx_axis_tready_int; +wire qsfp1_tx_axis_tlast_int; +wire qsfp1_tx_axis_tuser_int; + +wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_tx_axis_tdata; +wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_tx_axis_tkeep; +wire qsfp1_mac_tx_axis_tvalid; +wire qsfp1_mac_tx_axis_tready; +wire qsfp1_mac_tx_axis_tlast; +wire qsfp1_mac_tx_axis_tuser; + +wire qsfp1_rx_clk_int; +wire qsfp1_rx_rst_int; + +wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_rx_axis_tdata_int; +wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_rx_axis_tkeep_int; +wire qsfp1_rx_axis_tvalid_int; +wire qsfp1_rx_axis_tlast_int; +wire qsfp1_rx_axis_tuser_int; + +wire qsfp0_txuserclk2; + +assign qsfp0_tx_clk_int = qsfp0_txuserclk2; +assign qsfp0_rx_clk_int = qsfp0_txuserclk2; + +wire qsfp1_txuserclk2; + +assign qsfp1_tx_clk_int = qsfp1_txuserclk2; +assign qsfp1_rx_clk_int = qsfp1_txuserclk2; + +cmac_pad #( + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .USER_WIDTH(1) +) +qsfp0_cmac_pad_inst ( + .clk(qsfp0_tx_clk_int), + .rst(qsfp0_tx_rst_int), + + .s_axis_tdata(qsfp0_tx_axis_tdata_int), + .s_axis_tkeep(qsfp0_tx_axis_tkeep_int), + .s_axis_tvalid(qsfp0_tx_axis_tvalid_int), + .s_axis_tready(qsfp0_tx_axis_tready_int), + .s_axis_tlast(qsfp0_tx_axis_tlast_int), + .s_axis_tuser(qsfp0_tx_axis_tuser_int), + + .m_axis_tdata(qsfp0_mac_tx_axis_tdata), + .m_axis_tkeep(qsfp0_mac_tx_axis_tkeep), + .m_axis_tvalid(qsfp0_mac_tx_axis_tvalid), + .m_axis_tready(qsfp0_mac_tx_axis_tready), + .m_axis_tlast(qsfp0_mac_tx_axis_tlast), + .m_axis_tuser(qsfp0_mac_tx_axis_tuser) +); + +cmac_usplus_0 +qsfp0_cmac_inst ( + .gt_rxp_in({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}), // input + .gt_rxn_in({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}), // input + .gt_txp_out({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}), // output + .gt_txn_out({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}), // output + .gt_txusrclk2(qsfp0_txuserclk2), // output + .gt_loopback_in(12'd0), // input [11:0] + .gt_rxrecclkout(), // output [3:0] + .gt_powergoodout(), // output [3:0] + .gt_ref_clk_out(clk_161mhz_ref_int), // output + .gtwiz_reset_tx_datapath(1'b0), // input + .gtwiz_reset_rx_datapath(1'b0), // input + .sys_reset(rst_125mhz_int), // input + .gt_ref_clk_p(qsfp0_mgt_refclk_1_p), // input + .gt_ref_clk_n(qsfp0_mgt_refclk_1_n), // input + .init_clk(clk_125mhz_int), // input + + .rx_axis_tvalid(qsfp0_rx_axis_tvalid_int), // output + .rx_axis_tdata(qsfp0_rx_axis_tdata_int), // output [511:0] + .rx_axis_tlast(qsfp0_rx_axis_tlast_int), // output + .rx_axis_tkeep(qsfp0_rx_axis_tkeep_int), // output [63:0] + .rx_axis_tuser(qsfp0_rx_axis_tuser_int), // output + + .rx_otn_bip8_0(), // output [7:0] + .rx_otn_bip8_1(), // output [7:0] + .rx_otn_bip8_2(), // output [7:0] + .rx_otn_bip8_3(), // output [7:0] + .rx_otn_bip8_4(), // output [7:0] + .rx_otn_data_0(), // output [65:0] + .rx_otn_data_1(), // output [65:0] + .rx_otn_data_2(), // output [65:0] + .rx_otn_data_3(), // output [65:0] + .rx_otn_data_4(), // output [65:0] + .rx_otn_ena(), // output + .rx_otn_lane0(), // output + .rx_otn_vlmarker(), // output + .rx_preambleout(), // output [55:0] + .usr_rx_reset(qsfp0_rx_rst_int), // output + .gt_rxusrclk2(), // output + + .stat_rx_aligned(), // output + .stat_rx_aligned_err(), // output + .stat_rx_bad_code(), // output [2:0] + .stat_rx_bad_fcs(), // output [2:0] + .stat_rx_bad_preamble(), // output + .stat_rx_bad_sfd(), // output + .stat_rx_bip_err_0(), // output + .stat_rx_bip_err_1(), // output + .stat_rx_bip_err_10(), // output + .stat_rx_bip_err_11(), // output + .stat_rx_bip_err_12(), // output + .stat_rx_bip_err_13(), // output + .stat_rx_bip_err_14(), // output + .stat_rx_bip_err_15(), // output + .stat_rx_bip_err_16(), // output + .stat_rx_bip_err_17(), // output + .stat_rx_bip_err_18(), // output + .stat_rx_bip_err_19(), // output + .stat_rx_bip_err_2(), // output + .stat_rx_bip_err_3(), // output + .stat_rx_bip_err_4(), // output + .stat_rx_bip_err_5(), // output + .stat_rx_bip_err_6(), // output + .stat_rx_bip_err_7(), // output + .stat_rx_bip_err_8(), // output + .stat_rx_bip_err_9(), // output + .stat_rx_block_lock(), // output [19:0] + .stat_rx_broadcast(), // output + .stat_rx_fragment(), // output [2:0] + .stat_rx_framing_err_0(), // output [1:0] + .stat_rx_framing_err_1(), // output [1:0] + .stat_rx_framing_err_10(), // output [1:0] + .stat_rx_framing_err_11(), // output [1:0] + .stat_rx_framing_err_12(), // output [1:0] + .stat_rx_framing_err_13(), // output [1:0] + .stat_rx_framing_err_14(), // output [1:0] + .stat_rx_framing_err_15(), // output [1:0] + .stat_rx_framing_err_16(), // output [1:0] + .stat_rx_framing_err_17(), // output [1:0] + .stat_rx_framing_err_18(), // output [1:0] + .stat_rx_framing_err_19(), // output [1:0] + .stat_rx_framing_err_2(), // output [1:0] + .stat_rx_framing_err_3(), // output [1:0] + .stat_rx_framing_err_4(), // output [1:0] + .stat_rx_framing_err_5(), // output [1:0] + .stat_rx_framing_err_6(), // output [1:0] + .stat_rx_framing_err_7(), // output [1:0] + .stat_rx_framing_err_8(), // output [1:0] + .stat_rx_framing_err_9(), // output [1:0] + .stat_rx_framing_err_valid_0(), // output + .stat_rx_framing_err_valid_1(), // output + .stat_rx_framing_err_valid_10(), // output + .stat_rx_framing_err_valid_11(), // output + .stat_rx_framing_err_valid_12(), // output + .stat_rx_framing_err_valid_13(), // output + .stat_rx_framing_err_valid_14(), // output + .stat_rx_framing_err_valid_15(), // output + .stat_rx_framing_err_valid_16(), // output + .stat_rx_framing_err_valid_17(), // output + .stat_rx_framing_err_valid_18(), // output + .stat_rx_framing_err_valid_19(), // output + .stat_rx_framing_err_valid_2(), // output + .stat_rx_framing_err_valid_3(), // output + .stat_rx_framing_err_valid_4(), // output + .stat_rx_framing_err_valid_5(), // output + .stat_rx_framing_err_valid_6(), // output + .stat_rx_framing_err_valid_7(), // output + .stat_rx_framing_err_valid_8(), // output + .stat_rx_framing_err_valid_9(), // output + .stat_rx_got_signal_os(), // output + .stat_rx_hi_ber(), // output + .stat_rx_inrangeerr(), // output + .stat_rx_internal_local_fault(), // output + .stat_rx_jabber(), // output + .stat_rx_local_fault(), // output + .stat_rx_mf_err(), // output [19:0] + .stat_rx_mf_len_err(), // output [19:0] + .stat_rx_mf_repeat_err(), // output [19:0] + .stat_rx_misaligned(), // output + .stat_rx_multicast(), // output + .stat_rx_oversize(), // output + .stat_rx_packet_1024_1518_bytes(), // output + .stat_rx_packet_128_255_bytes(), // output + .stat_rx_packet_1519_1522_bytes(), // output + .stat_rx_packet_1523_1548_bytes(), // output + .stat_rx_packet_1549_2047_bytes(), // output + .stat_rx_packet_2048_4095_bytes(), // output + .stat_rx_packet_256_511_bytes(), // output + .stat_rx_packet_4096_8191_bytes(), // output + .stat_rx_packet_512_1023_bytes(), // output + .stat_rx_packet_64_bytes(), // output + .stat_rx_packet_65_127_bytes(), // output + .stat_rx_packet_8192_9215_bytes(), // output + .stat_rx_packet_bad_fcs(), // output + .stat_rx_packet_large(), // output + .stat_rx_packet_small(), // output [2:0] + + .ctl_rx_enable(1'b1), // input + .ctl_rx_force_resync(1'b0), // input + .ctl_rx_test_pattern(1'b0), // input + .ctl_rsfec_ieee_error_indication_mode(1'b0), // input + .ctl_rx_rsfec_enable(1'b1), // input + .ctl_rx_rsfec_enable_correction(1'b1), // input + .ctl_rx_rsfec_enable_indication(1'b1), // input + .core_rx_reset(1'b0), // input + .rx_clk(qsfp0_rx_clk_int), // input + + .stat_rx_received_local_fault(), // output + .stat_rx_remote_fault(), // output + .stat_rx_status(), // output + .stat_rx_stomped_fcs(), // output [2:0] + .stat_rx_synced(), // output [19:0] + .stat_rx_synced_err(), // output [19:0] + .stat_rx_test_pattern_mismatch(), // output [2:0] + .stat_rx_toolong(), // output + .stat_rx_total_bytes(), // output [6:0] + .stat_rx_total_good_bytes(), // output [13:0] + .stat_rx_total_good_packets(), // output + .stat_rx_total_packets(), // output [2:0] + .stat_rx_truncated(), // output + .stat_rx_undersize(), // output [2:0] + .stat_rx_unicast(), // output + .stat_rx_vlan(), // output + .stat_rx_pcsl_demuxed(), // output [19:0] + .stat_rx_pcsl_number_0(), // output [4:0] + .stat_rx_pcsl_number_1(), // output [4:0] + .stat_rx_pcsl_number_10(), // output [4:0] + .stat_rx_pcsl_number_11(), // output [4:0] + .stat_rx_pcsl_number_12(), // output [4:0] + .stat_rx_pcsl_number_13(), // output [4:0] + .stat_rx_pcsl_number_14(), // output [4:0] + .stat_rx_pcsl_number_15(), // output [4:0] + .stat_rx_pcsl_number_16(), // output [4:0] + .stat_rx_pcsl_number_17(), // output [4:0] + .stat_rx_pcsl_number_18(), // output [4:0] + .stat_rx_pcsl_number_19(), // output [4:0] + .stat_rx_pcsl_number_2(), // output [4:0] + .stat_rx_pcsl_number_3(), // output [4:0] + .stat_rx_pcsl_number_4(), // output [4:0] + .stat_rx_pcsl_number_5(), // output [4:0] + .stat_rx_pcsl_number_6(), // output [4:0] + .stat_rx_pcsl_number_7(), // output [4:0] + .stat_rx_pcsl_number_8(), // output [4:0] + .stat_rx_pcsl_number_9(), // output [4:0] + .stat_rx_rsfec_am_lock0(), // output + .stat_rx_rsfec_am_lock1(), // output + .stat_rx_rsfec_am_lock2(), // output + .stat_rx_rsfec_am_lock3(), // output + .stat_rx_rsfec_corrected_cw_inc(), // output + .stat_rx_rsfec_cw_inc(), // output + .stat_rx_rsfec_err_count0_inc(), // output [2:0] + .stat_rx_rsfec_err_count1_inc(), // output [2:0] + .stat_rx_rsfec_err_count2_inc(), // output [2:0] + .stat_rx_rsfec_err_count3_inc(), // output [2:0] + .stat_rx_rsfec_hi_ser(), // output + .stat_rx_rsfec_lane_alignment_status(), // output + .stat_rx_rsfec_lane_fill_0(), // output [13:0] + .stat_rx_rsfec_lane_fill_1(), // output [13:0] + .stat_rx_rsfec_lane_fill_2(), // output [13:0] + .stat_rx_rsfec_lane_fill_3(), // output [13:0] + .stat_rx_rsfec_lane_mapping(), // output [7:0] + .stat_rx_rsfec_uncorrected_cw_inc(), // output + + .stat_tx_bad_fcs(), // output + .stat_tx_broadcast(), // output + .stat_tx_frame_error(), // output + .stat_tx_local_fault(), // output + .stat_tx_multicast(), // output + .stat_tx_packet_1024_1518_bytes(), // output + .stat_tx_packet_128_255_bytes(), // output + .stat_tx_packet_1519_1522_bytes(), // output + .stat_tx_packet_1523_1548_bytes(), // output + .stat_tx_packet_1549_2047_bytes(), // output + .stat_tx_packet_2048_4095_bytes(), // output + .stat_tx_packet_256_511_bytes(), // output + .stat_tx_packet_4096_8191_bytes(), // output + .stat_tx_packet_512_1023_bytes(), // output + .stat_tx_packet_64_bytes(), // output + .stat_tx_packet_65_127_bytes(), // output + .stat_tx_packet_8192_9215_bytes(), // output + .stat_tx_packet_large(), // output + .stat_tx_packet_small(), // output + .stat_tx_total_bytes(), // output [5:0] + .stat_tx_total_good_bytes(), // output [13:0] + .stat_tx_total_good_packets(), // output + .stat_tx_total_packets(), // output + .stat_tx_unicast(), // output + .stat_tx_vlan(), // output + + .ctl_tx_enable(1'b1), // input + .ctl_tx_test_pattern(1'b0), // input + .ctl_tx_rsfec_enable(1'b1), // input + .ctl_tx_send_idle(1'b0), // input + .ctl_tx_send_rfi(1'b0), // input + .ctl_tx_send_lfi(1'b0), // input + .core_tx_reset(1'b0), // input + + .tx_axis_tready(qsfp0_mac_tx_axis_tready), // output + .tx_axis_tvalid(qsfp0_mac_tx_axis_tvalid), // input + .tx_axis_tdata(qsfp0_mac_tx_axis_tdata), // input [511:0] + .tx_axis_tlast(qsfp0_mac_tx_axis_tlast), // input + .tx_axis_tkeep(qsfp0_mac_tx_axis_tkeep), // input [63:0] + .tx_axis_tuser(qsfp0_mac_tx_axis_tuser), // input + + .tx_ovfout(), // output + .tx_unfout(), // output + .tx_preamblein(56'd0), // input [55:0] + .usr_tx_reset(qsfp0_tx_rst_int), // output + + .core_drp_reset(1'b0), // input + .drp_clk(1'b0), // input + .drp_addr(10'd0), // input [9:0] + .drp_di(16'd0), // input [15:0] + .drp_en(1'b0), // input + .drp_do(), // output [15:0] + .drp_rdy(), // output + .drp_we(1'b0) // input +); + +cmac_pad #( + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .USER_WIDTH(1) +) +qsfp1_cmac_pad_inst ( + .clk(qsfp1_tx_clk_int), + .rst(qsfp1_tx_rst_int), + + .s_axis_tdata(qsfp1_tx_axis_tdata_int), + .s_axis_tkeep(qsfp1_tx_axis_tkeep_int), + .s_axis_tvalid(qsfp1_tx_axis_tvalid_int), + .s_axis_tready(qsfp1_tx_axis_tready_int), + .s_axis_tlast(qsfp1_tx_axis_tlast_int), + .s_axis_tuser(qsfp1_tx_axis_tuser_int), + + .m_axis_tdata(qsfp1_mac_tx_axis_tdata), + .m_axis_tkeep(qsfp1_mac_tx_axis_tkeep), + .m_axis_tvalid(qsfp1_mac_tx_axis_tvalid), + .m_axis_tready(qsfp1_mac_tx_axis_tready), + .m_axis_tlast(qsfp1_mac_tx_axis_tlast), + .m_axis_tuser(qsfp1_mac_tx_axis_tuser) +); + +cmac_usplus_1 +qsfp1_cmac_inst ( + .gt_rxp_in({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}), // input + .gt_rxn_in({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}), // input + .gt_txp_out({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}), // output + .gt_txn_out({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}), // output + .gt_txusrclk2(qsfp1_txuserclk2), // output + .gt_loopback_in(12'd0), // input [11:0] + .gt_rxrecclkout(), // output [3:0] + .gt_powergoodout(), // output [3:0] + .gt_ref_clk_out(), // output + .gtwiz_reset_tx_datapath(1'b0), // input + .gtwiz_reset_rx_datapath(1'b0), // input + .sys_reset(rst_125mhz_int), // input + .gt_ref_clk_p(qsfp1_mgt_refclk_1_p), // input + .gt_ref_clk_n(qsfp1_mgt_refclk_1_n), // input + .init_clk(clk_125mhz_int), // input + + .rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), // output + .rx_axis_tdata(qsfp1_rx_axis_tdata_int), // output [511:0] + .rx_axis_tlast(qsfp1_rx_axis_tlast_int), // output + .rx_axis_tkeep(qsfp1_rx_axis_tkeep_int), // output [63:0] + .rx_axis_tuser(qsfp1_rx_axis_tuser_int), // output + + .rx_otn_bip8_0(), // output [7:0] + .rx_otn_bip8_1(), // output [7:0] + .rx_otn_bip8_2(), // output [7:0] + .rx_otn_bip8_3(), // output [7:0] + .rx_otn_bip8_4(), // output [7:0] + .rx_otn_data_0(), // output [65:0] + .rx_otn_data_1(), // output [65:0] + .rx_otn_data_2(), // output [65:0] + .rx_otn_data_3(), // output [65:0] + .rx_otn_data_4(), // output [65:0] + .rx_otn_ena(), // output + .rx_otn_lane0(), // output + .rx_otn_vlmarker(), // output + .rx_preambleout(), // output [55:0] + .usr_rx_reset(qsfp1_rx_rst_int), // output + .gt_rxusrclk2(), // output + + .stat_rx_aligned(), // output + .stat_rx_aligned_err(), // output + .stat_rx_bad_code(), // output [2:0] + .stat_rx_bad_fcs(), // output [2:0] + .stat_rx_bad_preamble(), // output + .stat_rx_bad_sfd(), // output + .stat_rx_bip_err_0(), // output + .stat_rx_bip_err_1(), // output + .stat_rx_bip_err_10(), // output + .stat_rx_bip_err_11(), // output + .stat_rx_bip_err_12(), // output + .stat_rx_bip_err_13(), // output + .stat_rx_bip_err_14(), // output + .stat_rx_bip_err_15(), // output + .stat_rx_bip_err_16(), // output + .stat_rx_bip_err_17(), // output + .stat_rx_bip_err_18(), // output + .stat_rx_bip_err_19(), // output + .stat_rx_bip_err_2(), // output + .stat_rx_bip_err_3(), // output + .stat_rx_bip_err_4(), // output + .stat_rx_bip_err_5(), // output + .stat_rx_bip_err_6(), // output + .stat_rx_bip_err_7(), // output + .stat_rx_bip_err_8(), // output + .stat_rx_bip_err_9(), // output + .stat_rx_block_lock(), // output [19:0] + .stat_rx_broadcast(), // output + .stat_rx_fragment(), // output [2:0] + .stat_rx_framing_err_0(), // output [1:0] + .stat_rx_framing_err_1(), // output [1:0] + .stat_rx_framing_err_10(), // output [1:0] + .stat_rx_framing_err_11(), // output [1:0] + .stat_rx_framing_err_12(), // output [1:0] + .stat_rx_framing_err_13(), // output [1:0] + .stat_rx_framing_err_14(), // output [1:0] + .stat_rx_framing_err_15(), // output [1:0] + .stat_rx_framing_err_16(), // output [1:0] + .stat_rx_framing_err_17(), // output [1:0] + .stat_rx_framing_err_18(), // output [1:0] + .stat_rx_framing_err_19(), // output [1:0] + .stat_rx_framing_err_2(), // output [1:0] + .stat_rx_framing_err_3(), // output [1:0] + .stat_rx_framing_err_4(), // output [1:0] + .stat_rx_framing_err_5(), // output [1:0] + .stat_rx_framing_err_6(), // output [1:0] + .stat_rx_framing_err_7(), // output [1:0] + .stat_rx_framing_err_8(), // output [1:0] + .stat_rx_framing_err_9(), // output [1:0] + .stat_rx_framing_err_valid_0(), // output + .stat_rx_framing_err_valid_1(), // output + .stat_rx_framing_err_valid_10(), // output + .stat_rx_framing_err_valid_11(), // output + .stat_rx_framing_err_valid_12(), // output + .stat_rx_framing_err_valid_13(), // output + .stat_rx_framing_err_valid_14(), // output + .stat_rx_framing_err_valid_15(), // output + .stat_rx_framing_err_valid_16(), // output + .stat_rx_framing_err_valid_17(), // output + .stat_rx_framing_err_valid_18(), // output + .stat_rx_framing_err_valid_19(), // output + .stat_rx_framing_err_valid_2(), // output + .stat_rx_framing_err_valid_3(), // output + .stat_rx_framing_err_valid_4(), // output + .stat_rx_framing_err_valid_5(), // output + .stat_rx_framing_err_valid_6(), // output + .stat_rx_framing_err_valid_7(), // output + .stat_rx_framing_err_valid_8(), // output + .stat_rx_framing_err_valid_9(), // output + .stat_rx_got_signal_os(), // output + .stat_rx_hi_ber(), // output + .stat_rx_inrangeerr(), // output + .stat_rx_internal_local_fault(), // output + .stat_rx_jabber(), // output + .stat_rx_local_fault(), // output + .stat_rx_mf_err(), // output [19:0] + .stat_rx_mf_len_err(), // output [19:0] + .stat_rx_mf_repeat_err(), // output [19:0] + .stat_rx_misaligned(), // output + .stat_rx_multicast(), // output + .stat_rx_oversize(), // output + .stat_rx_packet_1024_1518_bytes(), // output + .stat_rx_packet_128_255_bytes(), // output + .stat_rx_packet_1519_1522_bytes(), // output + .stat_rx_packet_1523_1548_bytes(), // output + .stat_rx_packet_1549_2047_bytes(), // output + .stat_rx_packet_2048_4095_bytes(), // output + .stat_rx_packet_256_511_bytes(), // output + .stat_rx_packet_4096_8191_bytes(), // output + .stat_rx_packet_512_1023_bytes(), // output + .stat_rx_packet_64_bytes(), // output + .stat_rx_packet_65_127_bytes(), // output + .stat_rx_packet_8192_9215_bytes(), // output + .stat_rx_packet_bad_fcs(), // output + .stat_rx_packet_large(), // output + .stat_rx_packet_small(), // output [2:0] + + .ctl_rx_enable(1'b1), // input + .ctl_rx_force_resync(1'b0), // input + .ctl_rx_test_pattern(1'b0), // input + .ctl_rsfec_ieee_error_indication_mode(1'b0), // input + .ctl_rx_rsfec_enable(1'b1), // input + .ctl_rx_rsfec_enable_correction(1'b1), // input + .ctl_rx_rsfec_enable_indication(1'b1), // input + .core_rx_reset(1'b0), // input + .rx_clk(qsfp1_rx_clk_int), // input + + .stat_rx_received_local_fault(), // output + .stat_rx_remote_fault(), // output + .stat_rx_status(), // output + .stat_rx_stomped_fcs(), // output [2:0] + .stat_rx_synced(), // output [19:0] + .stat_rx_synced_err(), // output [19:0] + .stat_rx_test_pattern_mismatch(), // output [2:0] + .stat_rx_toolong(), // output + .stat_rx_total_bytes(), // output [6:0] + .stat_rx_total_good_bytes(), // output [13:0] + .stat_rx_total_good_packets(), // output + .stat_rx_total_packets(), // output [2:0] + .stat_rx_truncated(), // output + .stat_rx_undersize(), // output [2:0] + .stat_rx_unicast(), // output + .stat_rx_vlan(), // output + .stat_rx_pcsl_demuxed(), // output [19:0] + .stat_rx_pcsl_number_0(), // output [4:0] + .stat_rx_pcsl_number_1(), // output [4:0] + .stat_rx_pcsl_number_10(), // output [4:0] + .stat_rx_pcsl_number_11(), // output [4:0] + .stat_rx_pcsl_number_12(), // output [4:0] + .stat_rx_pcsl_number_13(), // output [4:0] + .stat_rx_pcsl_number_14(), // output [4:0] + .stat_rx_pcsl_number_15(), // output [4:0] + .stat_rx_pcsl_number_16(), // output [4:0] + .stat_rx_pcsl_number_17(), // output [4:0] + .stat_rx_pcsl_number_18(), // output [4:0] + .stat_rx_pcsl_number_19(), // output [4:0] + .stat_rx_pcsl_number_2(), // output [4:0] + .stat_rx_pcsl_number_3(), // output [4:0] + .stat_rx_pcsl_number_4(), // output [4:0] + .stat_rx_pcsl_number_5(), // output [4:0] + .stat_rx_pcsl_number_6(), // output [4:0] + .stat_rx_pcsl_number_7(), // output [4:0] + .stat_rx_pcsl_number_8(), // output [4:0] + .stat_rx_pcsl_number_9(), // output [4:0] + .stat_rx_rsfec_am_lock0(), // output + .stat_rx_rsfec_am_lock1(), // output + .stat_rx_rsfec_am_lock2(), // output + .stat_rx_rsfec_am_lock3(), // output + .stat_rx_rsfec_corrected_cw_inc(), // output + .stat_rx_rsfec_cw_inc(), // output + .stat_rx_rsfec_err_count0_inc(), // output [2:0] + .stat_rx_rsfec_err_count1_inc(), // output [2:0] + .stat_rx_rsfec_err_count2_inc(), // output [2:0] + .stat_rx_rsfec_err_count3_inc(), // output [2:0] + .stat_rx_rsfec_hi_ser(), // output + .stat_rx_rsfec_lane_alignment_status(), // output + .stat_rx_rsfec_lane_fill_0(), // output [13:0] + .stat_rx_rsfec_lane_fill_1(), // output [13:0] + .stat_rx_rsfec_lane_fill_2(), // output [13:0] + .stat_rx_rsfec_lane_fill_3(), // output [13:0] + .stat_rx_rsfec_lane_mapping(), // output [7:0] + .stat_rx_rsfec_uncorrected_cw_inc(), // output + + .stat_tx_bad_fcs(), // output + .stat_tx_broadcast(), // output + .stat_tx_frame_error(), // output + .stat_tx_local_fault(), // output + .stat_tx_multicast(), // output + .stat_tx_packet_1024_1518_bytes(), // output + .stat_tx_packet_128_255_bytes(), // output + .stat_tx_packet_1519_1522_bytes(), // output + .stat_tx_packet_1523_1548_bytes(), // output + .stat_tx_packet_1549_2047_bytes(), // output + .stat_tx_packet_2048_4095_bytes(), // output + .stat_tx_packet_256_511_bytes(), // output + .stat_tx_packet_4096_8191_bytes(), // output + .stat_tx_packet_512_1023_bytes(), // output + .stat_tx_packet_64_bytes(), // output + .stat_tx_packet_65_127_bytes(), // output + .stat_tx_packet_8192_9215_bytes(), // output + .stat_tx_packet_large(), // output + .stat_tx_packet_small(), // output + .stat_tx_total_bytes(), // output [5:0] + .stat_tx_total_good_bytes(), // output [13:0] + .stat_tx_total_good_packets(), // output + .stat_tx_total_packets(), // output + .stat_tx_unicast(), // output + .stat_tx_vlan(), // output + + .ctl_tx_enable(1'b1), // input + .ctl_tx_test_pattern(1'b0), // input + .ctl_tx_rsfec_enable(1'b1), // input + .ctl_tx_send_idle(1'b0), // input + .ctl_tx_send_rfi(1'b0), // input + .ctl_tx_send_lfi(1'b0), // input + .core_tx_reset(1'b0), // input + + .tx_axis_tready(qsfp1_mac_tx_axis_tready), // output + .tx_axis_tvalid(qsfp1_mac_tx_axis_tvalid), // input + .tx_axis_tdata(qsfp1_mac_tx_axis_tdata), // input [511:0] + .tx_axis_tlast(qsfp1_mac_tx_axis_tlast), // input + .tx_axis_tkeep(qsfp1_mac_tx_axis_tkeep), // input [63:0] + .tx_axis_tuser(qsfp1_mac_tx_axis_tuser), // input + + .tx_ovfout(), // output + .tx_unfout(), // output + .tx_preamblein(56'd0), // input [55:0] + .usr_tx_reset(qsfp1_tx_rst_int), // output + + .core_drp_reset(1'b0), // input + .drp_clk(1'b0), // input + .drp_addr(10'd0), // input [9:0] + .drp_di(16'd0), // input [15:0] + .drp_en(1'b0), // input + .drp_do(), // output [15:0] + .drp_rdy(), // output + .drp_we(1'b0) // input +); + +fpga_core #( + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), + .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), + .BAR0_APERTURE(BAR0_APERTURE) +) +core_inst ( + /* + * Clock: 250 MHz + * Synchronous reset + */ + .clk_250mhz(pcie_user_clk), + .rst_250mhz(pcie_user_reset), + + /* + * PCIe + */ + .m_axis_rq_tdata(axis_rq_tdata), + .m_axis_rq_tkeep(axis_rq_tkeep), + .m_axis_rq_tlast(axis_rq_tlast), + .m_axis_rq_tready(axis_rq_tready), + .m_axis_rq_tuser(axis_rq_tuser), + .m_axis_rq_tvalid(axis_rq_tvalid), + + .s_axis_rc_tdata(axis_rc_tdata), + .s_axis_rc_tkeep(axis_rc_tkeep), + .s_axis_rc_tlast(axis_rc_tlast), + .s_axis_rc_tready(axis_rc_tready), + .s_axis_rc_tuser(axis_rc_tuser), + .s_axis_rc_tvalid(axis_rc_tvalid), + + .s_axis_cq_tdata(axis_cq_tdata), + .s_axis_cq_tkeep(axis_cq_tkeep), + .s_axis_cq_tlast(axis_cq_tlast), + .s_axis_cq_tready(axis_cq_tready), + .s_axis_cq_tuser(axis_cq_tuser), + .s_axis_cq_tvalid(axis_cq_tvalid), + + .m_axis_cc_tdata(axis_cc_tdata), + .m_axis_cc_tkeep(axis_cc_tkeep), + .m_axis_cc_tlast(axis_cc_tlast), + .m_axis_cc_tready(axis_cc_tready), + .m_axis_cc_tuser(axis_cc_tuser), + .m_axis_cc_tvalid(axis_cc_tvalid), + + .s_axis_rq_seq_num_0(pcie_rq_seq_num0_reg), + .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0_reg), + .s_axis_rq_seq_num_1(pcie_rq_seq_num1_reg), + .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1_reg), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .status_error_cor(status_error_cor), + .status_error_uncor(status_error_uncor), + + /* + * Ethernet: QSFP28 + */ + .qsfp0_tx_clk(qsfp0_tx_clk_int), + .qsfp0_tx_rst(qsfp0_tx_rst_int), + .qsfp0_tx_axis_tdata(qsfp0_tx_axis_tdata_int), + .qsfp0_tx_axis_tkeep(qsfp0_tx_axis_tkeep_int), + .qsfp0_tx_axis_tvalid(qsfp0_tx_axis_tvalid_int), + .qsfp0_tx_axis_tready(qsfp0_tx_axis_tready_int), + .qsfp0_tx_axis_tlast(qsfp0_tx_axis_tlast_int), + .qsfp0_tx_axis_tuser(qsfp0_tx_axis_tuser_int), + .qsfp0_rx_clk(qsfp0_rx_clk_int), + .qsfp0_rx_rst(qsfp0_rx_rst_int), + .qsfp0_rx_axis_tdata(qsfp0_rx_axis_tdata_int), + .qsfp0_rx_axis_tkeep(qsfp0_rx_axis_tkeep_int), + .qsfp0_rx_axis_tvalid(qsfp0_rx_axis_tvalid_int), + .qsfp0_rx_axis_tlast(qsfp0_rx_axis_tlast_int), + .qsfp0_rx_axis_tuser(qsfp0_rx_axis_tuser_int), + + .qsfp1_tx_clk(qsfp1_tx_clk_int), + .qsfp1_tx_rst(qsfp1_tx_rst_int), + .qsfp1_tx_axis_tdata(qsfp1_tx_axis_tdata_int), + .qsfp1_tx_axis_tkeep(qsfp1_tx_axis_tkeep_int), + .qsfp1_tx_axis_tvalid(qsfp1_tx_axis_tvalid_int), + .qsfp1_tx_axis_tready(qsfp1_tx_axis_tready_int), + .qsfp1_tx_axis_tlast(qsfp1_tx_axis_tlast_int), + .qsfp1_tx_axis_tuser(qsfp1_tx_axis_tuser_int), + .qsfp1_rx_clk(qsfp1_rx_clk_int), + .qsfp1_rx_rst(qsfp1_rx_rst_int), + .qsfp1_rx_axis_tdata(qsfp1_rx_axis_tdata_int), + .qsfp1_rx_axis_tkeep(qsfp1_rx_axis_tkeep_int), + .qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), + .qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast_int), + .qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser_int) +); + +endmodule diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v new file mode 100644 index 000000000..c65302bd0 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -0,0 +1,2343 @@ +/* + +Copyright 2019, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * FPGA core logic + */ +module fpga_core # +( + parameter TARGET = "XILINX", + parameter AXIS_PCIE_DATA_WIDTH = 512, + parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + parameter AXIS_PCIE_RC_USER_WIDTH = 161, + parameter AXIS_PCIE_RQ_USER_WIDTH = 137, + parameter AXIS_PCIE_CQ_USER_WIDTH = 183, + parameter AXIS_PCIE_CC_USER_WIDTH = 81, + parameter RQ_SEQ_NUM_WIDTH = 6, + parameter BAR0_APERTURE = 24, + parameter AXIS_ETH_DATA_WIDTH = 512, + parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8 +) +( + /* + * Clock: 250 MHz + * Synchronous reset + */ + input wire clk_250mhz, + input wire rst_250mhz, + + /* + * PCIe + */ + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, + output wire m_axis_rq_tlast, + input wire m_axis_rq_tready, + output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, + output wire m_axis_rq_tvalid, + + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, + input wire s_axis_rc_tlast, + output wire s_axis_rc_tready, + input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, + input wire s_axis_rc_tvalid, + + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, + input wire s_axis_cq_tlast, + output wire s_axis_cq_tready, + input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, + input wire s_axis_cq_tvalid, + + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, + output wire m_axis_cc_tlast, + input wire m_axis_cc_tready, + output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, + output wire m_axis_cc_tvalid, + + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, + input wire s_axis_rq_seq_num_valid_0, + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, + input wire s_axis_rq_seq_num_valid_1, + + input wire [1:0] pcie_tfc_nph_av, + input wire [1:0] pcie_tfc_npd_av, + + input wire [2:0] cfg_max_payload, + input wire [2:0] cfg_max_read_req, + + output wire [9:0] cfg_mgmt_addr, + output wire [7:0] cfg_mgmt_function_number, + output wire cfg_mgmt_write, + output wire [31:0] cfg_mgmt_write_data, + output wire [3:0] cfg_mgmt_byte_enable, + output wire cfg_mgmt_read, + input wire [31:0] cfg_mgmt_read_data, + input wire cfg_mgmt_read_write_done, + + input wire [7:0] cfg_fc_ph, + input wire [11:0] cfg_fc_pd, + input wire [7:0] cfg_fc_nph, + input wire [11:0] cfg_fc_npd, + input wire [7:0] cfg_fc_cplh, + input wire [11:0] cfg_fc_cpld, + output wire [2:0] cfg_fc_sel, + + input wire [3:0] cfg_interrupt_msi_enable, + input wire [11:0] cfg_interrupt_msi_mmenable, + input wire cfg_interrupt_msi_mask_update, + input wire [31:0] cfg_interrupt_msi_data, + output wire [3:0] cfg_interrupt_msi_select, + output wire [31:0] cfg_interrupt_msi_int, + output wire [31:0] cfg_interrupt_msi_pending_status, + output wire cfg_interrupt_msi_pending_status_data_enable, + output wire [3:0] cfg_interrupt_msi_pending_status_function_num, + input wire cfg_interrupt_msi_sent, + input wire cfg_interrupt_msi_fail, + output wire [2:0] cfg_interrupt_msi_attr, + output wire cfg_interrupt_msi_tph_present, + output wire [1:0] cfg_interrupt_msi_tph_type, + output wire [8:0] cfg_interrupt_msi_tph_st_tag, + output wire [3:0] cfg_interrupt_msi_function_number, + + output wire status_error_cor, + output wire status_error_uncor, + + /* + * Ethernet: QSFP28 + */ + input wire qsfp0_tx_clk, + input wire qsfp0_tx_rst, + + output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_tx_axis_tdata, + output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_tx_axis_tkeep, + output wire qsfp0_tx_axis_tvalid, + input wire qsfp0_tx_axis_tready, + output wire qsfp0_tx_axis_tlast, + output wire qsfp0_tx_axis_tuser, + + input wire qsfp0_rx_clk, + input wire qsfp0_rx_rst, + + input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_rx_axis_tdata, + input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_rx_axis_tkeep, + input wire qsfp0_rx_axis_tvalid, + input wire qsfp0_rx_axis_tlast, + input wire qsfp0_rx_axis_tuser, + + input wire qsfp1_tx_clk, + input wire qsfp1_tx_rst, + + output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_tx_axis_tdata, + output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_tx_axis_tkeep, + output wire qsfp1_tx_axis_tvalid, + input wire qsfp1_tx_axis_tready, + output wire qsfp1_tx_axis_tlast, + output wire qsfp1_tx_axis_tuser, + + input wire qsfp1_rx_clk, + input wire qsfp1_rx_rst, + + input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_rx_axis_tdata, + input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_rx_axis_tkeep, + input wire qsfp1_rx_axis_tvalid, + input wire qsfp1_rx_axis_tlast, + input wire qsfp1_rx_axis_tuser +); + +// PHC parameters +parameter PTP_PERIOD_NS_WIDTH = 4; +parameter PTP_OFFSET_NS_WIDTH = 32; +parameter PTP_FNS_WIDTH = 32; +parameter PTP_PERIOD_NS = 4'd4; +parameter PTP_PERIOD_FNS = 32'd0; + +// FW and board IDs +parameter FW_ID = 32'd0; +parameter FW_VER = {16'd0, 16'd1}; +parameter BOARD_ID = {16'h10ee, 16'h9118}; +parameter BOARD_VER = {16'd0, 16'd1}; +parameter FPGA_ID = 32'h4B7D093; + +// Structural parameters +parameter IF_COUNT = 2; +parameter PORTS_PER_IF = 1; + +parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; + +// Queue manager parameters (interface) +parameter EVENT_QUEUE_OP_TABLE_SIZE = 32; +parameter TX_QUEUE_OP_TABLE_SIZE = 32; +parameter RX_QUEUE_OP_TABLE_SIZE = 32; +parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE; +parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE; +parameter TX_QUEUE_INDEX_WIDTH = 13; +parameter RX_QUEUE_INDEX_WIDTH = 8; +parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH; +parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH; +parameter EVENT_QUEUE_PIPELINE = 3; +parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0); +parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0); +parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE; +parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; + +// TX and RX engine parameters (port) +parameter TX_DESC_TABLE_SIZE = 32; +parameter TX_PKT_TABLE_SIZE = 8; +parameter RX_DESC_TABLE_SIZE = 32; +parameter RX_PKT_TABLE_SIZE = 8; + +// Scheduler parameters (port) +parameter TX_SCHEDULER = "RR"; +parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE; +parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE; +parameter TDMA_INDEX_WIDTH = 6; + +// Timstamping parameters (port) +parameter LOGIC_PTP_PERIOD_NS = 6'h4; +parameter LOGIC_PTP_PERIOD_FNS = 16'h0000; +parameter IF_PTP_PERIOD_NS = 6'h3; +parameter IF_PTP_PERIOD_FNS = 16'h1a60; +parameter PTP_TS_ENABLE = 0; +parameter PTP_TS_WIDTH = 96; +parameter TX_PTP_TS_FIFO_DEPTH = 32; +parameter RX_PTP_TS_FIFO_DEPTH = 32; + +// Interface parameters (port) +parameter TX_CHECKSUM_ENABLE = 1; +parameter RX_RSS_ENABLE = 1; +parameter RX_HASH_ENABLE = 1; +parameter RX_CHECKSUM_ENABLE = 1; +parameter ENABLE_PADDING = 1; +parameter ENABLE_DIC = 1; +parameter MIN_FRAME_LENGTH = 64; +parameter TX_FIFO_DEPTH = 32768; +parameter RX_FIFO_DEPTH = 131072; +parameter MAX_TX_SIZE = 16384; +parameter MAX_RX_SIZE = 16384; + +// AXI lite interface parameters +parameter AXIL_DATA_WIDTH = 32; +parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8); +parameter AXIL_ADDR_WIDTH = BAR0_APERTURE; + +parameter IF_AXIL_ADDR_WIDTH = AXIL_ADDR_WIDTH-$clog2(IF_COUNT); +parameter AXIL_CSR_ADDR_WIDTH = IF_AXIL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); + +// AXI stream interface parameters +parameter AXIS_DATA_WIDTH = AXIS_ETH_DATA_WIDTH; +parameter AXIS_KEEP_WIDTH = AXIS_ETH_KEEP_WIDTH; + +// PCIe DMA parameters +parameter PCIE_ADDR_WIDTH = 64; +parameter PCIE_DMA_LEN_WIDTH = 16; +parameter PCIE_DMA_TAG_WIDTH = 16; +parameter IF_PCIE_DMA_TAG_WIDTH = PCIE_DMA_TAG_WIDTH-$clog2(IF_COUNT)-1; +parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2; +parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT; +parameter SEG_ADDR_WIDTH = 12; +parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8; +parameter IF_RAM_SEL_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1; +parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; +parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); +parameter RAM_PIPELINE = 2; + +parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; +parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; + +// parameter sizing helpers +function [31:0] w_32(input [31:0] val); + w_32 = val; +endfunction + +// AXI lite connections +wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr; +wire [2:0] axil_pcie_awprot; +wire axil_pcie_awvalid; +wire axil_pcie_awready; +wire [AXIL_DATA_WIDTH-1:0] axil_pcie_wdata; +wire [AXIL_STRB_WIDTH-1:0] axil_pcie_wstrb; +wire axil_pcie_wvalid; +wire axil_pcie_wready; +wire [1:0] axil_pcie_bresp; +wire axil_pcie_bvalid; +wire axil_pcie_bready; +wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_araddr; +wire [2:0] axil_pcie_arprot; +wire axil_pcie_arvalid; +wire axil_pcie_arready; +wire [AXIL_DATA_WIDTH-1:0] axil_pcie_rdata; +wire [1:0] axil_pcie_rresp; +wire axil_pcie_rvalid; +wire axil_pcie_rready; + +wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; +wire [2:0] axil_csr_awprot; +wire axil_csr_awvalid; +wire axil_csr_awready; +wire [AXIL_DATA_WIDTH-1:0] axil_csr_wdata; +wire [AXIL_STRB_WIDTH-1:0] axil_csr_wstrb; +wire axil_csr_wvalid; +wire axil_csr_wready; +wire [1:0] axil_csr_bresp; +wire axil_csr_bvalid; +wire axil_csr_bready; +wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr; +wire [2:0] axil_csr_arprot; +wire axil_csr_arvalid; +wire axil_csr_arready; +wire [AXIL_DATA_WIDTH-1:0] axil_csr_rdata; +wire [1:0] axil_csr_rresp; +wire axil_csr_rvalid; +wire axil_csr_rready; + +// DMA connections +wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready; +wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready; + +// Error handling +wire [1:0] status_error_uncor_int; +wire [1:0] status_error_cor_int; + +wire [31:0] msi_irq; + +wire ext_tag_enable; + +// PCIe DMA control +wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr; +wire [RAM_SEL_WIDTH-1:0] pcie_dma_read_desc_ram_sel; +wire [RAM_ADDR_WIDTH-1:0] pcie_dma_read_desc_ram_addr; +wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_read_desc_len; +wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_tag; +wire pcie_dma_read_desc_valid; +wire pcie_dma_read_desc_ready; + +wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; +wire pcie_dma_read_desc_status_valid; + +wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; +wire [RAM_SEL_WIDTH-1:0] pcie_dma_write_desc_ram_sel; +wire [RAM_ADDR_WIDTH-1:0] pcie_dma_write_desc_ram_addr; +wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_write_desc_len; +wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_tag; +wire pcie_dma_write_desc_valid; +wire pcie_dma_write_desc_ready; + +wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; +wire pcie_dma_write_desc_status_valid; + +wire pcie_dma_enable = 1; + +wire [95:0] ptp_ts_96; +wire ptp_ts_step; +wire ptp_pps; + +// control registers +reg axil_csr_awready_reg = 1'b0; +reg axil_csr_wready_reg = 1'b0; +reg axil_csr_bvalid_reg = 1'b0; +reg axil_csr_arready_reg = 1'b0; +reg [AXIL_DATA_WIDTH-1:0] axil_csr_rdata_reg = {AXIL_DATA_WIDTH{1'b0}}; +reg axil_csr_rvalid_reg = 1'b0; + +// reg qsfp0_modsell_reg = 1'b0; +// reg qsfp1_modsell_reg = 1'b0; + +// reg qsfp0_lpmode_reg = 1'b0; +// reg qsfp1_lpmode_reg = 1'b0; + +// reg qsfp0_resetl_reg = 1'b1; +// reg qsfp1_resetl_reg = 1'b1; + +// reg i2c_scl_o_reg = 1'b1; +// reg i2c_sda_o_reg = 1'b1; + +reg pcie_dma_enable_reg = 0; + +reg [95:0] get_ptp_ts_96_reg = 0; +reg [95:0] set_ptp_ts_96_reg = 0; +reg set_ptp_ts_96_valid_reg = 0; +reg [PTP_PERIOD_NS_WIDTH-1:0] set_ptp_period_ns_reg = 0; +reg [PTP_FNS_WIDTH-1:0] set_ptp_period_fns_reg = 0; +reg set_ptp_period_valid_reg = 0; +reg [PTP_OFFSET_NS_WIDTH-1:0] set_ptp_offset_ns_reg = 0; +reg [PTP_FNS_WIDTH-1:0] set_ptp_offset_fns_reg = 0; +reg [15:0] set_ptp_offset_count_reg = 0; +reg set_ptp_offset_valid_reg = 0; +wire set_ptp_offset_active; + +assign axil_csr_awready = axil_csr_awready_reg; +assign axil_csr_wready = axil_csr_wready_reg; +assign axil_csr_bresp = 2'b00; +assign axil_csr_bvalid = axil_csr_bvalid_reg; +assign axil_csr_arready = axil_csr_arready_reg; +assign axil_csr_rdata = axil_csr_rdata_reg; +assign axil_csr_rresp = 2'b00; +assign axil_csr_rvalid = axil_csr_rvalid_reg; + +//assign pcie_dma_enable = pcie_dma_enable_reg; + +always @(posedge clk_250mhz) begin + axil_csr_awready_reg <= 1'b0; + axil_csr_wready_reg <= 1'b0; + axil_csr_bvalid_reg <= axil_csr_bvalid_reg && !axil_csr_bready; + axil_csr_arready_reg <= 1'b0; + axil_csr_rvalid_reg <= axil_csr_rvalid_reg && !axil_csr_rready; + + pcie_dma_enable_reg <= pcie_dma_enable_reg; + + set_ptp_ts_96_valid_reg <= 1'b0; + set_ptp_period_valid_reg <= 1'b0; + set_ptp_offset_valid_reg <= 1'b0; + + if (axil_csr_awvalid && axil_csr_wvalid && !axil_csr_bvalid) begin + // write operation + axil_csr_awready_reg <= 1'b1; + axil_csr_wready_reg <= 1'b1; + axil_csr_bvalid_reg <= 1'b1; + + case ({axil_csr_awaddr[15:2], 2'b00}) + // GPIO + 16'h0100: begin + // GPIO out + // if (axil_csr_wstrb[1]) begin + // qsfp0_modsell_reg <= axil_csr_wdata[9]; + // qsfp1_modsell_reg <= axil_csr_wdata[11]; + // end + // if (axil_csr_wstrb[0]) begin + // qsfp0_resetl_reg <= axil_csr_wdata[0]; + // qsfp0_lpmode_reg <= axil_csr_wdata[2]; + // qsfp1_resetl_reg <= axil_csr_wdata[4]; + // qsfp1_lpmode_reg <= axil_csr_wdata[6]; + // end + // if (axil_csr_wstrb[2]) begin + // i2c_scl_o_reg <= axil_csr_wdata[16]; + // i2c_sda_o_reg <= axil_csr_wdata[17]; + // end + end + // PHC + 16'h0230: set_ptp_ts_96_reg[15:0] <= axil_csr_wdata; // PTP set fns + 16'h0234: set_ptp_ts_96_reg[45:16] <= axil_csr_wdata; // PTP set ns + 16'h0238: set_ptp_ts_96_reg[79:48] <= axil_csr_wdata; // PTP set sec l + 16'h023C: begin + // PTP set sec h + set_ptp_ts_96_reg[95:80] <= axil_csr_wdata; + set_ptp_ts_96_valid_reg <= 1'b1; + end + 16'h0240: set_ptp_period_fns_reg <= axil_csr_wdata; // PTP period fns + 16'h0244: begin + // PTP period ns + set_ptp_period_ns_reg <= axil_csr_wdata; + set_ptp_period_valid_reg <= 1'b1; + end + 16'h0250: set_ptp_offset_fns_reg <= axil_csr_wdata; // PTP offset fns + 16'h0254: set_ptp_offset_ns_reg <= axil_csr_wdata; // PTP offset ns + 16'h0258: begin + // PTP offset count + set_ptp_offset_count_reg <= axil_csr_wdata; + set_ptp_offset_valid_reg <= 1'b1; + end + endcase + end + + if (axil_csr_arvalid && !axil_csr_rvalid) begin + // read operation + axil_csr_arready_reg <= 1'b1; + axil_csr_rvalid_reg <= 1'b1; + axil_csr_rdata_reg <= {AXIL_DATA_WIDTH{1'b0}}; + + case ({axil_csr_araddr[15:2], 2'b00}) + 16'h0000: axil_csr_rdata_reg <= FW_ID; // fw_id + 16'h0004: axil_csr_rdata_reg <= FW_VER; // fw_ver + 16'h0008: axil_csr_rdata_reg <= BOARD_ID; // board_id + 16'h000C: axil_csr_rdata_reg <= BOARD_VER; // board_ver + 16'h0010: axil_csr_rdata_reg <= 1; // phc_count + 16'h0014: axil_csr_rdata_reg <= 16'h0200; // phc_offset + 16'h0018: axil_csr_rdata_reg <= 16'h0080; // phc_stride + 16'h0020: axil_csr_rdata_reg <= IF_COUNT; // if_count + 16'h0024: axil_csr_rdata_reg <= 2**IF_AXIL_ADDR_WIDTH; // if_stride + 16'h002C: axil_csr_rdata_reg <= 2**AXIL_CSR_ADDR_WIDTH; // if_csr_offset + 16'h0040: axil_csr_rdata_reg <= FPGA_ID; // fpga_id + // GPIO + 16'h0100: begin + // GPIO out + // axil_csr_rdata_reg[9] <= qsfp0_modsell_reg; + // axil_csr_rdata_reg[11] <= qsfp1_modsell_reg; + // axil_csr_rdata_reg[0] <= qsfp0_resetl_reg; + // axil_csr_rdata_reg[2] <= qsfp0_lpmode_reg; + // axil_csr_rdata_reg[4] <= qsfp1_resetl_reg; + // axil_csr_rdata_reg[6] <= qsfp1_lpmode_reg; + // axil_csr_rdata_reg[16] <= i2c_scl_o_reg; + // axil_csr_rdata_reg[17] <= i2c_sda_o_reg; + end + 16'h0104: begin + // GPIO in + // axil_csr_rdata_reg[8] <= qsfp0_modprsl; + // axil_csr_rdata_reg[9] <= qsfp0_modsell; + // axil_csr_rdata_reg[10] <= qsfp1_modprsl; + // axil_csr_rdata_reg[11] <= qsfp1_modsell; + // axil_csr_rdata_reg[0] <= qsfp0_resetl; + // axil_csr_rdata_reg[1] <= qsfp0_intl; + // axil_csr_rdata_reg[2] <= qsfp0_lpmode; + // axil_csr_rdata_reg[4] <= qsfp1_resetl; + // axil_csr_rdata_reg[5] <= qsfp1_intl; + // axil_csr_rdata_reg[6] <= qsfp1_lpmode; + // axil_csr_rdata_reg[16] <= i2c_scl_i; + // axil_csr_rdata_reg[17] <= i2c_sda_i; + end + // PHC + 16'h0200: axil_csr_rdata_reg <= {8'd0, 8'd0, 8'd0, 8'd0}; // PHC features + 16'h0210: axil_csr_rdata_reg <= ptp_ts_96[15:0]; // PTP cur fns + 16'h0214: axil_csr_rdata_reg <= ptp_ts_96[45:16]; // PTP cur ns + 16'h0218: axil_csr_rdata_reg <= ptp_ts_96[79:48]; // PTP cur sec l + 16'h021C: axil_csr_rdata_reg <= ptp_ts_96[95:80]; // PTP cur sec h + 16'h0220: begin + // PTP get fns + get_ptp_ts_96_reg <= ptp_ts_96; + axil_csr_rdata_reg <= ptp_ts_96[15:0]; + end + 16'h0224: axil_csr_rdata_reg <= get_ptp_ts_96_reg[45:16]; // PTP get ns + 16'h0228: axil_csr_rdata_reg <= get_ptp_ts_96_reg[79:48]; // PTP get sec l + 16'h022C: axil_csr_rdata_reg <= get_ptp_ts_96_reg[95:80]; // PTP get sec h + 16'h0230: axil_csr_rdata_reg <= set_ptp_ts_96_reg[15:0]; // PTP set fns + 16'h0234: axil_csr_rdata_reg <= set_ptp_ts_96_reg[45:16]; // PTP set ns + 16'h0238: axil_csr_rdata_reg <= set_ptp_ts_96_reg[79:48]; // PTP set sec l + 16'h023C: axil_csr_rdata_reg <= set_ptp_ts_96_reg[95:80]; // PTP set sec h + 16'h0240: axil_csr_rdata_reg <= set_ptp_period_fns_reg; // PTP period fns + 16'h0244: axil_csr_rdata_reg <= set_ptp_period_ns_reg; // PTP period ns + 16'h0248: axil_csr_rdata_reg <= PTP_PERIOD_FNS; // PTP nom period fns + 16'h024C: axil_csr_rdata_reg <= PTP_PERIOD_NS; // PTP nom period ns + 16'h0250: axil_csr_rdata_reg <= set_ptp_offset_fns_reg; // PTP offset fns + 16'h0254: axil_csr_rdata_reg <= set_ptp_offset_ns_reg; // PTP offset ns + 16'h0258: axil_csr_rdata_reg <= set_ptp_offset_count_reg; // PTP offset count + 16'h025C: axil_csr_rdata_reg <= set_ptp_offset_active; // PTP offset status + endcase + end + + if (rst_250mhz) begin + axil_csr_awready_reg <= 1'b0; + axil_csr_wready_reg <= 1'b0; + axil_csr_bvalid_reg <= 1'b0; + axil_csr_arready_reg <= 1'b0; + axil_csr_rvalid_reg <= 1'b0; + + // qsfp0_modsell_reg <= 1'b1; + // qsfp1_modsell_reg <= 1'b1; + + // qsfp0_lpmode_reg <= 1'b0; + // qsfp1_lpmode_reg <= 1'b0; + + // qsfp0_resetl_reg <= 1'b1; + // qsfp1_resetl_reg <= 1'b1; + + // i2c_scl_o_reg <= 1'b1; + // i2c_sda_o_reg <= 1'b1; + + pcie_dma_enable_reg <= 1'b0; + end +end + +pcie_us_cfg #( + .PF_COUNT(1), + .VF_COUNT(0), + .VF_OFFSET(4), + .PCIE_CAP_OFFSET(12'h070) +) +pcie_us_cfg_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Configuration outputs + */ + .ext_tag_enable(ext_tag_enable), + .max_read_request_size(), + .max_payload_size(), + + /* + * Interface to Ultrascale PCIe IP core + */ + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done) +); + +pcie_us_axil_master #( + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), + .AXI_DATA_WIDTH(AXIL_DATA_WIDTH), + .AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH), + .ENABLE_PARITY(0) +) +pcie_us_axil_master_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * AXI input (CQ) + */ + .s_axis_cq_tdata(s_axis_cq_tdata), + .s_axis_cq_tkeep(s_axis_cq_tkeep), + .s_axis_cq_tvalid(s_axis_cq_tvalid), + .s_axis_cq_tready(s_axis_cq_tready), + .s_axis_cq_tlast(s_axis_cq_tlast), + .s_axis_cq_tuser(s_axis_cq_tuser), + + /* + * AXI input (CC) + */ + .m_axis_cc_tdata(m_axis_cc_tdata), + .m_axis_cc_tkeep(m_axis_cc_tkeep), + .m_axis_cc_tvalid(m_axis_cc_tvalid), + .m_axis_cc_tready(m_axis_cc_tready), + .m_axis_cc_tlast(m_axis_cc_tlast), + .m_axis_cc_tuser(m_axis_cc_tuser), + + /* + * AXI Lite Master output + */ + .m_axil_awaddr(axil_pcie_awaddr), + .m_axil_awprot(axil_pcie_awprot), + .m_axil_awvalid(axil_pcie_awvalid), + .m_axil_awready(axil_pcie_awready), + .m_axil_wdata(axil_pcie_wdata), + .m_axil_wstrb(axil_pcie_wstrb), + .m_axil_wvalid(axil_pcie_wvalid), + .m_axil_wready(axil_pcie_wready), + .m_axil_bresp(axil_pcie_bresp), + .m_axil_bvalid(axil_pcie_bvalid), + .m_axil_bready(axil_pcie_bready), + .m_axil_araddr(axil_pcie_araddr), + .m_axil_arprot(axil_pcie_arprot), + .m_axil_arvalid(axil_pcie_arvalid), + .m_axil_arready(axil_pcie_arready), + .m_axil_rdata(axil_pcie_rdata), + .m_axil_rresp(axil_pcie_rresp), + .m_axil_rvalid(axil_pcie_rvalid), + .m_axil_rready(axil_pcie_rready), + + /* + * Configuration + */ + .completer_id({8'd0, 5'd0, 3'd0}), + .completer_id_enable(1'b0), + + /* + * Status + */ + .status_error_cor(status_error_cor_int[0]), + .status_error_uncor(status_error_uncor_int[0]) +); + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r; +wire axis_rc_tlast_r; +wire axis_rc_tready_r; +wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r; +wire axis_rc_tvalid_r; + +axis_register #( + .DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .KEEP_ENABLE(1), + .KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .LAST_ENABLE(1), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH) +) +rc_reg ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * AXI input + */ + .s_axis_tdata(s_axis_rc_tdata), + .s_axis_tkeep(s_axis_rc_tkeep), + .s_axis_tvalid(s_axis_rc_tvalid), + .s_axis_tready(s_axis_rc_tready), + .s_axis_tlast(s_axis_rc_tlast), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(s_axis_rc_tuser), + + /* + * AXI output + */ + .m_axis_tdata(axis_rc_tdata_r), + .m_axis_tkeep(axis_rc_tkeep_r), + .m_axis_tvalid(axis_rc_tvalid_r), + .m_axis_tready(axis_rc_tready_r), + .m_axis_tlast(axis_rc_tlast_r), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(axis_rc_tuser_r) +); + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata_r; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep_r; +wire axis_rq_tlast_r; +wire axis_rq_tready_r; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser_r; +wire axis_rq_tvalid_r; + +axis_register #( + .DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .KEEP_ENABLE(1), + .KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .LAST_ENABLE(1), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH) +) +rq_reg ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * AXI input + */ + .s_axis_tdata(axis_rq_tdata_r), + .s_axis_tkeep(axis_rq_tkeep_r), + .s_axis_tvalid(axis_rq_tvalid_r), + .s_axis_tready(axis_rq_tready_r), + .s_axis_tlast(axis_rq_tlast_r), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(axis_rq_tuser_r), + + /* + * AXI output + */ + .m_axis_tdata(m_axis_rq_tdata), + .m_axis_tkeep(m_axis_rq_tkeep), + .m_axis_tvalid(m_axis_rq_tvalid), + .m_axis_tready(m_axis_rq_tready), + .m_axis_tlast(m_axis_rq_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(m_axis_rq_tuser) +); + +assign cfg_fc_sel = 3'b100; + +wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; +wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; +wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; + +dma_if_pcie_us # +( + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), + .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), + .RQ_SEQ_NUM_ENABLE(1), + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .RAM_SEL_WIDTH(RAM_SEL_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH), + .PCIE_TAG_COUNT(64), + .PCIE_EXT_TAG_ENABLE(1), + .LEN_WIDTH(PCIE_DMA_LEN_WIDTH), + .TAG_WIDTH(PCIE_DMA_TAG_WIDTH), + .READ_OP_TABLE_SIZE(64), + .READ_TX_LIMIT(16), + .READ_TX_FC_ENABLE(1), + .WRITE_OP_TABLE_SIZE(16), + .WRITE_TX_LIMIT(3), + .WRITE_TX_FC_ENABLE(1) +) +dma_if_pcie_us_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * AXI input (RC) + */ + .s_axis_rc_tdata(axis_rc_tdata_r), + .s_axis_rc_tkeep(axis_rc_tkeep_r), + .s_axis_rc_tvalid(axis_rc_tvalid_r), + .s_axis_rc_tready(axis_rc_tready_r), + .s_axis_rc_tlast(axis_rc_tlast_r), + .s_axis_rc_tuser(axis_rc_tuser_r), + + /* + * AXI output (RQ) + */ + .m_axis_rq_tdata(axis_rq_tdata_r), + .m_axis_rq_tkeep(axis_rq_tkeep_r), + .m_axis_rq_tvalid(axis_rq_tvalid_r), + .m_axis_rq_tready(axis_rq_tready_r), + .m_axis_rq_tlast(axis_rq_tlast_r), + .m_axis_rq_tuser(axis_rq_tuser_r), + + /* + * Transmit sequence number input + */ + .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0), + .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), + .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), + .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + + /* + * Transmit flow control + */ + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), + + /* + * AXI read descriptor input + */ + .s_axis_read_desc_pcie_addr(pcie_dma_read_desc_pcie_addr), + .s_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel), + .s_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr), + .s_axis_read_desc_len(pcie_dma_read_desc_len), + .s_axis_read_desc_tag(pcie_dma_read_desc_tag), + .s_axis_read_desc_valid(pcie_dma_read_desc_valid), + .s_axis_read_desc_ready(pcie_dma_read_desc_ready), + + /* + * AXI read descriptor status output + */ + .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), + .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), + + /* + * AXI write descriptor input + */ + .s_axis_write_desc_pcie_addr(pcie_dma_write_desc_pcie_addr), + .s_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel), + .s_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr), + .s_axis_write_desc_len(pcie_dma_write_desc_len), + .s_axis_write_desc_tag(pcie_dma_write_desc_tag), + .s_axis_write_desc_valid(pcie_dma_write_desc_valid), + .s_axis_write_desc_ready(pcie_dma_write_desc_ready), + + /* + * AXI write descriptor status output + */ + .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), + .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), + + /* + * RAM interface + */ + .ram_wr_cmd_sel(dma_ram_wr_cmd_sel), + .ram_wr_cmd_be(dma_ram_wr_cmd_be), + .ram_wr_cmd_addr(dma_ram_wr_cmd_addr), + .ram_wr_cmd_data(dma_ram_wr_cmd_data), + .ram_wr_cmd_valid(dma_ram_wr_cmd_valid), + .ram_wr_cmd_ready(dma_ram_wr_cmd_ready), + .ram_rd_cmd_sel(dma_ram_rd_cmd_sel), + .ram_rd_cmd_addr(dma_ram_rd_cmd_addr), + .ram_rd_cmd_valid(dma_ram_rd_cmd_valid), + .ram_rd_cmd_ready(dma_ram_rd_cmd_ready), + .ram_rd_resp_data(dma_ram_rd_resp_data), + .ram_rd_resp_valid(dma_ram_rd_resp_valid), + .ram_rd_resp_ready(dma_ram_rd_resp_ready), + + /* + * Configuration + */ + .read_enable(pcie_dma_enable), + .write_enable(pcie_dma_enable), + .ext_tag_enable(ext_tag_enable), + .requester_id({8'd0, 5'd0, 3'd0}), + .requester_id_enable(1'b0), + .max_read_request_size(cfg_max_read_req), + .max_payload_size(cfg_max_payload), + + /* + * Status + */ + .status_error_cor(status_error_cor_int[1]), + .status_error_uncor(status_error_uncor_int[1]) +); + +pulse_merge #( + .INPUT_WIDTH(2), + .COUNT_WIDTH(4) +) +status_error_cor_pm_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + .pulse_in(status_error_cor_int), + .count_out(), + .pulse_out(status_error_cor) +); + +pulse_merge #( + .INPUT_WIDTH(2), + .COUNT_WIDTH(4) +) +status_error_uncor_pm_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + .pulse_in(status_error_uncor_int), + .count_out(), + .pulse_out(status_error_uncor) +); + +pcie_us_msi #( + .MSI_COUNT(32) +) +pcie_us_msi_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + .msi_irq(msi_irq), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_vf_enable(0), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number) +); + +wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr; +wire [IF_COUNT*3-1:0] axil_if_awprot; +wire [IF_COUNT-1:0] axil_if_awvalid; +wire [IF_COUNT-1:0] axil_if_awready; +wire [IF_COUNT*AXIL_DATA_WIDTH-1:0] axil_if_wdata; +wire [IF_COUNT*AXIL_STRB_WIDTH-1:0] axil_if_wstrb; +wire [IF_COUNT-1:0] axil_if_wvalid; +wire [IF_COUNT-1:0] axil_if_wready; +wire [IF_COUNT*2-1:0] axil_if_bresp; +wire [IF_COUNT-1:0] axil_if_bvalid; +wire [IF_COUNT-1:0] axil_if_bready; +wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_araddr; +wire [IF_COUNT*3-1:0] axil_if_arprot; +wire [IF_COUNT-1:0] axil_if_arvalid; +wire [IF_COUNT-1:0] axil_if_arready; +wire [IF_COUNT*AXIL_DATA_WIDTH-1:0] axil_if_rdata; +wire [IF_COUNT*2-1:0] axil_if_rresp; +wire [IF_COUNT-1:0] axil_if_rvalid; +wire [IF_COUNT-1:0] axil_if_rready; + +wire [IF_COUNT*AXIL_CSR_ADDR_WIDTH-1:0] axil_if_csr_awaddr; +wire [IF_COUNT*3-1:0] axil_if_csr_awprot; +wire [IF_COUNT-1:0] axil_if_csr_awvalid; +wire [IF_COUNT-1:0] axil_if_csr_awready; +wire [IF_COUNT*AXIL_DATA_WIDTH-1:0] axil_if_csr_wdata; +wire [IF_COUNT*AXIL_STRB_WIDTH-1:0] axil_if_csr_wstrb; +wire [IF_COUNT-1:0] axil_if_csr_wvalid; +wire [IF_COUNT-1:0] axil_if_csr_wready; +wire [IF_COUNT*2-1:0] axil_if_csr_bresp; +wire [IF_COUNT-1:0] axil_if_csr_bvalid; +wire [IF_COUNT-1:0] axil_if_csr_bready; +wire [IF_COUNT*AXIL_CSR_ADDR_WIDTH-1:0] axil_if_csr_araddr; +wire [IF_COUNT*3-1:0] axil_if_csr_arprot; +wire [IF_COUNT-1:0] axil_if_csr_arvalid; +wire [IF_COUNT-1:0] axil_if_csr_arready; +wire [IF_COUNT*AXIL_DATA_WIDTH-1:0] axil_if_csr_rdata; +wire [IF_COUNT*2-1:0] axil_if_csr_rresp; +wire [IF_COUNT-1:0] axil_if_csr_rvalid; +wire [IF_COUNT-1:0] axil_if_csr_rready; + +axil_interconnect #( + .DATA_WIDTH(AXIL_DATA_WIDTH), + .ADDR_WIDTH(AXIL_ADDR_WIDTH), + .S_COUNT(1), + .M_COUNT(IF_COUNT), + .M_BASE_ADDR(0), + .M_ADDR_WIDTH({IF_COUNT{w_32(IF_AXIL_ADDR_WIDTH)}}), + .M_CONNECT_READ({IF_COUNT{1'b1}}), + .M_CONNECT_WRITE({IF_COUNT{1'b1}}) +) +axil_interconnect_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .s_axil_awaddr(axil_pcie_awaddr), + .s_axil_awprot(axil_pcie_awprot), + .s_axil_awvalid(axil_pcie_awvalid), + .s_axil_awready(axil_pcie_awready), + .s_axil_wdata(axil_pcie_wdata), + .s_axil_wstrb(axil_pcie_wstrb), + .s_axil_wvalid(axil_pcie_wvalid), + .s_axil_wready(axil_pcie_wready), + .s_axil_bresp(axil_pcie_bresp), + .s_axil_bvalid(axil_pcie_bvalid), + .s_axil_bready(axil_pcie_bready), + .s_axil_araddr(axil_pcie_araddr), + .s_axil_arprot(axil_pcie_arprot), + .s_axil_arvalid(axil_pcie_arvalid), + .s_axil_arready(axil_pcie_arready), + .s_axil_rdata(axil_pcie_rdata), + .s_axil_rresp(axil_pcie_rresp), + .s_axil_rvalid(axil_pcie_rvalid), + .s_axil_rready(axil_pcie_rready), + .m_axil_awaddr(axil_if_awaddr), + .m_axil_awprot(axil_if_awprot), + .m_axil_awvalid(axil_if_awvalid), + .m_axil_awready(axil_if_awready), + .m_axil_wdata(axil_if_wdata), + .m_axil_wstrb(axil_if_wstrb), + .m_axil_wvalid(axil_if_wvalid), + .m_axil_wready(axil_if_wready), + .m_axil_bresp(axil_if_bresp), + .m_axil_bvalid(axil_if_bvalid), + .m_axil_bready(axil_if_bready), + .m_axil_araddr(axil_if_araddr), + .m_axil_arprot(axil_if_arprot), + .m_axil_arvalid(axil_if_arvalid), + .m_axil_arready(axil_if_arready), + .m_axil_rdata(axil_if_rdata), + .m_axil_rresp(axil_if_rresp), + .m_axil_rvalid(axil_if_rvalid), + .m_axil_rready(axil_if_rready) +); + +axil_interconnect #( + .DATA_WIDTH(AXIL_DATA_WIDTH), + .ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .S_COUNT(IF_COUNT), + .M_COUNT(1), + .M_BASE_ADDR(0), + .M_ADDR_WIDTH({w_32(AXIL_CSR_ADDR_WIDTH-1)}), + .M_CONNECT_READ({1{{IF_COUNT{1'b1}}}}), + .M_CONNECT_WRITE({1{{IF_COUNT{1'b1}}}}) +) +axil_csr_interconnect_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .s_axil_awaddr(axil_if_csr_awaddr), + .s_axil_awprot(axil_if_csr_awprot), + .s_axil_awvalid(axil_if_csr_awvalid), + .s_axil_awready(axil_if_csr_awready), + .s_axil_wdata(axil_if_csr_wdata), + .s_axil_wstrb(axil_if_csr_wstrb), + .s_axil_wvalid(axil_if_csr_wvalid), + .s_axil_wready(axil_if_csr_wready), + .s_axil_bresp(axil_if_csr_bresp), + .s_axil_bvalid(axil_if_csr_bvalid), + .s_axil_bready(axil_if_csr_bready), + .s_axil_araddr(axil_if_csr_araddr), + .s_axil_arprot(axil_if_csr_arprot), + .s_axil_arvalid(axil_if_csr_arvalid), + .s_axil_arready(axil_if_csr_arready), + .s_axil_rdata(axil_if_csr_rdata), + .s_axil_rresp(axil_if_csr_rresp), + .s_axil_rvalid(axil_if_csr_rvalid), + .s_axil_rready(axil_if_csr_rready), + .m_axil_awaddr( {axil_csr_awaddr}), + .m_axil_awprot( {axil_csr_awprot}), + .m_axil_awvalid( {axil_csr_awvalid}), + .m_axil_awready( {axil_csr_awready}), + .m_axil_wdata( {axil_csr_wdata}), + .m_axil_wstrb( {axil_csr_wstrb}), + .m_axil_wvalid( {axil_csr_wvalid}), + .m_axil_wready( {axil_csr_wready}), + .m_axil_bresp( {axil_csr_bresp}), + .m_axil_bvalid( {axil_csr_bvalid}), + .m_axil_bready( {axil_csr_bready}), + .m_axil_araddr( {axil_csr_araddr}), + .m_axil_arprot( {axil_csr_arprot}), + .m_axil_arvalid( {axil_csr_arvalid}), + .m_axil_arready( {axil_csr_arready}), + .m_axil_rdata( {axil_csr_rdata}), + .m_axil_rresp( {axil_csr_rresp}), + .m_axil_rvalid( {axil_csr_rvalid}), + .m_axil_rready( {axil_csr_rready}) +); + +wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_read_desc_pcie_addr; +wire [RAM_SEL_WIDTH-2:0] pcie_ctrl_dma_read_desc_ram_sel; +wire [RAM_ADDR_WIDTH-1:0] pcie_ctrl_dma_read_desc_ram_addr; +wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_ctrl_dma_read_desc_len; +wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_tag; +wire pcie_ctrl_dma_read_desc_valid; +wire pcie_ctrl_dma_read_desc_ready; + +wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; +wire pcie_ctrl_dma_read_desc_status_valid; + +wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; +wire [RAM_SEL_WIDTH-2:0] pcie_ctrl_dma_write_desc_ram_sel; +wire [RAM_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_ram_addr; +wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_ctrl_dma_write_desc_len; +wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_tag; +wire pcie_ctrl_dma_write_desc_valid; +wire pcie_ctrl_dma_write_desc_ready; + +wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; +wire pcie_ctrl_dma_write_desc_status_valid; + +wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; +wire [RAM_SEL_WIDTH-2:0] pcie_data_dma_read_desc_ram_sel; +wire [RAM_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_ram_addr; +wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_data_dma_read_desc_len; +wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_tag; +wire pcie_data_dma_read_desc_valid; +wire pcie_data_dma_read_desc_ready; + +wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; +wire pcie_data_dma_read_desc_status_valid; + +wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; +wire [RAM_SEL_WIDTH-2:0] pcie_data_dma_write_desc_ram_sel; +wire [RAM_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_ram_addr; +wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_data_dma_write_desc_len; +wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_tag; +wire pcie_data_dma_write_desc_valid; +wire pcie_data_dma_write_desc_ready; + +wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; +wire pcie_data_dma_write_desc_status_valid; + +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; + +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; + +dma_if_mux # +( + .PORTS(2), + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .S_RAM_SEL_WIDTH(RAM_SEL_WIDTH-1), + .M_RAM_SEL_WIDTH(RAM_SEL_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), + .LEN_WIDTH(PCIE_DMA_LEN_WIDTH), + .S_TAG_WIDTH(PCIE_DMA_TAG_WIDTH-1), + .M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH), + .ARB_TYPE("PRIORITY"), + .LSB_PRIORITY("HIGH") +) +dma_if_mux_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Read descriptor output (to DMA interface) + */ + .m_axis_read_desc_dma_addr(pcie_dma_read_desc_pcie_addr), + .m_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel), + .m_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr), + .m_axis_read_desc_len(pcie_dma_read_desc_len), + .m_axis_read_desc_tag(pcie_dma_read_desc_tag), + .m_axis_read_desc_valid(pcie_dma_read_desc_valid), + .m_axis_read_desc_ready(pcie_dma_read_desc_ready), + + /* + * Read descriptor status input (from DMA interface) + */ + .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), + .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), + + /* + * Read descriptor input + */ + .s_axis_read_desc_dma_addr({pcie_data_dma_read_desc_pcie_addr, pcie_ctrl_dma_read_desc_pcie_addr}), + .s_axis_read_desc_ram_sel({pcie_data_dma_read_desc_ram_sel, pcie_ctrl_dma_read_desc_ram_sel}), + .s_axis_read_desc_ram_addr({pcie_data_dma_read_desc_ram_addr, pcie_ctrl_dma_read_desc_ram_addr}), + .s_axis_read_desc_len({pcie_data_dma_read_desc_len, pcie_ctrl_dma_read_desc_len}), + .s_axis_read_desc_tag({pcie_data_dma_read_desc_tag, pcie_ctrl_dma_read_desc_tag}), + .s_axis_read_desc_valid({pcie_data_dma_read_desc_valid, pcie_ctrl_dma_read_desc_valid}), + .s_axis_read_desc_ready({pcie_data_dma_read_desc_ready, pcie_ctrl_dma_read_desc_ready}), + + /* + * Read descriptor status output + */ + .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), + .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), + + /* + * Write descriptor output (to DMA interface) + */ + .m_axis_write_desc_dma_addr(pcie_dma_write_desc_pcie_addr), + .m_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel), + .m_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr), + .m_axis_write_desc_len(pcie_dma_write_desc_len), + .m_axis_write_desc_tag(pcie_dma_write_desc_tag), + .m_axis_write_desc_valid(pcie_dma_write_desc_valid), + .m_axis_write_desc_ready(pcie_dma_write_desc_ready), + + /* + * Write descriptor status input (from DMA interface) + */ + .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), + .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), + + /* + * Write descriptor input + */ + .s_axis_write_desc_dma_addr({pcie_data_dma_write_desc_pcie_addr, pcie_ctrl_dma_write_desc_pcie_addr}), + .s_axis_write_desc_ram_sel({pcie_data_dma_write_desc_ram_sel, pcie_ctrl_dma_write_desc_ram_sel}), + .s_axis_write_desc_ram_addr({pcie_data_dma_write_desc_ram_addr, pcie_ctrl_dma_write_desc_ram_addr}), + .s_axis_write_desc_len({pcie_data_dma_write_desc_len, pcie_ctrl_dma_write_desc_len}), + .s_axis_write_desc_tag({pcie_data_dma_write_desc_tag, pcie_ctrl_dma_write_desc_tag}), + .s_axis_write_desc_valid({pcie_data_dma_write_desc_valid, pcie_ctrl_dma_write_desc_valid}), + .s_axis_write_desc_ready({pcie_data_dma_write_desc_ready, pcie_ctrl_dma_write_desc_ready}), + + /* + * Write descriptor status output + */ + .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), + .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), + + /* + * RAM interface (from DMA interface) + */ + .if_ram_wr_cmd_sel(dma_ram_wr_cmd_sel), + .if_ram_wr_cmd_be(dma_ram_wr_cmd_be), + .if_ram_wr_cmd_addr(dma_ram_wr_cmd_addr), + .if_ram_wr_cmd_data(dma_ram_wr_cmd_data), + .if_ram_wr_cmd_valid(dma_ram_wr_cmd_valid), + .if_ram_wr_cmd_ready(dma_ram_wr_cmd_ready), + .if_ram_rd_cmd_sel(dma_ram_rd_cmd_sel), + .if_ram_rd_cmd_addr(dma_ram_rd_cmd_addr), + .if_ram_rd_cmd_valid(dma_ram_rd_cmd_valid), + .if_ram_rd_cmd_ready(dma_ram_rd_cmd_ready), + .if_ram_rd_resp_data(dma_ram_rd_resp_data), + .if_ram_rd_resp_valid(dma_ram_rd_resp_valid), + .if_ram_rd_resp_ready(dma_ram_rd_resp_ready), + + /* + * RAM interface + */ + .ram_wr_cmd_sel({data_dma_ram_wr_cmd_sel, ctrl_dma_ram_wr_cmd_sel}), + .ram_wr_cmd_be({data_dma_ram_wr_cmd_be, ctrl_dma_ram_wr_cmd_be}), + .ram_wr_cmd_addr({data_dma_ram_wr_cmd_addr, ctrl_dma_ram_wr_cmd_addr}), + .ram_wr_cmd_data({data_dma_ram_wr_cmd_data, ctrl_dma_ram_wr_cmd_data}), + .ram_wr_cmd_valid({data_dma_ram_wr_cmd_valid, ctrl_dma_ram_wr_cmd_valid}), + .ram_wr_cmd_ready({data_dma_ram_wr_cmd_ready, ctrl_dma_ram_wr_cmd_ready}), + .ram_rd_cmd_sel({data_dma_ram_rd_cmd_sel, ctrl_dma_ram_rd_cmd_sel}), + .ram_rd_cmd_addr({data_dma_ram_rd_cmd_addr, ctrl_dma_ram_rd_cmd_addr}), + .ram_rd_cmd_valid({data_dma_ram_rd_cmd_valid, ctrl_dma_ram_rd_cmd_valid}), + .ram_rd_cmd_ready({data_dma_ram_rd_cmd_ready, ctrl_dma_ram_rd_cmd_ready}), + .ram_rd_resp_data({data_dma_ram_rd_resp_data, ctrl_dma_ram_rd_resp_data}), + .ram_rd_resp_valid({data_dma_ram_rd_resp_valid, ctrl_dma_ram_rd_resp_valid}), + .ram_rd_resp_ready({data_dma_ram_rd_resp_ready, ctrl_dma_ram_rd_resp_ready}) +); + +wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_pcie_addr; +wire [IF_COUNT*IF_RAM_SEL_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_ram_sel; +wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_ram_addr; +wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_len; +wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_tag; +wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid; +wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; + +wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; +wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; + +wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; +wire [IF_COUNT*IF_RAM_SEL_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_ram_sel; +wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_ram_addr; +wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_len; +wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_tag; +wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid; +wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; + +wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; +wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; + +wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; +wire [IF_COUNT*IF_RAM_SEL_WIDTH-1:0] if_pcie_data_dma_read_desc_ram_sel; +wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_ram_addr; +wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_data_dma_read_desc_len; +wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_tag; +wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid; +wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; + +wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; +wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; + +wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; +wire [IF_COUNT*IF_RAM_SEL_WIDTH-1:0] if_pcie_data_dma_write_desc_ram_sel; +wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_ram_addr; +wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_data_dma_write_desc_len; +wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_tag; +wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid; +wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; + +wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; +wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; + +wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; +wire [IF_COUNT*SEG_COUNT*SEG_BE_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_be; +wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_addr; +wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_data; +wire [IF_COUNT*SEG_COUNT-1:0] if_ctrl_dma_ram_wr_cmd_valid; +wire [IF_COUNT*SEG_COUNT-1:0] if_ctrl_dma_ram_wr_cmd_ready; +wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_rd_cmd_sel; +wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_ctrl_dma_ram_rd_cmd_addr; +wire [IF_COUNT*SEG_COUNT-1:0] if_ctrl_dma_ram_rd_cmd_valid; +wire [IF_COUNT*SEG_COUNT-1:0] if_ctrl_dma_ram_rd_cmd_ready; +wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_ctrl_dma_ram_rd_resp_data; +wire [IF_COUNT*SEG_COUNT-1:0] if_ctrl_dma_ram_rd_resp_valid; +wire [IF_COUNT*SEG_COUNT-1:0] if_ctrl_dma_ram_rd_resp_ready; + +wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_data_dma_ram_wr_cmd_sel; +wire [IF_COUNT*SEG_COUNT*SEG_BE_WIDTH-1:0] if_data_dma_ram_wr_cmd_be; +wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_data_dma_ram_wr_cmd_addr; +wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_data_dma_ram_wr_cmd_data; +wire [IF_COUNT*SEG_COUNT-1:0] if_data_dma_ram_wr_cmd_valid; +wire [IF_COUNT*SEG_COUNT-1:0] if_data_dma_ram_wr_cmd_ready; +wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_data_dma_ram_rd_cmd_sel; +wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_data_dma_ram_rd_cmd_addr; +wire [IF_COUNT*SEG_COUNT-1:0] if_data_dma_ram_rd_cmd_valid; +wire [IF_COUNT*SEG_COUNT-1:0] if_data_dma_ram_rd_cmd_ready; +wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_data_dma_ram_rd_resp_data; +wire [IF_COUNT*SEG_COUNT-1:0] if_data_dma_ram_rd_resp_valid; +wire [IF_COUNT*SEG_COUNT-1:0] if_data_dma_ram_rd_resp_ready; + +if (IF_COUNT > 1) begin + + dma_if_mux # + ( + .PORTS(IF_COUNT), + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .S_RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH), + .M_RAM_SEL_WIDTH(RAM_SEL_WIDTH-1), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), + .LEN_WIDTH(PCIE_DMA_LEN_WIDTH), + .S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH), + .M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH-1), + .ARB_TYPE("ROUND_ROBIN"), + .LSB_PRIORITY("HIGH") + ) + dma_if_mux_ctrl_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Read descriptor output (to DMA interface) + */ + .m_axis_read_desc_dma_addr(pcie_ctrl_dma_read_desc_pcie_addr), + .m_axis_read_desc_ram_sel(pcie_ctrl_dma_read_desc_ram_sel), + .m_axis_read_desc_ram_addr(pcie_ctrl_dma_read_desc_ram_addr), + .m_axis_read_desc_len(pcie_ctrl_dma_read_desc_len), + .m_axis_read_desc_tag(pcie_ctrl_dma_read_desc_tag), + .m_axis_read_desc_valid(pcie_ctrl_dma_read_desc_valid), + .m_axis_read_desc_ready(pcie_ctrl_dma_read_desc_ready), + + /* + * Read descriptor status input (from DMA interface) + */ + .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), + .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), + + /* + * Read descriptor input + */ + .s_axis_read_desc_dma_addr(if_pcie_ctrl_dma_read_desc_pcie_addr), + .s_axis_read_desc_ram_sel(if_pcie_ctrl_dma_read_desc_ram_sel), + .s_axis_read_desc_ram_addr(if_pcie_ctrl_dma_read_desc_ram_addr), + .s_axis_read_desc_len(if_pcie_ctrl_dma_read_desc_len), + .s_axis_read_desc_tag(if_pcie_ctrl_dma_read_desc_tag), + .s_axis_read_desc_valid(if_pcie_ctrl_dma_read_desc_valid), + .s_axis_read_desc_ready(if_pcie_ctrl_dma_read_desc_ready), + + /* + * Read descriptor status output + */ + .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), + .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), + + /* + * Write descriptor output (to DMA interface) + */ + .m_axis_write_desc_dma_addr(pcie_ctrl_dma_write_desc_pcie_addr), + .m_axis_write_desc_ram_sel(pcie_ctrl_dma_write_desc_ram_sel), + .m_axis_write_desc_ram_addr(pcie_ctrl_dma_write_desc_ram_addr), + .m_axis_write_desc_len(pcie_ctrl_dma_write_desc_len), + .m_axis_write_desc_tag(pcie_ctrl_dma_write_desc_tag), + .m_axis_write_desc_valid(pcie_ctrl_dma_write_desc_valid), + .m_axis_write_desc_ready(pcie_ctrl_dma_write_desc_ready), + + /* + * Write descriptor status input (from DMA interface) + */ + .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), + .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), + + /* + * Write descriptor input + */ + .s_axis_write_desc_dma_addr(if_pcie_ctrl_dma_write_desc_pcie_addr), + .s_axis_write_desc_ram_sel(if_pcie_ctrl_dma_write_desc_ram_sel), + .s_axis_write_desc_ram_addr(if_pcie_ctrl_dma_write_desc_ram_addr), + .s_axis_write_desc_len(if_pcie_ctrl_dma_write_desc_len), + .s_axis_write_desc_tag(if_pcie_ctrl_dma_write_desc_tag), + .s_axis_write_desc_valid(if_pcie_ctrl_dma_write_desc_valid), + .s_axis_write_desc_ready(if_pcie_ctrl_dma_write_desc_ready), + + /* + * Write descriptor status output + */ + .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), + .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), + + /* + * RAM interface (from DMA interface) + */ + .if_ram_wr_cmd_sel(ctrl_dma_ram_wr_cmd_sel), + .if_ram_wr_cmd_be(ctrl_dma_ram_wr_cmd_be), + .if_ram_wr_cmd_addr(ctrl_dma_ram_wr_cmd_addr), + .if_ram_wr_cmd_data(ctrl_dma_ram_wr_cmd_data), + .if_ram_wr_cmd_valid(ctrl_dma_ram_wr_cmd_valid), + .if_ram_wr_cmd_ready(ctrl_dma_ram_wr_cmd_ready), + .if_ram_rd_cmd_sel(ctrl_dma_ram_rd_cmd_sel), + .if_ram_rd_cmd_addr(ctrl_dma_ram_rd_cmd_addr), + .if_ram_rd_cmd_valid(ctrl_dma_ram_rd_cmd_valid), + .if_ram_rd_cmd_ready(ctrl_dma_ram_rd_cmd_ready), + .if_ram_rd_resp_data(ctrl_dma_ram_rd_resp_data), + .if_ram_rd_resp_valid(ctrl_dma_ram_rd_resp_valid), + .if_ram_rd_resp_ready(ctrl_dma_ram_rd_resp_ready), + + /* + * RAM interface + */ + .ram_wr_cmd_sel(if_ctrl_dma_ram_wr_cmd_sel), + .ram_wr_cmd_be(if_ctrl_dma_ram_wr_cmd_be), + .ram_wr_cmd_addr(if_ctrl_dma_ram_wr_cmd_addr), + .ram_wr_cmd_data(if_ctrl_dma_ram_wr_cmd_data), + .ram_wr_cmd_valid(if_ctrl_dma_ram_wr_cmd_valid), + .ram_wr_cmd_ready(if_ctrl_dma_ram_wr_cmd_ready), + .ram_rd_cmd_sel(if_ctrl_dma_ram_rd_cmd_sel), + .ram_rd_cmd_addr(if_ctrl_dma_ram_rd_cmd_addr), + .ram_rd_cmd_valid(if_ctrl_dma_ram_rd_cmd_valid), + .ram_rd_cmd_ready(if_ctrl_dma_ram_rd_cmd_ready), + .ram_rd_resp_data(if_ctrl_dma_ram_rd_resp_data), + .ram_rd_resp_valid(if_ctrl_dma_ram_rd_resp_valid), + .ram_rd_resp_ready(if_ctrl_dma_ram_rd_resp_ready) + ); + + dma_if_mux # + ( + .PORTS(IF_COUNT), + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .S_RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH), + .M_RAM_SEL_WIDTH(RAM_SEL_WIDTH-1), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), + .LEN_WIDTH(PCIE_DMA_LEN_WIDTH), + .S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH), + .M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH-1), + .ARB_TYPE("ROUND_ROBIN"), + .LSB_PRIORITY("HIGH") + ) + dma_if_mux_data_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Read descriptor output (to DMA interface) + */ + .m_axis_read_desc_dma_addr(pcie_data_dma_read_desc_pcie_addr), + .m_axis_read_desc_ram_sel(pcie_data_dma_read_desc_ram_sel), + .m_axis_read_desc_ram_addr(pcie_data_dma_read_desc_ram_addr), + .m_axis_read_desc_len(pcie_data_dma_read_desc_len), + .m_axis_read_desc_tag(pcie_data_dma_read_desc_tag), + .m_axis_read_desc_valid(pcie_data_dma_read_desc_valid), + .m_axis_read_desc_ready(pcie_data_dma_read_desc_ready), + + /* + * Read descriptor status input (from DMA interface) + */ + .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), + .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), + + /* + * Read descriptor input + */ + .s_axis_read_desc_dma_addr(if_pcie_data_dma_read_desc_pcie_addr), + .s_axis_read_desc_ram_sel(if_pcie_data_dma_read_desc_ram_sel), + .s_axis_read_desc_ram_addr(if_pcie_data_dma_read_desc_ram_addr), + .s_axis_read_desc_len(if_pcie_data_dma_read_desc_len), + .s_axis_read_desc_tag(if_pcie_data_dma_read_desc_tag), + .s_axis_read_desc_valid(if_pcie_data_dma_read_desc_valid), + .s_axis_read_desc_ready(if_pcie_data_dma_read_desc_ready), + + /* + * Read descriptor status output + */ + .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), + .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), + + /* + * Write descriptor output (to DMA interface) + */ + .m_axis_write_desc_dma_addr(pcie_data_dma_write_desc_pcie_addr), + .m_axis_write_desc_ram_sel(pcie_data_dma_write_desc_ram_sel), + .m_axis_write_desc_ram_addr(pcie_data_dma_write_desc_ram_addr), + .m_axis_write_desc_len(pcie_data_dma_write_desc_len), + .m_axis_write_desc_tag(pcie_data_dma_write_desc_tag), + .m_axis_write_desc_valid(pcie_data_dma_write_desc_valid), + .m_axis_write_desc_ready(pcie_data_dma_write_desc_ready), + + /* + * Write descriptor status input (from DMA interface) + */ + .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), + .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), + + /* + * Write descriptor input + */ + .s_axis_write_desc_dma_addr(if_pcie_data_dma_write_desc_pcie_addr), + .s_axis_write_desc_ram_sel(if_pcie_data_dma_write_desc_ram_sel), + .s_axis_write_desc_ram_addr(if_pcie_data_dma_write_desc_ram_addr), + .s_axis_write_desc_len(if_pcie_data_dma_write_desc_len), + .s_axis_write_desc_tag(if_pcie_data_dma_write_desc_tag), + .s_axis_write_desc_valid(if_pcie_data_dma_write_desc_valid), + .s_axis_write_desc_ready(if_pcie_data_dma_write_desc_ready), + + /* + * Write descriptor status output + */ + .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), + .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), + + /* + * RAM interface (from DMA interface) + */ + .if_ram_wr_cmd_sel(data_dma_ram_wr_cmd_sel), + .if_ram_wr_cmd_be(data_dma_ram_wr_cmd_be), + .if_ram_wr_cmd_addr(data_dma_ram_wr_cmd_addr), + .if_ram_wr_cmd_data(data_dma_ram_wr_cmd_data), + .if_ram_wr_cmd_valid(data_dma_ram_wr_cmd_valid), + .if_ram_wr_cmd_ready(data_dma_ram_wr_cmd_ready), + .if_ram_rd_cmd_sel(data_dma_ram_rd_cmd_sel), + .if_ram_rd_cmd_addr(data_dma_ram_rd_cmd_addr), + .if_ram_rd_cmd_valid(data_dma_ram_rd_cmd_valid), + .if_ram_rd_cmd_ready(data_dma_ram_rd_cmd_ready), + .if_ram_rd_resp_data(data_dma_ram_rd_resp_data), + .if_ram_rd_resp_valid(data_dma_ram_rd_resp_valid), + .if_ram_rd_resp_ready(data_dma_ram_rd_resp_ready), + + /* + * RAM interface + */ + .ram_wr_cmd_sel(if_data_dma_ram_wr_cmd_sel), + .ram_wr_cmd_be(if_data_dma_ram_wr_cmd_be), + .ram_wr_cmd_addr(if_data_dma_ram_wr_cmd_addr), + .ram_wr_cmd_data(if_data_dma_ram_wr_cmd_data), + .ram_wr_cmd_valid(if_data_dma_ram_wr_cmd_valid), + .ram_wr_cmd_ready(if_data_dma_ram_wr_cmd_ready), + .ram_rd_cmd_sel(if_data_dma_ram_rd_cmd_sel), + .ram_rd_cmd_addr(if_data_dma_ram_rd_cmd_addr), + .ram_rd_cmd_valid(if_data_dma_ram_rd_cmd_valid), + .ram_rd_cmd_ready(if_data_dma_ram_rd_cmd_ready), + .ram_rd_resp_data(if_data_dma_ram_rd_resp_data), + .ram_rd_resp_valid(if_data_dma_ram_rd_resp_valid), + .ram_rd_resp_ready(if_data_dma_ram_rd_resp_ready) + ); + +end else begin + + assign pcie_ctrl_dma_read_desc_pcie_addr = if_pcie_ctrl_dma_read_desc_pcie_addr; + assign pcie_ctrl_dma_read_desc_ram_sel = if_pcie_ctrl_dma_read_desc_ram_sel; + assign pcie_ctrl_dma_read_desc_ram_addr = if_pcie_ctrl_dma_read_desc_ram_addr; + assign pcie_ctrl_dma_read_desc_len = if_pcie_ctrl_dma_read_desc_len; + assign pcie_ctrl_dma_read_desc_tag = if_pcie_ctrl_dma_read_desc_tag; + assign pcie_ctrl_dma_read_desc_valid = if_pcie_ctrl_dma_read_desc_valid; + assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; + + assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; + assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; + + assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; + assign pcie_ctrl_dma_write_desc_ram_sel = if_pcie_ctrl_dma_write_desc_ram_sel; + assign pcie_ctrl_dma_write_desc_ram_addr = if_pcie_ctrl_dma_write_desc_ram_addr; + assign pcie_ctrl_dma_write_desc_len = if_pcie_ctrl_dma_write_desc_len; + assign pcie_ctrl_dma_write_desc_tag = if_pcie_ctrl_dma_write_desc_tag; + assign pcie_ctrl_dma_write_desc_valid = if_pcie_ctrl_dma_write_desc_valid; + assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; + + assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; + assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; + + assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; + assign if_ctrl_dma_ram_wr_cmd_be = ctrl_dma_ram_wr_cmd_be; + assign if_ctrl_dma_ram_wr_cmd_addr = ctrl_dma_ram_wr_cmd_addr; + assign if_ctrl_dma_ram_wr_cmd_data = ctrl_dma_ram_wr_cmd_data; + assign if_ctrl_dma_ram_wr_cmd_valid = ctrl_dma_ram_wr_cmd_valid; + assign ctrl_dma_ram_wr_cmd_ready = if_ctrl_dma_ram_wr_cmd_ready; + assign if_ctrl_dma_ram_rd_cmd_sel = ctrl_dma_ram_rd_cmd_sel; + assign if_ctrl_dma_ram_rd_cmd_addr = ctrl_dma_ram_rd_cmd_addr; + assign if_ctrl_dma_ram_rd_cmd_valid = ctrl_dma_ram_rd_cmd_valid; + assign ctrl_dma_ram_rd_cmd_ready = if_ctrl_dma_ram_rd_cmd_ready; + assign ctrl_dma_ram_rd_resp_data = if_ctrl_dma_ram_rd_resp_data; + assign ctrl_dma_ram_rd_resp_valid = if_ctrl_dma_ram_rd_resp_valid; + assign if_ctrl_dma_ram_rd_resp_ready = ctrl_dma_ram_rd_resp_ready; + + assign pcie_data_dma_read_desc_pcie_addr = if_pcie_data_dma_read_desc_pcie_addr; + assign pcie_data_dma_read_desc_ram_sel = if_pcie_data_dma_read_desc_ram_sel; + assign pcie_data_dma_read_desc_ram_addr = if_pcie_data_dma_read_desc_ram_addr; + assign pcie_data_dma_read_desc_len = if_pcie_data_dma_read_desc_len; + assign pcie_data_dma_read_desc_tag = if_pcie_data_dma_read_desc_tag; + assign pcie_data_dma_read_desc_valid = if_pcie_data_dma_read_desc_valid; + assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; + + assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; + assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; + + assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; + assign pcie_data_dma_write_desc_ram_sel = if_pcie_data_dma_write_desc_ram_sel; + assign pcie_data_dma_write_desc_ram_addr = if_pcie_data_dma_write_desc_ram_addr; + assign pcie_data_dma_write_desc_len = if_pcie_data_dma_write_desc_len; + assign pcie_data_dma_write_desc_tag = if_pcie_data_dma_write_desc_tag; + assign pcie_data_dma_write_desc_valid = if_pcie_data_dma_write_desc_valid; + assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; + + assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; + assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; + + assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; + assign if_data_dma_ram_wr_cmd_be = data_dma_ram_wr_cmd_be; + assign if_data_dma_ram_wr_cmd_addr = data_dma_ram_wr_cmd_addr; + assign if_data_dma_ram_wr_cmd_data = data_dma_ram_wr_cmd_data; + assign if_data_dma_ram_wr_cmd_valid = data_dma_ram_wr_cmd_valid; + assign data_dma_ram_wr_cmd_ready = if_data_dma_ram_wr_cmd_ready; + assign if_data_dma_ram_rd_cmd_sel = data_dma_ram_rd_cmd_sel; + assign if_data_dma_ram_rd_cmd_addr = data_dma_ram_rd_cmd_addr; + assign if_data_dma_ram_rd_cmd_valid = data_dma_ram_rd_cmd_valid; + assign data_dma_ram_rd_cmd_ready = if_data_dma_ram_rd_cmd_ready; + assign data_dma_ram_rd_resp_data = if_data_dma_ram_rd_resp_data; + assign data_dma_ram_rd_resp_valid = if_data_dma_ram_rd_resp_valid; + assign if_data_dma_ram_rd_resp_ready = data_dma_ram_rd_resp_ready; + +end + +// PTP clock +ptp_clock #( + .PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH), + .OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH), + .FNS_WIDTH(PTP_FNS_WIDTH), + .PERIOD_NS(PTP_PERIOD_NS), + .PERIOD_FNS(PTP_PERIOD_FNS), + .DRIFT_ENABLE(0) +) +ptp_clock_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Timestamp inputs for synchronization + */ + .input_ts_96(set_ptp_ts_96_reg), + .input_ts_96_valid(set_ptp_ts_96_valid_reg), + .input_ts_64(0), + .input_ts_64_valid(1'b0), + + /* + * Period adjustment + */ + .input_period_ns(set_ptp_period_ns_reg), + .input_period_fns(set_ptp_period_fns_reg), + .input_period_valid(set_ptp_period_valid_reg), + + /* + * Offset adjustment + */ + .input_adj_ns(set_ptp_offset_ns_reg), + .input_adj_fns(set_ptp_offset_fns_reg), + .input_adj_count(set_ptp_offset_count_reg), + .input_adj_valid(set_ptp_offset_valid_reg), + .input_adj_active(set_ptp_offset_active), + + /* + * Drift adjustment + */ + .input_drift_ns(0), + .input_drift_fns(0), + .input_drift_rate(0), + .input_drift_valid(0), + + /* + * Timestamp outputs + */ + .output_ts_96(ptp_ts_96), + .output_ts_64(), + .output_ts_step(ptp_ts_step), + + /* + * PPS output + */ + .output_pps(ptp_pps) +); + +reg [26:0] pps_led_counter_reg = 0; +reg pps_led_reg = 0; + +always @(posedge clk_250mhz) begin + if (ptp_pps) begin + pps_led_counter_reg <= 125000000; + end else if (pps_led_counter_reg > 0) begin + pps_led_counter_reg <= pps_led_counter_reg - 1; + end + + pps_led_reg <= pps_led_counter_reg > 0; +end + +wire [PORT_COUNT-1:0] port_tx_clk; +wire [PORT_COUNT-1:0] port_tx_rst; +wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] port_tx_axis_tdata; +wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] port_tx_axis_tkeep; +wire [PORT_COUNT-1:0] port_tx_axis_tvalid; +wire [PORT_COUNT-1:0] port_tx_axis_tready; +wire [PORT_COUNT-1:0] port_tx_axis_tlast; +wire [PORT_COUNT-1:0] port_tx_axis_tuser; + +wire [PORT_COUNT-1:0] port_rx_clk; +wire [PORT_COUNT-1:0] port_rx_rst; +wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] port_rx_axis_tdata; +wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] port_rx_axis_tkeep; +wire [PORT_COUNT-1:0] port_rx_axis_tvalid; +wire [PORT_COUNT-1:0] port_rx_axis_tlast; +wire [PORT_COUNT-1:0] port_rx_axis_tuser; + +// assign led[0] = pps_led_reg; +// assign led[2:1] = 0; + +wire [IF_COUNT*32-1:0] if_msi_irq; + +// counts QSFP 0 QSFP 1 +// IF PORT 0_1234 1_1234 +// 1 1 0 (0.0) +// 1 2 0 (0.0) 1 (0.1) +// 2 1 0 (0.0) 1 (1.0) + +localparam QSFP0_IND = 0; +localparam QSFP1_IND = 1; + +generate + genvar m, n; + + if (QSFP0_IND >= 0 && QSFP0_IND < PORT_COUNT) begin + assign port_tx_clk[QSFP0_IND] = qsfp0_tx_clk; + assign port_tx_rst[QSFP0_IND] = qsfp0_tx_rst; + assign qsfp0_tx_axis_tdata = port_tx_axis_tdata[QSFP0_IND*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]; + assign qsfp0_tx_axis_tkeep = port_tx_axis_tkeep[QSFP0_IND*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]; + assign qsfp0_tx_axis_tvalid = port_tx_axis_tvalid[QSFP0_IND]; + assign port_tx_axis_tready[QSFP0_IND] = qsfp0_tx_axis_tready; + assign qsfp0_tx_axis_tlast = port_tx_axis_tlast[QSFP0_IND]; + assign qsfp0_tx_axis_tuser = port_tx_axis_tuser[QSFP0_IND]; + + assign port_rx_clk[QSFP0_IND] = qsfp0_rx_clk; + assign port_rx_rst[QSFP0_IND] = qsfp0_rx_rst; + assign port_rx_axis_tdata[QSFP0_IND*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH] = qsfp0_rx_axis_tdata; + assign port_rx_axis_tkeep[QSFP0_IND*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH] = qsfp0_rx_axis_tkeep; + assign port_rx_axis_tvalid[QSFP0_IND] = qsfp0_rx_axis_tvalid; + assign port_rx_axis_tlast[QSFP0_IND] = qsfp0_rx_axis_tlast; + assign port_rx_axis_tuser[QSFP0_IND] = qsfp0_rx_axis_tuser; + end else begin + assign qsfp0_tx_axis_tdata = {AXIS_ETH_DATA_WIDTH{1'b0}}; + assign qsfp0_tx_axis_tkeep = {AXIS_ETH_KEEP_WIDTH{1'b0}}; + assign qsfp0_tx_axis_tvalid = 1'b0; + assign qsfp0_tx_axis_tlast = 1'b0; + assign qsfp0_tx_axis_tuser = 1'b0; + end + + if (QSFP1_IND >= 0 && QSFP1_IND < PORT_COUNT) begin + assign port_tx_clk[QSFP1_IND] = qsfp1_tx_clk; + assign port_tx_rst[QSFP1_IND] = qsfp1_tx_rst; + assign qsfp1_tx_axis_tdata = port_tx_axis_tdata[QSFP1_IND*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]; + assign qsfp1_tx_axis_tkeep = port_tx_axis_tkeep[QSFP1_IND*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]; + assign qsfp1_tx_axis_tvalid = port_tx_axis_tvalid[QSFP1_IND]; + assign port_tx_axis_tready[QSFP1_IND] = qsfp1_tx_axis_tready; + assign qsfp1_tx_axis_tlast = port_tx_axis_tlast[QSFP1_IND]; + assign qsfp1_tx_axis_tuser = port_tx_axis_tuser[QSFP1_IND]; + + assign port_rx_clk[QSFP1_IND] = qsfp1_rx_clk; + assign port_rx_rst[QSFP1_IND] = qsfp1_rx_rst; + assign port_rx_axis_tdata[QSFP1_IND*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH] = qsfp1_rx_axis_tdata; + assign port_rx_axis_tkeep[QSFP1_IND*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH] = qsfp1_rx_axis_tkeep; + assign port_rx_axis_tvalid[QSFP1_IND] = qsfp1_rx_axis_tvalid; + assign port_rx_axis_tlast[QSFP1_IND] = qsfp1_rx_axis_tlast; + assign port_rx_axis_tuser[QSFP1_IND] = qsfp1_rx_axis_tuser; + end else begin + assign qsfp1_tx_axis_tdata = {AXIS_ETH_DATA_WIDTH{1'b0}}; + assign qsfp1_tx_axis_tkeep = {AXIS_ETH_KEEP_WIDTH{1'b0}}; + assign qsfp1_tx_axis_tvalid = 1'b0; + assign qsfp1_tx_axis_tlast = 1'b0; + assign qsfp1_tx_axis_tuser = 1'b0; + end + + case (IF_COUNT) + 1: assign msi_irq = if_msi_irq[0*32+:32]; + 2: assign msi_irq = if_msi_irq[0*32+:32] | if_msi_irq[1*32+:32]; + endcase + + for (n = 0; n < IF_COUNT; n = n + 1) begin : iface + + wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata; + wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep; + wire [PORTS_PER_IF-1:0] tx_axis_tvalid; + wire [PORTS_PER_IF-1:0] tx_axis_tready; + wire [PORTS_PER_IF-1:0] tx_axis_tlast; + wire [PORTS_PER_IF-1:0] tx_axis_tuser; + + wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] tx_ptp_ts_96; + wire [PORTS_PER_IF-1:0] tx_ptp_ts_valid; + wire [PORTS_PER_IF-1:0] tx_ptp_ts_ready; + + wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] rx_axis_tdata; + wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep; + wire [PORTS_PER_IF-1:0] rx_axis_tvalid; + wire [PORTS_PER_IF-1:0] rx_axis_tready; + wire [PORTS_PER_IF-1:0] rx_axis_tlast; + wire [PORTS_PER_IF-1:0] rx_axis_tuser; + + wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] rx_ptp_ts_96; + wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; + wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; + + interface #( + .PORTS(PORTS_PER_IF), + .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), + .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH), + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), + .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), + .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), + .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), + .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), + .TX_SCHEDULER(TX_SCHEDULER), + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + .INT_WIDTH(8), + .QUEUE_PTR_WIDTH(16), + .LOG_QUEUE_SIZE_WIDTH(4), + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_RSS_ENABLE(RX_RSS_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH), + .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE) + ) + interface_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * DMA read descriptor output (control) + */ + .m_axis_ctrl_dma_read_desc_dma_addr(if_pcie_ctrl_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]), + .m_axis_ctrl_dma_read_desc_ram_sel(if_pcie_ctrl_dma_read_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]), + .m_axis_ctrl_dma_read_desc_ram_addr(if_pcie_ctrl_dma_read_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]), + .m_axis_ctrl_dma_read_desc_len(if_pcie_ctrl_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]), + .m_axis_ctrl_dma_read_desc_tag(if_pcie_ctrl_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), + .m_axis_ctrl_dma_read_desc_valid(if_pcie_ctrl_dma_read_desc_valid[n]), + .m_axis_ctrl_dma_read_desc_ready(if_pcie_ctrl_dma_read_desc_ready[n]), + + /* + * DMA read descriptor status input (control) + */ + .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), + .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), + + /* + * DMA write descriptor output (control) + */ + .m_axis_ctrl_dma_write_desc_dma_addr(if_pcie_ctrl_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]), + .m_axis_ctrl_dma_write_desc_ram_sel(if_pcie_ctrl_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]), + .m_axis_ctrl_dma_write_desc_ram_addr(if_pcie_ctrl_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]), + .m_axis_ctrl_dma_write_desc_len(if_pcie_ctrl_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]), + .m_axis_ctrl_dma_write_desc_tag(if_pcie_ctrl_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), + .m_axis_ctrl_dma_write_desc_valid(if_pcie_ctrl_dma_write_desc_valid[n]), + .m_axis_ctrl_dma_write_desc_ready(if_pcie_ctrl_dma_write_desc_ready[n]), + + /* + * DMA write descriptor status input (control) + */ + .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), + .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), + + /* + * DMA read descriptor output (data) + */ + .m_axis_data_dma_read_desc_dma_addr(if_pcie_data_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]), + .m_axis_data_dma_read_desc_ram_sel(if_pcie_data_dma_read_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]), + .m_axis_data_dma_read_desc_ram_addr(if_pcie_data_dma_read_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]), + .m_axis_data_dma_read_desc_len(if_pcie_data_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]), + .m_axis_data_dma_read_desc_tag(if_pcie_data_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), + .m_axis_data_dma_read_desc_valid(if_pcie_data_dma_read_desc_valid[n]), + .m_axis_data_dma_read_desc_ready(if_pcie_data_dma_read_desc_ready[n]), + + /* + * DMA read descriptor status input (data) + */ + .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), + .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), + + /* + * DMA write descriptor output (data) + */ + .m_axis_data_dma_write_desc_dma_addr(if_pcie_data_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]), + .m_axis_data_dma_write_desc_ram_sel(if_pcie_data_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]), + .m_axis_data_dma_write_desc_ram_addr(if_pcie_data_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]), + .m_axis_data_dma_write_desc_len(if_pcie_data_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]), + .m_axis_data_dma_write_desc_tag(if_pcie_data_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), + .m_axis_data_dma_write_desc_valid(if_pcie_data_dma_write_desc_valid[n]), + .m_axis_data_dma_write_desc_ready(if_pcie_data_dma_write_desc_ready[n]), + + /* + * DMA write descriptor status input (data) + */ + .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), + .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), + + /* + * AXI-Lite slave interface + */ + .s_axil_awaddr(axil_if_awaddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]), + .s_axil_awprot(axil_if_awprot[n*3 +: 3]), + .s_axil_awvalid(axil_if_awvalid[n]), + .s_axil_awready(axil_if_awready[n]), + .s_axil_wdata(axil_if_wdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]), + .s_axil_wstrb(axil_if_wstrb[n*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]), + .s_axil_wvalid(axil_if_wvalid[n]), + .s_axil_wready(axil_if_wready[n]), + .s_axil_bresp(axil_if_bresp[n*2 +: 2]), + .s_axil_bvalid(axil_if_bvalid[n]), + .s_axil_bready(axil_if_bready[n]), + .s_axil_araddr(axil_if_araddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]), + .s_axil_arprot(axil_if_arprot[n*3 +: 3]), + .s_axil_arvalid(axil_if_arvalid[n]), + .s_axil_arready(axil_if_arready[n]), + .s_axil_rdata(axil_if_rdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]), + .s_axil_rresp(axil_if_rresp[n*2 +: 2]), + .s_axil_rvalid(axil_if_rvalid[n]), + .s_axil_rready(axil_if_rready[n]), + + /* + * AXI-Lite master interface (passthrough for NIC control and status) + */ + .m_axil_csr_awaddr(axil_if_csr_awaddr[n*AXIL_CSR_ADDR_WIDTH +: AXIL_CSR_ADDR_WIDTH]), + .m_axil_csr_awprot(axil_if_csr_awprot[n*3 +: 3]), + .m_axil_csr_awvalid(axil_if_csr_awvalid[n]), + .m_axil_csr_awready(axil_if_csr_awready[n]), + .m_axil_csr_wdata(axil_if_csr_wdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]), + .m_axil_csr_wstrb(axil_if_csr_wstrb[n*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]), + .m_axil_csr_wvalid(axil_if_csr_wvalid[n]), + .m_axil_csr_wready(axil_if_csr_wready[n]), + .m_axil_csr_bresp(axil_if_csr_bresp[n*2 +: 2]), + .m_axil_csr_bvalid(axil_if_csr_bvalid[n]), + .m_axil_csr_bready(axil_if_csr_bready[n]), + .m_axil_csr_araddr(axil_if_csr_araddr[n*AXIL_CSR_ADDR_WIDTH +: AXIL_CSR_ADDR_WIDTH]), + .m_axil_csr_arprot(axil_if_csr_arprot[n*3 +: 3]), + .m_axil_csr_arvalid(axil_if_csr_arvalid[n]), + .m_axil_csr_arready(axil_if_csr_arready[n]), + .m_axil_csr_rdata(axil_if_csr_rdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]), + .m_axil_csr_rresp(axil_if_csr_rresp[n*2 +: 2]), + .m_axil_csr_rvalid(axil_if_csr_rvalid[n]), + .m_axil_csr_rready(axil_if_csr_rready[n]), + + /* + * RAM interface (control) + */ + .ctrl_dma_ram_wr_cmd_sel(if_ctrl_dma_ram_wr_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]), + .ctrl_dma_ram_wr_cmd_be(if_ctrl_dma_ram_wr_cmd_be[SEG_COUNT*SEG_BE_WIDTH*n +: SEG_COUNT*SEG_BE_WIDTH]), + .ctrl_dma_ram_wr_cmd_addr(if_ctrl_dma_ram_wr_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]), + .ctrl_dma_ram_wr_cmd_data(if_ctrl_dma_ram_wr_cmd_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]), + .ctrl_dma_ram_wr_cmd_valid(if_ctrl_dma_ram_wr_cmd_valid[SEG_COUNT*n +: SEG_COUNT]), + .ctrl_dma_ram_wr_cmd_ready(if_ctrl_dma_ram_wr_cmd_ready[SEG_COUNT*n +: SEG_COUNT]), + .ctrl_dma_ram_rd_cmd_sel(if_ctrl_dma_ram_rd_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]), + .ctrl_dma_ram_rd_cmd_addr(if_ctrl_dma_ram_rd_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]), + .ctrl_dma_ram_rd_cmd_valid(if_ctrl_dma_ram_rd_cmd_valid[SEG_COUNT*n +: SEG_COUNT]), + .ctrl_dma_ram_rd_cmd_ready(if_ctrl_dma_ram_rd_cmd_ready[SEG_COUNT*n +: SEG_COUNT]), + .ctrl_dma_ram_rd_resp_data(if_ctrl_dma_ram_rd_resp_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]), + .ctrl_dma_ram_rd_resp_valid(if_ctrl_dma_ram_rd_resp_valid[SEG_COUNT*n +: SEG_COUNT]), + .ctrl_dma_ram_rd_resp_ready(if_ctrl_dma_ram_rd_resp_ready[SEG_COUNT*n +: SEG_COUNT]), + + /* + * RAM interface (data) + */ + .data_dma_ram_wr_cmd_sel(if_data_dma_ram_wr_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]), + .data_dma_ram_wr_cmd_be(if_data_dma_ram_wr_cmd_be[SEG_COUNT*SEG_BE_WIDTH*n +: SEG_COUNT*SEG_BE_WIDTH]), + .data_dma_ram_wr_cmd_addr(if_data_dma_ram_wr_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]), + .data_dma_ram_wr_cmd_data(if_data_dma_ram_wr_cmd_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]), + .data_dma_ram_wr_cmd_valid(if_data_dma_ram_wr_cmd_valid[SEG_COUNT*n +: SEG_COUNT]), + .data_dma_ram_wr_cmd_ready(if_data_dma_ram_wr_cmd_ready[SEG_COUNT*n +: SEG_COUNT]), + .data_dma_ram_rd_cmd_sel(if_data_dma_ram_rd_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]), + .data_dma_ram_rd_cmd_addr(if_data_dma_ram_rd_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]), + .data_dma_ram_rd_cmd_valid(if_data_dma_ram_rd_cmd_valid[SEG_COUNT*n +: SEG_COUNT]), + .data_dma_ram_rd_cmd_ready(if_data_dma_ram_rd_cmd_ready[SEG_COUNT*n +: SEG_COUNT]), + .data_dma_ram_rd_resp_data(if_data_dma_ram_rd_resp_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]), + .data_dma_ram_rd_resp_valid(if_data_dma_ram_rd_resp_valid[SEG_COUNT*n +: SEG_COUNT]), + .data_dma_ram_rd_resp_ready(if_data_dma_ram_rd_resp_ready[SEG_COUNT*n +: SEG_COUNT]), + + /* + * Transmit data output + */ + .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tkeep(tx_axis_tkeep), + .tx_axis_tvalid(tx_axis_tvalid), + .tx_axis_tready(tx_axis_tready), + .tx_axis_tlast(tx_axis_tlast), + .tx_axis_tuser(tx_axis_tuser), + + /* + * Transmit timestamp input + */ + .s_axis_tx_ptp_ts_96(tx_ptp_ts_96), + .s_axis_tx_ptp_ts_valid(tx_ptp_ts_valid), + .s_axis_tx_ptp_ts_ready(tx_ptp_ts_ready), + + /* + * Receive data input + */ + .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tkeep(rx_axis_tkeep), + .rx_axis_tvalid(rx_axis_tvalid), + .rx_axis_tready(rx_axis_tready), + .rx_axis_tlast(rx_axis_tlast), + .rx_axis_tuser(rx_axis_tuser), + + /* + * Receive timestamp input + */ + .s_axis_rx_ptp_ts_96(rx_ptp_ts_96), + .s_axis_rx_ptp_ts_valid(rx_ptp_ts_valid), + .s_axis_rx_ptp_ts_ready(rx_ptp_ts_ready), + + /* + * PTP clock + */ + .ptp_ts_96(ptp_ts_96), + .ptp_ts_step(ptp_ts_step), + + /* + * MSI interrupts + */ + .msi_irq(if_msi_irq[n*32 +: 32]) + ); + + for (m = 0; m < PORTS_PER_IF; m = m + 1) begin : mac + + wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_pipe; + wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_pipe; + wire tx_axis_tvalid_pipe; + wire tx_axis_tready_pipe; + wire tx_axis_tlast_pipe; + wire tx_axis_tuser_pipe; + + // wire [PTP_TS_WIDTH-1:0] tx_ptp_ts_96_pipe; + // wire tx_ptp_ts_valid_pipe; + // wire tx_ptp_ts_ready_pipe; + + wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata_pipe; + wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep_pipe; + wire rx_axis_tvalid_pipe; + wire rx_axis_tready_pipe; + wire rx_axis_tlast_pipe; + wire rx_axis_tuser_pipe; + + // wire [PTP_TS_WIDTH-1:0] rx_ptp_ts_96_pipe; + // wire rx_ptp_ts_valid_pipe; + // wire rx_ptp_ts_ready_pipe; + + axis_pipeline_register #( + .DATA_WIDTH(AXIS_DATA_WIDTH), + .KEEP_ENABLE(AXIS_KEEP_WIDTH > 1), + .KEEP_WIDTH(AXIS_KEEP_WIDTH), + .LAST_ENABLE(1), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(1), + .REG_TYPE(2), + .LENGTH(2) + ) + tx_reg ( + .clk(clk_250mhz), + .rst(rst_250mhz), + // AXI input + .s_axis_tdata(tx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]), + .s_axis_tkeep(tx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]), + .s_axis_tvalid(tx_axis_tvalid[m +: 1]), + .s_axis_tready(tx_axis_tready[m +: 1]), + .s_axis_tlast(tx_axis_tlast[m +: 1]), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(tx_axis_tuser[m +: 1]), + // AXI output + .m_axis_tdata(tx_axis_tdata_pipe), + .m_axis_tkeep(tx_axis_tkeep_pipe), + .m_axis_tvalid(tx_axis_tvalid_pipe), + .m_axis_tready(tx_axis_tready_pipe), + .m_axis_tlast(tx_axis_tlast_pipe), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(tx_axis_tuser_pipe) + ); + + axis_pipeline_register #( + .DATA_WIDTH(AXIS_DATA_WIDTH), + .KEEP_ENABLE(AXIS_KEEP_WIDTH > 1), + .KEEP_WIDTH(AXIS_KEEP_WIDTH), + .LAST_ENABLE(1), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(1), + .REG_TYPE(2), + .LENGTH(2) + ) + rx_reg ( + .clk(clk_250mhz), + .rst(rst_250mhz), + // AXI input + .s_axis_tdata(rx_axis_tdata_pipe), + .s_axis_tkeep(rx_axis_tkeep_pipe), + .s_axis_tvalid(rx_axis_tvalid_pipe), + .s_axis_tready(rx_axis_tready_pipe), + .s_axis_tlast(rx_axis_tlast_pipe), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(rx_axis_tuser_pipe), + // AXI output + .m_axis_tdata(rx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]), + .m_axis_tkeep(rx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]), + .m_axis_tvalid(rx_axis_tvalid[m +: 1]), + .m_axis_tready(rx_axis_tready[m +: 1]), + .m_axis_tlast(rx_axis_tlast[m +: 1]), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(rx_axis_tuser[m +: 1]) + ); + + axis_async_fifo #( + .DEPTH(TX_FIFO_DEPTH), + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_ENABLE(AXIS_ETH_KEEP_WIDTH > 1), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .LAST_ENABLE(1), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(1), + .FRAME_FIFO(1), + .USER_BAD_FRAME_VALUE(1'b1), + .USER_BAD_FRAME_MASK(1'b1), + .DROP_BAD_FRAME(1), + .DROP_WHEN_FULL(0) + ) + mac_tx_fifo_inst ( + // Common reset + .async_rst(rst_250mhz | port_tx_rst[n*PORTS_PER_IF+m]), + // AXI input + .s_clk(clk_250mhz), + .s_axis_tdata(tx_axis_tdata_pipe), + .s_axis_tkeep(tx_axis_tkeep_pipe), + .s_axis_tvalid(tx_axis_tvalid_pipe), + .s_axis_tready(tx_axis_tready_pipe), + .s_axis_tlast(tx_axis_tlast_pipe), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(tx_axis_tuser_pipe), + // AXI output + .m_clk(port_tx_clk[n*PORTS_PER_IF+m]), + .m_axis_tdata(port_tx_axis_tdata[(n*PORTS_PER_IF+m)*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .m_axis_tkeep(port_tx_axis_tkeep[(n*PORTS_PER_IF+m)*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .m_axis_tvalid(port_tx_axis_tvalid[n*PORTS_PER_IF+m]), + .m_axis_tready(port_tx_axis_tready[n*PORTS_PER_IF+m]), + .m_axis_tlast(port_tx_axis_tlast[n*PORTS_PER_IF+m]), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(port_tx_axis_tuser[n*PORTS_PER_IF+m]), + // Status + .s_status_overflow(), + .s_status_bad_frame(), + .s_status_good_frame(), + .m_status_overflow(), + .m_status_bad_frame(), + .m_status_good_frame() + ); + + axis_async_fifo #( + .DEPTH(RX_FIFO_DEPTH), + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_ENABLE(AXIS_ETH_KEEP_WIDTH > 1), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .LAST_ENABLE(1), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(1), + .FRAME_FIFO(1), + .USER_BAD_FRAME_VALUE(1'b1), + .USER_BAD_FRAME_MASK(1'b1), + .DROP_BAD_FRAME(1), + .DROP_WHEN_FULL(1) + ) + mac_rx_fifo_inst ( + // Common reset + .async_rst(port_rx_rst[n*PORTS_PER_IF+m] | rst_250mhz), + // AXI input + .s_clk(port_rx_clk[n*PORTS_PER_IF+m]), + .s_axis_tdata(port_rx_axis_tdata[(n*PORTS_PER_IF+m)*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .s_axis_tkeep(port_rx_axis_tkeep[(n*PORTS_PER_IF+m)*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .s_axis_tvalid(port_rx_axis_tvalid[n*PORTS_PER_IF+m]), + .s_axis_tready(), + .s_axis_tlast(port_rx_axis_tlast[n*PORTS_PER_IF+m]), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(port_rx_axis_tuser[n*PORTS_PER_IF+m]), + // AXI output + .m_clk(clk_250mhz), + .m_axis_tdata(rx_axis_tdata_pipe), + .m_axis_tkeep(rx_axis_tkeep_pipe), + .m_axis_tvalid(rx_axis_tvalid_pipe), + .m_axis_tready(rx_axis_tready_pipe), + .m_axis_tlast(rx_axis_tlast_pipe), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(rx_axis_tuser_pipe), + // Status + .s_status_overflow(), + .s_status_bad_frame(), + .s_status_good_frame(), + .m_status_overflow(), + .m_status_bad_frame(), + .m_status_good_frame() + ); + + end + + end + +endgenerate + +endmodule diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/sync_signal.v b/fpga/mqnic/AU280/fpga_100g/rtl/sync_signal.v new file mode 100644 index 000000000..b2a8ce3de --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/rtl/sync_signal.v @@ -0,0 +1,58 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`timescale 1 ns / 1 ps + +/* + * Synchronizes an asyncronous signal to a given clock by using a pipeline of + * two registers. + */ +module sync_signal #( + parameter WIDTH=1, // width of the input and output signals + parameter N=2 // depth of synchronizer +)( + input wire clk, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [WIDTH-1:0] sync_reg[N-1:0]; + +/* + * The synchronized output is the last register in the pipeline. + */ +assign out = sync_reg[N-1]; + +integer k; + +always @(posedge clk) begin + sync_reg[0] <= in; + for (k = 1; k < N; k = k + 1) begin + sync_reg[k] <= sync_reg[k-1]; + end +end + +endmodule diff --git a/fpga/mqnic/AU280/fpga_100g/tb/axis_ep.py b/fpga/mqnic/AU280/fpga_100g/tb/axis_ep.py new file mode 120000 index 000000000..385bb0300 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/tb/axis_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/axis_ep.py \ No newline at end of file diff --git a/fpga/mqnic/AU280/fpga_100g/tb/eth_ep.py b/fpga/mqnic/AU280/fpga_100g/tb/eth_ep.py new file mode 120000 index 000000000..bac19feea --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/tb/eth_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/eth_ep.py \ No newline at end of file diff --git a/fpga/mqnic/AU280/fpga_100g/tb/ip_ep.py b/fpga/mqnic/AU280/fpga_100g/tb/ip_ep.py new file mode 120000 index 000000000..6dfa928a7 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/tb/ip_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/ip_ep.py \ No newline at end of file diff --git a/fpga/mqnic/AU280/fpga_100g/tb/mqnic.py b/fpga/mqnic/AU280/fpga_100g/tb/mqnic.py new file mode 120000 index 000000000..f2c96aec4 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/tb/mqnic.py @@ -0,0 +1 @@ +../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/AU280/fpga_100g/tb/pcie.py b/fpga/mqnic/AU280/fpga_100g/tb/pcie.py new file mode 120000 index 000000000..abea2f963 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/tb/pcie.py @@ -0,0 +1 @@ +../lib/pcie/tb/pcie.py \ No newline at end of file diff --git a/fpga/mqnic/AU280/fpga_100g/tb/pcie_us.py b/fpga/mqnic/AU280/fpga_100g/tb/pcie_us.py new file mode 120000 index 000000000..ef028ec29 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/tb/pcie_us.py @@ -0,0 +1 @@ +../lib/pcie/tb/pcie_us.py \ No newline at end of file diff --git a/fpga/mqnic/AU280/fpga_100g/tb/pcie_usp.py b/fpga/mqnic/AU280/fpga_100g/tb/pcie_usp.py new file mode 120000 index 000000000..8ce355a22 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/tb/pcie_usp.py @@ -0,0 +1 @@ +../lib/pcie/tb/pcie_usp.py \ No newline at end of file diff --git a/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py new file mode 100755 index 000000000..f5fd7a10b --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py @@ -0,0 +1,903 @@ +#!/usr/bin/env python +""" + +Copyright 2019, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +""" + +from myhdl import * +import os + +import pcie +import pcie_usp +import axis_ep +import eth_ep +import udp_ep + +import struct + +import mqnic + +module = 'fpga_core' +testbench = 'test_%s' % module + +srcs = [] + +srcs.append("../rtl/%s.v" % module) +srcs.append("../rtl/common/interface.v") +srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/cpl_write.v") +srcs.append("../rtl/common/cpl_op_mux.v") +srcs.append("../rtl/common/desc_fetch.v") +srcs.append("../rtl/common/desc_op_mux.v") +srcs.append("../rtl/common/queue_manager.v") +srcs.append("../rtl/common/cpl_queue_manager.v") +srcs.append("../rtl/common/tx_engine.v") +srcs.append("../rtl/common/rx_engine.v") +srcs.append("../rtl/common/tx_checksum.v") +srcs.append("../rtl/common/rx_hash.v") +srcs.append("../rtl/common/rx_checksum.v") +srcs.append("../rtl/common/tx_scheduler_rr.v") +srcs.append("../rtl/common/event_mux.v") +srcs.append("../rtl/common/tdma_scheduler.v") +srcs.append("../lib/eth/rtl/ptp_clock.v") +srcs.append("../lib/eth/rtl/ptp_clock_cdc.v") +srcs.append("../lib/eth/rtl/ptp_ts_extract.v") +srcs.append("../lib/axi/rtl/axil_interconnect.v") +srcs.append("../lib/axi/rtl/arbiter.v") +srcs.append("../lib/axi/rtl/priority_encoder.v") +srcs.append("../lib/axis/rtl/axis_adapter.v") +srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_fifo.v") +srcs.append("../lib/axis/rtl/axis_register.v") +srcs.append("../lib/axis/rtl/axis_pipeline_register.v") +srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v") +srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v") +srcs.append("../lib/pcie/rtl/dma_if_pcie_us_rd.v") +srcs.append("../lib/pcie/rtl/dma_if_pcie_us_wr.v") +srcs.append("../lib/pcie/rtl/dma_if_mux.v") +srcs.append("../lib/pcie/rtl/dma_if_mux_rd.v") +srcs.append("../lib/pcie/rtl/dma_if_mux_wr.v") +srcs.append("../lib/pcie/rtl/dma_psdpram.v") +srcs.append("../lib/pcie/rtl/dma_client_axis_sink.v") +srcs.append("../lib/pcie/rtl/dma_client_axis_source.v") +srcs.append("../lib/pcie/rtl/pcie_us_cfg.v") +srcs.append("../lib/pcie/rtl/pcie_us_msi.v") +srcs.append("../lib/pcie/rtl/pcie_tag_manager.v") +srcs.append("../lib/pcie/rtl/pulse_merge.v") +srcs.append("%s.v" % testbench) + +src = ' '.join(srcs) + +build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) + +def frame_checksum(frame): + data = frame[14:] + + csum = 0 + odd = False + + for b in data: + if odd: + csum += b + else: + csum += b << 8 + odd = not odd + + csum = (csum & 0xffff) + (csum >> 16) + csum = (csum & 0xffff) + (csum >> 16) + + return csum + +def bench(): + + # Parameters + AXIS_PCIE_DATA_WIDTH = 512 + AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_RC_USER_WIDTH = 161 + AXIS_PCIE_RQ_USER_WIDTH = 137 + AXIS_PCIE_CQ_USER_WIDTH = 183 + AXIS_PCIE_CC_USER_WIDTH = 81 + RQ_SEQ_NUM_WIDTH = 6 + BAR0_APERTURE = 24 + AXIS_ETH_DATA_WIDTH = 512 + AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8 + + # Inputs + clk = Signal(bool(0)) + rst = Signal(bool(0)) + current_test = Signal(intbv(0)[8:]) + + clk_250mhz = Signal(bool(0)) + rst_250mhz = Signal(bool(0)) + m_axis_rq_tready = Signal(bool(0)) + s_axis_rc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]) + s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) + s_axis_rc_tlast = Signal(bool(0)) + s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:]) + s_axis_rc_tvalid = Signal(bool(0)) + s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]) + s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) + s_axis_cq_tlast = Signal(bool(0)) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) + s_axis_cq_tvalid = Signal(bool(0)) + m_axis_cc_tready = Signal(bool(0)) + s_axis_rq_seq_num_0 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) + s_axis_rq_seq_num_valid_0 = Signal(bool(0)) + s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) + s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tfc_nph_av = Signal(intbv(15)[4:]) + pcie_tfc_npd_av = Signal(intbv(15)[4:]) + cfg_max_payload = Signal(intbv(0)[2:]) + cfg_max_read_req = Signal(intbv(0)[3:]) + cfg_mgmt_read_data = Signal(intbv(0)[32:]) + cfg_mgmt_read_write_done = Signal(bool(0)) + cfg_fc_ph = Signal(intbv(0)[8:]) + cfg_fc_pd = Signal(intbv(0)[12:]) + cfg_fc_nph = Signal(intbv(0)[8:]) + cfg_fc_npd = Signal(intbv(0)[12:]) + cfg_fc_cplh = Signal(intbv(0)[8:]) + cfg_fc_cpld = Signal(intbv(0)[12:]) + cfg_interrupt_msi_enable = Signal(intbv(0)[4:]) + cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:]) + cfg_interrupt_msi_mask_update = Signal(bool(0)) + cfg_interrupt_msi_data = Signal(intbv(0)[32:]) + cfg_interrupt_msi_sent = Signal(bool(0)) + cfg_interrupt_msi_fail = Signal(bool(0)) + qsfp0_tx_clk = Signal(bool(0)) + qsfp0_tx_rst = Signal(bool(0)) + qsfp0_rx_clk = Signal(bool(0)) + qsfp0_rx_rst = Signal(bool(0)) + qsfp0_tx_axis_tready = Signal(bool(0)) + qsfp0_rx_axis_tdata = Signal(intbv(0)[AXIS_ETH_DATA_WIDTH:]) + qsfp0_rx_axis_tkeep = Signal(intbv(0)[AXIS_ETH_KEEP_WIDTH:]) + qsfp0_rx_axis_tvalid = Signal(bool(0)) + qsfp0_rx_axis_tlast = Signal(bool(0)) + qsfp0_rx_axis_tuser = Signal(bool(0)) + qsfp1_tx_clk = Signal(bool(0)) + qsfp1_tx_rst = Signal(bool(0)) + qsfp1_rx_clk = Signal(bool(0)) + qsfp1_rx_rst = Signal(bool(0)) + qsfp1_tx_axis_tready = Signal(bool(0)) + qsfp1_rx_axis_tdata = Signal(intbv(0)[AXIS_ETH_DATA_WIDTH:]) + qsfp1_rx_axis_tkeep = Signal(intbv(0)[AXIS_ETH_KEEP_WIDTH:]) + qsfp1_rx_axis_tvalid = Signal(bool(0)) + qsfp1_rx_axis_tlast = Signal(bool(0)) + qsfp1_rx_axis_tuser = Signal(bool(0)) + + # Outputs + m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]) + m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) + m_axis_rq_tlast = Signal(bool(0)) + m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) + m_axis_rq_tvalid = Signal(bool(0)) + s_axis_rc_tready = Signal(bool(0)) + s_axis_cq_tready = Signal(bool(0)) + m_axis_cc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]) + m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) + m_axis_cc_tlast = Signal(bool(0)) + m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:]) + m_axis_cc_tvalid = Signal(bool(0)) + status_error_cor = Signal(bool(0)) + status_error_uncor = Signal(bool(0)) + cfg_mgmt_addr = Signal(intbv(0)[10:]) + cfg_mgmt_function_number = Signal(intbv(0)[8:]) + cfg_mgmt_write = Signal(bool(0)) + cfg_mgmt_write_data = Signal(intbv(0)[32:]) + cfg_mgmt_byte_enable = Signal(intbv(0)[4:]) + cfg_mgmt_read = Signal(bool(0)) + cfg_fc_sel = Signal(intbv(4)[3:]) + cfg_interrupt_msi_int = Signal(intbv(0)[32:]) + cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:]) + cfg_interrupt_msi_select = Signal(intbv(0)[2:]) + cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[2:]) + cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0)) + cfg_interrupt_msi_attr = Signal(intbv(0)[3:]) + cfg_interrupt_msi_tph_present = Signal(bool(0)) + cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:]) + cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[8:]) + cfg_interrupt_msi_function_number = Signal(intbv(0)[8:]) + qsfp0_tx_axis_tdata = Signal(intbv(0)[AXIS_ETH_DATA_WIDTH:]) + qsfp0_tx_axis_tkeep = Signal(intbv(0)[AXIS_ETH_KEEP_WIDTH:]) + qsfp0_tx_axis_tvalid = Signal(bool(0)) + qsfp0_tx_axis_tlast = Signal(bool(0)) + qsfp0_tx_axis_tuser = Signal(bool(0)) + qsfp1_tx_axis_tdata = Signal(intbv(0)[AXIS_ETH_DATA_WIDTH:]) + qsfp1_tx_axis_tkeep = Signal(intbv(0)[AXIS_ETH_KEEP_WIDTH:]) + qsfp1_tx_axis_tvalid = Signal(bool(0)) + qsfp1_tx_axis_tlast = Signal(bool(0)) + qsfp1_tx_axis_tuser = Signal(bool(0)) + + # sources and sinks + qsfp0_source = axis_ep.AXIStreamSource() + qsfp0_source_pause = Signal(bool(False)) + + qsfp0_source_logic = qsfp0_source.create_logic( + qsfp0_rx_clk, + qsfp0_rx_rst, + tdata=qsfp0_rx_axis_tdata, + tkeep=qsfp0_rx_axis_tkeep, + tvalid=qsfp0_rx_axis_tvalid, + tlast=qsfp0_rx_axis_tlast, + tuser=qsfp0_rx_axis_tuser, + pause=qsfp0_source_pause, + name='qsfp0_source' + ) + + qsfp0_sink = axis_ep.AXIStreamSink() + qsfp0_sink_pause = Signal(bool(False)) + + qsfp0_sink_logic = qsfp0_sink.create_logic( + qsfp0_tx_clk, + qsfp0_tx_rst, + tdata=qsfp0_tx_axis_tdata, + tkeep=qsfp0_tx_axis_tkeep, + tvalid=qsfp0_tx_axis_tvalid, + tready=qsfp0_tx_axis_tready, + tlast=qsfp0_tx_axis_tlast, + tuser=qsfp0_tx_axis_tuser, + pause=qsfp0_sink_pause, + name='qsfp0_sink' + ) + + qsfp1_source = axis_ep.AXIStreamSource() + qsfp1_source_pause = Signal(bool(False)) + + qsfp1_source_logic = qsfp1_source.create_logic( + qsfp1_rx_clk, + qsfp1_rx_rst, + tdata=qsfp1_rx_axis_tdata, + tkeep=qsfp1_rx_axis_tkeep, + tvalid=qsfp1_rx_axis_tvalid, + tlast=qsfp1_rx_axis_tlast, + tuser=qsfp1_rx_axis_tuser, + pause=qsfp1_source_pause, + name='qsfp1_source' + ) + + qsfp1_sink = axis_ep.AXIStreamSink() + qsfp1_sink_pause = Signal(bool(False)) + + qsfp1_sink_logic = qsfp1_sink.create_logic( + qsfp1_tx_clk, + qsfp1_tx_rst, + tdata=qsfp1_tx_axis_tdata, + tkeep=qsfp1_tx_axis_tkeep, + tvalid=qsfp1_tx_axis_tvalid, + tready=qsfp1_tx_axis_tready, + tlast=qsfp1_tx_axis_tlast, + tuser=qsfp1_tx_axis_tuser, + pause=qsfp1_sink_pause, + name='qsfp1_sink' + ) + + # Clock and Reset Interface + user_clk=Signal(bool(0)) + user_reset=Signal(bool(0)) + sys_clk=Signal(bool(0)) + sys_reset=Signal(bool(0)) + + # PCIe devices + rc = pcie.RootComplex() + + rc.max_payload_size = 0x1 # 256 bytes + rc.max_read_request_size = 0x5 # 4096 bytes + + driver = mqnic.Driver(rc) + + dev = pcie_usp.UltrascalePlusPCIe() + + dev.pcie_generation = 3 + dev.pcie_link_width = 16 + dev.user_clock_frequency = 250e6 + + dev.functions[0].msi_multiple_message_capable = 5 + + dev.functions[0].configure_bar(0, 2**BAR0_APERTURE) + + rc.make_port().connect(dev) + + cq_pause = Signal(bool(0)) + cc_pause = Signal(bool(0)) + rq_pause = Signal(bool(0)) + rc_pause = Signal(bool(0)) + + pcie_logic = dev.create_logic( + # Completer reQuest Interface + m_axis_cq_tdata=s_axis_cq_tdata, + m_axis_cq_tuser=s_axis_cq_tuser, + m_axis_cq_tlast=s_axis_cq_tlast, + m_axis_cq_tkeep=s_axis_cq_tkeep, + m_axis_cq_tvalid=s_axis_cq_tvalid, + m_axis_cq_tready=s_axis_cq_tready, + #pcie_cq_np_req=pcie_cq_np_req, + pcie_cq_np_req=Signal(intbv(3)[2:]), + #pcie_cq_np_req_count=pcie_cq_np_req_count, + + # Completer Completion Interface + s_axis_cc_tdata=m_axis_cc_tdata, + s_axis_cc_tuser=m_axis_cc_tuser, + s_axis_cc_tlast=m_axis_cc_tlast, + s_axis_cc_tkeep=m_axis_cc_tkeep, + s_axis_cc_tvalid=m_axis_cc_tvalid, + s_axis_cc_tready=m_axis_cc_tready, + + # Requester reQuest Interface + s_axis_rq_tdata=m_axis_rq_tdata, + s_axis_rq_tuser=m_axis_rq_tuser, + s_axis_rq_tlast=m_axis_rq_tlast, + s_axis_rq_tkeep=m_axis_rq_tkeep, + s_axis_rq_tvalid=m_axis_rq_tvalid, + s_axis_rq_tready=m_axis_rq_tready, + pcie_rq_seq_num0=s_axis_rq_seq_num_0, + pcie_rq_seq_num_vld0=s_axis_rq_seq_num_valid_0, + pcie_rq_seq_num1=s_axis_rq_seq_num_1, + pcie_rq_seq_num_vld1=s_axis_rq_seq_num_valid_1, + #pcie_rq_tag0=pcie_rq_tag0, + #pcie_rq_tag1=pcie_rq_tag1, + #pcie_rq_tag_av=pcie_rq_tag_av, + #pcie_rq_tag_vld0=pcie_rq_tag_vld0, + #pcie_rq_tag_vld1=pcie_rq_tag_vld1, + + # Requester Completion Interface + m_axis_rc_tdata=s_axis_rc_tdata, + m_axis_rc_tuser=s_axis_rc_tuser, + m_axis_rc_tlast=s_axis_rc_tlast, + m_axis_rc_tkeep=s_axis_rc_tkeep, + m_axis_rc_tvalid=s_axis_rc_tvalid, + m_axis_rc_tready=s_axis_rc_tready, + + # Transmit Flow Control Interface + #pcie_tfc_nph_av=pcie_tfc_nph_av, + #pcie_tfc_npd_av=pcie_tfc_npd_av, + + # Configuration Management Interface + cfg_mgmt_addr=cfg_mgmt_addr, + cfg_mgmt_function_number=cfg_mgmt_function_number, + cfg_mgmt_write=cfg_mgmt_write, + cfg_mgmt_write_data=cfg_mgmt_write_data, + cfg_mgmt_byte_enable=cfg_mgmt_byte_enable, + cfg_mgmt_read=cfg_mgmt_read, + cfg_mgmt_read_data=cfg_mgmt_read_data, + cfg_mgmt_read_write_done=cfg_mgmt_read_write_done, + #cfg_mgmt_debug_access=cfg_mgmt_debug_access, + + # Configuration Status Interface + #cfg_phy_link_down=cfg_phy_link_down, + #cfg_phy_link_status=cfg_phy_link_status, + #cfg_negotiated_width=cfg_negotiated_width, + #cfg_current_speed=cfg_current_speed, + cfg_max_payload=cfg_max_payload, + cfg_max_read_req=cfg_max_read_req, + #cfg_function_status=cfg_function_status, + #cfg_vf_status=cfg_vf_status, + #cfg_function_power_state=cfg_function_power_state, + #cfg_vf_power_state=cfg_vf_power_state, + #cfg_link_power_state=cfg_link_power_state, + #cfg_err_cor_out=cfg_err_cor_out, + #cfg_err_nonfatal_out=cfg_err_nonfatal_out, + #cfg_err_fatal_out=cfg_err_fatal_out, + #cfg_local_err_out=cfg_local_err_out, + #cfg_local_err_valid=cfg_local_err_valid, + #cfg_rx_pm_state=cfg_rx_pm_state, + #cfg_tx_pm_state=cfg_tx_pm_state, + #cfg_ltssm_state=cfg_ltssm_state, + #cfg_rcb_status=cfg_rcb_status, + #cfg_obff_enable=cfg_obff_enable, + #cfg_pl_status_change=cfg_pl_status_change, + #cfg_tph_requester_enable=cfg_tph_requester_enable, + #cfg_tph_st_mode=cfg_tph_st_mode, + #cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable, + #cfg_vf_tph_st_mode=cfg_vf_tph_st_mode, + + # Configuration Received Message Interface + #cfg_msg_received=cfg_msg_received, + #cfg_msg_received_data=cfg_msg_received_data, + #cfg_msg_received_type=cfg_msg_received_type, + + # Configuration Transmit Message Interface + #cfg_msg_transmit=cfg_msg_transmit, + #cfg_msg_transmit_type=cfg_msg_transmit_type, + #cfg_msg_transmit_data=cfg_msg_transmit_data, + #cfg_msg_transmit_done=cfg_msg_transmit_done, + + # Configuration Flow Control Interface + cfg_fc_ph=cfg_fc_ph, + cfg_fc_pd=cfg_fc_pd, + cfg_fc_nph=cfg_fc_nph, + cfg_fc_npd=cfg_fc_npd, + cfg_fc_cplh=cfg_fc_cplh, + cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=cfg_fc_sel, + + # Configuration Control Interface + #cfg_hot_reset_in=cfg_hot_reset_in, + #cfg_hot_reset_out=cfg_hot_reset_out, + #cfg_config_space_enable=cfg_config_space_enable, + #cfg_dsn=cfg_dsn, + #cfg_ds_port_number=cfg_ds_port_number, + #cfg_ds_bus_number=cfg_ds_bus_number, + #cfg_ds_device_number=cfg_ds_device_number, + #cfg_ds_function_number=cfg_ds_function_number, + #cfg_power_state_change_ack=cfg_power_state_change_ack, + #cfg_power_state_change_interrupt=cfg_power_state_change_interrupt, + cfg_err_cor_in=status_error_cor, + cfg_err_uncor_in=status_error_uncor, + #cfg_flr_done=cfg_flr_done, + #cfg_vf_flr_done=cfg_vf_flr_done, + #cfg_flr_in_process=cfg_flr_in_process, + #cfg_vf_flr_in_process=cfg_vf_flr_in_process, + #cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready, + #cfg_link_training_enable=cfg_link_training_enable, + + # Configuration Interrupt Controller Interface + #cfg_interrupt_int=cfg_interrupt_int, + #cfg_interrupt_sent=cfg_interrupt_sent, + #cfg_interrupt_pending=cfg_interrupt_pending, + cfg_interrupt_msi_enable=cfg_interrupt_msi_enable, + cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable, + cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update, + cfg_interrupt_msi_data=cfg_interrupt_msi_data, + cfg_interrupt_msi_select=cfg_interrupt_msi_select, + cfg_interrupt_msi_int=cfg_interrupt_msi_int, + cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status, + cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable, + cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num, + cfg_interrupt_msi_sent=cfg_interrupt_msi_sent, + cfg_interrupt_msi_fail=cfg_interrupt_msi_fail, + #cfg_interrupt_msix_enable=cfg_interrupt_msix_enable, + #cfg_interrupt_msix_mask=cfg_interrupt_msix_mask, + #cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable, + #cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask, + #cfg_interrupt_msix_address=cfg_interrupt_msix_address, + #cfg_interrupt_msix_data=cfg_interrupt_msix_data, + #cfg_interrupt_msix_int=cfg_interrupt_msix_int, + #cfg_interrupt_msix_vec_pending=cfg_interrupt_msix_vec_pending, + #cfg_interrupt_msix_vec_pending_status=cfg_interrupt_msix_vec_pending_status, + cfg_interrupt_msi_attr=cfg_interrupt_msi_attr, + cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present, + cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type, + cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag, + cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number, + + # Configuration Extend Interface + #cfg_ext_read_received=cfg_ext_read_received, + #cfg_ext_write_received=cfg_ext_write_received, + #cfg_ext_register_number=cfg_ext_register_number, + #cfg_ext_function_number=cfg_ext_function_number, + #cfg_ext_write_data=cfg_ext_write_data, + #cfg_ext_write_byte_enable=cfg_ext_write_byte_enable, + #cfg_ext_read_data=cfg_ext_read_data, + #cfg_ext_read_data_valid=cfg_ext_read_data_valid, + + # Clock and Reset Interface + user_clk=user_clk, + user_reset=user_reset, + sys_clk=sys_clk, + sys_clk_gt=sys_clk, + sys_reset=sys_reset, + #phy_rdy_out=phy_rdy_out, + + cq_pause=cq_pause, + cc_pause=cc_pause, + rq_pause=rq_pause, + rc_pause=rc_pause + ) + + # DUT + if os.system(build_cmd): + raise Exception("Error running build command") + + dut = Cosimulation( + "vvp -m myhdl %s.vvp -lxt2" % testbench, + clk=clk, + rst=rst, + current_test=current_test, + clk_250mhz=user_clk, + rst_250mhz=user_reset, + m_axis_rq_tdata=m_axis_rq_tdata, + m_axis_rq_tkeep=m_axis_rq_tkeep, + m_axis_rq_tlast=m_axis_rq_tlast, + m_axis_rq_tready=m_axis_rq_tready, + m_axis_rq_tuser=m_axis_rq_tuser, + m_axis_rq_tvalid=m_axis_rq_tvalid, + s_axis_rc_tdata=s_axis_rc_tdata, + s_axis_rc_tkeep=s_axis_rc_tkeep, + s_axis_rc_tlast=s_axis_rc_tlast, + s_axis_rc_tready=s_axis_rc_tready, + s_axis_rc_tuser=s_axis_rc_tuser, + s_axis_rc_tvalid=s_axis_rc_tvalid, + s_axis_cq_tdata=s_axis_cq_tdata, + s_axis_cq_tkeep=s_axis_cq_tkeep, + s_axis_cq_tlast=s_axis_cq_tlast, + s_axis_cq_tready=s_axis_cq_tready, + s_axis_cq_tuser=s_axis_cq_tuser, + s_axis_cq_tvalid=s_axis_cq_tvalid, + m_axis_cc_tdata=m_axis_cc_tdata, + m_axis_cc_tkeep=m_axis_cc_tkeep, + m_axis_cc_tlast=m_axis_cc_tlast, + m_axis_cc_tready=m_axis_cc_tready, + m_axis_cc_tuser=m_axis_cc_tuser, + m_axis_cc_tvalid=m_axis_cc_tvalid, + s_axis_rq_seq_num_0=s_axis_rq_seq_num_0, + s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0, + s_axis_rq_seq_num_1=s_axis_rq_seq_num_1, + s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1, + pcie_tfc_nph_av=pcie_tfc_nph_av, + pcie_tfc_npd_av=pcie_tfc_npd_av, + cfg_max_payload=cfg_max_payload, + cfg_max_read_req=cfg_max_read_req, + cfg_mgmt_addr=cfg_mgmt_addr, + cfg_mgmt_function_number=cfg_mgmt_function_number, + cfg_mgmt_write=cfg_mgmt_write, + cfg_mgmt_write_data=cfg_mgmt_write_data, + cfg_mgmt_byte_enable=cfg_mgmt_byte_enable, + cfg_mgmt_read=cfg_mgmt_read, + cfg_mgmt_read_data=cfg_mgmt_read_data, + cfg_mgmt_read_write_done=cfg_mgmt_read_write_done, + cfg_fc_ph=cfg_fc_ph, + cfg_fc_pd=cfg_fc_pd, + cfg_fc_nph=cfg_fc_nph, + cfg_fc_npd=cfg_fc_npd, + cfg_fc_cplh=cfg_fc_cplh, + cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=cfg_fc_sel, + cfg_interrupt_msi_enable=cfg_interrupt_msi_enable, + cfg_interrupt_msi_int=cfg_interrupt_msi_int, + cfg_interrupt_msi_sent=cfg_interrupt_msi_sent, + cfg_interrupt_msi_fail=cfg_interrupt_msi_fail, + cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable, + cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status, + cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update, + cfg_interrupt_msi_select=cfg_interrupt_msi_select, + cfg_interrupt_msi_data=cfg_interrupt_msi_data, + cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num, + cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable, + cfg_interrupt_msi_attr=cfg_interrupt_msi_attr, + cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present, + cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type, + cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag, + cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number, + status_error_cor=status_error_cor, + status_error_uncor=status_error_uncor, + qsfp0_tx_clk=qsfp0_tx_clk, + qsfp0_tx_rst=qsfp0_tx_rst, + qsfp0_tx_axis_tdata=qsfp0_tx_axis_tdata, + qsfp0_tx_axis_tkeep=qsfp0_tx_axis_tkeep, + qsfp0_tx_axis_tvalid=qsfp0_tx_axis_tvalid, + qsfp0_tx_axis_tready=qsfp0_tx_axis_tready, + qsfp0_tx_axis_tlast=qsfp0_tx_axis_tlast, + qsfp0_tx_axis_tuser=qsfp0_tx_axis_tuser, + qsfp0_rx_clk=qsfp0_rx_clk, + qsfp0_rx_rst=qsfp0_rx_rst, + qsfp0_rx_axis_tdata=qsfp0_rx_axis_tdata, + qsfp0_rx_axis_tkeep=qsfp0_rx_axis_tkeep, + qsfp0_rx_axis_tvalid=qsfp0_rx_axis_tvalid, + qsfp0_rx_axis_tlast=qsfp0_rx_axis_tlast, + qsfp0_rx_axis_tuser=qsfp0_rx_axis_tuser, + qsfp1_tx_clk=qsfp1_tx_clk, + qsfp1_tx_rst=qsfp1_tx_rst, + qsfp1_tx_axis_tdata=qsfp1_tx_axis_tdata, + qsfp1_tx_axis_tkeep=qsfp1_tx_axis_tkeep, + qsfp1_tx_axis_tvalid=qsfp1_tx_axis_tvalid, + qsfp1_tx_axis_tready=qsfp1_tx_axis_tready, + qsfp1_tx_axis_tlast=qsfp1_tx_axis_tlast, + qsfp1_tx_axis_tuser=qsfp1_tx_axis_tuser, + qsfp1_rx_clk=qsfp1_rx_clk, + qsfp1_rx_rst=qsfp1_rx_rst, + qsfp1_rx_axis_tdata=qsfp1_rx_axis_tdata, + qsfp1_rx_axis_tkeep=qsfp1_rx_axis_tkeep, + qsfp1_rx_axis_tvalid=qsfp1_rx_axis_tvalid, + qsfp1_rx_axis_tlast=qsfp1_rx_axis_tlast, + qsfp1_rx_axis_tuser=qsfp1_rx_axis_tuser + ) + + @always(delay(5)) + def clkgen(): + clk.next = not clk + + @always(delay(2)) + def qsfp_clkgen(): + qsfp0_tx_clk.next = not qsfp0_tx_clk + qsfp0_rx_clk.next = not qsfp0_rx_clk + qsfp1_tx_clk.next = not qsfp1_tx_clk + qsfp1_rx_clk.next = not qsfp1_rx_clk + + @always_comb + def clk_logic(): + sys_clk.next = clk + sys_reset.next = not rst + + loopback_enable = Signal(bool(0)) + + @instance + def loopback(): + while True: + + yield clk.posedge + + if loopback_enable: + if not qsfp0_sink.empty(): + pkt = qsfp0_sink.recv() + qsfp0_source.send(pkt) + if not qsfp1_sink.empty(): + pkt = qsfp1_sink.recv() + qsfp1_source.send(pkt) + + @instance + def check(): + yield delay(100) + yield clk.posedge + rst.next = 1 + qsfp0_tx_rst.next = 1 + qsfp0_rx_rst.next = 1 + qsfp1_tx_rst.next = 1 + qsfp1_rx_rst.next = 1 + yield clk.posedge + yield delay(100) + rst.next = 0 + qsfp0_tx_rst.next = 0 + qsfp0_rx_rst.next = 0 + qsfp1_tx_rst.next = 0 + qsfp1_rx_rst.next = 0 + yield clk.posedge + yield delay(100) + yield clk.posedge + + # testbench stimulus + + current_tag = 1 + + yield clk.posedge + print("test 1: enumeration") + current_test.next = 1 + + yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) + + dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc + dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc + + yield delay(100) + + yield clk.posedge + print("test 2: init NIC") + current_test.next = 2 + + #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); + #print(data) + + #yield delay(1000) + + #raise StopSimulation + + yield from driver.init_dev(dev.functions[0].get_id()) + yield from driver.interfaces[0].open() + #yield from driver.interfaces[1].open() + + # enable queues + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+mqnic.MQNIC_PORT_REG_SCHED_ENABLE, 0x00000001) + for k in range(driver.interfaces[0].tx_queue_count): + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+4*k, 0x00000003) + + yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete + + yield delay(100) + + yield clk.posedge + print("test 3: send and receive a packet") + current_test.next = 3 + + # test bad packet + #qsfp0_source.send(b'\x55\x55\x55\x55\x55\xd5'+bytearray(range(128))) + + data = bytearray([x%256 for x in range(1024)]) + + yield from driver.interfaces[0].start_xmit(data, 0) + + yield qsfp0_sink.wait() + + pkt = qsfp0_sink.recv() + print(pkt) + + qsfp0_source.send(pkt) + + yield driver.interfaces[0].wait() + + pkt = driver.interfaces[0].recv() + + print(pkt) + assert frame_checksum(pkt.data) == pkt.rx_checksum + + # yield from driver.interfaces[1].start_xmit(data, 0) + + # yield qsfp0_sink.wait() + + # pkt = qsfp0_sink.recv() + # print(pkt) + + # qsfp0_source.send(pkt) + + # yield driver.interfaces[1].wait() + + # pkt = driver.interfaces[1].recv() + + # print(pkt) + # assert frame_checksum(pkt.data) == pkt.rx_checksum + + yield delay(100) + + yield clk.posedge + print("test 4: checksum tests") + current_test.next = 4 + + test_frame = udp_ep.UDPFrame() + test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame.eth_src_mac = 0x5A5152535455 + test_frame.eth_type = 0x0800 + test_frame.ip_version = 4 + test_frame.ip_ihl = 5 + test_frame.ip_length = None + test_frame.ip_identification = 0 + test_frame.ip_flags = 2 + test_frame.ip_fragment_offset = 0 + test_frame.ip_ttl = 64 + test_frame.ip_protocol = 0x11 + test_frame.ip_header_checksum = None + test_frame.ip_source_ip = 0xc0a80164 + test_frame.ip_dest_ip = 0xc0a80165 + test_frame.udp_source_port = 1 + test_frame.udp_dest_port = 2 + test_frame.udp_length = None + test_frame.udp_checksum = None + test_frame.payload = bytearray((x%256 for x in range(256))) + + test_frame.set_udp_pseudo_header_checksum() + + axis_frame = test_frame.build_axis() + + yield from driver.interfaces[0].start_xmit(axis_frame.data, 0, 34, 6) + + yield qsfp0_sink.wait() + + pkt = qsfp0_sink.recv() + print(pkt) + + qsfp0_source.send(pkt) + + yield driver.interfaces[0].wait() + + pkt = driver.interfaces[0].recv() + + print(pkt) + + assert pkt.rx_checksum == frame_checksum(pkt.data) + + check_frame = udp_ep.UDPFrame() + check_frame.parse_axis(pkt.data) + + assert check_frame.verify_checksums() + + yield delay(100) + + yield clk.posedge + print("test 5: multiple small packets") + current_test.next = 5 + + count = 64 + + pkts = [bytearray([(x+k)%256 for x in range(64)]) for k in range(count)] + + loopback_enable.next = True + + for p in pkts: + yield from driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = driver.interfaces[0].recv() + + if not pkt: + yield driver.interfaces[0].wait() + pkt = driver.interfaces[0].recv() + + print(pkt) + assert pkt.data == pkts[k] + assert frame_checksum(pkt.data) == pkt.rx_checksum + + loopback_enable.next = False + + yield delay(100) + + yield clk.posedge + print("test 6: multiple large packets") + current_test.next = 6 + + count = 64 + + pkts = [bytearray([(x+k)%256 for x in range(1514)]) for k in range(count)] + + loopback_enable.next = True + + for p in pkts: + yield from driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = driver.interfaces[0].recv() + + if not pkt: + yield driver.interfaces[0].wait() + pkt = driver.interfaces[0].recv() + + print(pkt) + assert pkt.data == pkts[k] + assert frame_checksum(pkt.data) == pkt.rx_checksum + + loopback_enable.next = False + + yield delay(100) + + yield clk.posedge + print("test 7: jumbo frames") + current_test.next = 7 + + count = 64 + + pkts = [bytearray([(x+k)%256 for x in range(9014)]) for k in range(count)] + + loopback_enable.next = True + + for p in pkts: + yield from driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = driver.interfaces[0].recv() + + if not pkt: + yield driver.interfaces[0].wait() + pkt = driver.interfaces[0].recv() + + print(pkt) + assert pkt.data == pkts[k] + assert frame_checksum(pkt.data) == pkt.rx_checksum + + loopback_enable.next = False + + yield delay(100) + + raise StopSimulation + + return instances() + +def test_bench(): + sim = Simulation(bench()) + sim.run() + +if __name__ == '__main__': + print("Running test...") + test_bench() diff --git a/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.v b/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.v new file mode 100644 index 000000000..95f1e9b4b --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.v @@ -0,0 +1,382 @@ +/* + +Copyright 2019, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Testbench for fpga_core + */ +module test_fpga_core; + +// Parameters +parameter AXIS_PCIE_DATA_WIDTH = 512; +parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RC_USER_WIDTH = 161; +parameter AXIS_PCIE_RQ_USER_WIDTH = 137; +parameter AXIS_PCIE_CQ_USER_WIDTH = 183; +parameter AXIS_PCIE_CC_USER_WIDTH = 81; +parameter RQ_SEQ_NUM_WIDTH = 6; +parameter BAR0_APERTURE = 24; +parameter AXIS_ETH_DATA_WIDTH = 512; +parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; + +// Inputs +reg clk = 0; +reg rst = 0; +reg [7:0] current_test = 0; + +reg clk_250mhz = 0; +reg rst_250mhz = 0; +reg m_axis_rq_tready = 0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata = 0; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep = 0; +reg s_axis_rc_tlast = 0; +reg [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser = 0; +reg s_axis_rc_tvalid = 0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; +reg s_axis_cq_tlast = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; +reg s_axis_cq_tvalid = 0; +reg m_axis_cc_tready = 0; +reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; +reg s_axis_rq_seq_num_valid_0 = 0; +reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; +reg s_axis_rq_seq_num_valid_1 = 0; +reg [3:0] pcie_tfc_nph_av = 0; +reg [3:0] pcie_tfc_npd_av = 0; +reg [2:0] cfg_max_payload = 0; +reg [2:0] cfg_max_read_req = 0; +reg [31:0] cfg_mgmt_read_data = 0; +reg cfg_mgmt_read_write_done = 0; +reg [7:0] cfg_fc_ph = 0; +reg [11:0] cfg_fc_pd = 0; +reg [7:0] cfg_fc_nph = 0; +reg [11:0] cfg_fc_npd = 0; +reg [7:0] cfg_fc_cplh = 0; +reg [11:0] cfg_fc_cpld = 0; +reg [3:0] cfg_interrupt_msi_enable = 0; +reg [11:0] cfg_interrupt_msi_mmenable = 0; +reg cfg_interrupt_msi_mask_update = 0; +reg [31:0] cfg_interrupt_msi_data = 0; +reg cfg_interrupt_msi_sent = 0; +reg cfg_interrupt_msi_fail = 0; +reg qsfp0_tx_clk = 0; +reg qsfp0_tx_rst = 0; +reg qsfp0_tx_axis_tready = 0; +reg qsfp0_rx_clk = 0; +reg qsfp0_rx_rst = 0; +reg [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_rx_axis_tdata = 0; +reg [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_rx_axis_tkeep = 0; +reg qsfp0_rx_axis_tvalid = 0; +reg qsfp0_rx_axis_tlast = 0; +reg qsfp0_rx_axis_tuser = 0; +reg qsfp1_tx_clk = 0; +reg qsfp1_tx_rst = 0; +reg qsfp1_tx_axis_tready = 0; +reg qsfp1_rx_clk = 0; +reg qsfp1_rx_rst = 0; +reg [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_rx_axis_tdata = 0; +reg [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_rx_axis_tkeep = 0; +reg qsfp1_rx_axis_tvalid = 0; +reg qsfp1_rx_axis_tlast = 0; +reg qsfp1_rx_axis_tuser = 0; + +// Outputs +wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep; +wire m_axis_rq_tlast; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser; +wire m_axis_rq_tvalid; +wire s_axis_rc_tready; +wire s_axis_cq_tready; +wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep; +wire m_axis_cc_tlast; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser; +wire m_axis_cc_tvalid; +wire [9:0] cfg_mgmt_addr; +wire [7:0] cfg_mgmt_function_number; +wire cfg_mgmt_write; +wire [31:0] cfg_mgmt_write_data; +wire [3:0] cfg_mgmt_byte_enable; +wire cfg_mgmt_read; +wire [2:0] cfg_fc_sel; +wire [3:0] cfg_interrupt_msi_select; +wire [31:0] cfg_interrupt_msi_int; +wire [31:0] cfg_interrupt_msi_pending_status; +wire cfg_interrupt_msi_pending_status_data_enable; +wire [3:0] cfg_interrupt_msi_pending_status_function_num; +wire [2:0] cfg_interrupt_msi_attr; +wire cfg_interrupt_msi_tph_present; +wire [1:0] cfg_interrupt_msi_tph_type; +wire [8:0] cfg_interrupt_msi_tph_st_tag; +wire [3:0] cfg_interrupt_msi_function_number; +wire status_error_cor; +wire status_error_uncor; +wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_tx_axis_tdata; +wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_tx_axis_tkeep; +wire qsfp0_tx_axis_tvalid; +wire qsfp0_tx_axis_tlast; +wire qsfp0_tx_axis_tuser; +wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_tx_axis_tdata; +wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_tx_axis_tkeep; +wire qsfp1_tx_axis_tvalid; +wire qsfp1_tx_axis_tlast; +wire qsfp1_tx_axis_tuser; + +initial begin + // myhdl integration + $from_myhdl( + clk_250mhz, + rst_250mhz, + current_test, + m_axis_rq_tready, + s_axis_rc_tdata, + s_axis_rc_tkeep, + s_axis_rc_tlast, + s_axis_rc_tuser, + s_axis_rc_tvalid, + s_axis_cq_tdata, + s_axis_cq_tkeep, + s_axis_cq_tlast, + s_axis_cq_tuser, + s_axis_cq_tvalid, + m_axis_cc_tready, + s_axis_rq_seq_num_0, + s_axis_rq_seq_num_valid_0, + s_axis_rq_seq_num_1, + s_axis_rq_seq_num_valid_1, + pcie_tfc_nph_av, + pcie_tfc_npd_av, + cfg_max_payload, + cfg_max_read_req, + cfg_mgmt_read_data, + cfg_mgmt_read_write_done, + cfg_fc_ph, + cfg_fc_pd, + cfg_fc_nph, + cfg_fc_npd, + cfg_fc_cplh, + cfg_fc_cpld, + cfg_interrupt_msi_enable, + cfg_interrupt_msi_mmenable, + cfg_interrupt_msi_mask_update, + cfg_interrupt_msi_data, + cfg_interrupt_msi_sent, + cfg_interrupt_msi_fail, + qsfp0_tx_clk, + qsfp0_tx_rst, + qsfp0_tx_axis_tready, + qsfp0_rx_clk, + qsfp0_rx_rst, + qsfp0_rx_axis_tdata, + qsfp0_rx_axis_tkeep, + qsfp0_rx_axis_tvalid, + qsfp0_rx_axis_tlast, + qsfp0_rx_axis_tuser, + qsfp1_tx_clk, + qsfp1_tx_rst, + qsfp1_tx_axis_tready, + qsfp1_rx_clk, + qsfp1_rx_rst, + qsfp1_rx_axis_tdata, + qsfp1_rx_axis_tkeep, + qsfp1_rx_axis_tvalid, + qsfp1_rx_axis_tlast, + qsfp1_rx_axis_tuser + ); + $to_myhdl( + m_axis_rq_tdata, + m_axis_rq_tkeep, + m_axis_rq_tlast, + m_axis_rq_tuser, + m_axis_rq_tvalid, + s_axis_rc_tready, + s_axis_cq_tready, + m_axis_cc_tdata, + m_axis_cc_tkeep, + m_axis_cc_tlast, + m_axis_cc_tuser, + m_axis_cc_tvalid, + cfg_mgmt_addr, + cfg_mgmt_function_number, + cfg_mgmt_write, + cfg_mgmt_write_data, + cfg_mgmt_byte_enable, + cfg_mgmt_read, + cfg_fc_sel, + cfg_interrupt_msi_select, + cfg_interrupt_msi_int, + cfg_interrupt_msi_pending_status, + cfg_interrupt_msi_pending_status_data_enable, + cfg_interrupt_msi_pending_status_function_num, + cfg_interrupt_msi_attr, + cfg_interrupt_msi_tph_present, + cfg_interrupt_msi_tph_type, + cfg_interrupt_msi_tph_st_tag, + cfg_interrupt_msi_function_number, + status_error_cor, + status_error_uncor, + qsfp0_tx_axis_tdata, + qsfp0_tx_axis_tkeep, + qsfp0_tx_axis_tvalid, + qsfp0_tx_axis_tlast, + qsfp0_tx_axis_tuser, + qsfp1_tx_axis_tdata, + qsfp1_tx_axis_tkeep, + qsfp1_tx_axis_tvalid, + qsfp1_tx_axis_tlast, + qsfp1_tx_axis_tuser + ); + + // dump file + $dumpfile("test_fpga_core.lxt"); + $dumpvars(0, test_fpga_core); +end + +fpga_core #( + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), + .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), + .BAR0_APERTURE(BAR0_APERTURE), + .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH) +) +UUT ( + .clk_250mhz(clk_250mhz), + .rst_250mhz(rst_250mhz), + .m_axis_rq_tdata(m_axis_rq_tdata), + .m_axis_rq_tkeep(m_axis_rq_tkeep), + .m_axis_rq_tlast(m_axis_rq_tlast), + .m_axis_rq_tready(m_axis_rq_tready), + .m_axis_rq_tuser(m_axis_rq_tuser), + .m_axis_rq_tvalid(m_axis_rq_tvalid), + .s_axis_rc_tdata(s_axis_rc_tdata), + .s_axis_rc_tkeep(s_axis_rc_tkeep), + .s_axis_rc_tlast(s_axis_rc_tlast), + .s_axis_rc_tready(s_axis_rc_tready), + .s_axis_rc_tuser(s_axis_rc_tuser), + .s_axis_rc_tvalid(s_axis_rc_tvalid), + .s_axis_cq_tdata(s_axis_cq_tdata), + .s_axis_cq_tkeep(s_axis_cq_tkeep), + .s_axis_cq_tlast(s_axis_cq_tlast), + .s_axis_cq_tready(s_axis_cq_tready), + .s_axis_cq_tuser(s_axis_cq_tuser), + .s_axis_cq_tvalid(s_axis_cq_tvalid), + .m_axis_cc_tdata(m_axis_cc_tdata), + .m_axis_cc_tkeep(m_axis_cc_tkeep), + .m_axis_cc_tlast(m_axis_cc_tlast), + .m_axis_cc_tready(m_axis_cc_tready), + .m_axis_cc_tuser(m_axis_cc_tuser), + .m_axis_cc_tvalid(m_axis_cc_tvalid), + .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0), + .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), + .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), + .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + .status_error_cor(status_error_cor), + .status_error_uncor(status_error_uncor), + .qsfp0_tx_clk(qsfp0_tx_clk), + .qsfp0_tx_rst(qsfp0_tx_rst), + .qsfp0_tx_axis_tdata(qsfp0_tx_axis_tdata), + .qsfp0_tx_axis_tkeep(qsfp0_tx_axis_tkeep), + .qsfp0_tx_axis_tvalid(qsfp0_tx_axis_tvalid), + .qsfp0_tx_axis_tready(qsfp0_tx_axis_tready), + .qsfp0_tx_axis_tlast(qsfp0_tx_axis_tlast), + .qsfp0_tx_axis_tuser(qsfp0_tx_axis_tuser), + .qsfp0_rx_clk(qsfp0_rx_clk), + .qsfp0_rx_rst(qsfp0_rx_rst), + .qsfp0_rx_axis_tdata(qsfp0_rx_axis_tdata), + .qsfp0_rx_axis_tkeep(qsfp0_rx_axis_tkeep), + .qsfp0_rx_axis_tvalid(qsfp0_rx_axis_tvalid), + .qsfp0_rx_axis_tlast(qsfp0_rx_axis_tlast), + .qsfp0_rx_axis_tuser(qsfp0_rx_axis_tuser), + .qsfp1_tx_clk(qsfp1_tx_clk), + .qsfp1_tx_rst(qsfp1_tx_rst), + .qsfp1_tx_axis_tdata(qsfp1_tx_axis_tdata), + .qsfp1_tx_axis_tkeep(qsfp1_tx_axis_tkeep), + .qsfp1_tx_axis_tvalid(qsfp1_tx_axis_tvalid), + .qsfp1_tx_axis_tready(qsfp1_tx_axis_tready), + .qsfp1_tx_axis_tlast(qsfp1_tx_axis_tlast), + .qsfp1_tx_axis_tuser(qsfp1_tx_axis_tuser), + .qsfp1_rx_clk(qsfp1_rx_clk), + .qsfp1_rx_rst(qsfp1_rx_rst), + .qsfp1_rx_axis_tdata(qsfp1_rx_axis_tdata), + .qsfp1_rx_axis_tkeep(qsfp1_rx_axis_tkeep), + .qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid), + .qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast), + .qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser) +); + +endmodule diff --git a/fpga/mqnic/AU280/fpga_100g/tb/udp_ep.py b/fpga/mqnic/AU280/fpga_100g/tb/udp_ep.py new file mode 120000 index 000000000..073c5d3c6 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/tb/udp_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/udp_ep.py \ No newline at end of file diff --git a/fpga/mqnic/AU280/fpga_100g/tb/xgmii_ep.py b/fpga/mqnic/AU280/fpga_100g/tb/xgmii_ep.py new file mode 120000 index 000000000..63b6d3567 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/tb/xgmii_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/xgmii_ep.py \ No newline at end of file