diff --git a/rtl/eth_mux.py b/rtl/eth_mux.py new file mode 100755 index 000000000..6d030f1a1 --- /dev/null +++ b/rtl/eth_mux.py @@ -0,0 +1,368 @@ +#!/usr/bin/env python +"""eth_mux + +Generates an Ethernet mux with the specified number of ports + +Usage: eth_mux [OPTION]... + -?, --help display this help and exit + -p, --ports specify number of ports + -n, --name specify module name + -o, --output specify output file name +""" + +import io +import sys +import getopt +from math import * +from jinja2 import Template + +class Usage(Exception): + def __init__(self, msg): + self.msg = msg + +def main(argv=None): + if argv is None: + argv = sys.argv + try: + try: + opts, args = getopt.getopt(argv[1:], "?n:p:o:", ["help", "name=", "ports=", "output="]) + except getopt.error as msg: + raise Usage(msg) + # more code, unchanged + except Usage as err: + print(err.msg, file=sys.stderr) + print("for help use --help", file=sys.stderr) + return 2 + + ports = 4 + name = None + out_name = None + + # process options + for o, a in opts: + if o in ('-?', '--help'): + print(__doc__) + sys.exit(0) + if o in ('-p', '--ports'): + ports = int(a) + if o in ('-n', '--name'): + name = a + if o in ('-o', '--output'): + out_name = a + + if name is None: + name = "eth_mux_{0}".format(ports) + + if out_name is None: + out_name = name + ".v" + + print("Opening file '%s'..." % out_name) + + try: + out_file = open(out_name, 'w') + except Exception as ex: + print("Error opening \"%s\": %s" %(out_name, ex.strerror), file=sys.stderr) + exit(1) + + print("Generating {0} port Ethernet mux {1}...".format(ports, name)) + + select_width = ceil(log2(ports)) + + t = Template(u"""/* + +Copyright (c) 2014 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Ethernet {{n}} port multiplexer + */ +module {{name}} +( + input wire clk, + input wire rst, + + /* + * Ethernet frame inputs + */ +{%- for p in ports %} + input wire input_{{p}}_eth_hdr_valid, + output wire input_{{p}}_eth_hdr_ready, + input wire [47:0] input_{{p}}_eth_dest_mac, + input wire [47:0] input_{{p}}_eth_src_mac, + input wire [15:0] input_{{p}}_eth_type, + input wire [7:0] input_{{p}}_eth_payload_tdata, + input wire input_{{p}}_eth_payload_tvalid, + output wire input_{{p}}_eth_payload_tready, + input wire input_{{p}}_eth_payload_tlast, + input wire input_{{p}}_eth_payload_tuser, +{% endfor %} + /* + * Ethernet frame output + */ + output wire output_eth_hdr_valid, + input wire output_eth_hdr_ready, + output wire [47:0] output_eth_dest_mac, + output wire [47:0] output_eth_src_mac, + output wire [15:0] output_eth_type, + output wire [7:0] output_eth_payload_tdata, + output wire output_eth_payload_tvalid, + input wire output_eth_payload_tready, + output wire output_eth_payload_tlast, + output wire output_eth_payload_tuser, + + /* + * Control + */ + input wire [{{w-1}}:0] select +); + +reg [{{w-1}}:0] select_reg = 0, select_next; +reg frame_reg = 0, frame_next; +{% for p in ports %} +reg input_{{p}}_eth_hdr_ready_reg = 0, input_{{p}}_eth_hdr_ready_next; +{%- endfor %} +{% for p in ports %} +reg input_{{p}}_eth_payload_tready_reg = 0, input_{{p}}_eth_payload_tready_next; +{%- endfor %} + +reg output_eth_hdr_valid_reg = 0, output_eth_hdr_valid_next; +reg [47:0] output_eth_dest_mac_reg = 0, output_eth_dest_mac_next; +reg [47:0] output_eth_src_mac_reg = 0, output_eth_src_mac_next; +reg [15:0] output_eth_type_reg = 0, output_eth_type_next; + +// internal datapath +reg [7:0] output_eth_payload_tdata_int; +reg output_eth_payload_tvalid_int; +reg output_eth_payload_tready_int = 0; +reg output_eth_payload_tlast_int; +reg output_eth_payload_tuser_int; +wire output_eth_payload_tready_int_early; +{% for p in ports %} +assign input_{{p}}_eth_hdr_ready = input_{{p}}_eth_hdr_ready_reg; +{%- endfor %} +{% for p in ports %} +assign input_{{p}}_eth_payload_tready = input_{{p}}_eth_payload_tready_reg; +{%- endfor %} + +assign output_eth_hdr_valid = output_eth_hdr_valid_reg; +assign output_eth_dest_mac = output_eth_dest_mac_reg; +assign output_eth_src_mac = output_eth_src_mac_reg; +assign output_eth_type = output_eth_type_reg; + +// mux for start of packet detection +reg selected_input_eth_hdr_valid; +reg [47:0] selected_input_eth_dest_mac; +reg [47:0] selected_input_eth_src_mac; +reg [15:0] selected_input_eth_type; +always @* begin + case (select) +{%- for p in ports %} + {{w}}'d{{p}}: begin + selected_input_eth_hdr_valid = input_{{p}}_eth_hdr_valid; + selected_input_eth_dest_mac = input_{{p}}_eth_dest_mac; + selected_input_eth_src_mac = input_{{p}}_eth_src_mac; + selected_input_eth_type = input_{{p}}_eth_type; + end +{%- endfor %} + endcase +end + +// mux for incoming packet +reg [7:0] current_input_tdata; +reg current_input_tvalid; +reg current_input_tready; +reg current_input_tlast; +reg current_input_tuser; +always @* begin + case (select_reg) +{%- for p in ports %} + {{w}}'d{{p}}: begin + current_input_tdata = input_{{p}}_eth_payload_tdata; + current_input_tvalid = input_{{p}}_eth_payload_tvalid; + current_input_tready = input_{{p}}_eth_payload_tready; + current_input_tlast = input_{{p}}_eth_payload_tlast; + current_input_tuser = input_{{p}}_eth_payload_tuser; + end +{%- endfor %} + endcase +end + +always @* begin + select_next = select_reg; + frame_next = frame_reg; +{% for p in ports %} + input_{{p}}_eth_hdr_ready_next = input_{{p}}_eth_hdr_ready_reg & ~input_{{p}}_eth_hdr_valid; +{%- endfor %} +{% for p in ports %} + input_{{p}}_eth_payload_tready_next = 0; +{%- endfor %} + + output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready; + output_eth_dest_mac_next = output_eth_dest_mac_reg; + output_eth_src_mac_next = output_eth_src_mac_reg; + output_eth_type_next = output_eth_type_reg; + + if (frame_reg) begin + if (current_input_tvalid & current_input_tready) begin + // end of frame detection + frame_next = ~current_input_tlast; + end + end else if (selected_input_eth_hdr_valid) begin + // start of frame, grab select value + frame_next = 1; + select_next = select; + output_eth_hdr_valid_next = 1; + output_eth_dest_mac_next = selected_input_eth_dest_mac; + output_eth_src_mac_next = selected_input_eth_src_mac; + output_eth_type_next = selected_input_eth_type; + end + + // generate ready signal on selected port + case (select_next) +{%- for p in ports %} + {{w}}'d{{p}}: begin + input_{{p}}_eth_hdr_ready_next = input_{{p}}_eth_hdr_ready_next | (frame_next & ~frame_reg); + input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + end +{%- endfor %} + endcase + + // pass through selected packet data + output_eth_payload_tdata_int = current_input_tdata; + output_eth_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg; + output_eth_payload_tlast_int = current_input_tlast; + output_eth_payload_tuser_int = current_input_tuser; +end + +always @(posedge clk or posedge rst) begin + if (rst) begin + select_reg <= 0; + frame_reg <= 0; +{%- for p in ports %} + input_{{p}}_eth_hdr_ready_reg <= 0; +{%- endfor %} +{%- for p in ports %} + input_{{p}}_eth_payload_tready_reg <= 0; +{%- endfor %} + output_eth_hdr_valid_reg <= 0; + output_eth_dest_mac_reg <= 0; + output_eth_src_mac_reg <= 0; + output_eth_type_reg <= 0; + end else begin + select_reg <= select_next; + frame_reg <= frame_next; +{%- for p in ports %} + input_{{p}}_eth_hdr_ready_reg <= input_{{p}}_eth_hdr_ready_next; +{%- endfor %} +{%- for p in ports %} + input_{{p}}_eth_payload_tready_reg <= input_{{p}}_eth_payload_tready_next; +{%- endfor %} + output_eth_hdr_valid_reg <= output_eth_hdr_valid_next; + output_eth_dest_mac_reg <= output_eth_dest_mac_next; + output_eth_src_mac_reg <= output_eth_src_mac_next; + output_eth_type_reg <= output_eth_type_next; + end +end + +// output datapath logic +reg [7:0] output_eth_payload_tdata_reg = 0; +reg output_eth_payload_tvalid_reg = 0; +reg output_eth_payload_tlast_reg = 0; +reg output_eth_payload_tuser_reg = 0; + +reg [7:0] temp_eth_payload_tdata_reg = 0; +reg temp_eth_payload_tvalid_reg = 0; +reg temp_eth_payload_tlast_reg = 0; +reg temp_eth_payload_tuser_reg = 0; + +assign output_eth_payload_tdata = output_eth_payload_tdata_reg; +assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg; +assign output_eth_payload_tlast = output_eth_payload_tlast_reg; +assign output_eth_payload_tuser = output_eth_payload_tuser_reg; + +// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle +assign output_eth_payload_tready_int_early = output_eth_payload_tready | (~temp_eth_payload_tvalid_reg & ~output_eth_payload_tvalid_reg) | (~temp_eth_payload_tvalid_reg & ~output_eth_payload_tvalid_int); + +always @(posedge clk or posedge rst) begin + if (rst) begin + output_eth_payload_tdata_reg <= 0; + output_eth_payload_tvalid_reg <= 0; + output_eth_payload_tlast_reg <= 0; + output_eth_payload_tuser_reg <= 0; + output_eth_payload_tready_int <= 0; + temp_eth_payload_tdata_reg <= 0; + temp_eth_payload_tvalid_reg <= 0; + temp_eth_payload_tlast_reg <= 0; + temp_eth_payload_tuser_reg <= 0; + end else begin + // transfer sink ready state to source + output_eth_payload_tready_int <= output_eth_payload_tready_int_early; + + if (output_eth_payload_tready_int) begin + // input is ready + if (output_eth_payload_tready | ~output_eth_payload_tvalid_reg) begin + // output is ready or currently not valid, transfer data to output + output_eth_payload_tdata_reg <= output_eth_payload_tdata_int; + output_eth_payload_tvalid_reg <= output_eth_payload_tvalid_int; + output_eth_payload_tlast_reg <= output_eth_payload_tlast_int; + output_eth_payload_tuser_reg <= output_eth_payload_tuser_int; + end else begin + // output is not ready, store input in temp + temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int; + temp_eth_payload_tvalid_reg <= output_eth_payload_tvalid_int; + temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int; + temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int; + end + end else if (output_eth_payload_tready) begin + // input is not ready, but output is ready + output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg; + output_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_reg; + output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg; + output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg; + temp_eth_payload_tdata_reg <= 0; + temp_eth_payload_tvalid_reg <= 0; + temp_eth_payload_tlast_reg <= 0; + temp_eth_payload_tuser_reg <= 0; + end + end +end + +endmodule + +""") + + out_file.write(t.render( + n=ports, + w=select_width, + name=name, + ports=range(ports) + )) + + print("Done") + +if __name__ == "__main__": + sys.exit(main()) + diff --git a/rtl/eth_mux_4.v b/rtl/eth_mux_4.v new file mode 100644 index 000000000..77e7b710c --- /dev/null +++ b/rtl/eth_mux_4.v @@ -0,0 +1,376 @@ +/* + +Copyright (c) 2014 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Ethernet 4 port multiplexer + */ +module eth_mux_4 +( + input wire clk, + input wire rst, + + /* + * Ethernet frame inputs + */ + input wire input_0_eth_hdr_valid, + output wire input_0_eth_hdr_ready, + input wire [47:0] input_0_eth_dest_mac, + input wire [47:0] input_0_eth_src_mac, + input wire [15:0] input_0_eth_type, + input wire [7:0] input_0_eth_payload_tdata, + input wire input_0_eth_payload_tvalid, + output wire input_0_eth_payload_tready, + input wire input_0_eth_payload_tlast, + input wire input_0_eth_payload_tuser, + + input wire input_1_eth_hdr_valid, + output wire input_1_eth_hdr_ready, + input wire [47:0] input_1_eth_dest_mac, + input wire [47:0] input_1_eth_src_mac, + input wire [15:0] input_1_eth_type, + input wire [7:0] input_1_eth_payload_tdata, + input wire input_1_eth_payload_tvalid, + output wire input_1_eth_payload_tready, + input wire input_1_eth_payload_tlast, + input wire input_1_eth_payload_tuser, + + input wire input_2_eth_hdr_valid, + output wire input_2_eth_hdr_ready, + input wire [47:0] input_2_eth_dest_mac, + input wire [47:0] input_2_eth_src_mac, + input wire [15:0] input_2_eth_type, + input wire [7:0] input_2_eth_payload_tdata, + input wire input_2_eth_payload_tvalid, + output wire input_2_eth_payload_tready, + input wire input_2_eth_payload_tlast, + input wire input_2_eth_payload_tuser, + + input wire input_3_eth_hdr_valid, + output wire input_3_eth_hdr_ready, + input wire [47:0] input_3_eth_dest_mac, + input wire [47:0] input_3_eth_src_mac, + input wire [15:0] input_3_eth_type, + input wire [7:0] input_3_eth_payload_tdata, + input wire input_3_eth_payload_tvalid, + output wire input_3_eth_payload_tready, + input wire input_3_eth_payload_tlast, + input wire input_3_eth_payload_tuser, + + /* + * Ethernet frame output + */ + output wire output_eth_hdr_valid, + input wire output_eth_hdr_ready, + output wire [47:0] output_eth_dest_mac, + output wire [47:0] output_eth_src_mac, + output wire [15:0] output_eth_type, + output wire [7:0] output_eth_payload_tdata, + output wire output_eth_payload_tvalid, + input wire output_eth_payload_tready, + output wire output_eth_payload_tlast, + output wire output_eth_payload_tuser, + + /* + * Control + */ + input wire [1:0] select +); + +reg [1:0] select_reg = 0, select_next; +reg frame_reg = 0, frame_next; + +reg input_0_eth_hdr_ready_reg = 0, input_0_eth_hdr_ready_next; +reg input_1_eth_hdr_ready_reg = 0, input_1_eth_hdr_ready_next; +reg input_2_eth_hdr_ready_reg = 0, input_2_eth_hdr_ready_next; +reg input_3_eth_hdr_ready_reg = 0, input_3_eth_hdr_ready_next; + +reg input_0_eth_payload_tready_reg = 0, input_0_eth_payload_tready_next; +reg input_1_eth_payload_tready_reg = 0, input_1_eth_payload_tready_next; +reg input_2_eth_payload_tready_reg = 0, input_2_eth_payload_tready_next; +reg input_3_eth_payload_tready_reg = 0, input_3_eth_payload_tready_next; + +reg output_eth_hdr_valid_reg = 0, output_eth_hdr_valid_next; +reg [47:0] output_eth_dest_mac_reg = 0, output_eth_dest_mac_next; +reg [47:0] output_eth_src_mac_reg = 0, output_eth_src_mac_next; +reg [15:0] output_eth_type_reg = 0, output_eth_type_next; + +// internal datapath +reg [7:0] output_eth_payload_tdata_int; +reg output_eth_payload_tvalid_int; +reg output_eth_payload_tready_int = 0; +reg output_eth_payload_tlast_int; +reg output_eth_payload_tuser_int; +wire output_eth_payload_tready_int_early; + +assign input_0_eth_hdr_ready = input_0_eth_hdr_ready_reg; +assign input_1_eth_hdr_ready = input_1_eth_hdr_ready_reg; +assign input_2_eth_hdr_ready = input_2_eth_hdr_ready_reg; +assign input_3_eth_hdr_ready = input_3_eth_hdr_ready_reg; + +assign input_0_eth_payload_tready = input_0_eth_payload_tready_reg; +assign input_1_eth_payload_tready = input_1_eth_payload_tready_reg; +assign input_2_eth_payload_tready = input_2_eth_payload_tready_reg; +assign input_3_eth_payload_tready = input_3_eth_payload_tready_reg; + +assign output_eth_hdr_valid = output_eth_hdr_valid_reg; +assign output_eth_dest_mac = output_eth_dest_mac_reg; +assign output_eth_src_mac = output_eth_src_mac_reg; +assign output_eth_type = output_eth_type_reg; + +// mux for start of packet detection +reg selected_input_eth_hdr_valid; +reg [47:0] selected_input_eth_dest_mac; +reg [47:0] selected_input_eth_src_mac; +reg [15:0] selected_input_eth_type; +always @* begin + case (select) + 2'd0: begin + selected_input_eth_hdr_valid = input_0_eth_hdr_valid; + selected_input_eth_dest_mac = input_0_eth_dest_mac; + selected_input_eth_src_mac = input_0_eth_src_mac; + selected_input_eth_type = input_0_eth_type; + end + 2'd1: begin + selected_input_eth_hdr_valid = input_1_eth_hdr_valid; + selected_input_eth_dest_mac = input_1_eth_dest_mac; + selected_input_eth_src_mac = input_1_eth_src_mac; + selected_input_eth_type = input_1_eth_type; + end + 2'd2: begin + selected_input_eth_hdr_valid = input_2_eth_hdr_valid; + selected_input_eth_dest_mac = input_2_eth_dest_mac; + selected_input_eth_src_mac = input_2_eth_src_mac; + selected_input_eth_type = input_2_eth_type; + end + 2'd3: begin + selected_input_eth_hdr_valid = input_3_eth_hdr_valid; + selected_input_eth_dest_mac = input_3_eth_dest_mac; + selected_input_eth_src_mac = input_3_eth_src_mac; + selected_input_eth_type = input_3_eth_type; + end + endcase +end + +// mux for incoming packet +reg [7:0] current_input_tdata; +reg current_input_tvalid; +reg current_input_tready; +reg current_input_tlast; +reg current_input_tuser; +always @* begin + case (select_reg) + 2'd0: begin + current_input_tdata = input_0_eth_payload_tdata; + current_input_tvalid = input_0_eth_payload_tvalid; + current_input_tready = input_0_eth_payload_tready; + current_input_tlast = input_0_eth_payload_tlast; + current_input_tuser = input_0_eth_payload_tuser; + end + 2'd1: begin + current_input_tdata = input_1_eth_payload_tdata; + current_input_tvalid = input_1_eth_payload_tvalid; + current_input_tready = input_1_eth_payload_tready; + current_input_tlast = input_1_eth_payload_tlast; + current_input_tuser = input_1_eth_payload_tuser; + end + 2'd2: begin + current_input_tdata = input_2_eth_payload_tdata; + current_input_tvalid = input_2_eth_payload_tvalid; + current_input_tready = input_2_eth_payload_tready; + current_input_tlast = input_2_eth_payload_tlast; + current_input_tuser = input_2_eth_payload_tuser; + end + 2'd3: begin + current_input_tdata = input_3_eth_payload_tdata; + current_input_tvalid = input_3_eth_payload_tvalid; + current_input_tready = input_3_eth_payload_tready; + current_input_tlast = input_3_eth_payload_tlast; + current_input_tuser = input_3_eth_payload_tuser; + end + endcase +end + +always @* begin + select_next = select_reg; + frame_next = frame_reg; + + input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_reg & ~input_0_eth_hdr_valid; + input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_reg & ~input_1_eth_hdr_valid; + input_2_eth_hdr_ready_next = input_2_eth_hdr_ready_reg & ~input_2_eth_hdr_valid; + input_3_eth_hdr_ready_next = input_3_eth_hdr_ready_reg & ~input_3_eth_hdr_valid; + + input_0_eth_payload_tready_next = 0; + input_1_eth_payload_tready_next = 0; + input_2_eth_payload_tready_next = 0; + input_3_eth_payload_tready_next = 0; + + output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready; + output_eth_dest_mac_next = output_eth_dest_mac_reg; + output_eth_src_mac_next = output_eth_src_mac_reg; + output_eth_type_next = output_eth_type_reg; + + if (frame_reg) begin + if (current_input_tvalid & current_input_tready) begin + // end of frame detection + frame_next = ~current_input_tlast; + end + end else if (selected_input_eth_hdr_valid) begin + // start of frame, grab select value + frame_next = 1; + select_next = select; + output_eth_hdr_valid_next = 1; + output_eth_dest_mac_next = selected_input_eth_dest_mac; + output_eth_src_mac_next = selected_input_eth_src_mac; + output_eth_type_next = selected_input_eth_type; + end + + // generate ready signal on selected port + case (select_next) + 2'd0: begin + input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_next | (frame_next & ~frame_reg); + input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + end + 2'd1: begin + input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_next | (frame_next & ~frame_reg); + input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + end + 2'd2: begin + input_2_eth_hdr_ready_next = input_2_eth_hdr_ready_next | (frame_next & ~frame_reg); + input_2_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + end + 2'd3: begin + input_3_eth_hdr_ready_next = input_3_eth_hdr_ready_next | (frame_next & ~frame_reg); + input_3_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + end + endcase + + // pass through selected packet data + output_eth_payload_tdata_int = current_input_tdata; + output_eth_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg; + output_eth_payload_tlast_int = current_input_tlast; + output_eth_payload_tuser_int = current_input_tuser; +end + +always @(posedge clk or posedge rst) begin + if (rst) begin + select_reg <= 0; + frame_reg <= 0; + input_0_eth_hdr_ready_reg <= 0; + input_1_eth_hdr_ready_reg <= 0; + input_2_eth_hdr_ready_reg <= 0; + input_3_eth_hdr_ready_reg <= 0; + input_0_eth_payload_tready_reg <= 0; + input_1_eth_payload_tready_reg <= 0; + input_2_eth_payload_tready_reg <= 0; + input_3_eth_payload_tready_reg <= 0; + output_eth_hdr_valid_reg <= 0; + output_eth_dest_mac_reg <= 0; + output_eth_src_mac_reg <= 0; + output_eth_type_reg <= 0; + end else begin + select_reg <= select_next; + frame_reg <= frame_next; + input_0_eth_hdr_ready_reg <= input_0_eth_hdr_ready_next; + input_1_eth_hdr_ready_reg <= input_1_eth_hdr_ready_next; + input_2_eth_hdr_ready_reg <= input_2_eth_hdr_ready_next; + input_3_eth_hdr_ready_reg <= input_3_eth_hdr_ready_next; + input_0_eth_payload_tready_reg <= input_0_eth_payload_tready_next; + input_1_eth_payload_tready_reg <= input_1_eth_payload_tready_next; + input_2_eth_payload_tready_reg <= input_2_eth_payload_tready_next; + input_3_eth_payload_tready_reg <= input_3_eth_payload_tready_next; + output_eth_hdr_valid_reg <= output_eth_hdr_valid_next; + output_eth_dest_mac_reg <= output_eth_dest_mac_next; + output_eth_src_mac_reg <= output_eth_src_mac_next; + output_eth_type_reg <= output_eth_type_next; + end +end + +// output datapath logic +reg [7:0] output_eth_payload_tdata_reg = 0; +reg output_eth_payload_tvalid_reg = 0; +reg output_eth_payload_tlast_reg = 0; +reg output_eth_payload_tuser_reg = 0; + +reg [7:0] temp_eth_payload_tdata_reg = 0; +reg temp_eth_payload_tvalid_reg = 0; +reg temp_eth_payload_tlast_reg = 0; +reg temp_eth_payload_tuser_reg = 0; + +assign output_eth_payload_tdata = output_eth_payload_tdata_reg; +assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg; +assign output_eth_payload_tlast = output_eth_payload_tlast_reg; +assign output_eth_payload_tuser = output_eth_payload_tuser_reg; + +// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle +assign output_eth_payload_tready_int_early = output_eth_payload_tready | (~temp_eth_payload_tvalid_reg & ~output_eth_payload_tvalid_reg) | (~temp_eth_payload_tvalid_reg & ~output_eth_payload_tvalid_int); + +always @(posedge clk or posedge rst) begin + if (rst) begin + output_eth_payload_tdata_reg <= 0; + output_eth_payload_tvalid_reg <= 0; + output_eth_payload_tlast_reg <= 0; + output_eth_payload_tuser_reg <= 0; + output_eth_payload_tready_int <= 0; + temp_eth_payload_tdata_reg <= 0; + temp_eth_payload_tvalid_reg <= 0; + temp_eth_payload_tlast_reg <= 0; + temp_eth_payload_tuser_reg <= 0; + end else begin + // transfer sink ready state to source + output_eth_payload_tready_int <= output_eth_payload_tready_int_early; + + if (output_eth_payload_tready_int) begin + // input is ready + if (output_eth_payload_tready | ~output_eth_payload_tvalid_reg) begin + // output is ready or currently not valid, transfer data to output + output_eth_payload_tdata_reg <= output_eth_payload_tdata_int; + output_eth_payload_tvalid_reg <= output_eth_payload_tvalid_int; + output_eth_payload_tlast_reg <= output_eth_payload_tlast_int; + output_eth_payload_tuser_reg <= output_eth_payload_tuser_int; + end else begin + // output is not ready, store input in temp + temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int; + temp_eth_payload_tvalid_reg <= output_eth_payload_tvalid_int; + temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int; + temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int; + end + end else if (output_eth_payload_tready) begin + // input is not ready, but output is ready + output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg; + output_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_reg; + output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg; + output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg; + temp_eth_payload_tdata_reg <= 0; + temp_eth_payload_tvalid_reg <= 0; + temp_eth_payload_tlast_reg <= 0; + temp_eth_payload_tuser_reg <= 0; + end + end +end + +endmodule diff --git a/rtl/eth_mux_64.py b/rtl/eth_mux_64.py new file mode 100755 index 000000000..d5a3a8f66 --- /dev/null +++ b/rtl/eth_mux_64.py @@ -0,0 +1,383 @@ +#!/usr/bin/env python +"""eth_mux_64 + +Generates an Ethernet mux with the specified number of ports + +Usage: eth_mux_64 [OPTION]... + -?, --help display this help and exit + -p, --ports specify number of ports + -n, --name specify module name + -o, --output specify output file name +""" + +import io +import sys +import getopt +from math import * +from jinja2 import Template + +class Usage(Exception): + def __init__(self, msg): + self.msg = msg + +def main(argv=None): + if argv is None: + argv = sys.argv + try: + try: + opts, args = getopt.getopt(argv[1:], "?n:p:o:", ["help", "name=", "ports=", "output="]) + except getopt.error as msg: + raise Usage(msg) + # more code, unchanged + except Usage as err: + print(err.msg, file=sys.stderr) + print("for help use --help", file=sys.stderr) + return 2 + + ports = 4 + name = None + out_name = None + + # process options + for o, a in opts: + if o in ('-?', '--help'): + print(__doc__) + sys.exit(0) + if o in ('-p', '--ports'): + ports = int(a) + if o in ('-n', '--name'): + name = a + if o in ('-o', '--output'): + out_name = a + + if name is None: + name = "eth_mux_64_{0}".format(ports) + + if out_name is None: + out_name = name + ".v" + + print("Opening file '%s'..." % out_name) + + try: + out_file = open(out_name, 'w') + except Exception as ex: + print("Error opening \"%s\": %s" %(out_name, ex.strerror), file=sys.stderr) + exit(1) + + print("Generating {0} port Ethernet mux {1}...".format(ports, name)) + + select_width = ceil(log2(ports)) + + t = Template(u"""/* + +Copyright (c) 2014 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Ethernet {{n}} port multiplexer (64 bit datapath) + */ +module {{name}} +( + input wire clk, + input wire rst, + + /* + * Ethernet frame inputs + */ +{%- for p in ports %} + input wire input_{{p}}_eth_hdr_valid, + output wire input_{{p}}_eth_hdr_ready, + input wire [47:0] input_{{p}}_eth_dest_mac, + input wire [47:0] input_{{p}}_eth_src_mac, + input wire [15:0] input_{{p}}_eth_type, + input wire [63:0] input_{{p}}_eth_payload_tdata, + input wire [7:0] input_{{p}}_eth_payload_tkeep, + input wire input_{{p}}_eth_payload_tvalid, + output wire input_{{p}}_eth_payload_tready, + input wire input_{{p}}_eth_payload_tlast, + input wire input_{{p}}_eth_payload_tuser, +{% endfor %} + /* + * Ethernet frame output + */ + output wire output_eth_hdr_valid, + input wire output_eth_hdr_ready, + output wire [47:0] output_eth_dest_mac, + output wire [47:0] output_eth_src_mac, + output wire [15:0] output_eth_type, + output wire [63:0] output_eth_payload_tdata, + output wire [7:0] output_eth_payload_tkeep, + output wire output_eth_payload_tvalid, + input wire output_eth_payload_tready, + output wire output_eth_payload_tlast, + output wire output_eth_payload_tuser, + + /* + * Control + */ + input wire [{{w-1}}:0] select +); + +reg [{{w-1}}:0] select_reg = 0, select_next; +reg frame_reg = 0, frame_next; +{% for p in ports %} +reg input_{{p}}_eth_hdr_ready_reg = 0, input_{{p}}_eth_hdr_ready_next; +{%- endfor %} +{% for p in ports %} +reg input_{{p}}_eth_payload_tready_reg = 0, input_{{p}}_eth_payload_tready_next; +{%- endfor %} + +reg output_eth_hdr_valid_reg = 0, output_eth_hdr_valid_next; +reg [47:0] output_eth_dest_mac_reg = 0, output_eth_dest_mac_next; +reg [47:0] output_eth_src_mac_reg = 0, output_eth_src_mac_next; +reg [15:0] output_eth_type_reg = 0, output_eth_type_next; + +// internal datapath +reg [63:0] output_eth_payload_tdata_int; +reg [7:0] output_eth_payload_tkeep_int; +reg output_eth_payload_tvalid_int; +reg output_eth_payload_tready_int = 0; +reg output_eth_payload_tlast_int; +reg output_eth_payload_tuser_int; +wire output_eth_payload_tready_int_early; +{% for p in ports %} +assign input_{{p}}_eth_hdr_ready = input_{{p}}_eth_hdr_ready_reg; +{%- endfor %} +{% for p in ports %} +assign input_{{p}}_eth_payload_tready = input_{{p}}_eth_payload_tready_reg; +{%- endfor %} + +assign output_eth_hdr_valid = output_eth_hdr_valid_reg; +assign output_eth_dest_mac = output_eth_dest_mac_reg; +assign output_eth_src_mac = output_eth_src_mac_reg; +assign output_eth_type = output_eth_type_reg; + +// mux for start of packet detection +reg selected_input_eth_hdr_valid; +reg [47:0] selected_input_eth_dest_mac; +reg [47:0] selected_input_eth_src_mac; +reg [15:0] selected_input_eth_type; +always @* begin + case (select) +{%- for p in ports %} + {{w}}'d{{p}}: begin + selected_input_eth_hdr_valid = input_{{p}}_eth_hdr_valid; + selected_input_eth_dest_mac = input_{{p}}_eth_dest_mac; + selected_input_eth_src_mac = input_{{p}}_eth_src_mac; + selected_input_eth_type = input_{{p}}_eth_type; + end +{%- endfor %} + endcase +end + +// mux for incoming packet +reg [63:0] current_input_tdata; +reg [7:0] current_input_tkeep; +reg current_input_tvalid; +reg current_input_tready; +reg current_input_tlast; +reg current_input_tuser; +always @* begin + case (select_reg) +{%- for p in ports %} + {{w}}'d{{p}}: begin + current_input_tdata = input_{{p}}_eth_payload_tdata; + current_input_tkeep = input_{{p}}_eth_payload_tkeep; + current_input_tvalid = input_{{p}}_eth_payload_tvalid; + current_input_tready = input_{{p}}_eth_payload_tready; + current_input_tlast = input_{{p}}_eth_payload_tlast; + current_input_tuser = input_{{p}}_eth_payload_tuser; + end +{%- endfor %} + endcase +end + +always @* begin + select_next = select_reg; + frame_next = frame_reg; +{% for p in ports %} + input_{{p}}_eth_hdr_ready_next = input_{{p}}_eth_hdr_ready_reg & ~input_{{p}}_eth_hdr_valid; +{%- endfor %} +{% for p in ports %} + input_{{p}}_eth_payload_tready_next = 0; +{%- endfor %} + + output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready; + output_eth_dest_mac_next = output_eth_dest_mac_reg; + output_eth_src_mac_next = output_eth_src_mac_reg; + output_eth_type_next = output_eth_type_reg; + + if (frame_reg) begin + if (current_input_tvalid & current_input_tready) begin + // end of frame detection + frame_next = ~current_input_tlast; + end + end else if (selected_input_eth_hdr_valid) begin + // start of frame, grab select value + frame_next = 1; + select_next = select; + output_eth_hdr_valid_next = 1; + output_eth_dest_mac_next = selected_input_eth_dest_mac; + output_eth_src_mac_next = selected_input_eth_src_mac; + output_eth_type_next = selected_input_eth_type; + end + + // generate ready signal on selected port + case (select_next) +{%- for p in ports %} + {{w}}'d{{p}}: begin + input_{{p}}_eth_hdr_ready_next = input_{{p}}_eth_hdr_ready_next | (frame_next & ~frame_reg); + input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + end +{%- endfor %} + endcase + + // pass through selected packet data + output_eth_payload_tdata_int = current_input_tdata; + output_eth_payload_tkeep_int = current_input_tkeep; + output_eth_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg; + output_eth_payload_tlast_int = current_input_tlast; + output_eth_payload_tuser_int = current_input_tuser; +end + +always @(posedge clk or posedge rst) begin + if (rst) begin + select_reg <= 0; + frame_reg <= 0; +{%- for p in ports %} + input_{{p}}_eth_hdr_ready_reg <= 0; +{%- endfor %} +{%- for p in ports %} + input_{{p}}_eth_payload_tready_reg <= 0; +{%- endfor %} + output_eth_hdr_valid_reg <= 0; + output_eth_dest_mac_reg <= 0; + output_eth_src_mac_reg <= 0; + output_eth_type_reg <= 0; + end else begin + select_reg <= select_next; + frame_reg <= frame_next; +{%- for p in ports %} + input_{{p}}_eth_hdr_ready_reg <= input_{{p}}_eth_hdr_ready_next; +{%- endfor %} +{%- for p in ports %} + input_{{p}}_eth_payload_tready_reg <= input_{{p}}_eth_payload_tready_next; +{%- endfor %} + output_eth_hdr_valid_reg <= output_eth_hdr_valid_next; + output_eth_dest_mac_reg <= output_eth_dest_mac_next; + output_eth_src_mac_reg <= output_eth_src_mac_next; + output_eth_type_reg <= output_eth_type_next; + end +end + +// output datapath logic +reg [63:0] output_eth_payload_tdata_reg = 0; +reg [7:0] output_eth_payload_tkeep_reg = 0; +reg output_eth_payload_tvalid_reg = 0; +reg output_eth_payload_tlast_reg = 0; +reg output_eth_payload_tuser_reg = 0; + +reg [63:0] temp_eth_payload_tdata_reg = 0; +reg [7:0] temp_eth_payload_tkeep_reg = 0; +reg temp_eth_payload_tvalid_reg = 0; +reg temp_eth_payload_tlast_reg = 0; +reg temp_eth_payload_tuser_reg = 0; + +assign output_eth_payload_tdata = output_eth_payload_tdata_reg; +assign output_eth_payload_tkeep = output_eth_payload_tkeep_reg; +assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg; +assign output_eth_payload_tlast = output_eth_payload_tlast_reg; +assign output_eth_payload_tuser = output_eth_payload_tuser_reg; + +// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle +assign output_eth_payload_tready_int_early = output_eth_payload_tready | (~temp_eth_payload_tvalid_reg & ~output_eth_payload_tvalid_reg) | (~temp_eth_payload_tvalid_reg & ~output_eth_payload_tvalid_int); + +always @(posedge clk or posedge rst) begin + if (rst) begin + output_eth_payload_tdata_reg <= 0; + output_eth_payload_tkeep_reg <= 0; + output_eth_payload_tvalid_reg <= 0; + output_eth_payload_tlast_reg <= 0; + output_eth_payload_tuser_reg <= 0; + output_eth_payload_tready_int <= 0; + temp_eth_payload_tdata_reg <= 0; + temp_eth_payload_tkeep_reg <= 0; + temp_eth_payload_tvalid_reg <= 0; + temp_eth_payload_tlast_reg <= 0; + temp_eth_payload_tuser_reg <= 0; + end else begin + // transfer sink ready state to source + output_eth_payload_tready_int <= output_eth_payload_tready_int_early; + + if (output_eth_payload_tready_int) begin + // input is ready + if (output_eth_payload_tready | ~output_eth_payload_tvalid_reg) begin + // output is ready or currently not valid, transfer data to output + output_eth_payload_tdata_reg <= output_eth_payload_tdata_int; + output_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int; + output_eth_payload_tvalid_reg <= output_eth_payload_tvalid_int; + output_eth_payload_tlast_reg <= output_eth_payload_tlast_int; + output_eth_payload_tuser_reg <= output_eth_payload_tuser_int; + end else begin + // output is not ready, store input in temp + temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int; + temp_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int; + temp_eth_payload_tvalid_reg <= output_eth_payload_tvalid_int; + temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int; + temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int; + end + end else if (output_eth_payload_tready) begin + // input is not ready, but output is ready + output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg; + output_eth_payload_tkeep_reg <= temp_eth_payload_tkeep_reg; + output_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_reg; + output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg; + output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg; + temp_eth_payload_tdata_reg <= 0; + temp_eth_payload_tkeep_reg <= 0; + temp_eth_payload_tvalid_reg <= 0; + temp_eth_payload_tlast_reg <= 0; + temp_eth_payload_tuser_reg <= 0; + end + end +end + +endmodule + +""") + + out_file.write(t.render( + n=ports, + w=select_width, + name=name, + ports=range(ports) + )) + + print("Done") + +if __name__ == "__main__": + sys.exit(main()) + diff --git a/rtl/eth_mux_64_4.v b/rtl/eth_mux_64_4.v new file mode 100644 index 000000000..7f849c350 --- /dev/null +++ b/rtl/eth_mux_64_4.v @@ -0,0 +1,397 @@ +/* + +Copyright (c) 2014 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Ethernet 4 port multiplexer (64 bit datapath) + */ +module eth_mux_64_4 +( + input wire clk, + input wire rst, + + /* + * Ethernet frame inputs + */ + input wire input_0_eth_hdr_valid, + output wire input_0_eth_hdr_ready, + input wire [47:0] input_0_eth_dest_mac, + input wire [47:0] input_0_eth_src_mac, + input wire [15:0] input_0_eth_type, + input wire [63:0] input_0_eth_payload_tdata, + input wire [7:0] input_0_eth_payload_tkeep, + input wire input_0_eth_payload_tvalid, + output wire input_0_eth_payload_tready, + input wire input_0_eth_payload_tlast, + input wire input_0_eth_payload_tuser, + + input wire input_1_eth_hdr_valid, + output wire input_1_eth_hdr_ready, + input wire [47:0] input_1_eth_dest_mac, + input wire [47:0] input_1_eth_src_mac, + input wire [15:0] input_1_eth_type, + input wire [63:0] input_1_eth_payload_tdata, + input wire [7:0] input_1_eth_payload_tkeep, + input wire input_1_eth_payload_tvalid, + output wire input_1_eth_payload_tready, + input wire input_1_eth_payload_tlast, + input wire input_1_eth_payload_tuser, + + input wire input_2_eth_hdr_valid, + output wire input_2_eth_hdr_ready, + input wire [47:0] input_2_eth_dest_mac, + input wire [47:0] input_2_eth_src_mac, + input wire [15:0] input_2_eth_type, + input wire [63:0] input_2_eth_payload_tdata, + input wire [7:0] input_2_eth_payload_tkeep, + input wire input_2_eth_payload_tvalid, + output wire input_2_eth_payload_tready, + input wire input_2_eth_payload_tlast, + input wire input_2_eth_payload_tuser, + + input wire input_3_eth_hdr_valid, + output wire input_3_eth_hdr_ready, + input wire [47:0] input_3_eth_dest_mac, + input wire [47:0] input_3_eth_src_mac, + input wire [15:0] input_3_eth_type, + input wire [63:0] input_3_eth_payload_tdata, + input wire [7:0] input_3_eth_payload_tkeep, + input wire input_3_eth_payload_tvalid, + output wire input_3_eth_payload_tready, + input wire input_3_eth_payload_tlast, + input wire input_3_eth_payload_tuser, + + /* + * Ethernet frame output + */ + output wire output_eth_hdr_valid, + input wire output_eth_hdr_ready, + output wire [47:0] output_eth_dest_mac, + output wire [47:0] output_eth_src_mac, + output wire [15:0] output_eth_type, + output wire [63:0] output_eth_payload_tdata, + output wire [7:0] output_eth_payload_tkeep, + output wire output_eth_payload_tvalid, + input wire output_eth_payload_tready, + output wire output_eth_payload_tlast, + output wire output_eth_payload_tuser, + + /* + * Control + */ + input wire [1:0] select +); + +reg [1:0] select_reg = 0, select_next; +reg frame_reg = 0, frame_next; + +reg input_0_eth_hdr_ready_reg = 0, input_0_eth_hdr_ready_next; +reg input_1_eth_hdr_ready_reg = 0, input_1_eth_hdr_ready_next; +reg input_2_eth_hdr_ready_reg = 0, input_2_eth_hdr_ready_next; +reg input_3_eth_hdr_ready_reg = 0, input_3_eth_hdr_ready_next; + +reg input_0_eth_payload_tready_reg = 0, input_0_eth_payload_tready_next; +reg input_1_eth_payload_tready_reg = 0, input_1_eth_payload_tready_next; +reg input_2_eth_payload_tready_reg = 0, input_2_eth_payload_tready_next; +reg input_3_eth_payload_tready_reg = 0, input_3_eth_payload_tready_next; + +reg output_eth_hdr_valid_reg = 0, output_eth_hdr_valid_next; +reg [47:0] output_eth_dest_mac_reg = 0, output_eth_dest_mac_next; +reg [47:0] output_eth_src_mac_reg = 0, output_eth_src_mac_next; +reg [15:0] output_eth_type_reg = 0, output_eth_type_next; + +// internal datapath +reg [63:0] output_eth_payload_tdata_int; +reg [7:0] output_eth_payload_tkeep_int; +reg output_eth_payload_tvalid_int; +reg output_eth_payload_tready_int = 0; +reg output_eth_payload_tlast_int; +reg output_eth_payload_tuser_int; +wire output_eth_payload_tready_int_early; + +assign input_0_eth_hdr_ready = input_0_eth_hdr_ready_reg; +assign input_1_eth_hdr_ready = input_1_eth_hdr_ready_reg; +assign input_2_eth_hdr_ready = input_2_eth_hdr_ready_reg; +assign input_3_eth_hdr_ready = input_3_eth_hdr_ready_reg; + +assign input_0_eth_payload_tready = input_0_eth_payload_tready_reg; +assign input_1_eth_payload_tready = input_1_eth_payload_tready_reg; +assign input_2_eth_payload_tready = input_2_eth_payload_tready_reg; +assign input_3_eth_payload_tready = input_3_eth_payload_tready_reg; + +assign output_eth_hdr_valid = output_eth_hdr_valid_reg; +assign output_eth_dest_mac = output_eth_dest_mac_reg; +assign output_eth_src_mac = output_eth_src_mac_reg; +assign output_eth_type = output_eth_type_reg; + +// mux for start of packet detection +reg selected_input_eth_hdr_valid; +reg [47:0] selected_input_eth_dest_mac; +reg [47:0] selected_input_eth_src_mac; +reg [15:0] selected_input_eth_type; +always @* begin + case (select) + 2'd0: begin + selected_input_eth_hdr_valid = input_0_eth_hdr_valid; + selected_input_eth_dest_mac = input_0_eth_dest_mac; + selected_input_eth_src_mac = input_0_eth_src_mac; + selected_input_eth_type = input_0_eth_type; + end + 2'd1: begin + selected_input_eth_hdr_valid = input_1_eth_hdr_valid; + selected_input_eth_dest_mac = input_1_eth_dest_mac; + selected_input_eth_src_mac = input_1_eth_src_mac; + selected_input_eth_type = input_1_eth_type; + end + 2'd2: begin + selected_input_eth_hdr_valid = input_2_eth_hdr_valid; + selected_input_eth_dest_mac = input_2_eth_dest_mac; + selected_input_eth_src_mac = input_2_eth_src_mac; + selected_input_eth_type = input_2_eth_type; + end + 2'd3: begin + selected_input_eth_hdr_valid = input_3_eth_hdr_valid; + selected_input_eth_dest_mac = input_3_eth_dest_mac; + selected_input_eth_src_mac = input_3_eth_src_mac; + selected_input_eth_type = input_3_eth_type; + end + endcase +end + +// mux for incoming packet +reg [63:0] current_input_tdata; +reg [7:0] current_input_tkeep; +reg current_input_tvalid; +reg current_input_tready; +reg current_input_tlast; +reg current_input_tuser; +always @* begin + case (select_reg) + 2'd0: begin + current_input_tdata = input_0_eth_payload_tdata; + current_input_tkeep = input_0_eth_payload_tkeep; + current_input_tvalid = input_0_eth_payload_tvalid; + current_input_tready = input_0_eth_payload_tready; + current_input_tlast = input_0_eth_payload_tlast; + current_input_tuser = input_0_eth_payload_tuser; + end + 2'd1: begin + current_input_tdata = input_1_eth_payload_tdata; + current_input_tkeep = input_1_eth_payload_tkeep; + current_input_tvalid = input_1_eth_payload_tvalid; + current_input_tready = input_1_eth_payload_tready; + current_input_tlast = input_1_eth_payload_tlast; + current_input_tuser = input_1_eth_payload_tuser; + end + 2'd2: begin + current_input_tdata = input_2_eth_payload_tdata; + current_input_tkeep = input_2_eth_payload_tkeep; + current_input_tvalid = input_2_eth_payload_tvalid; + current_input_tready = input_2_eth_payload_tready; + current_input_tlast = input_2_eth_payload_tlast; + current_input_tuser = input_2_eth_payload_tuser; + end + 2'd3: begin + current_input_tdata = input_3_eth_payload_tdata; + current_input_tkeep = input_3_eth_payload_tkeep; + current_input_tvalid = input_3_eth_payload_tvalid; + current_input_tready = input_3_eth_payload_tready; + current_input_tlast = input_3_eth_payload_tlast; + current_input_tuser = input_3_eth_payload_tuser; + end + endcase +end + +always @* begin + select_next = select_reg; + frame_next = frame_reg; + + input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_reg & ~input_0_eth_hdr_valid; + input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_reg & ~input_1_eth_hdr_valid; + input_2_eth_hdr_ready_next = input_2_eth_hdr_ready_reg & ~input_2_eth_hdr_valid; + input_3_eth_hdr_ready_next = input_3_eth_hdr_ready_reg & ~input_3_eth_hdr_valid; + + input_0_eth_payload_tready_next = 0; + input_1_eth_payload_tready_next = 0; + input_2_eth_payload_tready_next = 0; + input_3_eth_payload_tready_next = 0; + + output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready; + output_eth_dest_mac_next = output_eth_dest_mac_reg; + output_eth_src_mac_next = output_eth_src_mac_reg; + output_eth_type_next = output_eth_type_reg; + + if (frame_reg) begin + if (current_input_tvalid & current_input_tready) begin + // end of frame detection + frame_next = ~current_input_tlast; + end + end else if (selected_input_eth_hdr_valid) begin + // start of frame, grab select value + frame_next = 1; + select_next = select; + output_eth_hdr_valid_next = 1; + output_eth_dest_mac_next = selected_input_eth_dest_mac; + output_eth_src_mac_next = selected_input_eth_src_mac; + output_eth_type_next = selected_input_eth_type; + end + + // generate ready signal on selected port + case (select_next) + 2'd0: begin + input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_next | (frame_next & ~frame_reg); + input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + end + 2'd1: begin + input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_next | (frame_next & ~frame_reg); + input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + end + 2'd2: begin + input_2_eth_hdr_ready_next = input_2_eth_hdr_ready_next | (frame_next & ~frame_reg); + input_2_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + end + 2'd3: begin + input_3_eth_hdr_ready_next = input_3_eth_hdr_ready_next | (frame_next & ~frame_reg); + input_3_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + end + endcase + + // pass through selected packet data + output_eth_payload_tdata_int = current_input_tdata; + output_eth_payload_tkeep_int = current_input_tkeep; + output_eth_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg; + output_eth_payload_tlast_int = current_input_tlast; + output_eth_payload_tuser_int = current_input_tuser; +end + +always @(posedge clk or posedge rst) begin + if (rst) begin + select_reg <= 0; + frame_reg <= 0; + input_0_eth_hdr_ready_reg <= 0; + input_1_eth_hdr_ready_reg <= 0; + input_2_eth_hdr_ready_reg <= 0; + input_3_eth_hdr_ready_reg <= 0; + input_0_eth_payload_tready_reg <= 0; + input_1_eth_payload_tready_reg <= 0; + input_2_eth_payload_tready_reg <= 0; + input_3_eth_payload_tready_reg <= 0; + output_eth_hdr_valid_reg <= 0; + output_eth_dest_mac_reg <= 0; + output_eth_src_mac_reg <= 0; + output_eth_type_reg <= 0; + end else begin + select_reg <= select_next; + frame_reg <= frame_next; + input_0_eth_hdr_ready_reg <= input_0_eth_hdr_ready_next; + input_1_eth_hdr_ready_reg <= input_1_eth_hdr_ready_next; + input_2_eth_hdr_ready_reg <= input_2_eth_hdr_ready_next; + input_3_eth_hdr_ready_reg <= input_3_eth_hdr_ready_next; + input_0_eth_payload_tready_reg <= input_0_eth_payload_tready_next; + input_1_eth_payload_tready_reg <= input_1_eth_payload_tready_next; + input_2_eth_payload_tready_reg <= input_2_eth_payload_tready_next; + input_3_eth_payload_tready_reg <= input_3_eth_payload_tready_next; + output_eth_hdr_valid_reg <= output_eth_hdr_valid_next; + output_eth_dest_mac_reg <= output_eth_dest_mac_next; + output_eth_src_mac_reg <= output_eth_src_mac_next; + output_eth_type_reg <= output_eth_type_next; + end +end + +// output datapath logic +reg [63:0] output_eth_payload_tdata_reg = 0; +reg [7:0] output_eth_payload_tkeep_reg = 0; +reg output_eth_payload_tvalid_reg = 0; +reg output_eth_payload_tlast_reg = 0; +reg output_eth_payload_tuser_reg = 0; + +reg [63:0] temp_eth_payload_tdata_reg = 0; +reg [7:0] temp_eth_payload_tkeep_reg = 0; +reg temp_eth_payload_tvalid_reg = 0; +reg temp_eth_payload_tlast_reg = 0; +reg temp_eth_payload_tuser_reg = 0; + +assign output_eth_payload_tdata = output_eth_payload_tdata_reg; +assign output_eth_payload_tkeep = output_eth_payload_tkeep_reg; +assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg; +assign output_eth_payload_tlast = output_eth_payload_tlast_reg; +assign output_eth_payload_tuser = output_eth_payload_tuser_reg; + +// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle +assign output_eth_payload_tready_int_early = output_eth_payload_tready | (~temp_eth_payload_tvalid_reg & ~output_eth_payload_tvalid_reg) | (~temp_eth_payload_tvalid_reg & ~output_eth_payload_tvalid_int); + +always @(posedge clk or posedge rst) begin + if (rst) begin + output_eth_payload_tdata_reg <= 0; + output_eth_payload_tkeep_reg <= 0; + output_eth_payload_tvalid_reg <= 0; + output_eth_payload_tlast_reg <= 0; + output_eth_payload_tuser_reg <= 0; + output_eth_payload_tready_int <= 0; + temp_eth_payload_tdata_reg <= 0; + temp_eth_payload_tkeep_reg <= 0; + temp_eth_payload_tvalid_reg <= 0; + temp_eth_payload_tlast_reg <= 0; + temp_eth_payload_tuser_reg <= 0; + end else begin + // transfer sink ready state to source + output_eth_payload_tready_int <= output_eth_payload_tready_int_early; + + if (output_eth_payload_tready_int) begin + // input is ready + if (output_eth_payload_tready | ~output_eth_payload_tvalid_reg) begin + // output is ready or currently not valid, transfer data to output + output_eth_payload_tdata_reg <= output_eth_payload_tdata_int; + output_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int; + output_eth_payload_tvalid_reg <= output_eth_payload_tvalid_int; + output_eth_payload_tlast_reg <= output_eth_payload_tlast_int; + output_eth_payload_tuser_reg <= output_eth_payload_tuser_int; + end else begin + // output is not ready, store input in temp + temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int; + temp_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int; + temp_eth_payload_tvalid_reg <= output_eth_payload_tvalid_int; + temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int; + temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int; + end + end else if (output_eth_payload_tready) begin + // input is not ready, but output is ready + output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg; + output_eth_payload_tkeep_reg <= temp_eth_payload_tkeep_reg; + output_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_reg; + output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg; + output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg; + temp_eth_payload_tdata_reg <= 0; + temp_eth_payload_tkeep_reg <= 0; + temp_eth_payload_tvalid_reg <= 0; + temp_eth_payload_tlast_reg <= 0; + temp_eth_payload_tuser_reg <= 0; + end + end +end + +endmodule diff --git a/tb/test_eth_mux_4.py b/tb/test_eth_mux_4.py new file mode 100755 index 000000000..9e468ace6 --- /dev/null +++ b/tb/test_eth_mux_4.py @@ -0,0 +1,648 @@ +#!/usr/bin/env python2 +""" + +Copyright (c) 2014 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +from myhdl import * +import os +from Queue import Queue + +import eth_ep + +module = 'eth_mux_4' + +srcs = [] + +srcs.append("../rtl/%s.v" % module) +srcs.append("test_%s.v" % module) + +src = ' '.join(srcs) + +build_cmd = "iverilog -o test_%s.vvp %s" % (module, src) + +def dut_eth_mux_4(clk, + rst, + current_test, + + input_0_eth_hdr_valid, + input_0_eth_hdr_ready, + input_0_eth_dest_mac, + input_0_eth_src_mac, + input_0_eth_type, + input_0_eth_payload_tdata, + input_0_eth_payload_tvalid, + input_0_eth_payload_tready, + input_0_eth_payload_tlast, + input_0_eth_payload_tuser, + input_1_eth_hdr_valid, + input_1_eth_hdr_ready, + input_1_eth_dest_mac, + input_1_eth_src_mac, + input_1_eth_type, + input_1_eth_payload_tdata, + input_1_eth_payload_tvalid, + input_1_eth_payload_tready, + input_1_eth_payload_tlast, + input_1_eth_payload_tuser, + input_2_eth_hdr_valid, + input_2_eth_hdr_ready, + input_2_eth_dest_mac, + input_2_eth_src_mac, + input_2_eth_type, + input_2_eth_payload_tdata, + input_2_eth_payload_tvalid, + input_2_eth_payload_tready, + input_2_eth_payload_tlast, + input_2_eth_payload_tuser, + input_3_eth_hdr_valid, + input_3_eth_hdr_ready, + input_3_eth_dest_mac, + input_3_eth_src_mac, + input_3_eth_type, + input_3_eth_payload_tdata, + input_3_eth_payload_tvalid, + input_3_eth_payload_tready, + input_3_eth_payload_tlast, + input_3_eth_payload_tuser, + + output_eth_hdr_valid, + output_eth_hdr_ready, + output_eth_dest_mac, + output_eth_src_mac, + output_eth_type, + output_eth_payload_tdata, + output_eth_payload_tvalid, + output_eth_payload_tready, + output_eth_payload_tlast, + output_eth_payload_tuser, + + select): + + if os.system(build_cmd): + raise Exception("Error running build command") + return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module, + clk=clk, + rst=rst, + current_test=current_test, + + input_0_eth_hdr_valid=input_0_eth_hdr_valid, + input_0_eth_hdr_ready=input_0_eth_hdr_ready, + input_0_eth_dest_mac=input_0_eth_dest_mac, + input_0_eth_src_mac=input_0_eth_src_mac, + input_0_eth_type=input_0_eth_type, + input_0_eth_payload_tdata=input_0_eth_payload_tdata, + input_0_eth_payload_tvalid=input_0_eth_payload_tvalid, + input_0_eth_payload_tready=input_0_eth_payload_tready, + input_0_eth_payload_tlast=input_0_eth_payload_tlast, + input_0_eth_payload_tuser=input_0_eth_payload_tuser, + input_1_eth_hdr_valid=input_1_eth_hdr_valid, + input_1_eth_hdr_ready=input_1_eth_hdr_ready, + input_1_eth_dest_mac=input_1_eth_dest_mac, + input_1_eth_src_mac=input_1_eth_src_mac, + input_1_eth_type=input_1_eth_type, + input_1_eth_payload_tdata=input_1_eth_payload_tdata, + input_1_eth_payload_tvalid=input_1_eth_payload_tvalid, + input_1_eth_payload_tready=input_1_eth_payload_tready, + input_1_eth_payload_tlast=input_1_eth_payload_tlast, + input_1_eth_payload_tuser=input_1_eth_payload_tuser, + input_2_eth_hdr_valid=input_2_eth_hdr_valid, + input_2_eth_hdr_ready=input_2_eth_hdr_ready, + input_2_eth_dest_mac=input_2_eth_dest_mac, + input_2_eth_src_mac=input_2_eth_src_mac, + input_2_eth_type=input_2_eth_type, + input_2_eth_payload_tdata=input_2_eth_payload_tdata, + input_2_eth_payload_tvalid=input_2_eth_payload_tvalid, + input_2_eth_payload_tready=input_2_eth_payload_tready, + input_2_eth_payload_tlast=input_2_eth_payload_tlast, + input_2_eth_payload_tuser=input_2_eth_payload_tuser, + input_3_eth_hdr_valid=input_3_eth_hdr_valid, + input_3_eth_hdr_ready=input_3_eth_hdr_ready, + input_3_eth_dest_mac=input_3_eth_dest_mac, + input_3_eth_src_mac=input_3_eth_src_mac, + input_3_eth_type=input_3_eth_type, + input_3_eth_payload_tdata=input_3_eth_payload_tdata, + input_3_eth_payload_tvalid=input_3_eth_payload_tvalid, + input_3_eth_payload_tready=input_3_eth_payload_tready, + input_3_eth_payload_tlast=input_3_eth_payload_tlast, + input_3_eth_payload_tuser=input_3_eth_payload_tuser, + + output_eth_hdr_valid=output_eth_hdr_valid, + output_eth_hdr_ready=output_eth_hdr_ready, + output_eth_dest_mac=output_eth_dest_mac, + output_eth_src_mac=output_eth_src_mac, + output_eth_type=output_eth_type, + output_eth_payload_tdata=output_eth_payload_tdata, + output_eth_payload_tvalid=output_eth_payload_tvalid, + output_eth_payload_tready=output_eth_payload_tready, + output_eth_payload_tlast=output_eth_payload_tlast, + output_eth_payload_tuser=output_eth_payload_tuser, + + select=select) + +def bench(): + + # Inputs + clk = Signal(bool(0)) + rst = Signal(bool(0)) + current_test = Signal(intbv(0)[8:]) + + input_0_eth_hdr_valid = Signal(bool(0)) + input_0_eth_dest_mac = Signal(intbv(0)[48:]) + input_0_eth_src_mac = Signal(intbv(0)[48:]) + input_0_eth_type = Signal(intbv(0)[16:]) + input_0_eth_payload_tdata = Signal(intbv(0)[8:]) + input_0_eth_payload_tvalid = Signal(bool(0)) + input_0_eth_payload_tlast = Signal(bool(0)) + input_0_eth_payload_tuser = Signal(bool(0)) + input_1_eth_hdr_valid = Signal(bool(0)) + input_1_eth_dest_mac = Signal(intbv(0)[48:]) + input_1_eth_src_mac = Signal(intbv(0)[48:]) + input_1_eth_type = Signal(intbv(0)[16:]) + input_1_eth_payload_tdata = Signal(intbv(0)[8:]) + input_1_eth_payload_tvalid = Signal(bool(0)) + input_1_eth_payload_tlast = Signal(bool(0)) + input_1_eth_payload_tuser = Signal(bool(0)) + input_2_eth_hdr_valid = Signal(bool(0)) + input_2_eth_dest_mac = Signal(intbv(0)[48:]) + input_2_eth_src_mac = Signal(intbv(0)[48:]) + input_2_eth_type = Signal(intbv(0)[16:]) + input_2_eth_payload_tdata = Signal(intbv(0)[8:]) + input_2_eth_payload_tvalid = Signal(bool(0)) + input_2_eth_payload_tlast = Signal(bool(0)) + input_2_eth_payload_tuser = Signal(bool(0)) + input_3_eth_hdr_valid = Signal(bool(0)) + input_3_eth_dest_mac = Signal(intbv(0)[48:]) + input_3_eth_src_mac = Signal(intbv(0)[48:]) + input_3_eth_type = Signal(intbv(0)[16:]) + input_3_eth_payload_tdata = Signal(intbv(0)[8:]) + input_3_eth_payload_tvalid = Signal(bool(0)) + input_3_eth_payload_tlast = Signal(bool(0)) + input_3_eth_payload_tuser = Signal(bool(0)) + + output_eth_payload_tready = Signal(bool(0)) + output_eth_hdr_ready = Signal(bool(0)) + + select = Signal(intbv(0)[2:]) + + # Outputs + input_0_eth_hdr_ready = Signal(bool(0)) + input_0_eth_payload_tready = Signal(bool(0)) + input_1_eth_hdr_ready = Signal(bool(0)) + input_1_eth_payload_tready = Signal(bool(0)) + input_2_eth_hdr_ready = Signal(bool(0)) + input_2_eth_payload_tready = Signal(bool(0)) + input_3_eth_hdr_ready = Signal(bool(0)) + input_3_eth_payload_tready = Signal(bool(0)) + + output_eth_hdr_valid = Signal(bool(0)) + output_eth_dest_mac = Signal(intbv(0)[48:]) + output_eth_src_mac = Signal(intbv(0)[48:]) + output_eth_type = Signal(intbv(0)[16:]) + output_eth_payload_tdata = Signal(intbv(0)[8:]) + output_eth_payload_tvalid = Signal(bool(0)) + output_eth_payload_tlast = Signal(bool(0)) + output_eth_payload_tuser = Signal(bool(0)) + + # sources and sinks + source_0_queue = Queue() + source_0_pause = Signal(bool(0)) + source_1_queue = Queue() + source_1_pause = Signal(bool(0)) + source_2_queue = Queue() + source_2_pause = Signal(bool(0)) + source_3_queue = Queue() + source_3_pause = Signal(bool(0)) + sink_queue = Queue() + sink_pause = Signal(bool(0)) + + source_0 = eth_ep.EthFrameSource(clk, + rst, + eth_hdr_ready=input_0_eth_hdr_ready, + eth_hdr_valid=input_0_eth_hdr_valid, + eth_dest_mac=input_0_eth_dest_mac, + eth_src_mac=input_0_eth_src_mac, + eth_type=input_0_eth_type, + eth_payload_tdata=input_0_eth_payload_tdata, + eth_payload_tvalid=input_0_eth_payload_tvalid, + eth_payload_tready=input_0_eth_payload_tready, + eth_payload_tlast=input_0_eth_payload_tlast, + eth_payload_tuser=input_0_eth_payload_tuser, + fifo=source_0_queue, + pause=source_0_pause, + name='source0') + + source_1 = eth_ep.EthFrameSource(clk, + rst, + eth_hdr_ready=input_1_eth_hdr_ready, + eth_hdr_valid=input_1_eth_hdr_valid, + eth_dest_mac=input_1_eth_dest_mac, + eth_src_mac=input_1_eth_src_mac, + eth_type=input_1_eth_type, + eth_payload_tdata=input_1_eth_payload_tdata, + eth_payload_tvalid=input_1_eth_payload_tvalid, + eth_payload_tready=input_1_eth_payload_tready, + eth_payload_tlast=input_1_eth_payload_tlast, + eth_payload_tuser=input_1_eth_payload_tuser, + fifo=source_1_queue, + pause=source_1_pause, + name='source1') + + source_2 = eth_ep.EthFrameSource(clk, + rst, + eth_hdr_ready=input_2_eth_hdr_ready, + eth_hdr_valid=input_2_eth_hdr_valid, + eth_dest_mac=input_2_eth_dest_mac, + eth_src_mac=input_2_eth_src_mac, + eth_type=input_2_eth_type, + eth_payload_tdata=input_2_eth_payload_tdata, + eth_payload_tvalid=input_2_eth_payload_tvalid, + eth_payload_tready=input_2_eth_payload_tready, + eth_payload_tlast=input_2_eth_payload_tlast, + eth_payload_tuser=input_2_eth_payload_tuser, + fifo=source_2_queue, + pause=source_2_pause, + name='source2') + + source_3 = eth_ep.EthFrameSource(clk, + rst, + eth_hdr_ready=input_3_eth_hdr_ready, + eth_hdr_valid=input_3_eth_hdr_valid, + eth_dest_mac=input_3_eth_dest_mac, + eth_src_mac=input_3_eth_src_mac, + eth_type=input_3_eth_type, + eth_payload_tdata=input_3_eth_payload_tdata, + eth_payload_tvalid=input_3_eth_payload_tvalid, + eth_payload_tready=input_3_eth_payload_tready, + eth_payload_tlast=input_3_eth_payload_tlast, + eth_payload_tuser=input_3_eth_payload_tuser, + fifo=source_3_queue, + pause=source_3_pause, + name='source3') + + sink = eth_ep.EthFrameSink(clk, + rst, + eth_hdr_ready=output_eth_hdr_ready, + eth_hdr_valid=output_eth_hdr_valid, + eth_dest_mac=output_eth_dest_mac, + eth_src_mac=output_eth_src_mac, + eth_type=output_eth_type, + eth_payload_tdata=output_eth_payload_tdata, + eth_payload_tvalid=output_eth_payload_tvalid, + eth_payload_tready=output_eth_payload_tready, + eth_payload_tlast=output_eth_payload_tlast, + eth_payload_tuser=output_eth_payload_tuser, + fifo=sink_queue, + pause=sink_pause, + name='sink') + + # DUT + dut = dut_eth_mux_4(clk, + rst, + current_test, + + input_0_eth_hdr_valid, + input_0_eth_hdr_ready, + input_0_eth_dest_mac, + input_0_eth_src_mac, + input_0_eth_type, + input_0_eth_payload_tdata, + input_0_eth_payload_tvalid, + input_0_eth_payload_tready, + input_0_eth_payload_tlast, + input_0_eth_payload_tuser, + input_1_eth_hdr_valid, + input_1_eth_hdr_ready, + input_1_eth_dest_mac, + input_1_eth_src_mac, + input_1_eth_type, + input_1_eth_payload_tdata, + input_1_eth_payload_tvalid, + input_1_eth_payload_tready, + input_1_eth_payload_tlast, + input_1_eth_payload_tuser, + input_2_eth_hdr_valid, + input_2_eth_hdr_ready, + input_2_eth_dest_mac, + input_2_eth_src_mac, + input_2_eth_type, + input_2_eth_payload_tdata, + input_2_eth_payload_tvalid, + input_2_eth_payload_tready, + input_2_eth_payload_tlast, + input_2_eth_payload_tuser, + input_3_eth_hdr_valid, + input_3_eth_hdr_ready, + input_3_eth_dest_mac, + input_3_eth_src_mac, + input_3_eth_type, + input_3_eth_payload_tdata, + input_3_eth_payload_tvalid, + input_3_eth_payload_tready, + input_3_eth_payload_tlast, + input_3_eth_payload_tuser, + + output_eth_hdr_valid, + output_eth_hdr_ready, + output_eth_dest_mac, + output_eth_src_mac, + output_eth_type, + output_eth_payload_tdata, + output_eth_payload_tvalid, + output_eth_payload_tready, + output_eth_payload_tlast, + output_eth_payload_tuser, + + select) + + @always(delay(4)) + def clkgen(): + clk.next = not clk + + @instance + def check(): + yield delay(100) + yield clk.posedge + rst.next = 1 + yield clk.posedge + rst.next = 0 + yield clk.posedge + yield delay(100) + yield clk.posedge + + yield clk.posedge + + yield clk.posedge + print("test 1: select port 0") + current_test.next = 1 + + select.next = 0 + + test_frame = eth_ep.EthFrame() + test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame.eth_src_mac = 0x5A5152535455 + test_frame.eth_type = 0x8000 + test_frame.payload = bytearray(range(32)) + + source_0_queue.put(test_frame) + yield clk.posedge + yield clk.posedge + + while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + yield clk.posedge + yield clk.posedge + yield clk.posedge + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame + + yield delay(100) + + yield clk.posedge + print("test 2: select port 1") + current_test.next = 2 + + select.next = 1 + + test_frame = eth_ep.EthFrame() + test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame.eth_src_mac = 0x5A5152535455 + test_frame.eth_type = 0x8000 + test_frame.payload = bytearray(range(32)) + + source_1_queue.put(test_frame) + yield clk.posedge + yield clk.posedge + + while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + yield clk.posedge + yield clk.posedge + yield clk.posedge + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame + + yield delay(100) + + yield clk.posedge + print("test 3: back-to-back packets, same port") + current_test.next = 3 + + select.next = 0 + + test_frame1 = eth_ep.EthFrame() + test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame1.eth_src_mac = 0x5A5152535455 + test_frame1.eth_type = 0x8000 + test_frame1.payload = bytearray(range(32)) + test_frame2 = eth_ep.EthFrame() + test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame2.eth_src_mac = 0x5A5152535455 + test_frame2.eth_type = 0x8000 + test_frame2.payload = bytearray(range(32)) + + source_0_queue.put(test_frame1) + source_0_queue.put(test_frame2) + yield clk.posedge + yield clk.posedge + + while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + yield clk.posedge + yield clk.posedge + yield clk.posedge + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame1 + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + + yield delay(100) + + yield clk.posedge + print("test 4: back-to-back packets, different ports") + current_test.next = 4 + + select.next = 1 + + test_frame1 = eth_ep.EthFrame() + test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame1.eth_src_mac = 0x5A5152535455 + test_frame1.eth_type = 0x8000 + test_frame1.payload = bytearray(range(32)) + test_frame2 = eth_ep.EthFrame() + test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame2.eth_src_mac = 0x5A5152535455 + test_frame2.eth_type = 0x8000 + test_frame2.payload = bytearray(range(32)) + + source_1_queue.put(test_frame1) + source_2_queue.put(test_frame2) + yield clk.posedge + yield clk.posedge + + while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + yield clk.posedge + select.next = 2 + yield clk.posedge + yield clk.posedge + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame1 + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + + yield delay(100) + + yield clk.posedge + print("test 5: alterate pause source") + current_test.next = 5 + + select.next = 1 + + test_frame1 = eth_ep.EthFrame() + test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame1.eth_src_mac = 0x5A5152535455 + test_frame1.eth_type = 0x8000 + test_frame1.payload = bytearray(range(32)) + test_frame2 = eth_ep.EthFrame() + test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame2.eth_src_mac = 0x5A5152535455 + test_frame2.eth_type = 0x8000 + test_frame2.payload = bytearray(range(32)) + + source_1_queue.put(test_frame1) + source_2_queue.put(test_frame2) + yield clk.posedge + yield clk.posedge + + while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + source_0_pause.next = True + source_1_pause.next = True + source_2_pause.next = True + source_3_pause.next = True + yield clk.posedge + yield clk.posedge + yield clk.posedge + source_0_pause.next = False + source_1_pause.next = False + source_2_pause.next = False + source_3_pause.next = False + yield clk.posedge + select.next = 2 + yield clk.posedge + yield clk.posedge + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame1 + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + + yield delay(100) + + yield clk.posedge + print("test 6: alterate pause sink") + current_test.next = 6 + + select.next = 1 + + test_frame1 = eth_ep.EthFrame() + test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame1.eth_src_mac = 0x5A5152535455 + test_frame1.eth_type = 0x8000 + test_frame1.payload = bytearray(range(32)) + test_frame2 = eth_ep.EthFrame() + test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame2.eth_src_mac = 0x5A5152535455 + test_frame2.eth_type = 0x8000 + test_frame2.payload = bytearray(range(32)) + + source_1_queue.put(test_frame1) + source_2_queue.put(test_frame2) + yield clk.posedge + yield clk.posedge + + while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + sink_pause.next = True + yield clk.posedge + yield clk.posedge + yield clk.posedge + sink_pause.next = False + yield clk.posedge + select.next = 2 + yield clk.posedge + yield clk.posedge + yield clk.posedge + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame1 + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + + yield delay(100) + + raise StopSimulation + + return dut, source_0, source_1, source_2, source_3, sink, clkgen, check + +def test_bench(): + os.chdir(os.path.dirname(os.path.abspath(__file__))) + sim = Simulation(bench()) + sim.run() + +if __name__ == '__main__': + print("Running test...") + test_bench() + diff --git a/tb/test_eth_mux_4.v b/tb/test_eth_mux_4.v new file mode 100644 index 000000000..7db7bdc39 --- /dev/null +++ b/tb/test_eth_mux_4.v @@ -0,0 +1,215 @@ +/* + +Copyright (c) 2014 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1 ns / 1 ps + +module test_eth_mux_4; + +// Inputs +reg clk = 0; +reg rst = 0; +reg [7:0] current_test = 0; + +reg input_0_eth_hdr_valid = 0; +reg [47:0] input_0_eth_dest_mac = 0; +reg [47:0] input_0_eth_src_mac = 0; +reg [15:0] input_0_eth_type = 0; +reg [7:0] input_0_eth_payload_tdata = 0; +reg input_0_eth_payload_tvalid = 0; +reg input_0_eth_payload_tlast = 0; +reg input_0_eth_payload_tuser = 0; +reg input_1_eth_hdr_valid = 0; +reg [47:0] input_1_eth_dest_mac = 0; +reg [47:0] input_1_eth_src_mac = 0; +reg [15:0] input_1_eth_type = 0; +reg [7:0] input_1_eth_payload_tdata = 0; +reg input_1_eth_payload_tvalid = 0; +reg input_1_eth_payload_tlast = 0; +reg input_1_eth_payload_tuser = 0; +reg input_2_eth_hdr_valid = 0; +reg [47:0] input_2_eth_dest_mac = 0; +reg [47:0] input_2_eth_src_mac = 0; +reg [15:0] input_2_eth_type = 0; +reg [7:0] input_2_eth_payload_tdata = 0; +reg input_2_eth_payload_tvalid = 0; +reg input_2_eth_payload_tlast = 0; +reg input_2_eth_payload_tuser = 0; +reg input_3_eth_hdr_valid = 0; +reg [47:0] input_3_eth_dest_mac = 0; +reg [47:0] input_3_eth_src_mac = 0; +reg [15:0] input_3_eth_type = 0; +reg [7:0] input_3_eth_payload_tdata = 0; +reg input_3_eth_payload_tvalid = 0; +reg input_3_eth_payload_tlast = 0; +reg input_3_eth_payload_tuser = 0; + +reg output_eth_hdr_ready = 0; +reg output_eth_payload_tready = 0; + +reg [1:0] select = 0; + +// Outputs +wire input_0_eth_payload_tready; +wire input_0_eth_hdr_ready; +wire input_1_eth_payload_tready; +wire input_1_eth_hdr_ready; +wire input_2_eth_payload_tready; +wire input_2_eth_hdr_ready; +wire input_3_eth_payload_tready; +wire input_3_eth_hdr_ready; + +wire output_eth_hdr_valid; +wire [47:0] output_eth_dest_mac; +wire [47:0] output_eth_src_mac; +wire [15:0] output_eth_type; +wire [7:0] output_eth_payload_tdata; +wire output_eth_payload_tvalid; +wire output_eth_payload_tlast; +wire output_eth_payload_tuser; + +initial begin + // myhdl integration + $from_myhdl(clk, + rst, + current_test, + input_0_eth_hdr_valid, + input_0_eth_dest_mac, + input_0_eth_src_mac, + input_0_eth_type, + input_0_eth_payload_tdata, + input_0_eth_payload_tvalid, + input_0_eth_payload_tlast, + input_0_eth_payload_tuser, + input_1_eth_hdr_valid, + input_1_eth_dest_mac, + input_1_eth_src_mac, + input_1_eth_type, + input_1_eth_payload_tdata, + input_1_eth_payload_tvalid, + input_1_eth_payload_tlast, + input_1_eth_payload_tuser, + input_2_eth_hdr_valid, + input_2_eth_dest_mac, + input_2_eth_src_mac, + input_2_eth_type, + input_2_eth_payload_tdata, + input_2_eth_payload_tvalid, + input_2_eth_payload_tlast, + input_2_eth_payload_tuser, + input_3_eth_hdr_valid, + input_3_eth_dest_mac, + input_3_eth_src_mac, + input_3_eth_type, + input_3_eth_payload_tdata, + input_3_eth_payload_tvalid, + input_3_eth_payload_tlast, + input_3_eth_payload_tuser, + output_eth_hdr_ready, + output_eth_payload_tready, + select); + $to_myhdl(input_0_eth_hdr_ready, + input_0_eth_payload_tready, + input_1_eth_hdr_ready, + input_1_eth_payload_tready, + input_2_eth_hdr_ready, + input_2_eth_payload_tready, + input_3_eth_hdr_ready, + input_3_eth_payload_tready, + output_eth_hdr_valid, + output_eth_dest_mac, + output_eth_src_mac, + output_eth_type, + output_eth_payload_tdata, + output_eth_payload_tvalid, + output_eth_payload_tlast, + output_eth_payload_tuser); + + // dump file + $dumpfile("test_eth_mux_4.lxt"); + $dumpvars(0, test_eth_mux_4); +end + +eth_mux_4 +UUT ( + .clk(clk), + .rst(rst), + // Ethernet frame inputs + .input_0_eth_hdr_valid(input_0_eth_hdr_valid), + .input_0_eth_hdr_ready(input_0_eth_hdr_ready), + .input_0_eth_dest_mac(input_0_eth_dest_mac), + .input_0_eth_src_mac(input_0_eth_src_mac), + .input_0_eth_type(input_0_eth_type), + .input_0_eth_payload_tdata(input_0_eth_payload_tdata), + .input_0_eth_payload_tvalid(input_0_eth_payload_tvalid), + .input_0_eth_payload_tready(input_0_eth_payload_tready), + .input_0_eth_payload_tlast(input_0_eth_payload_tlast), + .input_0_eth_payload_tuser(input_0_eth_payload_tuser), + .input_1_eth_hdr_valid(input_1_eth_hdr_valid), + .input_1_eth_hdr_ready(input_1_eth_hdr_ready), + .input_1_eth_dest_mac(input_1_eth_dest_mac), + .input_1_eth_src_mac(input_1_eth_src_mac), + .input_1_eth_type(input_1_eth_type), + .input_1_eth_payload_tdata(input_1_eth_payload_tdata), + .input_1_eth_payload_tvalid(input_1_eth_payload_tvalid), + .input_1_eth_payload_tready(input_1_eth_payload_tready), + .input_1_eth_payload_tlast(input_1_eth_payload_tlast), + .input_1_eth_payload_tuser(input_1_eth_payload_tuser), + .input_2_eth_hdr_valid(input_2_eth_hdr_valid), + .input_2_eth_hdr_ready(input_2_eth_hdr_ready), + .input_2_eth_dest_mac(input_2_eth_dest_mac), + .input_2_eth_src_mac(input_2_eth_src_mac), + .input_2_eth_type(input_2_eth_type), + .input_2_eth_payload_tdata(input_2_eth_payload_tdata), + .input_2_eth_payload_tvalid(input_2_eth_payload_tvalid), + .input_2_eth_payload_tready(input_2_eth_payload_tready), + .input_2_eth_payload_tlast(input_2_eth_payload_tlast), + .input_2_eth_payload_tuser(input_2_eth_payload_tuser), + .input_3_eth_hdr_valid(input_3_eth_hdr_valid), + .input_3_eth_hdr_ready(input_3_eth_hdr_ready), + .input_3_eth_dest_mac(input_3_eth_dest_mac), + .input_3_eth_src_mac(input_3_eth_src_mac), + .input_3_eth_type(input_3_eth_type), + .input_3_eth_payload_tdata(input_3_eth_payload_tdata), + .input_3_eth_payload_tvalid(input_3_eth_payload_tvalid), + .input_3_eth_payload_tready(input_3_eth_payload_tready), + .input_3_eth_payload_tlast(input_3_eth_payload_tlast), + .input_3_eth_payload_tuser(input_3_eth_payload_tuser), + // Ethernet frame output + .output_eth_hdr_valid(output_eth_hdr_valid), + .output_eth_hdr_ready(output_eth_hdr_ready), + .output_eth_dest_mac(output_eth_dest_mac), + .output_eth_src_mac(output_eth_src_mac), + .output_eth_type(output_eth_type), + .output_eth_payload_tdata(output_eth_payload_tdata), + .output_eth_payload_tvalid(output_eth_payload_tvalid), + .output_eth_payload_tready(output_eth_payload_tready), + .output_eth_payload_tlast(output_eth_payload_tlast), + .output_eth_payload_tuser(output_eth_payload_tuser), + // Control + .select(select) +); + +endmodule diff --git a/tb/test_eth_mux_64_4.py b/tb/test_eth_mux_64_4.py new file mode 100755 index 000000000..e044429b2 --- /dev/null +++ b/tb/test_eth_mux_64_4.py @@ -0,0 +1,673 @@ +#!/usr/bin/env python2 +""" + +Copyright (c) 2014 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +from myhdl import * +import os +from Queue import Queue + +import eth_ep + +module = 'eth_mux_64_4' + +srcs = [] + +srcs.append("../rtl/%s.v" % module) +srcs.append("test_%s.v" % module) + +src = ' '.join(srcs) + +build_cmd = "iverilog -o test_%s.vvp %s" % (module, src) + +def dut_eth_mux_64_4(clk, + rst, + current_test, + + input_0_eth_hdr_valid, + input_0_eth_hdr_ready, + input_0_eth_dest_mac, + input_0_eth_src_mac, + input_0_eth_type, + input_0_eth_payload_tdata, + input_0_eth_payload_tkeep, + input_0_eth_payload_tvalid, + input_0_eth_payload_tready, + input_0_eth_payload_tlast, + input_0_eth_payload_tuser, + input_1_eth_hdr_valid, + input_1_eth_hdr_ready, + input_1_eth_dest_mac, + input_1_eth_src_mac, + input_1_eth_type, + input_1_eth_payload_tdata, + input_1_eth_payload_tkeep, + input_1_eth_payload_tvalid, + input_1_eth_payload_tready, + input_1_eth_payload_tlast, + input_1_eth_payload_tuser, + input_2_eth_hdr_valid, + input_2_eth_hdr_ready, + input_2_eth_dest_mac, + input_2_eth_src_mac, + input_2_eth_type, + input_2_eth_payload_tdata, + input_2_eth_payload_tkeep, + input_2_eth_payload_tvalid, + input_2_eth_payload_tready, + input_2_eth_payload_tlast, + input_2_eth_payload_tuser, + input_3_eth_hdr_valid, + input_3_eth_hdr_ready, + input_3_eth_dest_mac, + input_3_eth_src_mac, + input_3_eth_type, + input_3_eth_payload_tdata, + input_3_eth_payload_tkeep, + input_3_eth_payload_tvalid, + input_3_eth_payload_tready, + input_3_eth_payload_tlast, + input_3_eth_payload_tuser, + + output_eth_hdr_valid, + output_eth_hdr_ready, + output_eth_dest_mac, + output_eth_src_mac, + output_eth_type, + output_eth_payload_tdata, + output_eth_payload_tkeep, + output_eth_payload_tvalid, + output_eth_payload_tready, + output_eth_payload_tlast, + output_eth_payload_tuser, + + select): + + if os.system(build_cmd): + raise Exception("Error running build command") + return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module, + clk=clk, + rst=rst, + current_test=current_test, + + input_0_eth_hdr_valid=input_0_eth_hdr_valid, + input_0_eth_hdr_ready=input_0_eth_hdr_ready, + input_0_eth_dest_mac=input_0_eth_dest_mac, + input_0_eth_src_mac=input_0_eth_src_mac, + input_0_eth_type=input_0_eth_type, + input_0_eth_payload_tdata=input_0_eth_payload_tdata, + input_0_eth_payload_tkeep=input_0_eth_payload_tkeep, + input_0_eth_payload_tvalid=input_0_eth_payload_tvalid, + input_0_eth_payload_tready=input_0_eth_payload_tready, + input_0_eth_payload_tlast=input_0_eth_payload_tlast, + input_0_eth_payload_tuser=input_0_eth_payload_tuser, + input_1_eth_hdr_valid=input_1_eth_hdr_valid, + input_1_eth_hdr_ready=input_1_eth_hdr_ready, + input_1_eth_dest_mac=input_1_eth_dest_mac, + input_1_eth_src_mac=input_1_eth_src_mac, + input_1_eth_type=input_1_eth_type, + input_1_eth_payload_tdata=input_1_eth_payload_tdata, + input_1_eth_payload_tkeep=input_1_eth_payload_tkeep, + input_1_eth_payload_tvalid=input_1_eth_payload_tvalid, + input_1_eth_payload_tready=input_1_eth_payload_tready, + input_1_eth_payload_tlast=input_1_eth_payload_tlast, + input_1_eth_payload_tuser=input_1_eth_payload_tuser, + input_2_eth_hdr_valid=input_2_eth_hdr_valid, + input_2_eth_hdr_ready=input_2_eth_hdr_ready, + input_2_eth_dest_mac=input_2_eth_dest_mac, + input_2_eth_src_mac=input_2_eth_src_mac, + input_2_eth_type=input_2_eth_type, + input_2_eth_payload_tdata=input_2_eth_payload_tdata, + input_2_eth_payload_tkeep=input_2_eth_payload_tkeep, + input_2_eth_payload_tvalid=input_2_eth_payload_tvalid, + input_2_eth_payload_tready=input_2_eth_payload_tready, + input_2_eth_payload_tlast=input_2_eth_payload_tlast, + input_2_eth_payload_tuser=input_2_eth_payload_tuser, + input_3_eth_hdr_valid=input_3_eth_hdr_valid, + input_3_eth_hdr_ready=input_3_eth_hdr_ready, + input_3_eth_dest_mac=input_3_eth_dest_mac, + input_3_eth_src_mac=input_3_eth_src_mac, + input_3_eth_type=input_3_eth_type, + input_3_eth_payload_tdata=input_3_eth_payload_tdata, + input_3_eth_payload_tkeep=input_3_eth_payload_tkeep, + input_3_eth_payload_tvalid=input_3_eth_payload_tvalid, + input_3_eth_payload_tready=input_3_eth_payload_tready, + input_3_eth_payload_tlast=input_3_eth_payload_tlast, + input_3_eth_payload_tuser=input_3_eth_payload_tuser, + + output_eth_hdr_valid=output_eth_hdr_valid, + output_eth_hdr_ready=output_eth_hdr_ready, + output_eth_dest_mac=output_eth_dest_mac, + output_eth_src_mac=output_eth_src_mac, + output_eth_type=output_eth_type, + output_eth_payload_tdata=output_eth_payload_tdata, + output_eth_payload_tkeep=output_eth_payload_tkeep, + output_eth_payload_tvalid=output_eth_payload_tvalid, + output_eth_payload_tready=output_eth_payload_tready, + output_eth_payload_tlast=output_eth_payload_tlast, + output_eth_payload_tuser=output_eth_payload_tuser, + + select=select) + +def bench(): + + # Inputs + clk = Signal(bool(0)) + rst = Signal(bool(0)) + current_test = Signal(intbv(0)[8:]) + + input_0_eth_hdr_valid = Signal(bool(0)) + input_0_eth_dest_mac = Signal(intbv(0)[48:]) + input_0_eth_src_mac = Signal(intbv(0)[48:]) + input_0_eth_type = Signal(intbv(0)[16:]) + input_0_eth_payload_tdata = Signal(intbv(0)[64:]) + input_0_eth_payload_tkeep = Signal(intbv(0)[8:]) + input_0_eth_payload_tvalid = Signal(bool(0)) + input_0_eth_payload_tlast = Signal(bool(0)) + input_0_eth_payload_tuser = Signal(bool(0)) + input_1_eth_hdr_valid = Signal(bool(0)) + input_1_eth_dest_mac = Signal(intbv(0)[48:]) + input_1_eth_src_mac = Signal(intbv(0)[48:]) + input_1_eth_type = Signal(intbv(0)[16:]) + input_1_eth_payload_tdata = Signal(intbv(0)[64:]) + input_1_eth_payload_tkeep = Signal(intbv(0)[8:]) + input_1_eth_payload_tvalid = Signal(bool(0)) + input_1_eth_payload_tlast = Signal(bool(0)) + input_1_eth_payload_tuser = Signal(bool(0)) + input_2_eth_hdr_valid = Signal(bool(0)) + input_2_eth_dest_mac = Signal(intbv(0)[48:]) + input_2_eth_src_mac = Signal(intbv(0)[48:]) + input_2_eth_type = Signal(intbv(0)[16:]) + input_2_eth_payload_tdata = Signal(intbv(0)[64:]) + input_2_eth_payload_tkeep = Signal(intbv(0)[8:]) + input_2_eth_payload_tvalid = Signal(bool(0)) + input_2_eth_payload_tlast = Signal(bool(0)) + input_2_eth_payload_tuser = Signal(bool(0)) + input_3_eth_hdr_valid = Signal(bool(0)) + input_3_eth_dest_mac = Signal(intbv(0)[48:]) + input_3_eth_src_mac = Signal(intbv(0)[48:]) + input_3_eth_type = Signal(intbv(0)[16:]) + input_3_eth_payload_tdata = Signal(intbv(0)[64:]) + input_3_eth_payload_tkeep = Signal(intbv(0)[8:]) + input_3_eth_payload_tvalid = Signal(bool(0)) + input_3_eth_payload_tlast = Signal(bool(0)) + input_3_eth_payload_tuser = Signal(bool(0)) + + output_eth_payload_tready = Signal(bool(0)) + output_eth_hdr_ready = Signal(bool(0)) + + select = Signal(intbv(0)[2:]) + + # Outputs + input_0_eth_hdr_ready = Signal(bool(0)) + input_0_eth_payload_tready = Signal(bool(0)) + input_1_eth_hdr_ready = Signal(bool(0)) + input_1_eth_payload_tready = Signal(bool(0)) + input_2_eth_hdr_ready = Signal(bool(0)) + input_2_eth_payload_tready = Signal(bool(0)) + input_3_eth_hdr_ready = Signal(bool(0)) + input_3_eth_payload_tready = Signal(bool(0)) + + output_eth_hdr_valid = Signal(bool(0)) + output_eth_dest_mac = Signal(intbv(0)[48:]) + output_eth_src_mac = Signal(intbv(0)[48:]) + output_eth_type = Signal(intbv(0)[16:]) + output_eth_payload_tdata = Signal(intbv(0)[64:]) + output_eth_payload_tkeep = Signal(intbv(0)[8:]) + output_eth_payload_tvalid = Signal(bool(0)) + output_eth_payload_tlast = Signal(bool(0)) + output_eth_payload_tuser = Signal(bool(0)) + + # sources and sinks + source_0_queue = Queue() + source_0_pause = Signal(bool(0)) + source_1_queue = Queue() + source_1_pause = Signal(bool(0)) + source_2_queue = Queue() + source_2_pause = Signal(bool(0)) + source_3_queue = Queue() + source_3_pause = Signal(bool(0)) + sink_queue = Queue() + sink_pause = Signal(bool(0)) + + source_0 = eth_ep.EthFrameSource(clk, + rst, + eth_hdr_ready=input_0_eth_hdr_ready, + eth_hdr_valid=input_0_eth_hdr_valid, + eth_dest_mac=input_0_eth_dest_mac, + eth_src_mac=input_0_eth_src_mac, + eth_type=input_0_eth_type, + eth_payload_tdata=input_0_eth_payload_tdata, + eth_payload_tkeep=input_0_eth_payload_tkeep, + eth_payload_tvalid=input_0_eth_payload_tvalid, + eth_payload_tready=input_0_eth_payload_tready, + eth_payload_tlast=input_0_eth_payload_tlast, + eth_payload_tuser=input_0_eth_payload_tuser, + fifo=source_0_queue, + pause=source_0_pause, + name='source0') + + source_1 = eth_ep.EthFrameSource(clk, + rst, + eth_hdr_ready=input_1_eth_hdr_ready, + eth_hdr_valid=input_1_eth_hdr_valid, + eth_dest_mac=input_1_eth_dest_mac, + eth_src_mac=input_1_eth_src_mac, + eth_type=input_1_eth_type, + eth_payload_tdata=input_1_eth_payload_tdata, + eth_payload_tkeep=input_1_eth_payload_tkeep, + eth_payload_tvalid=input_1_eth_payload_tvalid, + eth_payload_tready=input_1_eth_payload_tready, + eth_payload_tlast=input_1_eth_payload_tlast, + eth_payload_tuser=input_1_eth_payload_tuser, + fifo=source_1_queue, + pause=source_1_pause, + name='source1') + + source_2 = eth_ep.EthFrameSource(clk, + rst, + eth_hdr_ready=input_2_eth_hdr_ready, + eth_hdr_valid=input_2_eth_hdr_valid, + eth_dest_mac=input_2_eth_dest_mac, + eth_src_mac=input_2_eth_src_mac, + eth_type=input_2_eth_type, + eth_payload_tdata=input_2_eth_payload_tdata, + eth_payload_tkeep=input_2_eth_payload_tkeep, + eth_payload_tvalid=input_2_eth_payload_tvalid, + eth_payload_tready=input_2_eth_payload_tready, + eth_payload_tlast=input_2_eth_payload_tlast, + eth_payload_tuser=input_2_eth_payload_tuser, + fifo=source_2_queue, + pause=source_2_pause, + name='source2') + + source_3 = eth_ep.EthFrameSource(clk, + rst, + eth_hdr_ready=input_3_eth_hdr_ready, + eth_hdr_valid=input_3_eth_hdr_valid, + eth_dest_mac=input_3_eth_dest_mac, + eth_src_mac=input_3_eth_src_mac, + eth_type=input_3_eth_type, + eth_payload_tdata=input_3_eth_payload_tdata, + eth_payload_tkeep=input_3_eth_payload_tkeep, + eth_payload_tvalid=input_3_eth_payload_tvalid, + eth_payload_tready=input_3_eth_payload_tready, + eth_payload_tlast=input_3_eth_payload_tlast, + eth_payload_tuser=input_3_eth_payload_tuser, + fifo=source_3_queue, + pause=source_3_pause, + name='source3') + + sink = eth_ep.EthFrameSink(clk, + rst, + eth_hdr_ready=output_eth_hdr_ready, + eth_hdr_valid=output_eth_hdr_valid, + eth_dest_mac=output_eth_dest_mac, + eth_src_mac=output_eth_src_mac, + eth_type=output_eth_type, + eth_payload_tdata=output_eth_payload_tdata, + eth_payload_tkeep=output_eth_payload_tkeep, + eth_payload_tvalid=output_eth_payload_tvalid, + eth_payload_tready=output_eth_payload_tready, + eth_payload_tlast=output_eth_payload_tlast, + eth_payload_tuser=output_eth_payload_tuser, + fifo=sink_queue, + pause=sink_pause, + name='sink') + + # DUT + dut = dut_eth_mux_64_4(clk, + rst, + current_test, + + input_0_eth_hdr_valid, + input_0_eth_hdr_ready, + input_0_eth_dest_mac, + input_0_eth_src_mac, + input_0_eth_type, + input_0_eth_payload_tdata, + input_0_eth_payload_tkeep, + input_0_eth_payload_tvalid, + input_0_eth_payload_tready, + input_0_eth_payload_tlast, + input_0_eth_payload_tuser, + input_1_eth_hdr_valid, + input_1_eth_hdr_ready, + input_1_eth_dest_mac, + input_1_eth_src_mac, + input_1_eth_type, + input_1_eth_payload_tdata, + input_1_eth_payload_tkeep, + input_1_eth_payload_tvalid, + input_1_eth_payload_tready, + input_1_eth_payload_tlast, + input_1_eth_payload_tuser, + input_2_eth_hdr_valid, + input_2_eth_hdr_ready, + input_2_eth_dest_mac, + input_2_eth_src_mac, + input_2_eth_type, + input_2_eth_payload_tdata, + input_2_eth_payload_tkeep, + input_2_eth_payload_tvalid, + input_2_eth_payload_tready, + input_2_eth_payload_tlast, + input_2_eth_payload_tuser, + input_3_eth_hdr_valid, + input_3_eth_hdr_ready, + input_3_eth_dest_mac, + input_3_eth_src_mac, + input_3_eth_type, + input_3_eth_payload_tdata, + input_3_eth_payload_tkeep, + input_3_eth_payload_tvalid, + input_3_eth_payload_tready, + input_3_eth_payload_tlast, + input_3_eth_payload_tuser, + + output_eth_hdr_valid, + output_eth_hdr_ready, + output_eth_dest_mac, + output_eth_src_mac, + output_eth_type, + output_eth_payload_tdata, + output_eth_payload_tkeep, + output_eth_payload_tvalid, + output_eth_payload_tready, + output_eth_payload_tlast, + output_eth_payload_tuser, + + select) + + @always(delay(4)) + def clkgen(): + clk.next = not clk + + @instance + def check(): + yield delay(100) + yield clk.posedge + rst.next = 1 + yield clk.posedge + rst.next = 0 + yield clk.posedge + yield delay(100) + yield clk.posedge + + yield clk.posedge + + yield clk.posedge + print("test 1: select port 0") + current_test.next = 1 + + select.next = 0 + + test_frame = eth_ep.EthFrame() + test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame.eth_src_mac = 0x5A5152535455 + test_frame.eth_type = 0x8000 + test_frame.payload = bytearray(range(32)) + + source_0_queue.put(test_frame) + yield clk.posedge + yield clk.posedge + + while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + yield clk.posedge + yield clk.posedge + yield clk.posedge + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame + + yield delay(100) + + yield clk.posedge + print("test 2: select port 1") + current_test.next = 2 + + select.next = 1 + + test_frame = eth_ep.EthFrame() + test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame.eth_src_mac = 0x5A5152535455 + test_frame.eth_type = 0x8000 + test_frame.payload = bytearray(range(32)) + + source_1_queue.put(test_frame) + yield clk.posedge + yield clk.posedge + + while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + yield clk.posedge + yield clk.posedge + yield clk.posedge + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame + + yield delay(100) + + yield clk.posedge + print("test 3: back-to-back packets, same port") + current_test.next = 3 + + select.next = 0 + + test_frame1 = eth_ep.EthFrame() + test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame1.eth_src_mac = 0x5A5152535455 + test_frame1.eth_type = 0x8000 + test_frame1.payload = bytearray(range(32)) + test_frame2 = eth_ep.EthFrame() + test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame2.eth_src_mac = 0x5A5152535455 + test_frame2.eth_type = 0x8000 + test_frame2.payload = bytearray(range(32)) + + source_0_queue.put(test_frame1) + source_0_queue.put(test_frame2) + yield clk.posedge + yield clk.posedge + + while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + yield clk.posedge + yield clk.posedge + yield clk.posedge + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame1 + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + + yield delay(100) + + yield clk.posedge + print("test 4: back-to-back packets, different ports") + current_test.next = 4 + + select.next = 1 + + test_frame1 = eth_ep.EthFrame() + test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame1.eth_src_mac = 0x5A5152535455 + test_frame1.eth_type = 0x8000 + test_frame1.payload = bytearray(range(32)) + test_frame2 = eth_ep.EthFrame() + test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame2.eth_src_mac = 0x5A5152535455 + test_frame2.eth_type = 0x8000 + test_frame2.payload = bytearray(range(32)) + + source_1_queue.put(test_frame1) + source_2_queue.put(test_frame2) + yield clk.posedge + yield clk.posedge + + while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + yield clk.posedge + select.next = 2 + yield clk.posedge + yield clk.posedge + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame1 + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + + yield delay(100) + + yield clk.posedge + print("test 5: alterate pause source") + current_test.next = 5 + + select.next = 1 + + test_frame1 = eth_ep.EthFrame() + test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame1.eth_src_mac = 0x5A5152535455 + test_frame1.eth_type = 0x8000 + test_frame1.payload = bytearray(range(32)) + test_frame2 = eth_ep.EthFrame() + test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame2.eth_src_mac = 0x5A5152535455 + test_frame2.eth_type = 0x8000 + test_frame2.payload = bytearray(range(32)) + + source_1_queue.put(test_frame1) + source_2_queue.put(test_frame2) + yield clk.posedge + yield clk.posedge + + while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + source_0_pause.next = True + source_1_pause.next = True + source_2_pause.next = True + source_3_pause.next = True + yield clk.posedge + yield clk.posedge + yield clk.posedge + source_0_pause.next = False + source_1_pause.next = False + source_2_pause.next = False + source_3_pause.next = False + yield clk.posedge + select.next = 2 + yield clk.posedge + yield clk.posedge + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame1 + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + + yield delay(100) + + yield clk.posedge + print("test 6: alterate pause sink") + current_test.next = 6 + + select.next = 1 + + test_frame1 = eth_ep.EthFrame() + test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame1.eth_src_mac = 0x5A5152535455 + test_frame1.eth_type = 0x8000 + test_frame1.payload = bytearray(range(32)) + test_frame2 = eth_ep.EthFrame() + test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 + test_frame2.eth_src_mac = 0x5A5152535455 + test_frame2.eth_type = 0x8000 + test_frame2.payload = bytearray(range(32)) + + source_1_queue.put(test_frame1) + source_2_queue.put(test_frame2) + yield clk.posedge + yield clk.posedge + + while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: + sink_pause.next = True + yield clk.posedge + yield clk.posedge + yield clk.posedge + sink_pause.next = False + yield clk.posedge + select.next = 2 + yield clk.posedge + yield clk.posedge + yield clk.posedge + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame1 + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + + yield delay(100) + + raise StopSimulation + + return dut, source_0, source_1, source_2, source_3, sink, clkgen, check + +def test_bench(): + os.chdir(os.path.dirname(os.path.abspath(__file__))) + sim = Simulation(bench()) + sim.run() + +if __name__ == '__main__': + print("Running test...") + test_bench() + diff --git a/tb/test_eth_mux_64_4.v b/tb/test_eth_mux_64_4.v new file mode 100644 index 000000000..e979f0a61 --- /dev/null +++ b/tb/test_eth_mux_64_4.v @@ -0,0 +1,230 @@ +/* + +Copyright (c) 2014 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1 ns / 1 ps + +module test_eth_mux_64_4; + +// Inputs +reg clk = 0; +reg rst = 0; +reg [7:0] current_test = 0; + +reg input_0_eth_hdr_valid = 0; +reg [47:0] input_0_eth_dest_mac = 0; +reg [47:0] input_0_eth_src_mac = 0; +reg [15:0] input_0_eth_type = 0; +reg [63:0] input_0_eth_payload_tdata = 0; +reg [7:0] input_0_eth_payload_tkeep = 0; +reg input_0_eth_payload_tvalid = 0; +reg input_0_eth_payload_tlast = 0; +reg input_0_eth_payload_tuser = 0; +reg input_1_eth_hdr_valid = 0; +reg [47:0] input_1_eth_dest_mac = 0; +reg [47:0] input_1_eth_src_mac = 0; +reg [15:0] input_1_eth_type = 0; +reg [63:0] input_1_eth_payload_tdata = 0; +reg [7:0] input_1_eth_payload_tkeep = 0; +reg input_1_eth_payload_tvalid = 0; +reg input_1_eth_payload_tlast = 0; +reg input_1_eth_payload_tuser = 0; +reg input_2_eth_hdr_valid = 0; +reg [47:0] input_2_eth_dest_mac = 0; +reg [47:0] input_2_eth_src_mac = 0; +reg [15:0] input_2_eth_type = 0; +reg [63:0] input_2_eth_payload_tdata = 0; +reg [7:0] input_2_eth_payload_tkeep = 0; +reg input_2_eth_payload_tvalid = 0; +reg input_2_eth_payload_tlast = 0; +reg input_2_eth_payload_tuser = 0; +reg input_3_eth_hdr_valid = 0; +reg [47:0] input_3_eth_dest_mac = 0; +reg [47:0] input_3_eth_src_mac = 0; +reg [15:0] input_3_eth_type = 0; +reg [63:0] input_3_eth_payload_tdata = 0; +reg [7:0] input_3_eth_payload_tkeep = 0; +reg input_3_eth_payload_tvalid = 0; +reg input_3_eth_payload_tlast = 0; +reg input_3_eth_payload_tuser = 0; + +reg output_eth_hdr_ready = 0; +reg output_eth_payload_tready = 0; + +reg [1:0] select = 0; + +// Outputs +wire input_0_eth_payload_tready; +wire input_0_eth_hdr_ready; +wire input_1_eth_payload_tready; +wire input_1_eth_hdr_ready; +wire input_2_eth_payload_tready; +wire input_2_eth_hdr_ready; +wire input_3_eth_payload_tready; +wire input_3_eth_hdr_ready; + +wire output_eth_hdr_valid; +wire [47:0] output_eth_dest_mac; +wire [47:0] output_eth_src_mac; +wire [15:0] output_eth_type; +wire [63:0] output_eth_payload_tdata; +wire [7:0] output_eth_payload_tkeep; +wire output_eth_payload_tvalid; +wire output_eth_payload_tlast; +wire output_eth_payload_tuser; + +initial begin + // myhdl integration + $from_myhdl(clk, + rst, + current_test, + input_0_eth_hdr_valid, + input_0_eth_dest_mac, + input_0_eth_src_mac, + input_0_eth_type, + input_0_eth_payload_tdata, + input_0_eth_payload_tkeep, + input_0_eth_payload_tvalid, + input_0_eth_payload_tlast, + input_0_eth_payload_tuser, + input_1_eth_hdr_valid, + input_1_eth_dest_mac, + input_1_eth_src_mac, + input_1_eth_type, + input_1_eth_payload_tdata, + input_1_eth_payload_tkeep, + input_1_eth_payload_tvalid, + input_1_eth_payload_tlast, + input_1_eth_payload_tuser, + input_2_eth_hdr_valid, + input_2_eth_dest_mac, + input_2_eth_src_mac, + input_2_eth_type, + input_2_eth_payload_tdata, + input_2_eth_payload_tkeep, + input_2_eth_payload_tvalid, + input_2_eth_payload_tlast, + input_2_eth_payload_tuser, + input_3_eth_hdr_valid, + input_3_eth_dest_mac, + input_3_eth_src_mac, + input_3_eth_type, + input_3_eth_payload_tdata, + input_3_eth_payload_tkeep, + input_3_eth_payload_tvalid, + input_3_eth_payload_tlast, + input_3_eth_payload_tuser, + output_eth_hdr_ready, + output_eth_payload_tready, + select); + $to_myhdl(input_0_eth_hdr_ready, + input_0_eth_payload_tready, + input_1_eth_hdr_ready, + input_1_eth_payload_tready, + input_2_eth_hdr_ready, + input_2_eth_payload_tready, + input_3_eth_hdr_ready, + input_3_eth_payload_tready, + output_eth_hdr_valid, + output_eth_dest_mac, + output_eth_src_mac, + output_eth_type, + output_eth_payload_tdata, + output_eth_payload_tkeep, + output_eth_payload_tvalid, + output_eth_payload_tlast, + output_eth_payload_tuser); + + // dump file + $dumpfile("test_eth_mux_64_4.lxt"); + $dumpvars(0, test_eth_mux_64_4); +end + +eth_mux_64_4 +UUT ( + .clk(clk), + .rst(rst), + // Ethernet frame inputs + .input_0_eth_hdr_valid(input_0_eth_hdr_valid), + .input_0_eth_hdr_ready(input_0_eth_hdr_ready), + .input_0_eth_dest_mac(input_0_eth_dest_mac), + .input_0_eth_src_mac(input_0_eth_src_mac), + .input_0_eth_type(input_0_eth_type), + .input_0_eth_payload_tdata(input_0_eth_payload_tdata), + .input_0_eth_payload_tkeep(input_0_eth_payload_tkeep), + .input_0_eth_payload_tvalid(input_0_eth_payload_tvalid), + .input_0_eth_payload_tready(input_0_eth_payload_tready), + .input_0_eth_payload_tlast(input_0_eth_payload_tlast), + .input_0_eth_payload_tuser(input_0_eth_payload_tuser), + .input_1_eth_hdr_valid(input_1_eth_hdr_valid), + .input_1_eth_hdr_ready(input_1_eth_hdr_ready), + .input_1_eth_dest_mac(input_1_eth_dest_mac), + .input_1_eth_src_mac(input_1_eth_src_mac), + .input_1_eth_type(input_1_eth_type), + .input_1_eth_payload_tdata(input_1_eth_payload_tdata), + .input_1_eth_payload_tkeep(input_1_eth_payload_tkeep), + .input_1_eth_payload_tvalid(input_1_eth_payload_tvalid), + .input_1_eth_payload_tready(input_1_eth_payload_tready), + .input_1_eth_payload_tlast(input_1_eth_payload_tlast), + .input_1_eth_payload_tuser(input_1_eth_payload_tuser), + .input_2_eth_hdr_valid(input_2_eth_hdr_valid), + .input_2_eth_hdr_ready(input_2_eth_hdr_ready), + .input_2_eth_dest_mac(input_2_eth_dest_mac), + .input_2_eth_src_mac(input_2_eth_src_mac), + .input_2_eth_type(input_2_eth_type), + .input_2_eth_payload_tdata(input_2_eth_payload_tdata), + .input_2_eth_payload_tkeep(input_2_eth_payload_tkeep), + .input_2_eth_payload_tvalid(input_2_eth_payload_tvalid), + .input_2_eth_payload_tready(input_2_eth_payload_tready), + .input_2_eth_payload_tlast(input_2_eth_payload_tlast), + .input_2_eth_payload_tuser(input_2_eth_payload_tuser), + .input_3_eth_hdr_valid(input_3_eth_hdr_valid), + .input_3_eth_hdr_ready(input_3_eth_hdr_ready), + .input_3_eth_dest_mac(input_3_eth_dest_mac), + .input_3_eth_src_mac(input_3_eth_src_mac), + .input_3_eth_type(input_3_eth_type), + .input_3_eth_payload_tdata(input_3_eth_payload_tdata), + .input_3_eth_payload_tkeep(input_3_eth_payload_tkeep), + .input_3_eth_payload_tvalid(input_3_eth_payload_tvalid), + .input_3_eth_payload_tready(input_3_eth_payload_tready), + .input_3_eth_payload_tlast(input_3_eth_payload_tlast), + .input_3_eth_payload_tuser(input_3_eth_payload_tuser), + // Ethernet frame output + .output_eth_hdr_valid(output_eth_hdr_valid), + .output_eth_hdr_ready(output_eth_hdr_ready), + .output_eth_dest_mac(output_eth_dest_mac), + .output_eth_src_mac(output_eth_src_mac), + .output_eth_type(output_eth_type), + .output_eth_payload_tdata(output_eth_payload_tdata), + .output_eth_payload_tkeep(output_eth_payload_tkeep), + .output_eth_payload_tvalid(output_eth_payload_tvalid), + .output_eth_payload_tready(output_eth_payload_tready), + .output_eth_payload_tlast(output_eth_payload_tlast), + .output_eth_payload_tuser(output_eth_payload_tuser), + // Control + .select(select) +); + +endmodule