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Update example designs for RX completion buffer management

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-05-30 18:38:43 -07:00
parent 3d2feb36dc
commit 9cee4f3808
48 changed files with 172 additions and 35 deletions
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6
example/ADM_PCIE_9V3/fpga/rtl/fpga.v
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@ -143,6 +143,7 @@ wire pcie_rq_seq_num_vld1;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -261,7 +262,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -407,7 +408,8 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),

5
example/ADM_PCIE_9V3/fpga/rtl/fpga_core.v
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@ -103,6 +103,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -158,6 +159,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_CPLH_FC_LIMIT(128),
.READ_CPLD_FC_LIMIT(2048),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.BAR0_APERTURE(BAR0_APERTURE),
@ -260,6 +263,8 @@ example_core_pcie_us_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
// .cfg_rcb_status(cfg_rcb_status),
.cfg_rcb_status(1'b1), // force RCB 128 due to insufficient CPLH limit in US+ PCIe HIP
/*
* Status

2
example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
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@ -167,7 +167,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

6
example/AU200/fpga/rtl/fpga.v
View File

@ -158,6 +158,7 @@ wire pcie_rq_seq_num_vld1;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -276,7 +277,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -421,7 +422,8 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),

5
example/AU200/fpga/rtl/fpga_core.v
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@ -102,6 +102,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -155,6 +156,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_CPLH_FC_LIMIT(128),
.READ_CPLD_FC_LIMIT(2048),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.BAR0_APERTURE(BAR0_APERTURE),
@ -257,6 +260,8 @@ example_core_pcie_us_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
// .cfg_rcb_status(cfg_rcb_status),
.cfg_rcb_status(1'b1), // force RCB 128 due to insufficient CPLH limit in US+ PCIe HIP
/*
* Status

2
example/AU200/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -167,7 +167,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

6
example/AU250/fpga/rtl/fpga.v
View File

@ -158,6 +158,7 @@ wire pcie_rq_seq_num_vld1;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -276,7 +277,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -421,7 +422,8 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),

5
example/AU250/fpga/rtl/fpga_core.v
View File

@ -102,6 +102,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -155,6 +156,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_CPLH_FC_LIMIT(128),
.READ_CPLD_FC_LIMIT(2048),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.BAR0_APERTURE(BAR0_APERTURE),
@ -257,6 +260,8 @@ example_core_pcie_us_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
// .cfg_rcb_status(cfg_rcb_status),
.cfg_rcb_status(1'b1), // force RCB 128 due to insufficient CPLH limit in US+ PCIe HIP
/*
* Status

2
example/AU250/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -167,7 +167,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

6
example/AU280/fpga/rtl/fpga.v
View File

@ -145,6 +145,7 @@ wire pcie_rq_seq_num_vld1;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -263,7 +264,7 @@ pcie4c_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -403,7 +404,8 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),

5
example/AU280/fpga/rtl/fpga_core.v
View File

@ -96,6 +96,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -147,6 +148,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_CPLH_FC_LIMIT(128),
.READ_CPLD_FC_LIMIT(2048),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.BAR0_APERTURE(BAR0_APERTURE),
@ -249,6 +252,8 @@ example_core_pcie_us_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
// .cfg_rcb_status(cfg_rcb_status),
.cfg_rcb_status(1'b1), // force RCB 128 due to insufficient CPLH limit in US+ PCIe HIP
/*
* Status

2
example/AU280/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -167,7 +167,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

6
example/AU50/fpga/rtl/fpga.v
View File

@ -148,6 +148,7 @@ wire pcie_rq_seq_num_vld1;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -266,7 +267,7 @@ pcie4c_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -412,7 +413,8 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),

5
example/AU50/fpga/rtl/fpga_core.v
View File

@ -103,6 +103,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -158,6 +159,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_CPLH_FC_LIMIT(128),
.READ_CPLD_FC_LIMIT(2048),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.BAR0_APERTURE(BAR0_APERTURE),
@ -260,6 +263,8 @@ example_core_pcie_us_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
// .cfg_rcb_status(cfg_rcb_status),
.cfg_rcb_status(1'b1), // force RCB 128 due to insufficient CPLH limit in US+ PCIe HIP
/*
* Status

2
example/AU50/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -167,7 +167,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
example/ExaNIC_X10/fpga/rtl/fpga.v
View File

@ -141,6 +141,7 @@ wire pcie_rq_seq_num_vld;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [18:0] cfg_mgmt_addr;
wire cfg_mgmt_write;
@ -249,7 +250,7 @@ pcie3_ultrascale_inst (
.cfg_local_error(),
.cfg_ltr_enable(),
.cfg_ltssm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_dpa_substate_change(),
.cfg_obff_enable(),
.cfg_pl_status_change(),
@ -401,6 +402,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_write(cfg_mgmt_write),

5
example/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -101,6 +101,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [18:0] cfg_mgmt_addr,
output wire cfg_mgmt_write,
@ -153,6 +154,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_CPLH_FC_LIMIT(64),
.READ_CPLD_FC_LIMIT(992),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.BAR0_APERTURE(BAR0_APERTURE),
@ -255,6 +258,8 @@ example_core_pcie_us_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
// .cfg_rcb_status(cfg_rcb_status),
.cfg_rcb_status(1'b1), // force RCB 128 due to insufficient CPLH limit in US PCIe HIP
/*
* Status

2
example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -142,7 +142,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

6
example/ExaNIC_X25/fpga/rtl/fpga.v
View File

@ -143,6 +143,7 @@ wire pcie_rq_seq_num_vld1;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -261,7 +262,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -407,7 +408,8 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),

5
example/ExaNIC_X25/fpga/rtl/fpga_core.v
View File

@ -103,6 +103,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -158,6 +159,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_CPLH_FC_LIMIT(128),
.READ_CPLD_FC_LIMIT(2048),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.BAR0_APERTURE(BAR0_APERTURE),
@ -260,6 +263,8 @@ example_core_pcie_us_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
// .cfg_rcb_status(cfg_rcb_status),
.cfg_rcb_status(1'b1), // force RCB 128 due to insufficient CPLH limit in US+ PCIe HIP
/*
* Status

2
example/ExaNIC_X25/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -167,7 +167,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
example/VCU108/fpga/rtl/fpga.v
View File

@ -176,6 +176,7 @@ wire pcie_rq_seq_num_vld;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [18:0] cfg_mgmt_addr;
wire cfg_mgmt_write;
@ -284,7 +285,7 @@ pcie3_ultrascale_inst (
.cfg_local_error(),
.cfg_ltr_enable(),
.cfg_ltssm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_dpa_substate_change(),
.cfg_obff_enable(),
.cfg_pl_status_change(),
@ -440,6 +441,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_write(cfg_mgmt_write),

5
example/VCU108/fpga/rtl/fpga_core.v
View File

@ -105,6 +105,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [18:0] cfg_mgmt_addr,
output wire cfg_mgmt_write,
@ -155,6 +156,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_CPLH_FC_LIMIT(64),
.READ_CPLD_FC_LIMIT(992),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.BAR0_APERTURE(BAR0_APERTURE),
@ -257,6 +260,8 @@ example_core_pcie_us_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
// .cfg_rcb_status(cfg_rcb_status),
.cfg_rcb_status(1'b1), // force RCB 128 due to insufficient CPLH limit in US PCIe HIP
/*
* Status

2
example/VCU108/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -142,7 +142,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

6
example/VCU118/fpga/rtl/fpga.v
View File

@ -178,6 +178,7 @@ wire pcie_rq_seq_num_vld1;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -296,7 +297,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -446,7 +447,8 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),

5
example/VCU118/fpga/rtl/fpga_core.v
View File

@ -107,6 +107,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -160,6 +161,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_CPLH_FC_LIMIT(128),
.READ_CPLD_FC_LIMIT(2048),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.BAR0_APERTURE(BAR0_APERTURE),
@ -262,6 +265,8 @@ example_core_pcie_us_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
// .cfg_rcb_status(cfg_rcb_status),
.cfg_rcb_status(1'b1), // force RCB 128 due to insufficient CPLH limit in US+ PCIe HIP
/*
* Status

2
example/VCU118/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -167,7 +167,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

6
example/VCU1525/fpga/rtl/fpga.v
View File

@ -158,6 +158,7 @@ wire pcie_rq_seq_num_vld1;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -276,7 +277,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -421,7 +422,8 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),

5
example/VCU1525/fpga/rtl/fpga_core.v
View File

@ -102,6 +102,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -155,6 +156,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_CPLH_FC_LIMIT(128),
.READ_CPLD_FC_LIMIT(2048),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.BAR0_APERTURE(BAR0_APERTURE),
@ -257,6 +260,8 @@ example_core_pcie_us_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
// .cfg_rcb_status(cfg_rcb_status),
.cfg_rcb_status(1'b1), // force RCB 128 due to insufficient CPLH limit in US+ PCIe HIP
/*
* Status

2
example/VCU1525/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -167,7 +167,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

6
example/ZCU106/fpga/rtl/fpga.v
View File

@ -178,6 +178,7 @@ wire pcie_rq_seq_num_vld1;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -296,7 +297,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -446,7 +447,8 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),

5
example/ZCU106/fpga/rtl/fpga_core.v
View File

@ -107,6 +107,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -160,6 +161,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_CPLH_FC_LIMIT(128),
.READ_CPLD_FC_LIMIT(2048),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.BAR0_APERTURE(BAR0_APERTURE),
@ -262,6 +265,8 @@ example_core_pcie_us_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
// .cfg_rcb_status(cfg_rcb_status),
.cfg_rcb_status(1'b1), // force RCB 128 due to insufficient CPLH limit in US+ PCIe HIP
/*
* Status

2
example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -167,7 +167,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

10
example/common/rtl/example_core_pcie.v
View File

@ -57,6 +57,10 @@ module example_core_pcie #
parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Completion header flow control credit limit (read)
parameter READ_CPLH_FC_LIMIT = 0,
// Completion data flow control credit limit (read)
parameter READ_CPLD_FC_LIMIT = READ_CPLH_FC_LIMIT*4,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
// In-flight transmit limit (write)
@ -158,6 +162,7 @@ module example_core_pcie #
*/
input wire [7:0] bus_num,
input wire ext_tag_enable,
input wire rcb_128b,
input wire [2:0] max_read_request_size,
input wire [2:0] max_payload_size,
input wire msix_enable,
@ -784,6 +789,8 @@ dma_if_pcie #(
.TAG_WIDTH(DMA_TAG_WIDTH),
.READ_OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.READ_TX_LIMIT(READ_TX_LIMIT),
.READ_CPLH_FC_LIMIT(READ_CPLH_FC_LIMIT),
.READ_CPLD_FC_LIMIT(READ_CPLD_FC_LIMIT),
.WRITE_OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.WRITE_TX_LIMIT(WRITE_TX_LIMIT),
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR),
@ -896,6 +903,7 @@ dma_if_pcie_inst (
.read_enable(1'b1),
.write_enable(1'b1),
.ext_tag_enable(ext_tag_enable),
.rcb_128b(rcb_128b),
.requester_id({bus_num, 5'd0, 3'd0}),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
@ -903,6 +911,8 @@ dma_if_pcie_inst (
/*
* Status
*/
.status_rd_busy(),
.status_wr_busy(),
.status_error_cor(status_error_cor_int[3]),
.status_error_uncor(status_error_uncor_int[3])
);

9
example/common/rtl/example_core_pcie_ptile.v
View File

@ -57,6 +57,10 @@ module example_core_pcie_ptile #
parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Completion header flow control credit limit (read)
parameter READ_CPLH_FC_LIMIT = 1144,
// Completion data flow control credit limit (read)
parameter READ_CPLD_FC_LIMIT = 2888,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
// In-flight transmit limit (write)
@ -189,6 +193,7 @@ wire pcie_tx_msix_wr_req_tlp_eop;
wire pcie_tx_msix_wr_req_tlp_ready;
wire ext_tag_enable;
wire rcb_128b;
wire [7:0] bus_num;
wire [2:0] max_read_request_size;
wire [2:0] max_payload_size;
@ -356,6 +361,7 @@ pcie_ptile_if_inst (
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.rcb_128b(rcb_128b),
.bus_num(bus_num),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
@ -376,6 +382,8 @@ example_core_pcie #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.READ_TX_LIMIT(READ_TX_LIMIT),
.READ_CPLH_FC_LIMIT(READ_CPLH_FC_LIMIT),
.READ_CPLD_FC_LIMIT(READ_CPLD_FC_LIMIT),
.WRITE_OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.WRITE_TX_LIMIT(WRITE_TX_LIMIT),
.TLP_FORCE_64_BIT_ADDR(0),
@ -470,6 +478,7 @@ core_pcie_inst (
*/
.bus_num(bus_num),
.ext_tag_enable(ext_tag_enable),
.rcb_128b(rcb_128b),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
.msix_enable(msix_enable),

9
example/common/rtl/example_core_pcie_s10.v
View File

@ -55,6 +55,10 @@ module example_core_pcie_s10 #
parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Completion header flow control credit limit (read)
parameter READ_CPLH_FC_LIMIT = 770,
// Completion data flow control credit limit (read)
parameter READ_CPLD_FC_LIMIT = 2500,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
// In-flight transmit limit (write)
@ -183,6 +187,7 @@ wire pcie_tx_msix_wr_req_tlp_eop;
wire pcie_tx_msix_wr_req_tlp_ready;
wire ext_tag_enable;
wire rcb_128b;
wire [7:0] bus_num;
wire [2:0] max_read_request_size;
wire [2:0] max_payload_size;
@ -358,6 +363,7 @@ pcie_s10_if_inst (
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.rcb_128b(rcb_128b),
.bus_num(bus_num),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
@ -383,6 +389,8 @@ example_core_pcie #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.READ_TX_LIMIT(READ_TX_LIMIT),
.READ_CPLH_FC_LIMIT(READ_CPLH_FC_LIMIT),
.READ_CPLD_FC_LIMIT(READ_CPLD_FC_LIMIT),
.WRITE_OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.WRITE_TX_LIMIT(WRITE_TX_LIMIT),
.TLP_FORCE_64_BIT_ADDR(0),
@ -477,6 +485,7 @@ core_pcie_inst (
*/
.bus_num(bus_num),
.ext_tag_enable(ext_tag_enable),
.rcb_128b(rcb_128b),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
.msix_enable(msix_enable),

8
example/common/rtl/example_core_pcie_us.v
View File

@ -67,6 +67,10 @@ module example_core_pcie_us #
parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
// Completion header flow control credit limit (read)
parameter READ_CPLH_FC_LIMIT = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 64 : 128,
// Completion data flow control credit limit (read)
parameter READ_CPLD_FC_LIMIT = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 992 : 2048,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1),
// In-flight transmit limit (write)
@ -147,6 +151,7 @@ module example_core_pcie_us #
*/
input wire [2:0] cfg_max_read_req,
input wire [2:0] cfg_max_payload,
input wire [3:0] cfg_rcb_status,
/*
* Configuration flow control interface
@ -513,6 +518,8 @@ example_core_pcie #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.READ_TX_LIMIT(READ_TX_LIMIT),
.READ_CPLH_FC_LIMIT(READ_CPLH_FC_LIMIT),
.READ_CPLD_FC_LIMIT(READ_CPLD_FC_LIMIT),
.WRITE_OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.WRITE_TX_LIMIT(WRITE_TX_LIMIT),
.TLP_FORCE_64_BIT_ADDR(1),
@ -607,6 +614,7 @@ core_pcie_inst (
*/
.bus_num(8'd0),
.ext_tag_enable(ext_tag_enable),
.rcb_128b(cfg_rcb_status[0]),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
.msix_enable(msix_enable),

2
example/common/tb/example_core_pcie/Makefile
View File

@ -60,6 +60,8 @@ export PARAM_IMM_ENABLE := 1
export PARAM_IMM_WIDTH := 32
export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_READ_CPLH_FC_LIMIT := 0
export PARAM_READ_CPLD_FC_LIMIT := $(shell expr $(PARAM_READ_CPLH_FC_LIMIT) \* 4 )
export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_TLP_FORCE_64_BIT_ADDR := 0

3
example/common/tb/example_core_pcie/test_example_core_pcie.py
View File

@ -121,6 +121,7 @@ class TB(object):
cfg_max_payload=dut.max_payload_size,
cfg_max_read_req=dut.max_read_request_size,
cfg_ext_tag_enable=dut.ext_tag_enable,
cfg_rcb=dut.rcb_128b,
)
self.dev.log.setLevel(logging.DEBUG)
@ -422,6 +423,8 @@ def test_example_core_pcie(request, pcie_data_width):
parameters['IMM_WIDTH'] = 32
parameters['READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
parameters['READ_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['READ_CPLH_FC_LIMIT'] = 0
parameters['READ_CPLD_FC_LIMIT'] = parameters['READ_CPLH_FC_LIMIT']*4
parameters['WRITE_OP_TABLE_SIZE'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['TLP_FORCE_64_BIT_ADDR'] = 0

2
example/common/tb/example_core_pcie_ptile/Makefile
View File

@ -70,6 +70,8 @@ export PARAM_IMM_ENABLE := 1
export PARAM_IMM_WIDTH := 32
export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_READ_CPLH_FC_LIMIT := 1144
export PARAM_READ_CPLD_FC_LIMIT := 2888
export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_BAR0_APERTURE := 24

2
example/common/tb/example_core_pcie_ptile/test_example_core_pcie_ptile.py
View File

@ -518,6 +518,8 @@ def test_example_core_pcie_ptile(request, data_width):
parameters['IMM_WIDTH'] = 32
parameters['READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
parameters['READ_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['READ_CPLH_FC_LIMIT'] = 1144
parameters['READ_CPLD_FC_LIMIT'] = 2888
parameters['WRITE_OP_TABLE_SIZE'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['BAR0_APERTURE'] = 24

2
example/common/tb/example_core_pcie_s10/Makefile
View File

@ -68,6 +68,8 @@ export PARAM_IMM_ENABLE := 1
export PARAM_IMM_WIDTH := 32
export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_READ_CPLH_FC_LIMIT := 770
export PARAM_READ_CPLD_FC_LIMIT := 2500
export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_BAR0_APERTURE := 24

2
example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py
View File

@ -465,6 +465,8 @@ def test_example_core_pcie_s10(request, data_width, l_tile):
parameters['IMM_WIDTH'] = 32
parameters['READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
parameters['READ_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['READ_CPLH_FC_LIMIT'] = 770
parameters['READ_CPLD_FC_LIMIT'] = 2500
parameters['WRITE_OP_TABLE_SIZE'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['BAR0_APERTURE'] = 24

2
example/common/tb/example_core_pcie_us/Makefile
View File

@ -74,6 +74,8 @@ export PARAM_IMM_ENABLE := 1
export PARAM_IMM_WIDTH := 32
export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_READ_CPLH_FC_LIMIT := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),64,128)
export PARAM_READ_CPLD_FC_LIMIT := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),992,2048)
export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_BAR0_APERTURE := 24

4
example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py
View File

@ -168,7 +168,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable
@ -566,6 +566,8 @@ def test_example_core_pcie_us(request, axis_pcie_data_width, straddle):
parameters['IMM_WIDTH'] = 32
parameters['READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
parameters['READ_TX_LIMIT'] = 2**(parameters['RQ_SEQ_NUM_WIDTH']-1)
parameters['READ_CPLH_FC_LIMIT'] = 64 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 128
parameters['READ_CPLD_FC_LIMIT'] = 992 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 2048
parameters['WRITE_OP_TABLE_SIZE'] = 2**(parameters['RQ_SEQ_NUM_WIDTH']-1)
parameters['WRITE_TX_LIMIT'] = 2**(parameters['RQ_SEQ_NUM_WIDTH']-1)
parameters['BAR0_APERTURE'] = 24

6
example/fb2CG/fpga/rtl/fpga.v
View File

@ -145,6 +145,7 @@ wire pcie_rq_seq_num_vld1;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -263,7 +264,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -448,7 +449,8 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),

5
example/fb2CG/fpga/rtl/fpga_core.v
View File

@ -104,6 +104,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -160,6 +161,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_CPLH_FC_LIMIT(128),
.READ_CPLD_FC_LIMIT(2048),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.BAR0_APERTURE(BAR0_APERTURE),
@ -262,6 +265,8 @@ example_core_pcie_us_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
// .cfg_rcb_status(cfg_rcb_status),
.cfg_rcb_status(1'b1), // force RCB 128 due to insufficient CPLH limit in US+ PCIe HIP
/*
* Status

2
example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -167,7 +167,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable