From 9dafc3aaeee08521142e6e5ccceb841ba1ccb7ff Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 6 Jul 2023 16:28:08 -0700 Subject: [PATCH] Use internal BYTE_LANES parameter Signed-off-by: Alex Forencich --- rtl/arp_eth_rx.v | 14 ++++++++------ rtl/arp_eth_tx.v | 16 +++++++++------- rtl/eth_axis_rx.v | 14 ++++++++------ rtl/eth_axis_tx.v | 16 +++++++++------- 4 files changed, 34 insertions(+), 26 deletions(-) diff --git a/rtl/arp_eth_rx.v b/rtl/arp_eth_rx.v index 4366ede3a..bfc74b1ef 100644 --- a/rtl/arp_eth_rx.v +++ b/rtl/arp_eth_rx.v @@ -86,17 +86,19 @@ module arp_eth_rx # output wire error_invalid_header ); +parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1; + parameter HDR_SIZE = 28; -parameter CYCLE_COUNT = (HDR_SIZE+KEEP_WIDTH-1)/KEEP_WIDTH; +parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES; parameter PTR_WIDTH = $clog2(CYCLE_COUNT); -parameter OFFSET = HDR_SIZE % KEEP_WIDTH; +parameter OFFSET = HDR_SIZE % BYTE_LANES; // bus width assertions initial begin - if (KEEP_WIDTH * 8 != DATA_WIDTH) begin + if (BYTE_LANES * 8 != DATA_WIDTH) begin $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)"); $finish; end @@ -215,8 +217,8 @@ always @* begin ptr_next = ptr_reg + 1; `define _HEADER_FIELD_(offset, field) \ - if (ptr_reg == offset/KEEP_WIDTH && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[offset%KEEP_WIDTH])) begin \ - field = s_eth_payload_axis_tdata[(offset%KEEP_WIDTH)*8 +: 8]; \ + if (ptr_reg == offset/BYTE_LANES && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[offset%BYTE_LANES])) begin \ + field = s_eth_payload_axis_tdata[(offset%BYTE_LANES)*8 +: 8]; \ end `_HEADER_FIELD_(0, m_arp_htype_next[1*8 +: 8]) @@ -248,7 +250,7 @@ always @* begin `_HEADER_FIELD_(26, m_arp_tpa_next[1*8 +: 8]) `_HEADER_FIELD_(27, m_arp_tpa_next[0*8 +: 8]) - if (ptr_reg == 27/KEEP_WIDTH && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[27%KEEP_WIDTH])) begin + if (ptr_reg == 27/BYTE_LANES && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[27%BYTE_LANES])) begin read_arp_header_next = 1'b0; end diff --git a/rtl/arp_eth_tx.v b/rtl/arp_eth_tx.v index 535c397c3..4fde08a5f 100644 --- a/rtl/arp_eth_tx.v +++ b/rtl/arp_eth_tx.v @@ -82,17 +82,19 @@ module arp_eth_tx # output wire busy ); +parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1; + parameter HDR_SIZE = 28; -parameter CYCLE_COUNT = (HDR_SIZE+KEEP_WIDTH-1)/KEEP_WIDTH; +parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES; parameter PTR_WIDTH = $clog2(CYCLE_COUNT); -parameter OFFSET = HDR_SIZE % KEEP_WIDTH; +parameter OFFSET = HDR_SIZE % BYTE_LANES; // bus width assertions initial begin - if (KEEP_WIDTH * 8 != DATA_WIDTH) begin + if (BYTE_LANES * 8 != DATA_WIDTH) begin $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)"); $finish; end @@ -196,9 +198,9 @@ always @* begin m_eth_payload_axis_tuser_int = 1'b0; `define _HEADER_FIELD_(offset, field) \ - if (ptr_reg == offset/KEEP_WIDTH) begin \ - m_eth_payload_axis_tdata_int[(offset%KEEP_WIDTH)*8 +: 8] = field; \ - m_eth_payload_axis_tkeep_int[offset%KEEP_WIDTH] = 1'b1; \ + if (ptr_reg == offset/BYTE_LANES) begin \ + m_eth_payload_axis_tdata_int[(offset%BYTE_LANES)*8 +: 8] = field; \ + m_eth_payload_axis_tkeep_int[offset%BYTE_LANES] = 1'b1; \ end `_HEADER_FIELD_(0, arp_htype_reg[1*8 +: 8]) @@ -230,7 +232,7 @@ always @* begin `_HEADER_FIELD_(26, arp_tpa_reg[1*8 +: 8]) `_HEADER_FIELD_(27, arp_tpa_reg[0*8 +: 8]) - if (ptr_reg == 27/KEEP_WIDTH) begin + if (ptr_reg == 27/BYTE_LANES) begin m_eth_payload_axis_tlast_int = 1'b1; send_arp_header_next = 1'b0; end diff --git a/rtl/eth_axis_rx.v b/rtl/eth_axis_rx.v index 2c713935b..bd56e28e4 100644 --- a/rtl/eth_axis_rx.v +++ b/rtl/eth_axis_rx.v @@ -77,17 +77,19 @@ module eth_axis_rx # output wire error_header_early_termination ); +parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1; + parameter HDR_SIZE = 14; -parameter CYCLE_COUNT = (HDR_SIZE+KEEP_WIDTH-1)/KEEP_WIDTH; +parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES; parameter PTR_WIDTH = $clog2(CYCLE_COUNT); -parameter OFFSET = HDR_SIZE % KEEP_WIDTH; +parameter OFFSET = HDR_SIZE % BYTE_LANES; // bus width assertions initial begin - if (KEEP_WIDTH * 8 != DATA_WIDTH) begin + if (BYTE_LANES * 8 != DATA_WIDTH) begin $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)"); $finish; end @@ -215,8 +217,8 @@ always @* begin ptr_next = ptr_reg + 1; `define _HEADER_FIELD_(offset, field) \ - if (ptr_reg == offset/KEEP_WIDTH && (!KEEP_ENABLE || s_axis_tkeep[offset%KEEP_WIDTH])) begin \ - field = s_axis_tdata[(offset%KEEP_WIDTH)*8 +: 8]; \ + if (ptr_reg == offset/BYTE_LANES && (!KEEP_ENABLE || s_axis_tkeep[offset%BYTE_LANES])) begin \ + field = s_axis_tdata[(offset%BYTE_LANES)*8 +: 8]; \ end `_HEADER_FIELD_(0, m_eth_dest_mac_next[5*8 +: 8]) @@ -234,7 +236,7 @@ always @* begin `_HEADER_FIELD_(12, m_eth_type_next[1*8 +: 8]) `_HEADER_FIELD_(13, m_eth_type_next[0*8 +: 8]) - if (ptr_reg == 13/KEEP_WIDTH && (!KEEP_ENABLE || s_axis_tkeep[13%KEEP_WIDTH])) begin + if (ptr_reg == 13/BYTE_LANES && (!KEEP_ENABLE || s_axis_tkeep[13%BYTE_LANES])) begin if (!shift_axis_tlast) begin m_eth_hdr_valid_next = 1'b1; read_eth_header_next = 1'b0; diff --git a/rtl/eth_axis_tx.v b/rtl/eth_axis_tx.v index f0ee5f16a..28c73b73b 100644 --- a/rtl/eth_axis_tx.v +++ b/rtl/eth_axis_tx.v @@ -76,17 +76,19 @@ module eth_axis_tx # output wire busy ); +parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1; + parameter HDR_SIZE = 14; -parameter CYCLE_COUNT = (HDR_SIZE+KEEP_WIDTH-1)/KEEP_WIDTH; +parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES; parameter PTR_WIDTH = $clog2(CYCLE_COUNT); -parameter OFFSET = HDR_SIZE % KEEP_WIDTH; +parameter OFFSET = HDR_SIZE % BYTE_LANES; // bus width assertions initial begin - if (KEEP_WIDTH * 8 != DATA_WIDTH) begin + if (BYTE_LANES * 8 != DATA_WIDTH) begin $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)"); $finish; end @@ -240,9 +242,9 @@ always @* begin m_axis_tvalid_int = 1'b1; `define _HEADER_FIELD_(offset, field) \ - if (ptr_reg == offset/KEEP_WIDTH) begin \ - m_axis_tdata_int[(offset%KEEP_WIDTH)*8 +: 8] = field; \ - m_axis_tkeep_int[offset%KEEP_WIDTH] = 1'b1; \ + if (ptr_reg == offset/BYTE_LANES) begin \ + m_axis_tdata_int[(offset%BYTE_LANES)*8 +: 8] = field; \ + m_axis_tkeep_int[offset%BYTE_LANES] = 1'b1; \ end `_HEADER_FIELD_(0, eth_dest_mac_reg[5*8 +: 8]) @@ -260,7 +262,7 @@ always @* begin `_HEADER_FIELD_(12, eth_type_reg[1*8 +: 8]) `_HEADER_FIELD_(13, eth_type_reg[0*8 +: 8]) - if (ptr_reg == 13/KEEP_WIDTH) begin + if (ptr_reg == 13/BYTE_LANES) begin if (!send_eth_payload_reg) begin s_eth_payload_axis_tready_next = m_axis_tready_int_early; send_eth_payload_next = 1'b1;