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fpga/mqnic/DK_DEV_1SMX_H_A: Add virtual I2C switch to control modsel pins

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-06-11 02:05:37 -07:00
parent 5099e4a3d5
commit 9f808c65b2
11 changed files with 234 additions and 165 deletions
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4
docs/source/devicelist.rst
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@ -83,8 +83,8 @@ This section details PCIe form-factor targets, which interface with a separate h
NetFPGA SUME Y N :sup:`7` N :sup:`8`
250-SoC Y N N :sup:`9`
XUP-P3R Y Y Y
DK-DEV-1SMX-H-A N :sup:`3` N :sup:`7` N
DK-DEV-1SMC-H-A N :sup:`3` N :sup:`7` N
DK-DEV-1SMX-H-A Y N :sup:`7` N
DK-DEV-1SMC-H-A Y N :sup:`7` N
DK-DEV-1SDX-P-A Y N :sup:`3` N :sup:`10`
DK-DEV-AGF014EA Y N :sup:`3` N
DE10-Agilex Y N :sup:`7` N :sup:`10`

15
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga.qsf
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@ -324,20 +324,23 @@ set_location_assignment PIN_AG6 -to "qsfp1_rx_n[3]" ;# GXBR4F_RX_CH4N
set_location_assignment PIN_AJ9 -to "refclk_qsfp1_p" ;# REFCLK_GXBR4F_CHBP
set_location_assignment PIN_AJ10 -to "refclk_qsfp1_n" ;# REFCLK_GXBR4F_CHBN
set_location_assignment PIN_AW17 -to "qsfp0_modsel_l"
# modsel pin functions appear to be swapped, possibly BMC FW bug (other pins not checked)
# set_location_assignment PIN_AW17 -to "qsfp0_modsel_l"
set_location_assignment PIN_BA17 -to "qsfp0_modsel_l"
set_location_assignment PIN_AV16 -to "qsfp0_reset_l"
set_location_assignment PIN_AW16 -to "qsfp0_modprs_l"
set_location_assignment PIN_BC16 -to "qsfp0_lpmode"
set_location_assignment PIN_BB16 -to "qsfp0_int_l"
set_location_assignment PIN_BA17 -to "qsfp1_modsel_l"
# set_location_assignment PIN_BA17 -to "qsfp1_modsel_l"
set_location_assignment PIN_AW17 -to "qsfp1_modsel_l"
set_location_assignment PIN_AY16 -to "qsfp1_reset_l"
set_location_assignment PIN_AY15 -to "qsfp1_modprs_l"
set_location_assignment PIN_BE15 -to "qsfp1_lpmode"
set_location_assignment PIN_BF15 -to "qsfp1_int_l"
set_location_assignment PIN_BD16 -to "qsfp_s10_i2c_sda"
set_location_assignment PIN_BJ16 -to "qsfp_s10_i2c_scl"
set_location_assignment PIN_BD16 -to "qsfp_i2c_sda"
set_location_assignment PIN_BJ16 -to "qsfp_i2c_scl"
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp0_tx_p[*]"
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp0_rx_p[*]"
@ -363,8 +366,8 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp1_modprs_l"
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp1_lpmode"
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp1_int_l"
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp_s10_i2c_sda"
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp_s10_i2c_scl"
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp_i2c_sda"
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp_i2c_scl"
set_instance_assignment -name IO_STANDARD "Differential LVPECL" -to "refclk_qsfp0_p"
set_instance_assignment -name IO_STANDARD "Differential LVPECL" -to "refclk_qsfp1_p"

1
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile
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@ -55,6 +55,7 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v

1
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile
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@ -55,6 +55,7 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v

1
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile
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@ -55,6 +55,7 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v

1
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile
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@ -55,6 +55,7 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v

74
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v
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@ -205,7 +205,10 @@ module fpga #
output wire qsfp1_reset_l,
input wire qsfp1_modprs_l,
output wire qsfp1_lpmode,
input wire qsfp1_int_l
input wire qsfp1_int_l,
inout wire qsfp_i2c_scl,
inout wire qsfp_i2c_sda
);
// PTP configuration
@ -252,6 +255,46 @@ sync_reset_100mhz_inst (
.out(rst_100mhz)
);
// GPIO
wire qsfp0_int_l_int;
wire qsfp0_modprs_l_int;
wire qsfp1_int_l_int;
wire qsfp1_modprs_l_int;
wire qsfp_i2c_scl_i;
wire qsfp_i2c_scl_o;
wire qsfp_i2c_scl_t;
wire qsfp_i2c_sda_i;
wire qsfp_i2c_sda_o;
wire qsfp_i2c_sda_t;
reg qsfp_i2c_scl_o_reg;
reg qsfp_i2c_scl_t_reg;
reg qsfp_i2c_sda_o_reg;
reg qsfp_i2c_sda_t_reg;
always @(posedge pcie_clk) begin
qsfp_i2c_scl_o_reg <= qsfp_i2c_scl_o;
qsfp_i2c_scl_t_reg <= qsfp_i2c_scl_t;
qsfp_i2c_sda_o_reg <= qsfp_i2c_sda_o;
qsfp_i2c_sda_t_reg <= qsfp_i2c_sda_t;
end
sync_signal #(
.WIDTH(6),
.N(2)
)
sync_signal_inst (
.clk(pcie_clk),
.in({qsfp0_int_l, qsfp0_modprs_l, qsfp1_int_l, qsfp1_modprs_l,
qsfp_i2c_scl, qsfp_i2c_sda}),
.out({qsfp0_int_l_int, qsfp0_modprs_l_int, qsfp1_int_l_int, qsfp1_modprs_l_int,
qsfp_i2c_scl_i, qsfp_i2c_sda_i})
);
assign qsfp_i2c_scl = qsfp_i2c_scl_t_reg ? 1'bz : qsfp_i2c_scl_o_reg;
assign qsfp_i2c_sda = qsfp_i2c_sda_t_reg ? 1'bz : qsfp_i2c_sda_o_reg;
// PCIe
wire coreclkout_hip;
wire reset_status;
@ -620,10 +663,6 @@ pcie pcie_hip_inst (
// XGMII 10G PHY
// QSFP0
assign qsfp0_modsel_l = 1'b0;
assign qsfp0_reset_l = 1'b1;
assign qsfp0_lpmode = 1'b0;
wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int;
@ -771,10 +810,6 @@ qsfp0_eth_xcvr_phy_quad (
);
// QSFP1
assign qsfp1_modsel_l = 1'b0;
assign qsfp1_reset_l = 1'b1;
assign qsfp1_lpmode = 1'b0;
wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
@ -1188,6 +1223,12 @@ core_inst (
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_status_4),
.qsfp0_modsel_l(qsfp0_modsel_l),
.qsfp0_reset_l(qsfp0_reset_l),
.qsfp0_modprs_l(qsfp0_modprs_l_int),
.qsfp0_lpmode(qsfp0_lpmode),
.qsfp0_int_l(qsfp0_int_l_int),
.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
@ -1235,7 +1276,20 @@ core_inst (
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_status_4)
.qsfp1_rx_status_4(qsfp1_rx_status_4),
.qsfp1_modsel_l(qsfp1_modsel_l),
.qsfp1_reset_l(qsfp1_reset_l),
.qsfp1_modprs_l(qsfp1_modprs_l_int),
.qsfp1_lpmode(qsfp1_lpmode),
.qsfp1_int_l(qsfp1_int_l_int),
.qsfp_i2c_scl_i(qsfp_i2c_scl_i),
.qsfp_i2c_scl_o(qsfp_i2c_scl_o),
.qsfp_i2c_scl_t(qsfp_i2c_scl_t),
.qsfp_i2c_sda_i(qsfp_i2c_sda_i),
.qsfp_i2c_sda_o(qsfp_i2c_sda_o),
.qsfp_i2c_sda_t(qsfp_i2c_sda_t)
);
endmodule

250
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v
View File

@ -289,6 +289,12 @@ module fpga_core #
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
output wire qsfp0_modsel_l,
output wire qsfp0_reset_l,
input wire qsfp0_modprs_l,
output wire qsfp0_lpmode,
input wire qsfp0_int_l,
input wire qsfp1_tx_clk_1,
input wire qsfp1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1,
@ -336,7 +342,20 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4
input wire qsfp1_rx_status_4,
output wire qsfp1_modsel_l,
output wire qsfp1_reset_l,
input wire qsfp1_modprs_l,
output wire qsfp1_lpmode,
input wire qsfp1_int_l,
input wire qsfp_i2c_scl_i,
output wire qsfp_i2c_scl_o,
output wire qsfp_i2c_scl_t,
input wire qsfp_i2c_sda_i,
output wire qsfp_i2c_sda_o,
output wire qsfp_i2c_sda_t
);
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
@ -408,22 +427,22 @@ reg ctrl_reg_wr_ack_reg = 1'b0;
reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}};
reg ctrl_reg_rd_ack_reg = 1'b0;
wire qsfp_i2c_select_scl_o;
wire qsfp_i2c_select_sda_o;
wire [7:0] qsfp_i2c_select;
wire qsfp_i2c_scl_i_int = qsfp_i2c_scl_i & qsfp_i2c_scl_o;
wire qsfp_i2c_sda_i_int = qsfp_i2c_sda_i & qsfp_i2c_sda_o;
reg qsfp0_reset_reg = 1'b0;
reg qsfp0_lp_mode_reg = 1'b0;
// reg qsfp0_i2c_scl_o_reg = 1'b1;
// reg qsfp0_i2c_sda_o_reg = 1'b1;
reg qsfp0_lpmode_reg = 1'b0;
reg qsfp1_reset_reg = 1'b0;
reg qsfp1_lp_mode_reg = 1'b0;
// reg qsfp1_i2c_scl_o_reg = 1'b1;
// reg qsfp1_i2c_sda_o_reg = 1'b1;
reg qsfp1_lpmode_reg = 1'b0;
// reg fpga_boot_reg = 1'b0;
// reg qspi_clk_reg = 1'b0;
// reg qspi_cs_reg = 1'b1;
// reg [3:0] qspi_dq_o_reg = 4'd0;
// reg [3:0] qspi_dq_oe_reg = 4'd0;
reg qsfp_i2c_scl_o_reg = 1'b1;
reg qsfp_i2c_sda_o_reg = 1'b1;
assign ctrl_reg_wr_wait = 1'b0;
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg;
@ -431,26 +450,45 @@ assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg;
assign ctrl_reg_rd_wait = 1'b0;
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg;
// assign qsfp0_reset_n = !qsfp0_reset_reg;
// assign qsfp0_lp_mode = qsfp0_lp_mode_reg;
// assign qsfp0_i2c_scl_o = qsfp0_i2c_scl_o_reg;
// assign qsfp0_i2c_scl_t = qsfp0_i2c_scl_o_reg;
// assign qsfp0_i2c_sda_o = qsfp0_i2c_sda_o_reg;
// assign qsfp0_i2c_sda_t = qsfp0_i2c_sda_o_reg;
// assign qsfp1_reset_n = !qsfp1_reset_reg;
// assign qsfp1_lp_mode = qsfp1_lp_mode_reg;
// assign qsfp1_i2c_scl_o = qsfp1_i2c_scl_o_reg;
// assign qsfp1_i2c_scl_t = qsfp1_i2c_scl_o_reg;
// assign qsfp1_i2c_sda_o = qsfp1_i2c_sda_o_reg;
// assign qsfp1_i2c_sda_t = qsfp1_i2c_sda_o_reg;
assign qsfp0_lpmode = qsfp0_lpmode_reg;
assign qsfp0_modsel_l = !qsfp_i2c_select[0];
assign qsfp0_reset_l = !qsfp0_reset_reg;
// assign fpga_boot = fpga_boot_reg;
assign qsfp1_lpmode = qsfp1_lpmode_reg;
assign qsfp1_modsel_l = !qsfp_i2c_select[1];
assign qsfp1_reset_l = !qsfp1_reset_reg;
// assign qspi_clk = qspi_clk_reg;
// assign qspi_cs = qspi_cs_reg;
// assign qspi_dq_o = qspi_dq_o_reg;
// assign qspi_dq_oe = qspi_dq_oe_reg;
assign qsfp_i2c_scl_o = qsfp_i2c_scl_o_reg & qsfp_i2c_select_scl_o;
assign qsfp_i2c_scl_t = qsfp_i2c_scl_o;
assign qsfp_i2c_sda_o = qsfp_i2c_sda_o_reg & qsfp_i2c_select_sda_o;
assign qsfp_i2c_sda_t = qsfp_i2c_sda_o;
i2c_single_reg #(
.FILTER_LEN(4),
.DEV_ADDR(7'h74)
)
qsfp_i2c_select_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* I2C interface
*/
.scl_i(qsfp_i2c_scl_i_int),
.scl_o(qsfp_i2c_select_scl_o),
.scl_t(),
.sda_i(qsfp_i2c_sda_i_int),
.sda_o(qsfp_i2c_select_sda_o),
.sda_t(),
/*
* Data register
*/
.data_in(8'd0),
.data_latch(1'b0),
.data_out(qsfp_i2c_select)
);
always @(posedge clk_250mhz) begin
ctrl_reg_wr_ack_reg <= 1'b0;
@ -461,54 +499,28 @@ always @(posedge clk_250mhz) begin
// write operation
ctrl_reg_wr_ack_reg <= 1'b0;
case ({ctrl_reg_wr_addr >> 2, 2'b00})
// 16'h0040: begin
// // FPGA ID
// fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD;
// end
// GPIO
// 16'h0110: begin
// // GPIO I2C 0
// if (ctrl_reg_wr_strb[0]) begin
// qsfp0_i2c_scl_o_reg <= ctrl_reg_wr_data[1];
// end
// if (ctrl_reg_wr_strb[1]) begin
// qsfp0_i2c_sda_o_reg <= ctrl_reg_wr_data[9];
// end
// end
// 16'h0114: begin
// // GPIO I2C 1
// if (ctrl_reg_wr_strb[0]) begin
// qsfp1_i2c_scl_o_reg <= ctrl_reg_wr_data[1];
// end
// if (ctrl_reg_wr_strb[1]) begin
// qsfp1_i2c_sda_o_reg <= ctrl_reg_wr_data[9];
// end
// end
// 16'h0120: begin
// // GPIO XCVR 0123
// if (ctrl_reg_wr_strb[0]) begin
// qsfp0_reset_reg <= ctrl_reg_wr_data[4];
// qsfp0_lp_mode_reg <= ctrl_reg_wr_data[5];
// end
// if (ctrl_reg_wr_strb[1]) begin
// qsfp1_reset_reg <= ctrl_reg_wr_data[12];
// qsfp1_lp_mode_reg <= ctrl_reg_wr_data[13];
// end
// end
// Flash
// 16'h0144: begin
// // QSPI control
// if (ctrl_reg_wr_strb[0]) begin
// qspi_dq_o_reg <= ctrl_reg_wr_data[3:0];
// end
// if (ctrl_reg_wr_strb[1]) begin
// qspi_dq_oe_reg <= ctrl_reg_wr_data[11:8];
// end
// if (ctrl_reg_wr_strb[2]) begin
// qspi_clk_reg <= ctrl_reg_wr_data[16];
// qspi_cs_reg <= ctrl_reg_wr_data[17];
// end
// end
// I2C 0
RBB+8'h0C: begin
// I2C ctrl: control
if (ctrl_reg_wr_strb[0]) begin
qsfp_i2c_scl_o_reg <= ctrl_reg_wr_data[1];
end
if (ctrl_reg_wr_strb[1]) begin
qsfp_i2c_sda_o_reg <= ctrl_reg_wr_data[9];
end
end
// XCVR GPIO
RBB+8'h1C: begin
// XCVR GPIO: control 0123
if (ctrl_reg_wr_strb[0]) begin
qsfp0_reset_reg <= ctrl_reg_wr_data[4];
qsfp0_lpmode_reg <= ctrl_reg_wr_data[5];
end
if (ctrl_reg_wr_strb[1]) begin
qsfp1_reset_reg <= ctrl_reg_wr_data[12];
qsfp1_lpmode_reg <= ctrl_reg_wr_data[13];
end
end
default: ctrl_reg_wr_ack_reg <= 1'b0;
endcase
end
@ -517,48 +529,32 @@ always @(posedge clk_250mhz) begin
// read operation
ctrl_reg_rd_ack_reg <= 1'b1;
case ({ctrl_reg_rd_addr >> 2, 2'b00})
// 16'h0040: ctrl_reg_rd_data_reg <= FPGA_ID; // FPGA ID
// GPIO
// 16'h0110: begin
// // GPIO I2C 0
// ctrl_reg_rd_data_reg[0] <= qsfp0_i2c_scl_i;
// ctrl_reg_rd_data_reg[1] <= qsfp0_i2c_scl_o_reg;
// ctrl_reg_rd_data_reg[8] <= qsfp0_i2c_sda_i;
// ctrl_reg_rd_data_reg[9] <= qsfp0_i2c_sda_o_reg;
// end
// 16'h0114: begin
// // GPIO I2C 1
// ctrl_reg_rd_data_reg[0] <= qsfp1_i2c_scl_i;
// ctrl_reg_rd_data_reg[1] <= qsfp1_i2c_scl_o_reg;
// ctrl_reg_rd_data_reg[8] <= qsfp1_i2c_sda_i;
// ctrl_reg_rd_data_reg[9] <= qsfp1_i2c_sda_o_reg;
// end
// 16'h0120: begin
// // GPIO XCVR 0123
// ctrl_reg_rd_data_reg[0] <= !qsfp0_mod_prsnt_n;
// ctrl_reg_rd_data_reg[1] <= !qsfp0_intr_n;
// ctrl_reg_rd_data_reg[4] <= qsfp0_reset_reg;
// ctrl_reg_rd_data_reg[5] <= qsfp0_lp_mode_reg;
// ctrl_reg_rd_data_reg[8] <= !qsfp1_mod_prsnt_n;
// ctrl_reg_rd_data_reg[9] <= !qsfp1_intr_n;
// ctrl_reg_rd_data_reg[12] <= qsfp1_reset_reg;
// ctrl_reg_rd_data_reg[13] <= qsfp1_lp_mode_reg;
// end
// Flash
// 16'h0140: begin
// // Flash ID
// ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
// ctrl_reg_rd_data_reg[15:8] <= 1; // configuration (one segment)
// ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
// ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
// end
// 16'h0144: begin
// // QSPI control
// ctrl_reg_rd_data_reg[3:0] <= qspi_dq_i;
// ctrl_reg_rd_data_reg[11:8] <= qspi_dq_oe;
// ctrl_reg_rd_data_reg[16] <= qspi_clk;
// ctrl_reg_rd_data_reg[17] <= qspi_cs;
// end
// I2C 0
RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version
RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header
RBB+8'h0C: begin
// I2C ctrl: control
ctrl_reg_rd_data_reg[0] <= qsfp_i2c_scl_i_int;
ctrl_reg_rd_data_reg[1] <= qsfp_i2c_scl_o_reg;
ctrl_reg_rd_data_reg[8] <= qsfp_i2c_sda_i_int;
ctrl_reg_rd_data_reg[9] <= qsfp_i2c_sda_o_reg;
end
// XCVR GPIO
RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type
RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version
RBB+8'h18: ctrl_reg_rd_data_reg <= 0; // XCVR GPIO: Next header
RBB+8'h1C: begin
// XCVR GPIO: control 0123
ctrl_reg_rd_data_reg[0] <= !qsfp0_modprs_l;
ctrl_reg_rd_data_reg[1] <= !qsfp0_int_l;
ctrl_reg_rd_data_reg[4] <= qsfp0_reset_reg;
ctrl_reg_rd_data_reg[5] <= qsfp0_lpmode_reg;
ctrl_reg_rd_data_reg[8] <= !qsfp1_modprs_l;
ctrl_reg_rd_data_reg[9] <= !qsfp1_int_l;
ctrl_reg_rd_data_reg[12] <= qsfp1_reset_reg;
ctrl_reg_rd_data_reg[13] <= qsfp1_lpmode_reg;
end
default: ctrl_reg_rd_ack_reg <= 1'b0;
endcase
end
@ -568,19 +564,13 @@ always @(posedge clk_250mhz) begin
ctrl_reg_rd_ack_reg <= 1'b0;
qsfp0_reset_reg <= 1'b0;
qsfp0_lp_mode_reg <= 1'b0;
// qsfp0_i2c_scl_o_reg <= 1'b1;
// qsfp0_i2c_sda_o_reg <= 1'b1;
qsfp0_lpmode_reg <= 1'b0;
qsfp1_reset_reg <= 1'b0;
qsfp1_lp_mode_reg <= 1'b0;
// qsfp1_i2c_scl_o_reg <= 1'b1;
// qsfp1_i2c_sda_o_reg <= 1'b1;
qsfp1_lpmode_reg <= 1'b0;
// qspi_clk_reg <= 1'b0;
// qspi_cs_reg <= 1'b1;
// qspi_dq_o_reg <= 4'd0;
// qspi_dq_oe_reg <= 4'd0;
qsfp_i2c_scl_o_reg <= 1'b1;
qsfp_i2c_sda_o_reg <= 1'b1;
end
end

1
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile
View File

@ -84,6 +84,7 @@ VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
VERILOG_SOURCES += ../../rtl/common/i2c_single_reg.v
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v

32
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -279,27 +279,24 @@ class TB(object):
dut.qsfp1_rx_status_3.setimmediatevalue(1)
dut.qsfp1_rx_status_4.setimmediatevalue(1)
# dut.qsfp0_i2c_scl_i.setimmediatevalue(1)
# dut.qsfp0_i2c_sda_i.setimmediatevalue(1)
# dut.qsfp0_intr_n.setimmediatevalue(1)
# dut.qsfp0_mod_prsnt_n.setimmediatevalue(0)
dut.qsfp0_rx_error_count_1.setimmediatevalue(0)
dut.qsfp0_rx_error_count_2.setimmediatevalue(0)
dut.qsfp0_rx_error_count_3.setimmediatevalue(0)
dut.qsfp0_rx_error_count_4.setimmediatevalue(0)
# dut.qsfp0_rx_error_count_0.setimmediatevalue(0)
# dut.qsfp0_rx_error_count_1.setimmediatevalue(0)
# dut.qsfp0_rx_error_count_2.setimmediatevalue(0)
# dut.qsfp0_rx_error_count_3.setimmediatevalue(0)
dut.qsfp1_rx_error_count_1.setimmediatevalue(0)
dut.qsfp1_rx_error_count_2.setimmediatevalue(0)
dut.qsfp1_rx_error_count_3.setimmediatevalue(0)
dut.qsfp1_rx_error_count_4.setimmediatevalue(0)
# dut.qsfp1_i2c_scl_i.setimmediatevalue(1)
# dut.qsfp1_i2c_sda_i.setimmediatevalue(1)
# dut.qsfp1_intr_n.setimmediatevalue(1)
# dut.qsfp1_mod_prsnt_n.setimmediatevalue(0)
dut.qsfp0_modprs_l.setimmediatevalue(0)
dut.qsfp0_int_l.setimmediatevalue(1)
# dut.qsfp1_rx_error_count_0.setimmediatevalue(0)
# dut.qsfp1_rx_error_count_1.setimmediatevalue(0)
# dut.qsfp1_rx_error_count_2.setimmediatevalue(0)
# dut.qsfp1_rx_error_count_3.setimmediatevalue(0)
dut.qsfp1_modprs_l.setimmediatevalue(0)
dut.qsfp1_int_l.setimmediatevalue(1)
# dut.qspi_dq_i.setimmediatevalue(0)
dut.qsfp_i2c_scl_i.setimmediatevalue(1)
dut.qsfp_i2c_sda_i.setimmediatevalue(1)
self.loopback_enable = False
cocotb.start_soon(self._run_loopback())
@ -634,6 +631,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
os.path.join(rtl_dir, "common", "tdma_ber.v"),
os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
os.path.join(rtl_dir, "common", "i2c_single_reg.v"),
os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),

19
modules/mqnic/mqnic_board.c
View File

@ -430,6 +430,25 @@ static int mqnic_generic_board_init(struct mqnic_dev *mqnic)
// read MACs from EEPROM
init_mac_list_from_eeprom_base(mqnic, mqnic->eeprom_i2c_client, 0x20, MQNIC_MAX_IF);
break;
case MQNIC_BOARD_ID_DK_DEV_1SMX_H_A:
request_module("at24");
// I2C adapter
adapter = mqnic_i2c_adapter_create(mqnic, 0);
// Virtual I2C MUX
mux = create_i2c_client(adapter, "pca9543", 0x74);
// J4 QSFP0
mqnic->mod_i2c_client[0] = create_i2c_client(get_i2c_mux_channel(mux, 0), "24c02", 0x50);
// J5 QSFP1
mqnic->mod_i2c_client[1] = create_i2c_client(get_i2c_mux_channel(mux, 1), "24c02", 0x50);
mqnic->mod_i2c_client_count = 2;
break;
case MQNIC_BOARD_ID_DK_DEV_1SDX_P_A: