From a0f46801a1b9d067d5ff317de9a019660e5e6abe Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 1 Nov 2022 14:40:58 -0700 Subject: [PATCH] Replace OUTPUT_PIPELINE with RAM_PIPELINE Signed-off-by: Alex Forencich --- rtl/axis_async_fifo.v | 29 ++++++++----------- rtl/axis_async_fifo_adapter.v | 6 ++-- rtl/axis_fifo.v | 23 ++++++--------- rtl/axis_fifo_adapter.v | 6 ++-- tb/axis_async_fifo/Makefile | 6 ++-- tb/axis_async_fifo/test_axis_async_fifo.py | 8 +++-- tb/axis_async_fifo_adapter/Makefile | 3 ++ .../test_axis_async_fifo_adapter.py | 1 + tb/axis_fifo/Makefile | 6 ++-- tb/axis_fifo/test_axis_fifo.py | 8 +++-- tb/axis_fifo_adapter/Makefile | 3 ++ .../test_axis_fifo_adapter.py | 1 + 12 files changed, 52 insertions(+), 48 deletions(-) diff --git a/rtl/axis_async_fifo.v b/rtl/axis_async_fifo.v index ff6d0f85f..f646e896e 100644 --- a/rtl/axis_async_fifo.v +++ b/rtl/axis_async_fifo.v @@ -58,8 +58,8 @@ module axis_async_fifo # parameter USER_ENABLE = 1, // tuser signal width parameter USER_WIDTH = 1, - // number of output pipeline registers - parameter PIPELINE_OUTPUT = 2, + // number of RAM pipeline registers + parameter RAM_PIPELINE = 1, // Frame FIFO mode - operate on frames instead of cycles // When set, m_axis_tvalid will not be deasserted within a frame // Requires LAST_ENABLE set @@ -123,11 +123,6 @@ parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH // check configuration initial begin - if (PIPELINE_OUTPUT < 1) begin - $error("Error: PIPELINE_OUTPUT must be at least 1 (instance %m)"); - $finish; - end - if (FRAME_FIFO && !LAST_ENABLE) begin $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)"); $finish; @@ -212,8 +207,8 @@ reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0]; reg [WIDTH-1:0] mem_read_data_reg; reg mem_read_data_valid_reg = 1'b0; -reg [WIDTH-1:0] m_axis_pipe_reg[PIPELINE_OUTPUT-1:0]; -reg [PIPELINE_OUTPUT-1:0] m_axis_tvalid_pipe_reg = 1'b0; +reg [WIDTH-1:0] m_axis_pipe_reg[RAM_PIPELINE+1-1:0]; +reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0; // full when first TWO MSBs do NOT match, but rest matches // (gray code equivalent of first MSB different but rest same) @@ -267,9 +262,9 @@ generate if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser; endgenerate -wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1]; +wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1]; -wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[PIPELINE_OUTPUT-1]; +wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1]; wire [DATA_WIDTH-1:0] m_axis_tdata_pipe = m_axis[DATA_WIDTH-1:0]; wire [KEEP_WIDTH-1:0] m_axis_tkeep_pipe = KEEP_ENABLE ? m_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}}; @@ -549,11 +544,11 @@ integer j; always @(posedge m_clk) begin if (m_axis_tready) begin // output ready; invalidate stage - m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1] <= 1'b0; + m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0; m_terminate_frame_reg <= 1'b0; end - for (j = PIPELINE_OUTPUT-1; j > 0; j = j - 1) begin + for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin if (m_axis_tready || ((~m_axis_tvalid_pipe_reg) >> j)) begin // output ready or bubble in pipeline; transfer down pipeline m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1]; @@ -587,7 +582,7 @@ always @(posedge m_clk) begin if (m_drop_frame_reg && (m_axis_tready || !m_axis_tvalid_pipe) && LAST_ENABLE) begin // terminate frame // (only for frame transfers interrupted by source reset) - m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1] <= 1'b1; + m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b1; m_terminate_frame_reg <= 1'b1; m_drop_frame_reg <= 1'b0; end @@ -596,8 +591,8 @@ always @(posedge m_clk) begin // if source side is reset during transfer, drop partial frame // empty output pipeline, except for last stage - if (PIPELINE_OUTPUT > 1) begin - m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-2:0] <= 0; + if (RAM_PIPELINE > 0) begin + m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-2:0] <= 0; end if (m_frame_reg && (!m_axis_tvalid || (m_axis_tvalid && !m_axis_tlast)) && @@ -615,7 +610,7 @@ always @(posedge m_clk) begin if (m_rst) begin rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}}; - m_axis_tvalid_pipe_reg <= {PIPELINE_OUTPUT{1'b0}}; + m_axis_tvalid_pipe_reg <= 0; m_frame_reg <= 1'b0; m_drop_frame_reg <= 1'b0; m_terminate_frame_reg <= 1'b0; diff --git a/rtl/axis_async_fifo_adapter.v b/rtl/axis_async_fifo_adapter.v index 848fcf501..a44ddb0cc 100644 --- a/rtl/axis_async_fifo_adapter.v +++ b/rtl/axis_async_fifo_adapter.v @@ -63,8 +63,8 @@ module axis_async_fifo_adapter # parameter USER_ENABLE = 1, // tuser signal width parameter USER_WIDTH = 1, - // number of output pipeline registers - parameter PIPELINE_OUTPUT = 2, + // number of RAM pipeline registers in FIFO + parameter RAM_PIPELINE = 1, // Frame FIFO mode - operate on frames instead of cycles // When set, m_axis_tvalid will not be deasserted within a frame // Requires LAST_ENABLE set @@ -314,7 +314,7 @@ axis_async_fifo #( .DEST_WIDTH(DEST_WIDTH), .USER_ENABLE(USER_ENABLE), .USER_WIDTH(USER_WIDTH), - .PIPELINE_OUTPUT(PIPELINE_OUTPUT), + .RAM_PIPELINE(RAM_PIPELINE), .FRAME_FIFO(FRAME_FIFO), .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE), .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK), diff --git a/rtl/axis_fifo.v b/rtl/axis_fifo.v index 2c9e3b30b..5a1c201b3 100644 --- a/rtl/axis_fifo.v +++ b/rtl/axis_fifo.v @@ -58,8 +58,8 @@ module axis_fifo # parameter USER_ENABLE = 1, // tuser signal width parameter USER_WIDTH = 1, - // number of output pipeline registers - parameter PIPELINE_OUTPUT = 2, + // number of RAM pipeline registers + parameter RAM_PIPELINE = 1, // Frame FIFO mode - operate on frames instead of cycles // When set, m_axis_tvalid will not be deasserted within a frame // Requires LAST_ENABLE set @@ -119,11 +119,6 @@ parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH // check configuration initial begin - if (PIPELINE_OUTPUT < 1) begin - $error("Error: PIPELINE_OUTPUT must be at least 1 (instance %m)"); - $finish; - end - if (FRAME_FIFO && !LAST_ENABLE) begin $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)"); $finish; @@ -166,8 +161,8 @@ reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0]; reg [WIDTH-1:0] mem_read_data_reg; reg mem_read_data_valid_reg = 1'b0; -reg [WIDTH-1:0] m_axis_pipe_reg[PIPELINE_OUTPUT-1:0]; -reg [PIPELINE_OUTPUT-1:0] m_axis_tvalid_pipe_reg = 1'b0; +reg [WIDTH-1:0] m_axis_pipe_reg[RAM_PIPELINE+1-1:0]; +reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0; // full when first MSB different but rest same wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); @@ -196,9 +191,9 @@ generate if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser; endgenerate -assign m_axis_tvalid = m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1]; +assign m_axis_tvalid = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1]; -wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[PIPELINE_OUTPUT-1]; +wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1]; assign m_axis_tdata = m_axis[DATA_WIDTH-1:0]; assign m_axis_tkeep = KEEP_ENABLE ? m_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}}; @@ -276,10 +271,10 @@ integer j; always @(posedge clk) begin if (m_axis_tready) begin // output ready; invalidate stage - m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1] <= 1'b0; + m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0; end - for (j = PIPELINE_OUTPUT-1; j > 0; j = j - 1) begin + for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin if (m_axis_tready || ((~m_axis_tvalid_pipe_reg) >> j)) begin // output ready or bubble in pipeline; transfer down pipeline m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1]; @@ -301,7 +296,7 @@ always @(posedge clk) begin if (rst) begin rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; - m_axis_tvalid_pipe_reg <= {PIPELINE_OUTPUT{1'b0}}; + m_axis_tvalid_pipe_reg <= 0; end end diff --git a/rtl/axis_fifo_adapter.v b/rtl/axis_fifo_adapter.v index 095d6ce74..759918319 100644 --- a/rtl/axis_fifo_adapter.v +++ b/rtl/axis_fifo_adapter.v @@ -63,8 +63,8 @@ module axis_fifo_adapter # parameter USER_ENABLE = 1, // tuser signal width parameter USER_WIDTH = 1, - // number of output pipeline registers - parameter PIPELINE_OUTPUT = 2, + // number of RAM pipeline registers in FIFO + parameter RAM_PIPELINE = 1, // Frame FIFO mode - operate on frames instead of cycles // When set, m_axis_tvalid will not be deasserted within a frame // Requires LAST_ENABLE set @@ -309,7 +309,7 @@ axis_fifo #( .DEST_WIDTH(DEST_WIDTH), .USER_ENABLE(USER_ENABLE), .USER_WIDTH(USER_WIDTH), - .PIPELINE_OUTPUT(PIPELINE_OUTPUT), + .RAM_PIPELINE(RAM_PIPELINE), .FRAME_FIFO(FRAME_FIFO), .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE), .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK), diff --git a/tb/axis_async_fifo/Makefile b/tb/axis_async_fifo/Makefile index f301f8b45..125d98c2f 100644 --- a/tb/axis_async_fifo/Makefile +++ b/tb/axis_async_fifo/Makefile @@ -43,7 +43,7 @@ export PARAM_DEST_ENABLE ?= 1 export PARAM_DEST_WIDTH ?= 8 export PARAM_USER_ENABLE ?= 1 export PARAM_USER_WIDTH ?= 1 -export PARAM_PIPELINE_OUTPUT ?= 2 +export PARAM_RAM_PIPELINE ?= 1 export PARAM_FRAME_FIFO ?= 1 export PARAM_USER_BAD_FRAME_VALUE ?= 1 export PARAM_USER_BAD_FRAME_MASK ?= 1 @@ -65,7 +65,7 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).FRAME_FIFO=$(PARAM_FRAME_FIFO) COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) @@ -91,7 +91,7 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GPIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT) + COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) COMPILE_ARGS += -GFRAME_FIFO=$(PARAM_FRAME_FIFO) COMPILE_ARGS += -GUSER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) COMPILE_ARGS += -GUSER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) diff --git a/tb/axis_async_fifo/test_axis_async_fifo.py b/tb/axis_async_fifo/test_axis_async_fifo.py index fb3026d8b..4bd5e0ad3 100644 --- a/tb/axis_async_fifo/test_axis_async_fifo.py +++ b/tb/axis_async_fifo/test_axis_async_fifo.py @@ -522,9 +522,11 @@ rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) @pytest.mark.parametrize(("s_clk", "m_clk"), [(10, 10), (10, 11), (11, 10)]) @pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame", "drop_when_full"), [(0, 0, 0, 0), (1, 0, 0, 0), (1, 1, 0, 0), (1, 1, 1, 0)]) +@pytest.mark.parametrize(("ram_pipeline"), + [0, 1, 4]) @pytest.mark.parametrize("data_width", [8, 16, 32, 64]) -def test_axis_async_fifo(request, data_width, frame_fifo, drop_oversize_frame, drop_bad_frame, - drop_when_full, s_clk, m_clk): +def test_axis_async_fifo(request, data_width, ram_pipeline, + frame_fifo, drop_oversize_frame, drop_bad_frame, drop_when_full, s_clk, m_clk): dut = "axis_async_fifo" module = os.path.splitext(os.path.basename(__file__))[0] @@ -547,7 +549,7 @@ def test_axis_async_fifo(request, data_width, frame_fifo, drop_oversize_frame, d parameters['DEST_WIDTH'] = 8 parameters['USER_ENABLE'] = 1 parameters['USER_WIDTH'] = 1 - parameters['PIPELINE_OUTPUT'] = 2 + parameters['RAM_PIPELINE'] = ram_pipeline parameters['FRAME_FIFO'] = frame_fifo parameters['USER_BAD_FRAME_VALUE'] = 1 parameters['USER_BAD_FRAME_MASK'] = 1 diff --git a/tb/axis_async_fifo_adapter/Makefile b/tb/axis_async_fifo_adapter/Makefile index c193ebb0d..0acd2ffdc 100644 --- a/tb/axis_async_fifo_adapter/Makefile +++ b/tb/axis_async_fifo_adapter/Makefile @@ -48,6 +48,7 @@ export PARAM_DEST_ENABLE ?= 1 export PARAM_DEST_WIDTH ?= 8 export PARAM_USER_ENABLE ?= 1 export PARAM_USER_WIDTH ?= 1 +export PARAM_RAM_PIPELINE ?= 1 export PARAM_FRAME_FIFO ?= 1 export PARAM_USER_BAD_FRAME_VALUE ?= 1 export PARAM_USER_BAD_FRAME_MASK ?= 1 @@ -71,6 +72,7 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).FRAME_FIFO=$(PARAM_FRAME_FIFO) COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) @@ -98,6 +100,7 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) COMPILE_ARGS += -GFRAME_FIFO=$(PARAM_FRAME_FIFO) COMPILE_ARGS += -GUSER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) COMPILE_ARGS += -GUSER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) diff --git a/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py b/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py index bae15ef00..44f05e1ec 100644 --- a/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py +++ b/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py @@ -546,6 +546,7 @@ def test_axis_async_fifo_adapter(request, s_data_width, m_data_width, frame_fifo parameters['DEST_WIDTH'] = 8 parameters['USER_ENABLE'] = 1 parameters['USER_WIDTH'] = 1 + parameters['RAM_PIPELINE'] = 1 parameters['FRAME_FIFO'] = frame_fifo parameters['USER_BAD_FRAME_VALUE'] = 1 parameters['USER_BAD_FRAME_MASK'] = 1 diff --git a/tb/axis_fifo/Makefile b/tb/axis_fifo/Makefile index fabad14d2..c5d57ca82 100644 --- a/tb/axis_fifo/Makefile +++ b/tb/axis_fifo/Makefile @@ -43,7 +43,7 @@ export PARAM_DEST_ENABLE ?= 1 export PARAM_DEST_WIDTH ?= 8 export PARAM_USER_ENABLE ?= 1 export PARAM_USER_WIDTH ?= 1 -export PARAM_PIPELINE_OUTPUT ?= 2 +export PARAM_RAM_PIPELINE ?= 1 export PARAM_FRAME_FIFO ?= 1 export PARAM_USER_BAD_FRAME_VALUE ?= 1 export PARAM_USER_BAD_FRAME_MASK ?= 1 @@ -65,7 +65,7 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).FRAME_FIFO=$(PARAM_FRAME_FIFO) COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) @@ -91,7 +91,7 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GPIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT) + COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) COMPILE_ARGS += -GFRAME_FIFO=$(PARAM_FRAME_FIFO) COMPILE_ARGS += -GUSER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) COMPILE_ARGS += -GUSER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) diff --git a/tb/axis_fifo/test_axis_fifo.py b/tb/axis_fifo/test_axis_fifo.py index db13ca87b..2615bc7c3 100644 --- a/tb/axis_fifo/test_axis_fifo.py +++ b/tb/axis_fifo/test_axis_fifo.py @@ -314,8 +314,12 @@ rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) @pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame", "drop_when_full"), [(0, 0, 0, 0), (1, 0, 0, 0), (1, 1, 0, 0), (1, 1, 1, 0)]) +@pytest.mark.parametrize(("ram_pipeline"), + [0, 1, 4]) @pytest.mark.parametrize("data_width", [8, 16, 32, 64]) -def test_axis_fifo(request, data_width, frame_fifo, drop_oversize_frame, drop_bad_frame, drop_when_full): +def test_axis_fifo(request, data_width, ram_pipeline, + frame_fifo, drop_oversize_frame, drop_bad_frame, drop_when_full): + dut = "axis_fifo" module = os.path.splitext(os.path.basename(__file__))[0] toplevel = dut @@ -337,7 +341,7 @@ def test_axis_fifo(request, data_width, frame_fifo, drop_oversize_frame, drop_ba parameters['DEST_WIDTH'] = 8 parameters['USER_ENABLE'] = 1 parameters['USER_WIDTH'] = 1 - parameters['PIPELINE_OUTPUT'] = 2 + parameters['RAM_PIPELINE'] = ram_pipeline parameters['FRAME_FIFO'] = frame_fifo parameters['USER_BAD_FRAME_VALUE'] = 1 parameters['USER_BAD_FRAME_MASK'] = 1 diff --git a/tb/axis_fifo_adapter/Makefile b/tb/axis_fifo_adapter/Makefile index 86e3f2f3c..35e3922be 100644 --- a/tb/axis_fifo_adapter/Makefile +++ b/tb/axis_fifo_adapter/Makefile @@ -48,6 +48,7 @@ export PARAM_DEST_ENABLE ?= 1 export PARAM_DEST_WIDTH ?= 8 export PARAM_USER_ENABLE ?= 1 export PARAM_USER_WIDTH ?= 1 +export PARAM_RAM_PIPELINE ?= 1 export PARAM_FRAME_FIFO ?= 1 export PARAM_USER_BAD_FRAME_VALUE ?= 1 export PARAM_USER_BAD_FRAME_MASK ?= 1 @@ -71,6 +72,7 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).FRAME_FIFO=$(PARAM_FRAME_FIFO) COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) @@ -98,6 +100,7 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) COMPILE_ARGS += -GFRAME_FIFO=$(PARAM_FRAME_FIFO) COMPILE_ARGS += -GUSER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) COMPILE_ARGS += -GUSER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) diff --git a/tb/axis_fifo_adapter/test_axis_fifo_adapter.py b/tb/axis_fifo_adapter/test_axis_fifo_adapter.py index bc3fc76ec..5f0ae6d73 100644 --- a/tb/axis_fifo_adapter/test_axis_fifo_adapter.py +++ b/tb/axis_fifo_adapter/test_axis_fifo_adapter.py @@ -342,6 +342,7 @@ def test_axis_fifo_adapter(request, s_data_width, m_data_width, frame_fifo, drop parameters['DEST_WIDTH'] = 8 parameters['USER_ENABLE'] = 1 parameters['USER_WIDTH'] = 1 + parameters['RAM_PIPELINE'] = 1 parameters['FRAME_FIFO'] = frame_fifo parameters['USER_BAD_FRAME_VALUE'] = 1 parameters['USER_BAD_FRAME_MASK'] = 1