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Add arbiter module

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Alex Forencich 2014-11-13 01:22:59 -08:00
parent 3399f284b2
commit a1633f27d8
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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Arbiter module
*/
module arbiter #
(
parameter PORTS = 4,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter TYPE = "PRIORITY",
// block until request deassert: "TRUE" or "FALSE"
parameter BLOCK = "TRUE"
)
(
input wire clk,
input wire rst,
input wire [PORTS-1:0] request,
output wire [PORTS-1:0] grant,
output wire grant_valid,
output wire [$clog2(PORTS)-1:0] grant_encoded
);
reg [PORTS-1:0] grant_reg = 0, grant_next;
reg grant_valid_reg = 0, grant_valid_next;
reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next;
assign grant_valid = grant_valid_reg;
assign grant = grant_reg;
assign grant_encoded = grant_encoded_reg;
wire request_valid;
wire [$clog2(PORTS)-1:0] request_index;
wire [PORTS-1:0] request_mask;
priority_encoder #(
.WIDTH(PORTS)
)
priority_encoder_inst (
.input_unencoded(request),
.output_valid(request_valid),
.output_encoded(request_index),
.output_unencoded(request_mask)
);
reg [PORTS-1:0] mask_reg = 0, mask_next;
wire masked_request_valid;
wire [$clog2(PORTS)-1:0] masked_request_index;
wire [PORTS-1:0] masked_request_mask;
priority_encoder #(
.WIDTH(PORTS)
)
priority_encoder_masked (
.input_unencoded(request & mask_reg),
.output_valid(masked_request_valid),
.output_encoded(masked_request_index),
.output_unencoded(masked_request_mask)
);
always @* begin
grant_next = 0;
grant_valid_next = 0;
grant_encoded_next = 0;
mask_next = mask_reg;
if (BLOCK == "TRUE" && grant_reg & request) begin
// granted request still asserted; hold it
grant_valid_next = grant_valid_reg;
grant_next = grant_reg;
grant_encoded_next = grant_encoded_reg;
end else if (request_valid) begin
if (TYPE == "PRIORITY") begin
grant_valid_next = 1;
grant_next = request_mask;
grant_encoded_next = request_index;
end else if (TYPE == "ROUND_ROBIN") begin
if (masked_request_valid) begin
grant_valid_next = 1;
grant_next = masked_request_mask;
grant_encoded_next = masked_request_index;
mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
end else begin
grant_valid_next = 1;
grant_next = request_mask;
grant_encoded_next = request_index;
mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
end
end
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
grant_reg <= 0;
grant_valid_reg <= 0;
grant_encoded_reg <= 0;
mask_reg <= 0;
end else begin
grant_reg <= grant_next;
grant_valid_reg <= grant_valid_next;
grant_encoded_reg <= grant_encoded_next;
mask_reg <= mask_next;
end
end
endmodule

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#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
module = 'arbiter'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/priority_encoder.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_arbiter(clk,
rst,
current_test,
request,
grant,
grant_valid,
grant_encoded):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
request=request,
grant=grant,
grant_valid=grant_valid,
grant_encoded=grant_encoded)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
request = Signal(intbv(0)[32:])
# Outputs
grant = Signal(intbv(0)[32:])
grant_valid = Signal(bool(0))
grant_encoded = Signal(intbv(0)[5:])
# DUT
dut = dut_arbiter(clk,
rst,
current_test,
request,
grant,
grant_valid,
grant_encoded)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: one bit")
current_test.next = 1
yield clk.posedge
for i in range(32):
l = [i]
request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
yield clk.posedge
request.next = 0
yield clk.posedge
assert grant == 1 << i
assert grant_encoded == i
yield clk.posedge
yield delay(100)
yield clk.posedge
print("test 2: two bits")
current_test.next = 2
for i in range(32):
for j in range(32):
l = [i, j]
request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
yield clk.posedge
request.next = 0
yield clk.posedge
assert grant == 1 << max(l)
assert grant_encoded == max(l)
request.next = 0
yield clk.posedge
print("test 3: five bits")
current_test.next = 3
for i in range(32):
l = [(i*x) % 32 for x in [1,2,3,4,5]]
request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
yield clk.posedge
request.next = 0
yield clk.posedge
assert grant == 1 << max(l)
assert grant_encoded == max(l)
prev = int(grant_encoded)
yield clk.posedge
yield delay(100)
raise StopSimulation
return dut, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_arbiter;
// parameters
localparam PORTS = 32;
localparam TYPE = "PRIORITY";
localparam BLOCK = "TRUE";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [PORTS-1:0] request = 0;
// Outputs
wire [PORTS-1:0] grant;
wire grant_valid;
wire [$clog2(PORTS)-1:0] grant_encoded;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
request);
$to_myhdl(grant,
grant_valid,
grant_encoded);
// dump file
$dumpfile("test_arbiter.lxt");
$dumpvars(0, test_arbiter);
end
arbiter #(
.PORTS(PORTS),
.TYPE(TYPE),
.BLOCK(BLOCK)
)
UUT (
.clk(clk),
.rst(rst),
.request(request),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule

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#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
module = 'arbiter'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/priority_encoder.v")
srcs.append("test_%s_rr.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_arbiter_rr(clk,
rst,
current_test,
request,
grant,
grant_valid,
grant_encoded):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
request=request,
grant=grant,
grant_valid=grant_valid,
grant_encoded=grant_encoded)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
request = Signal(intbv(0)[32:])
# Outputs
grant = Signal(intbv(0)[32:])
grant_valid = Signal(bool(0))
grant_encoded = Signal(intbv(0)[5:])
# DUT
dut = dut_arbiter_rr(clk,
rst,
current_test,
request,
grant,
grant_valid,
grant_encoded)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
prev = 0
print("test 1: one bit")
current_test.next = 1
yield clk.posedge
for i in range(32):
l = [i]
request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
yield clk.posedge
request.next = 0
yield clk.posedge
# emulate round robin
l2 = [x for x in l if x < prev]
if len(l2) == 0:
l2 = l
g = max(l2)
assert grant == 1 << g
assert grant_encoded == g
prev = int(grant_encoded)
yield clk.posedge
yield delay(100)
yield clk.posedge
print("test 2: cycle")
current_test.next = 2
for i in range(32):
l = [0, 5, 10, 15, 20, 25, 30]
request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
yield clk.posedge
request.next = 0
yield clk.posedge
# emulate round robin
l2 = [x for x in l if x < prev]
if len(l2) == 0:
l2 = l
g = max(l2)
assert grant == 1 << g
assert grant_encoded == g
prev = int(grant_encoded)
yield clk.posedge
yield delay(100)
yield clk.posedge
print("test 3: two bits")
current_test.next = 3
for i in range(32):
for j in range(32):
l = [i, j]
request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
yield clk.posedge
request.next = 0
yield clk.posedge
# emulate round robin
l2 = [x for x in l if x < prev]
if len(l2) == 0:
l2 = l
g = max(l2)
assert grant == 1 << g
assert grant_encoded == g
prev = int(grant_encoded)
yield clk.posedge
yield delay(100)
yield clk.posedge
print("test 4: five bits")
current_test.next = 4
for i in range(32):
l = [(i*x) % 32 for x in [1,2,3,4,5]]
request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
yield clk.posedge
request.next = 0
yield clk.posedge
# emulate round robin
l2 = [x for x in l if x < prev]
if len(l2) == 0:
l2 = l
g = max(l2)
assert grant == 1 << g
assert grant_encoded == g
prev = int(grant_encoded)
yield clk.posedge
yield delay(100)
yield clk.posedge
yield delay(100)
raise StopSimulation
return dut, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_arbiter_rr;
// parameters
localparam PORTS = 32;
localparam TYPE = "ROUND_ROBIN";
localparam BLOCK = "TRUE";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [PORTS-1:0] request = 0;
// Outputs
wire [PORTS-1:0] grant;
wire grant_valid;
wire [$clog2(PORTS)-1:0] grant_encoded;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
request);
$to_myhdl(grant,
grant_valid,
grant_encoded);
// dump file
$dumpfile("test_arbiter_rr.lxt");
$dumpvars(0, test_arbiter_rr);
end
arbiter #(
.PORTS(PORTS),
.TYPE(TYPE),
.BLOCK(BLOCK)
)
UUT (
.clk(clk),
.rst(rst),
.request(request),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule