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Add AXI shared interconnect and testbench
This commit is contained in:
Alex Forencich
parent
1753a2e6cf
commit
a25c4b17eb
19
README.md
19
README.md
@ -15,17 +15,17 @@ intelligent bus cosimulation endpoints.
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### axi_adapter module
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AXI width adapter module with parametrizable data and address interface widths.
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Supports INCR burst types and narrow bursts. Wrapper for axi_adapter_rd and axi_adapter_wr.
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Supports INCR burst types and narrow bursts. Wrapper for axi_adapter_rd and axi_adapter_wr.
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### axi_adapter_rd module
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AXI width adapter module with parametrizable data and address interface widths.
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Supports INCR burst types and narrow bursts.
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Supports INCR burst types and narrow bursts.
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### axi_adapter_wr module
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AXI width adapter module with parametrizable data and address interface widths.
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Supports INCR burst types and narrow bursts.
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Supports INCR burst types and narrow bursts.
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### axi_fifo module
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@ -48,6 +48,12 @@ channels only. Supports all burst types. Optionally can delay the address
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channel until the write data is shifted completely into the write data FIFO,
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or the current burst completely fills the write data FIFO.
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### axi_interconnect module
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AXI shared interconnect with parametrizable data and address interface
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widths. Supports all burst types. Small in area, but does not support
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concurrent operations.
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### axi_ram module
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AXI RAM with parametrizable data and address interface widths. Supports FIXED
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@ -77,7 +83,7 @@ changed or bypassed.
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### axil_adapter module
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AXI lite width adapter module with parametrizable data and address interface
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widths. Wrapper for axi_adapter_rd and axi_adapter_wr.
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widths. Wrapper for axi_adapter_rd and axi_adapter_wr.
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### axil_adapter_rd module
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@ -92,7 +98,7 @@ widths.
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### axil_interconnect module
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AXI lite shared interconnect with parametrizable data and address interface
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widths. Small in area, but does not support concurrent operations.
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widths. Small in area, but does not support concurrent operations.
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### axil_ram module
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@ -189,6 +195,7 @@ registers can be individually bypassed.
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rtl/axi_fifo.v : AXI FIFO
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rtl/axi_fifo_rd.v : AXI FIFO (read)
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rtl/axi_fifo_wr.v : AXI FIFO (write)
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rtl/axi_interconnect.v : AXI shared interconnect
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rtl/axi_ram.v : AXI RAM
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rtl/axi_register.v : AXI register
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rtl/axi_register_rd.v : AXI register (read)
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@ -196,7 +203,7 @@ registers can be individually bypassed.
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rtl/axil_adapter.v : AXI lite width converter
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rtl/axil_adapter_rd.v : AXI lite width converter (read)
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rtl/axil_adapter_wr.v : AXI lite width converter (write)
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rtl/axil_interconnect.v : AXI lite interconnect
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rtl/axil_interconnect.v : AXI lite shared interconnect
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rtl/axil_ram.v : AXI lite RAM
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rtl/axil_register.v : AXI lite register
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rtl/axil_register_rd.v : AXI lite register (read)
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872
rtl/axi_interconnect.v
Normal file
872
rtl/axi_interconnect.v
Normal file
@ -0,0 +1,872 @@
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/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4 interconnect
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*/
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module axi_interconnect #
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(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 32,
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parameter STRB_WIDTH = (DATA_WIDTH/8),
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parameter ID_WIDTH = 8,
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parameter AWUSER_ENABLE = 0,
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parameter AWUSER_WIDTH = 1,
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parameter WUSER_ENABLE = 0,
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parameter WUSER_WIDTH = 1,
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parameter BUSER_ENABLE = 0,
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parameter BUSER_WIDTH = 1,
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parameter ARUSER_ENABLE = 0,
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parameter ARUSER_WIDTH = 1,
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parameter RUSER_ENABLE = 0,
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parameter RUSER_WIDTH = 1,
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parameter FORWARD_ID = 0,
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parameter S_COUNT = 4,
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parameter M_COUNT = 4,
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parameter M_BASE_ADDR = {32'h03000000, 32'h02000000, 32'h01000000, 32'h00000000},
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parameter M_ADDR_WIDTH = {32'd24, 32'd24, 32'd24, 32'd24},
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parameter M_CONNECT_READ = {4'b1111, 4'b1111, 4'b1111, 4'b1111},
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parameter M_CONNECT_WRITE = {4'b1111, 4'b1111, 4'b1111, 4'b1111}
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI slave interfaces
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*/
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input wire [S_COUNT*ID_WIDTH-1:0] s_axi_awid,
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input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_awaddr,
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input wire [S_COUNT*8-1:0] s_axi_awlen,
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input wire [S_COUNT*3-1:0] s_axi_awsize,
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input wire [S_COUNT*2-1:0] s_axi_awburst,
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input wire [S_COUNT-1:0] s_axi_awlock,
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input wire [S_COUNT*4-1:0] s_axi_awcache,
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input wire [S_COUNT*3-1:0] s_axi_awprot,
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input wire [S_COUNT*4-1:0] s_axi_awqos,
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input wire [S_COUNT*4-1:0] s_axi_awregion,
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input wire [S_COUNT*AWUSER_WIDTH-1:0] s_axi_awuser,
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input wire [S_COUNT-1:0] s_axi_awvalid,
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output wire [S_COUNT-1:0] s_axi_awready,
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input wire [S_COUNT*DATA_WIDTH-1:0] s_axi_wdata,
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input wire [S_COUNT*STRB_WIDTH-1:0] s_axi_wstrb,
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input wire [S_COUNT-1:0] s_axi_wlast,
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input wire [S_COUNT*WUSER_WIDTH-1:0] s_axi_wuser,
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input wire [S_COUNT-1:0] s_axi_wvalid,
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output wire [S_COUNT-1:0] s_axi_wready,
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output wire [S_COUNT*ID_WIDTH-1:0] s_axi_bid,
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output wire [S_COUNT*2-1:0] s_axi_bresp,
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output wire [S_COUNT*BUSER_WIDTH-1:0] s_axi_buser,
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output wire [S_COUNT-1:0] s_axi_bvalid,
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input wire [S_COUNT-1:0] s_axi_bready,
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input wire [S_COUNT*ID_WIDTH-1:0] s_axi_arid,
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input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr,
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input wire [S_COUNT*8-1:0] s_axi_arlen,
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input wire [S_COUNT*3-1:0] s_axi_arsize,
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input wire [S_COUNT*2-1:0] s_axi_arburst,
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input wire [S_COUNT-1:0] s_axi_arlock,
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input wire [S_COUNT*4-1:0] s_axi_arcache,
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input wire [S_COUNT*3-1:0] s_axi_arprot,
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input wire [S_COUNT*4-1:0] s_axi_arqos,
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input wire [S_COUNT*4-1:0] s_axi_arregion,
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input wire [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser,
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input wire [S_COUNT-1:0] s_axi_arvalid,
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output wire [S_COUNT-1:0] s_axi_arready,
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output wire [S_COUNT*ID_WIDTH-1:0] s_axi_rid,
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output wire [S_COUNT*DATA_WIDTH-1:0] s_axi_rdata,
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output wire [S_COUNT*2-1:0] s_axi_rresp,
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output wire [S_COUNT-1:0] s_axi_rlast,
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output wire [S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser,
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output wire [S_COUNT-1:0] s_axi_rvalid,
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input wire [S_COUNT-1:0] s_axi_rready,
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/*
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* AXI master interfaces
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*/
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output wire [M_COUNT*ID_WIDTH-1:0] m_axi_awid,
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output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [M_COUNT*8-1:0] m_axi_awlen,
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output wire [M_COUNT*3-1:0] m_axi_awsize,
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output wire [M_COUNT*2-1:0] m_axi_awburst,
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output wire [M_COUNT-1:0] m_axi_awlock,
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output wire [M_COUNT*4-1:0] m_axi_awcache,
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output wire [M_COUNT*3-1:0] m_axi_awprot,
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output wire [M_COUNT*4-1:0] m_axi_awqos,
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output wire [M_COUNT*4-1:0] m_axi_awregion,
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output wire [M_COUNT*AWUSER_WIDTH-1:0] m_axi_awuser,
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output wire [M_COUNT-1:0] m_axi_awvalid,
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input wire [M_COUNT-1:0] m_axi_awready,
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output wire [M_COUNT*DATA_WIDTH-1:0] m_axi_wdata,
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output wire [M_COUNT*STRB_WIDTH-1:0] m_axi_wstrb,
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output wire [M_COUNT-1:0] m_axi_wlast,
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output wire [M_COUNT*WUSER_WIDTH-1:0] m_axi_wuser,
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output wire [M_COUNT-1:0] m_axi_wvalid,
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input wire [M_COUNT-1:0] m_axi_wready,
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input wire [M_COUNT*ID_WIDTH-1:0] m_axi_bid,
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input wire [M_COUNT*2-1:0] m_axi_bresp,
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input wire [M_COUNT*BUSER_WIDTH-1:0] m_axi_buser,
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input wire [M_COUNT-1:0] m_axi_bvalid,
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output wire [M_COUNT-1:0] m_axi_bready,
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output wire [M_COUNT*ID_WIDTH-1:0] m_axi_arid,
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output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [M_COUNT*8-1:0] m_axi_arlen,
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output wire [M_COUNT*3-1:0] m_axi_arsize,
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output wire [M_COUNT*2-1:0] m_axi_arburst,
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output wire [M_COUNT-1:0] m_axi_arlock,
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output wire [M_COUNT*4-1:0] m_axi_arcache,
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output wire [M_COUNT*3-1:0] m_axi_arprot,
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output wire [M_COUNT*4-1:0] m_axi_arqos,
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output wire [M_COUNT*4-1:0] m_axi_arregion,
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output wire [M_COUNT*ARUSER_WIDTH-1:0] m_axi_aruser,
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output wire [M_COUNT-1:0] m_axi_arvalid,
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input wire [M_COUNT-1:0] m_axi_arready,
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input wire [M_COUNT*ID_WIDTH-1:0] m_axi_rid,
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input wire [M_COUNT*DATA_WIDTH-1:0] m_axi_rdata,
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input wire [M_COUNT*2-1:0] m_axi_rresp,
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input wire [M_COUNT-1:0] m_axi_rlast,
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input wire [M_COUNT*RUSER_WIDTH-1:0] m_axi_ruser,
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input wire [M_COUNT-1:0] m_axi_rvalid,
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output wire [M_COUNT-1:0] m_axi_rready
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);
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parameter CL_S_COUNT = $clog2(S_COUNT);
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parameter CL_M_COUNT = $clog2(M_COUNT);
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parameter AUSER_WIDTH = AWUSER_WIDTH > ARUSER_WIDTH ? AWUSER_WIDTH : ARUSER_WIDTH;
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integer i, j;
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// check configuration
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initial begin
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for (i = 0; i < M_COUNT; i = i + 1) begin
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if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 0 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
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$error("Error: value out of range");
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$finish;
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end
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end
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end
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localparam [2:0]
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STATE_IDLE = 3'd0,
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STATE_DECODE = 3'd1,
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STATE_WRITE = 3'd2,
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STATE_WRITE_RESP = 3'd3,
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STATE_WRITE_DROP = 3'd4,
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STATE_READ = 3'd5,
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STATE_READ_DROP = 3'd6,
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STATE_WAIT_IDLE = 3'd7;
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reg [2:0] state_reg = STATE_IDLE, state_next;
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reg match;
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reg [CL_M_COUNT-1:0] m_select_reg = 2'd0, m_select_next;
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reg [ID_WIDTH-1:0] axi_id_reg = {ID_WIDTH{1'b0}}, axi_id_next;
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reg [ADDR_WIDTH-1:0] axi_addr_reg = {ADDR_WIDTH{1'b0}}, axi_addr_next;
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reg axi_addr_valid_reg = 1'b0, axi_addr_valid_next;
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reg [7:0] axi_len_reg = 8'd0, axi_len_next;
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reg [2:0] axi_size_reg = 3'd0, axi_size_next;
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reg [1:0] axi_burst_reg = 2'd0, axi_burst_next;
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reg axi_lock_reg = 1'b0, axi_lock_next;
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reg [3:0] axi_cache_reg = 4'd0, axi_cache_next;
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reg [2:0] axi_prot_reg = 3'b000, axi_prot_next;
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reg [3:0] axi_qos_reg = 4'd0, axi_qos_next;
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reg [3:0] axi_region_reg = 4'd0, axi_region_next;
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reg [AUSER_WIDTH-1:0] axi_auser_reg = {AUSER_WIDTH{1'b0}}, axi_auser_next;
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reg [1:0] axi_bresp_reg = 2'b00, axi_bresp_next;
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reg [BUSER_WIDTH-1:0] axi_buser_reg = {BUSER_WIDTH{1'b0}}, axi_buser_next;
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reg [S_COUNT-1:0] s_axi_awready_reg = 0, s_axi_awready_next;
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reg [S_COUNT-1:0] s_axi_wready_reg = 0, s_axi_wready_next;
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reg [S_COUNT-1:0] s_axi_bvalid_reg = 0, s_axi_bvalid_next;
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reg [S_COUNT-1:0] s_axi_arready_reg = 0, s_axi_arready_next;
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//reg [S_COUNT-1:0] s_axi_rvalid_reg = 0, s_axi_rvalid_next;
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reg [M_COUNT-1:0] m_axi_awvalid_reg = 0, m_axi_awvalid_next;
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//reg [M_COUNT-1:0] m_axi_wvalid_reg = 0, m_axi_wvalid_next;
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reg [M_COUNT-1:0] m_axi_bready_reg = 0, m_axi_bready_next;
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reg [M_COUNT-1:0] m_axi_arvalid_reg = 0, m_axi_arvalid_next;
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reg [M_COUNT-1:0] m_axi_rready_reg = 0, m_axi_rready_next;
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// internal datapath
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reg [ID_WIDTH-1:0] s_axi_rid_int;
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reg [DATA_WIDTH-1:0] s_axi_rdata_int;
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reg [1:0] s_axi_rresp_int;
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reg s_axi_rlast_int;
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reg [RUSER_WIDTH-1:0] s_axi_ruser_int;
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reg s_axi_rvalid_int;
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reg s_axi_rready_int_reg = 1'b0;
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wire s_axi_rready_int_early;
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reg [DATA_WIDTH-1:0] m_axi_wdata_int;
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reg [STRB_WIDTH-1:0] m_axi_wstrb_int;
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reg m_axi_wlast_int;
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reg [WUSER_WIDTH-1:0] m_axi_wuser_int;
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reg m_axi_wvalid_int;
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reg m_axi_wready_int_reg = 1'b0;
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wire m_axi_wready_int_early;
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assign s_axi_awready = s_axi_awready_reg;
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assign s_axi_wready = s_axi_wready_reg;
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assign s_axi_bid = {S_COUNT{axi_id_reg}};
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assign s_axi_bresp = {S_COUNT{axi_bresp_reg}};
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assign s_axi_buser = {S_COUNT{BUSER_ENABLE ? axi_buser_reg[BUSER_WIDTH-1:0] : {BUSER_WIDTH{1'b0}}}};
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assign s_axi_bvalid = s_axi_bvalid_reg;
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assign s_axi_arready = s_axi_arready_reg;
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assign m_axi_awid = {M_COUNT{FORWARD_ID ? axi_id_reg : {ID_WIDTH{1'b0}}}};
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assign m_axi_awaddr = {M_COUNT{axi_addr_reg}};
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assign m_axi_awlen = {M_COUNT{axi_len_reg}};
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assign m_axi_awsize = {M_COUNT{axi_size_reg}};
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assign m_axi_awburst = {M_COUNT{axi_burst_reg}};
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assign m_axi_awlock = {M_COUNT{axi_lock_reg}};
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assign m_axi_awcache = {M_COUNT{axi_cache_reg}};
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assign m_axi_awprot = {M_COUNT{axi_prot_reg}};
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assign m_axi_awqos = {M_COUNT{axi_qos_reg}};
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assign m_axi_awregion = {M_COUNT{axi_region_reg}};
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assign m_axi_awuser = {M_COUNT{AWUSER_ENABLE ? axi_auser_reg[AWUSER_WIDTH-1:0] : {AWUSER_WIDTH{1'b0}}}};
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assign m_axi_awvalid = m_axi_awvalid_reg;
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assign m_axi_bready = m_axi_bready_reg;
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assign m_axi_arid = {M_COUNT{FORWARD_ID ? axi_id_reg : {ID_WIDTH{1'b0}}}};
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assign m_axi_araddr = {M_COUNT{axi_addr_reg}};
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assign m_axi_arlen = {M_COUNT{axi_len_reg}};
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assign m_axi_arsize = {M_COUNT{axi_size_reg}};
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assign m_axi_arburst = {M_COUNT{axi_burst_reg}};
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assign m_axi_arlock = {M_COUNT{axi_lock_reg}};
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assign m_axi_arcache = {M_COUNT{axi_cache_reg}};
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assign m_axi_arprot = {M_COUNT{axi_prot_reg}};
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assign m_axi_arqos = {M_COUNT{axi_qos_reg}};
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assign m_axi_arregion = {M_COUNT{axi_region_reg}};
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assign m_axi_aruser = {M_COUNT{ARUSER_ENABLE ? axi_auser_reg[ARUSER_WIDTH-1:0] : {ARUSER_WIDTH{1'b0}}}};
|
||||
assign m_axi_arvalid = m_axi_arvalid_reg;
|
||||
assign m_axi_rready = m_axi_rready_reg;
|
||||
|
||||
// slave side mux
|
||||
wire [ID_WIDTH-1:0] current_s_axi_awid = s_axi_awid[s_select*ID_WIDTH +: ID_WIDTH];
|
||||
wire [ADDR_WIDTH-1:0] current_s_axi_awaddr = s_axi_awaddr[s_select*ADDR_WIDTH +: ADDR_WIDTH];
|
||||
wire [7:0] current_s_axi_awlen = s_axi_awlen[s_select*8 +: 8];
|
||||
wire [2:0] current_s_axi_awsize = s_axi_awsize[s_select*3 +: 3];
|
||||
wire [1:0] current_s_axi_awburst = s_axi_awburst[s_select*2 +: 2];
|
||||
wire current_s_axi_awlock = s_axi_awlock[s_select];
|
||||
wire [3:0] current_s_axi_awcache = s_axi_awcache[s_select*4 +: 4];
|
||||
wire [2:0] current_s_axi_awprot = s_axi_awprot[s_select*3 +: 3];
|
||||
wire [3:0] current_s_axi_awqos = s_axi_awqos[s_select*4 +: 4];
|
||||
wire [3:0] current_s_axi_awregion = s_axi_awregion[s_select*4 +: 4];
|
||||
wire [AWUSER_WIDTH-1:0] current_s_axi_awuser = s_axi_awuser[s_select*AWUSER_WIDTH +: AWUSER_WIDTH];
|
||||
wire current_s_axi_awvalid = s_axi_awvalid[s_select];
|
||||
wire current_s_axi_awready = s_axi_awready[s_select];
|
||||
wire [DATA_WIDTH-1:0] current_s_axi_wdata = s_axi_wdata[s_select*DATA_WIDTH +: DATA_WIDTH];
|
||||
wire [STRB_WIDTH-1:0] current_s_axi_wstrb = s_axi_wstrb[s_select*STRB_WIDTH +: STRB_WIDTH];
|
||||
wire current_s_axi_wlast = s_axi_wlast[s_select];
|
||||
wire [WUSER_WIDTH-1:0] current_s_axi_wuser = s_axi_wuser[s_select*WUSER_WIDTH +: WUSER_WIDTH];
|
||||
wire current_s_axi_wvalid = s_axi_wvalid[s_select];
|
||||
wire current_s_axi_wready = s_axi_wready[s_select];
|
||||
wire [ID_WIDTH-1:0] current_s_axi_bid = s_axi_bid[s_select*ID_WIDTH +: ID_WIDTH];
|
||||
wire [1:0] current_s_axi_bresp = s_axi_bresp[s_select*2 +: 2];
|
||||
wire [BUSER_WIDTH-1:0] current_s_axi_buser = s_axi_buser[s_select*BUSER_WIDTH +: BUSER_WIDTH];
|
||||
wire current_s_axi_bvalid = s_axi_bvalid[s_select];
|
||||
wire current_s_axi_bready = s_axi_bready[s_select];
|
||||
wire [ID_WIDTH-1:0] current_s_axi_arid = s_axi_arid[s_select*ID_WIDTH +: ID_WIDTH];
|
||||
wire [ADDR_WIDTH-1:0] current_s_axi_araddr = s_axi_araddr[s_select*ADDR_WIDTH +: ADDR_WIDTH];
|
||||
wire [7:0] current_s_axi_arlen = s_axi_arlen[s_select*8 +: 8];
|
||||
wire [2:0] current_s_axi_arsize = s_axi_arsize[s_select*3 +: 3];
|
||||
wire [1:0] current_s_axi_arburst = s_axi_arburst[s_select*2 +: 2];
|
||||
wire current_s_axi_arlock = s_axi_arlock[s_select];
|
||||
wire [3:0] current_s_axi_arcache = s_axi_arcache[s_select*4 +: 4];
|
||||
wire [2:0] current_s_axi_arprot = s_axi_arprot[s_select*3 +: 3];
|
||||
wire [3:0] current_s_axi_arqos = s_axi_arqos[s_select*4 +: 4];
|
||||
wire [3:0] current_s_axi_arregion = s_axi_arregion[s_select*4 +: 4];
|
||||
wire [ARUSER_WIDTH-1:0] current_s_axi_aruser = s_axi_aruser[s_select*ARUSER_WIDTH +: ARUSER_WIDTH];
|
||||
wire current_s_axi_arvalid = s_axi_arvalid[s_select];
|
||||
wire current_s_axi_arready = s_axi_arready[s_select];
|
||||
wire [ID_WIDTH-1:0] current_s_axi_rid = s_axi_rid[s_select*ID_WIDTH +: ID_WIDTH];
|
||||
wire [DATA_WIDTH-1:0] current_s_axi_rdata = s_axi_rdata[s_select*DATA_WIDTH +: DATA_WIDTH];
|
||||
wire [1:0] current_s_axi_rresp = s_axi_rresp[s_select*2 +: 2];
|
||||
wire current_s_axi_rlast = s_axi_rlast[s_select];
|
||||
wire [RUSER_WIDTH-1:0] current_s_axi_ruser = s_axi_ruser[s_select*RUSER_WIDTH +: RUSER_WIDTH];
|
||||
wire current_s_axi_rvalid = s_axi_rvalid[s_select];
|
||||
wire current_s_axi_rready = s_axi_rready[s_select];
|
||||
|
||||
// master side mux
|
||||
wire [ID_WIDTH-1:0] current_m_axi_awid = m_axi_awid[m_select_reg*ID_WIDTH +: ID_WIDTH];
|
||||
wire [ADDR_WIDTH-1:0] current_m_axi_awaddr = m_axi_awaddr[m_select_reg*ADDR_WIDTH +: ADDR_WIDTH];
|
||||
wire [7:0] current_m_axi_awlen = m_axi_awlen[m_select_reg*8 +: 8];
|
||||
wire [2:0] current_m_axi_awsize = m_axi_awsize[m_select_reg*3 +: 3];
|
||||
wire [1:0] current_m_axi_awburst = m_axi_awburst[m_select_reg*2 +: 2];
|
||||
wire current_m_axi_awlock = m_axi_awlock[m_select_reg];
|
||||
wire [3:0] current_m_axi_awcache = m_axi_awcache[m_select_reg*4 +: 4];
|
||||
wire [2:0] current_m_axi_awprot = m_axi_awprot[m_select_reg*3 +: 3];
|
||||
wire [3:0] current_m_axi_awqos = m_axi_awqos[m_select_reg*4 +: 4];
|
||||
wire [3:0] current_m_axi_awregion = m_axi_awregion[m_select_reg*4 +: 4];
|
||||
wire [AWUSER_WIDTH-1:0] current_m_axi_awuser = m_axi_awuser[m_select_reg*AWUSER_WIDTH +: AWUSER_WIDTH];
|
||||
wire current_m_axi_awvalid = m_axi_awvalid[m_select_reg];
|
||||
wire current_m_axi_awready = m_axi_awready[m_select_reg];
|
||||
wire [DATA_WIDTH-1:0] current_m_axi_wdata = m_axi_wdata[m_select_reg*DATA_WIDTH +: DATA_WIDTH];
|
||||
wire [STRB_WIDTH-1:0] current_m_axi_wstrb = m_axi_wstrb[m_select_reg*STRB_WIDTH +: STRB_WIDTH];
|
||||
wire current_m_axi_wlast = m_axi_wlast[m_select_reg];
|
||||
wire [WUSER_WIDTH-1:0] current_m_axi_wuser = m_axi_wuser[m_select_reg*WUSER_WIDTH +: WUSER_WIDTH];
|
||||
wire current_m_axi_wvalid = m_axi_wvalid[m_select_reg];
|
||||
wire current_m_axi_wready = m_axi_wready[m_select_reg];
|
||||
wire [ID_WIDTH-1:0] current_m_axi_bid = m_axi_bid[m_select_reg*ID_WIDTH +: ID_WIDTH];
|
||||
wire [1:0] current_m_axi_bresp = m_axi_bresp[m_select_reg*2 +: 2];
|
||||
wire [BUSER_WIDTH-1:0] current_m_axi_buser = m_axi_buser[m_select_reg*BUSER_WIDTH +: BUSER_WIDTH];
|
||||
wire current_m_axi_bvalid = m_axi_bvalid[m_select_reg];
|
||||
wire current_m_axi_bready = m_axi_bready[m_select_reg];
|
||||
wire [ID_WIDTH-1:0] current_m_axi_arid = m_axi_arid[m_select_reg*ID_WIDTH +: ID_WIDTH];
|
||||
wire [ADDR_WIDTH-1:0] current_m_axi_araddr = m_axi_araddr[m_select_reg*ADDR_WIDTH +: ADDR_WIDTH];
|
||||
wire [7:0] current_m_axi_arlen = m_axi_arlen[m_select_reg*8 +: 8];
|
||||
wire [2:0] current_m_axi_arsize = m_axi_arsize[m_select_reg*3 +: 3];
|
||||
wire [1:0] current_m_axi_arburst = m_axi_arburst[m_select_reg*2 +: 2];
|
||||
wire current_m_axi_arlock = m_axi_arlock[m_select_reg];
|
||||
wire [3:0] current_m_axi_arcache = m_axi_arcache[m_select_reg*4 +: 4];
|
||||
wire [2:0] current_m_axi_arprot = m_axi_arprot[m_select_reg*3 +: 3];
|
||||
wire [3:0] current_m_axi_arqos = m_axi_arqos[m_select_reg*4 +: 4];
|
||||
wire [3:0] current_m_axi_arregion = m_axi_arregion[m_select_reg*4 +: 4];
|
||||
wire [ARUSER_WIDTH-1:0] current_m_axi_aruser = m_axi_aruser[m_select_reg*ARUSER_WIDTH +: ARUSER_WIDTH];
|
||||
wire current_m_axi_arvalid = m_axi_arvalid[m_select_reg];
|
||||
wire current_m_axi_arready = m_axi_arready[m_select_reg];
|
||||
wire [ID_WIDTH-1:0] current_m_axi_rid = m_axi_rid[m_select_reg*ID_WIDTH +: ID_WIDTH];
|
||||
wire [DATA_WIDTH-1:0] current_m_axi_rdata = m_axi_rdata[m_select_reg*DATA_WIDTH +: DATA_WIDTH];
|
||||
wire [1:0] current_m_axi_rresp = m_axi_rresp[m_select_reg*2 +: 2];
|
||||
wire current_m_axi_rlast = m_axi_rlast[m_select_reg];
|
||||
wire [RUSER_WIDTH-1:0] current_m_axi_ruser = m_axi_ruser[m_select_reg*RUSER_WIDTH +: RUSER_WIDTH];
|
||||
wire current_m_axi_rvalid = m_axi_rvalid[m_select_reg];
|
||||
wire current_m_axi_rready = m_axi_rready[m_select_reg];
|
||||
|
||||
// arbiter instance
|
||||
wire [S_COUNT*2-1:0] request;
|
||||
wire [S_COUNT*2-1:0] acknowledge;
|
||||
wire [S_COUNT*2-1:0] grant;
|
||||
wire grant_valid;
|
||||
wire [CL_S_COUNT:0] grant_encoded;
|
||||
|
||||
wire read = grant_encoded[0];
|
||||
wire [CL_S_COUNT-1:0] s_select = grant_encoded[CL_S_COUNT:1];
|
||||
|
||||
arbiter #(
|
||||
.PORTS(S_COUNT*2),
|
||||
.TYPE("ROUND_ROBIN"),
|
||||
.BLOCK("ACKNOWLEDGE"),
|
||||
.LSB_PRIORITY("HIGH")
|
||||
)
|
||||
arb_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.request(request),
|
||||
.acknowledge(acknowledge),
|
||||
.grant(grant),
|
||||
.grant_valid(grant_valid),
|
||||
.grant_encoded(grant_encoded)
|
||||
);
|
||||
|
||||
genvar n;
|
||||
|
||||
// request generation
|
||||
generate
|
||||
for (n = 0; n < S_COUNT; n = n + 1) begin
|
||||
assign request[2*n] = s_axi_awvalid[n];
|
||||
assign request[2*n+1] = s_axi_arvalid[n];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// acknowledge generation
|
||||
generate
|
||||
for (n = 0; n < S_COUNT; n = n + 1) begin
|
||||
assign acknowledge[2*n] = grant[2*n] && s_axi_bvalid[n] && s_axi_bready[n];
|
||||
assign acknowledge[2*n+1] = grant[2*n+1] && s_axi_rvalid[n] && s_axi_rready[n] && s_axi_rlast[n];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @* begin
|
||||
state_next = STATE_IDLE;
|
||||
|
||||
match = 1'b0;
|
||||
|
||||
m_select_next = m_select_reg;
|
||||
axi_id_next = axi_id_reg;
|
||||
axi_addr_next = axi_addr_reg;
|
||||
axi_addr_valid_next = axi_addr_valid_reg;
|
||||
axi_len_next = axi_len_reg;
|
||||
axi_size_next = axi_size_reg;
|
||||
axi_burst_next = axi_burst_reg;
|
||||
axi_lock_next = axi_lock_reg;
|
||||
axi_cache_next = axi_cache_reg;
|
||||
axi_prot_next = axi_prot_reg;
|
||||
axi_qos_next = axi_qos_reg;
|
||||
axi_region_next = axi_region_reg;
|
||||
axi_auser_next = axi_auser_reg;
|
||||
axi_bresp_next = axi_bresp_reg;
|
||||
axi_buser_next = axi_buser_reg;
|
||||
|
||||
s_axi_awready_next = 0;
|
||||
s_axi_wready_next = 0;
|
||||
s_axi_bvalid_next = s_axi_bvalid_reg & ~s_axi_bready;
|
||||
s_axi_arready_next = 0;
|
||||
|
||||
m_axi_awvalid_next = m_axi_awvalid_reg & ~m_axi_awready;
|
||||
m_axi_bready_next = 0;
|
||||
m_axi_arvalid_next = m_axi_arvalid_reg & ~m_axi_arready;
|
||||
m_axi_rready_next = 0;
|
||||
|
||||
s_axi_rid_int = axi_id_reg;
|
||||
s_axi_rdata_int = current_m_axi_rdata;
|
||||
s_axi_rresp_int = current_m_axi_rresp;
|
||||
s_axi_rlast_int = current_m_axi_rlast;
|
||||
s_axi_ruser_int = current_m_axi_ruser;
|
||||
s_axi_rvalid_int = 1'b0;
|
||||
|
||||
m_axi_wdata_int = current_s_axi_wdata;
|
||||
m_axi_wstrb_int = current_s_axi_wstrb;
|
||||
m_axi_wlast_int = current_s_axi_wlast;
|
||||
m_axi_wuser_int = current_s_axi_wuser;
|
||||
m_axi_wvalid_int = 1'b0;
|
||||
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
// idle state; wait for arbitration
|
||||
|
||||
if (grant_valid) begin
|
||||
|
||||
axi_addr_valid_next = 1'b1;
|
||||
|
||||
if (read) begin
|
||||
// reading
|
||||
axi_addr_next = current_s_axi_araddr;
|
||||
axi_prot_next = current_s_axi_arprot;
|
||||
axi_id_next = current_s_axi_arid;
|
||||
axi_addr_next = current_s_axi_araddr;
|
||||
axi_len_next = current_s_axi_arlen;
|
||||
axi_size_next = current_s_axi_arsize;
|
||||
axi_burst_next = current_s_axi_arburst;
|
||||
axi_lock_next = current_s_axi_arlock;
|
||||
axi_cache_next = current_s_axi_arcache;
|
||||
axi_prot_next = current_s_axi_arprot;
|
||||
axi_qos_next = current_s_axi_arqos;
|
||||
axi_region_next = current_s_axi_arregion;
|
||||
axi_auser_next = current_s_axi_aruser;
|
||||
s_axi_arready_next[s_select] = 1'b1;
|
||||
end else begin
|
||||
// writing
|
||||
axi_addr_next = current_s_axi_awaddr;
|
||||
axi_prot_next = current_s_axi_awprot;
|
||||
axi_id_next = current_s_axi_awid;
|
||||
axi_addr_next = current_s_axi_awaddr;
|
||||
axi_len_next = current_s_axi_awlen;
|
||||
axi_size_next = current_s_axi_awsize;
|
||||
axi_burst_next = current_s_axi_awburst;
|
||||
axi_lock_next = current_s_axi_awlock;
|
||||
axi_cache_next = current_s_axi_awcache;
|
||||
axi_prot_next = current_s_axi_awprot;
|
||||
axi_qos_next = current_s_axi_awqos;
|
||||
axi_region_next = current_s_axi_awregion;
|
||||
axi_auser_next = current_s_axi_awuser;
|
||||
s_axi_awready_next[s_select] = 1'b1;
|
||||
end
|
||||
|
||||
state_next = STATE_DECODE;
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
STATE_DECODE: begin
|
||||
// decode state; determine master interface
|
||||
|
||||
match = 1'b0;
|
||||
for (i = 0; i < M_COUNT; i = i + 1) begin
|
||||
if (M_ADDR_WIDTH[i*32 +: 32] && (read ? M_CONNECT_READ[i][s_select] : M_CONNECT_WRITE[i][s_select]) && (axi_addr_reg >> M_ADDR_WIDTH[i*32 +: 32]) == (M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[i*32 +: 32])) begin
|
||||
m_select_next = i;
|
||||
match = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
if (match) begin
|
||||
if (read) begin
|
||||
// reading
|
||||
m_axi_rready_next[m_select_reg] = s_axi_rready_int_early;
|
||||
state_next = STATE_READ;
|
||||
end else begin
|
||||
// writing
|
||||
s_axi_wready_next[s_select] = m_axi_wready_int_early;
|
||||
state_next = STATE_WRITE;
|
||||
end
|
||||
end else begin
|
||||
// no match; return decode error
|
||||
if (read) begin
|
||||
// reading
|
||||
state_next = STATE_READ_DROP;
|
||||
end else begin
|
||||
// writing
|
||||
axi_bresp_next = 2'b11;
|
||||
s_axi_wready_next[s_select] = 1'b1;
|
||||
state_next = STATE_WRITE_DROP;
|
||||
end
|
||||
end
|
||||
end
|
||||
STATE_WRITE: begin
|
||||
// write state; store and forward write data
|
||||
s_axi_wready_next[s_select] = m_axi_wready_int_early;
|
||||
|
||||
if (axi_addr_valid_reg) begin
|
||||
m_axi_awvalid_next[m_select_reg] = 1'b1;
|
||||
end
|
||||
axi_addr_valid_next = 1'b0;
|
||||
|
||||
if (current_s_axi_wready && current_s_axi_wvalid) begin
|
||||
m_axi_wdata_int = current_s_axi_wdata;
|
||||
m_axi_wstrb_int = current_s_axi_wstrb;
|
||||
m_axi_wlast_int = current_s_axi_wlast;
|
||||
m_axi_wuser_int = current_s_axi_wuser;
|
||||
m_axi_wvalid_int = 1'b1;
|
||||
|
||||
if (current_s_axi_wlast) begin
|
||||
s_axi_wready_next[s_select] = 1'b0;
|
||||
m_axi_bready_next[m_select_reg] = 1'b1;
|
||||
state_next = STATE_WRITE_RESP;
|
||||
end else begin
|
||||
state_next = STATE_WRITE;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_WRITE;
|
||||
end
|
||||
end
|
||||
STATE_WRITE_RESP: begin
|
||||
// write response state; store and forward write response
|
||||
m_axi_bready_next[m_select_reg] = 1'b1;
|
||||
|
||||
if (current_m_axi_bready && current_m_axi_bvalid) begin
|
||||
m_axi_bready_next[m_select_reg] = 1'b0;
|
||||
axi_bresp_next = current_m_axi_bresp;
|
||||
s_axi_bvalid_next[s_select] = 1'b1;
|
||||
state_next = STATE_WAIT_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_WRITE_RESP;
|
||||
end
|
||||
end
|
||||
STATE_WRITE_DROP: begin
|
||||
// write drop state; drop write data
|
||||
s_axi_wready_next[s_select] = 1'b1;
|
||||
|
||||
axi_addr_valid_next = 1'b0;
|
||||
|
||||
if (current_s_axi_wready && current_s_axi_wvalid) begin
|
||||
s_axi_wready_next[s_select] = 1'b0;
|
||||
s_axi_bvalid_next[s_select] = 1'b1;
|
||||
state_next = STATE_WAIT_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_WRITE_DROP;
|
||||
end
|
||||
end
|
||||
STATE_READ: begin
|
||||
// read state; store and forward read response
|
||||
m_axi_rready_next[m_select_reg] = s_axi_rready_int_early;
|
||||
|
||||
if (axi_addr_valid_reg) begin
|
||||
m_axi_arvalid_next[m_select_reg] = 1'b1;
|
||||
end
|
||||
axi_addr_valid_next = 1'b0;
|
||||
|
||||
if (current_m_axi_rready && current_m_axi_rvalid) begin
|
||||
s_axi_rid_int = axi_id_reg;
|
||||
s_axi_rdata_int = current_m_axi_rdata;
|
||||
s_axi_rresp_int = current_m_axi_rresp;
|
||||
s_axi_rlast_int = current_m_axi_rlast;
|
||||
s_axi_ruser_int = current_m_axi_ruser;
|
||||
s_axi_rvalid_int = 1'b1;
|
||||
|
||||
if (current_m_axi_rlast) begin
|
||||
m_axi_rready_next[m_select_reg] = 1'b0;
|
||||
state_next = STATE_WAIT_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_READ;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_READ;
|
||||
end
|
||||
end
|
||||
STATE_READ_DROP: begin
|
||||
// read drop state; generate decode error read response
|
||||
|
||||
s_axi_rid_int = axi_id_reg;
|
||||
s_axi_rdata_int = {DATA_WIDTH{1'b0}};
|
||||
s_axi_rresp_int = 2'b11;
|
||||
s_axi_rlast_int = axi_len_reg == 0;
|
||||
s_axi_ruser_int = {RUSER_WIDTH{1'b0}};
|
||||
s_axi_rvalid_int = 1'b1;
|
||||
|
||||
if (s_axi_rready_int_reg) begin
|
||||
axi_len_next = axi_len_reg - 1;
|
||||
if (axi_len_reg == 0) begin
|
||||
state_next = STATE_WAIT_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_READ_DROP;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_READ_DROP;
|
||||
end
|
||||
end
|
||||
STATE_WAIT_IDLE: begin
|
||||
// wait for idle state; wait untl grant valid is deasserted
|
||||
|
||||
if (!grant_valid || acknowledge) begin
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_WAIT_IDLE;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
|
||||
s_axi_awready_reg <= 0;
|
||||
s_axi_wready_reg <= 0;
|
||||
s_axi_bvalid_reg <= 0;
|
||||
s_axi_arready_reg <= 0;
|
||||
s_axi_rvalid_reg <= 0;
|
||||
|
||||
m_axi_awvalid_reg <= 0;
|
||||
m_axi_wvalid_reg <= 0;
|
||||
m_axi_bready_reg <= 0;
|
||||
m_axi_arvalid_reg <= 0;
|
||||
m_axi_rready_reg <= 0;
|
||||
end else begin
|
||||
state_reg <= state_next;
|
||||
|
||||
s_axi_awready_reg <= s_axi_awready_next;
|
||||
s_axi_wready_reg <= s_axi_wready_next;
|
||||
s_axi_bvalid_reg <= s_axi_bvalid_next;
|
||||
s_axi_arready_reg <= s_axi_arready_next;
|
||||
s_axi_rvalid_reg <= s_axi_rvalid_next;
|
||||
|
||||
m_axi_awvalid_reg <= m_axi_awvalid_next;
|
||||
m_axi_wvalid_reg <= m_axi_wvalid_next;
|
||||
m_axi_bready_reg <= m_axi_bready_next;
|
||||
m_axi_arvalid_reg <= m_axi_arvalid_next;
|
||||
m_axi_rready_reg <= m_axi_rready_next;
|
||||
end
|
||||
|
||||
m_select_reg <= m_select_next;
|
||||
axi_id_reg <= axi_id_next;
|
||||
axi_addr_reg <= axi_addr_next;
|
||||
axi_addr_valid_reg <= axi_addr_valid_next;
|
||||
axi_len_reg <= axi_len_next;
|
||||
axi_size_reg <= axi_size_next;
|
||||
axi_burst_reg <= axi_burst_next;
|
||||
axi_lock_reg <= axi_lock_next;
|
||||
axi_cache_reg <= axi_cache_next;
|
||||
axi_prot_reg <= axi_prot_next;
|
||||
axi_qos_reg <= axi_qos_next;
|
||||
axi_region_reg <= axi_region_next;
|
||||
axi_auser_reg <= axi_auser_next;
|
||||
axi_bresp_reg <= axi_bresp_next;
|
||||
axi_buser_reg <= axi_buser_next;
|
||||
end
|
||||
|
||||
// output datapath logic (R channel)
|
||||
reg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}};
|
||||
reg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [1:0] s_axi_rresp_reg = 2'd0;
|
||||
reg s_axi_rlast_reg = 1'b0;
|
||||
reg [RUSER_WIDTH-1:0] s_axi_ruser_reg = 1'b0;
|
||||
reg [S_COUNT-1:0] s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
|
||||
|
||||
reg [ID_WIDTH-1:0] temp_s_axi_rid_reg = {ID_WIDTH{1'b0}};
|
||||
reg [DATA_WIDTH-1:0] temp_s_axi_rdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [1:0] temp_s_axi_rresp_reg = 2'd0;
|
||||
reg temp_s_axi_rlast_reg = 1'b0;
|
||||
reg [RUSER_WIDTH-1:0] temp_s_axi_ruser_reg = 1'b0;
|
||||
reg temp_s_axi_rvalid_reg = 1'b0, temp_s_axi_rvalid_next;
|
||||
|
||||
// datapath control
|
||||
reg store_axi_r_int_to_output;
|
||||
reg store_axi_r_int_to_temp;
|
||||
reg store_axi_r_temp_to_output;
|
||||
|
||||
assign s_axi_rid = {S_COUNT{s_axi_rid_reg}};
|
||||
assign s_axi_rdata = {S_COUNT{s_axi_rdata_reg}};
|
||||
assign s_axi_rresp = {S_COUNT{s_axi_rresp_reg}};
|
||||
assign s_axi_rlast = {S_COUNT{s_axi_rlast_reg}};
|
||||
assign s_axi_ruser = {S_COUNT{RUSER_ENABLE ? s_axi_ruser_reg : {RUSER_WIDTH{1'b0}}}};
|
||||
assign s_axi_rvalid = s_axi_rvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign s_axi_rready_int_early = current_s_axi_rready | (~temp_s_axi_rvalid_reg & (~current_s_axi_rvalid | ~s_axi_rvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
s_axi_rvalid_next = s_axi_rvalid_reg;
|
||||
temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg;
|
||||
|
||||
store_axi_r_int_to_output = 1'b0;
|
||||
store_axi_r_int_to_temp = 1'b0;
|
||||
store_axi_r_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axi_rready_int_reg) begin
|
||||
// input is ready
|
||||
if (current_s_axi_rready | ~current_s_axi_rvalid) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
s_axi_rvalid_next[s_select] = s_axi_rvalid_int;
|
||||
store_axi_r_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_s_axi_rvalid_next = s_axi_rvalid_int;
|
||||
store_axi_r_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (current_s_axi_rready) begin
|
||||
// input is not ready, but output is ready
|
||||
s_axi_rvalid_next[s_select] = temp_s_axi_rvalid_reg;
|
||||
temp_s_axi_rvalid_next = 1'b0;
|
||||
store_axi_r_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
s_axi_rvalid_reg <= 1'b0;
|
||||
s_axi_rready_int_reg <= 1'b0;
|
||||
temp_s_axi_rvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
s_axi_rvalid_reg <= s_axi_rvalid_next;
|
||||
s_axi_rready_int_reg <= s_axi_rready_int_early;
|
||||
temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_axi_r_int_to_output) begin
|
||||
s_axi_rid_reg <= s_axi_rid_int;
|
||||
s_axi_rdata_reg <= s_axi_rdata_int;
|
||||
s_axi_rresp_reg <= s_axi_rresp_int;
|
||||
s_axi_rlast_reg <= s_axi_rlast_int;
|
||||
s_axi_ruser_reg <= s_axi_ruser_int;
|
||||
end else if (store_axi_r_temp_to_output) begin
|
||||
s_axi_rid_reg <= temp_s_axi_rid_reg;
|
||||
s_axi_rdata_reg <= temp_s_axi_rdata_reg;
|
||||
s_axi_rresp_reg <= temp_s_axi_rresp_reg;
|
||||
s_axi_rlast_reg <= temp_s_axi_rlast_reg;
|
||||
s_axi_ruser_reg <= temp_s_axi_ruser_reg;
|
||||
end
|
||||
|
||||
if (store_axi_r_int_to_temp) begin
|
||||
temp_s_axi_rid_reg <= s_axi_rid_int;
|
||||
temp_s_axi_rdata_reg <= s_axi_rdata_int;
|
||||
temp_s_axi_rresp_reg <= s_axi_rresp_int;
|
||||
temp_s_axi_rlast_reg <= s_axi_rlast_int;
|
||||
temp_s_axi_ruser_reg <= s_axi_ruser_int;
|
||||
end
|
||||
end
|
||||
|
||||
// output datapath logic (W channel)
|
||||
reg [DATA_WIDTH-1:0] m_axi_wdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [STRB_WIDTH-1:0] m_axi_wstrb_reg = {STRB_WIDTH{1'b0}};
|
||||
reg m_axi_wlast_reg = 1'b0;
|
||||
reg [WUSER_WIDTH-1:0] m_axi_wuser_reg = 1'b0;
|
||||
reg [M_COUNT-1:0] m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
|
||||
|
||||
reg [DATA_WIDTH-1:0] temp_m_axi_wdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [STRB_WIDTH-1:0] temp_m_axi_wstrb_reg = {STRB_WIDTH{1'b0}};
|
||||
reg temp_m_axi_wlast_reg = 1'b0;
|
||||
reg [WUSER_WIDTH-1:0] temp_m_axi_wuser_reg = 1'b0;
|
||||
reg temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next;
|
||||
|
||||
// datapath control
|
||||
reg store_axi_w_int_to_output;
|
||||
reg store_axi_w_int_to_temp;
|
||||
reg store_axi_w_temp_to_output;
|
||||
|
||||
assign m_axi_wdata = {M_COUNT{m_axi_wdata_reg}};
|
||||
assign m_axi_wstrb = {M_COUNT{m_axi_wstrb_reg}};
|
||||
assign m_axi_wlast = {M_COUNT{m_axi_wlast_reg}};
|
||||
assign m_axi_wuser = {M_COUNT{WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}}}};
|
||||
assign m_axi_wvalid = m_axi_wvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign m_axi_wready_int_early = current_m_axi_wready | (~temp_m_axi_wvalid_reg & (~current_m_axi_wvalid | ~m_axi_wvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_wvalid_next = m_axi_wvalid_reg;
|
||||
temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
|
||||
|
||||
store_axi_w_int_to_output = 1'b0;
|
||||
store_axi_w_int_to_temp = 1'b0;
|
||||
store_axi_w_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axi_wready_int_reg) begin
|
||||
// input is ready
|
||||
if (current_m_axi_wready | ~current_m_axi_wvalid) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axi_wvalid_next[m_select_reg] = m_axi_wvalid_int;
|
||||
store_axi_w_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axi_wvalid_next = m_axi_wvalid_int;
|
||||
store_axi_w_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (current_m_axi_wready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axi_wvalid_next[m_select_reg] = temp_m_axi_wvalid_reg;
|
||||
temp_m_axi_wvalid_next = 1'b0;
|
||||
store_axi_w_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
m_axi_wvalid_reg <= 1'b0;
|
||||
m_axi_wready_int_reg <= 1'b0;
|
||||
temp_m_axi_wvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
m_axi_wvalid_reg <= m_axi_wvalid_next;
|
||||
m_axi_wready_int_reg <= m_axi_wready_int_early;
|
||||
temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_axi_w_int_to_output) begin
|
||||
m_axi_wdata_reg <= m_axi_wdata_int;
|
||||
m_axi_wstrb_reg <= m_axi_wstrb_int;
|
||||
m_axi_wlast_reg <= m_axi_wlast_int;
|
||||
m_axi_wuser_reg <= m_axi_wuser_int;
|
||||
end else if (store_axi_w_temp_to_output) begin
|
||||
m_axi_wdata_reg <= temp_m_axi_wdata_reg;
|
||||
m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
|
||||
m_axi_wlast_reg <= temp_m_axi_wlast_reg;
|
||||
m_axi_wuser_reg <= temp_m_axi_wuser_reg;
|
||||
end
|
||||
|
||||
if (store_axi_w_int_to_temp) begin
|
||||
temp_m_axi_wdata_reg <= m_axi_wdata_int;
|
||||
temp_m_axi_wstrb_reg <= m_axi_wstrb_int;
|
||||
temp_m_axi_wlast_reg <= m_axi_wlast_int;
|
||||
temp_m_axi_wuser_reg <= m_axi_wuser_int;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
741
tb/test_axi_interconnect_4x4.py
Executable file
741
tb/test_axi_interconnect_4x4.py
Executable file
@ -0,0 +1,741 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
|
||||
Copyright (c) 2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
"""
|
||||
|
||||
from myhdl import *
|
||||
import os
|
||||
|
||||
import axi
|
||||
|
||||
module = 'axi_interconnect'
|
||||
testbench = 'test_%s_4x4' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("../rtl/arbiter.v")
|
||||
srcs.append("../rtl/priority_encoder.v")
|
||||
srcs.append("%s.v" % testbench)
|
||||
|
||||
src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
DATA_WIDTH = 32
|
||||
ADDR_WIDTH = 32
|
||||
STRB_WIDTH = (DATA_WIDTH/8)
|
||||
ID_WIDTH = 8
|
||||
AWUSER_ENABLE = 0
|
||||
AWUSER_WIDTH = 1
|
||||
WUSER_ENABLE = 0
|
||||
WUSER_WIDTH = 1
|
||||
BUSER_ENABLE = 0
|
||||
BUSER_WIDTH = 1
|
||||
ARUSER_ENABLE = 0
|
||||
ARUSER_WIDTH = 1
|
||||
RUSER_ENABLE = 0
|
||||
RUSER_WIDTH = 1
|
||||
FORWARD_ID = 1
|
||||
S_COUNT = 4
|
||||
M_COUNT = 4
|
||||
M_BASE_ADDR = [0x00000000, 0x01000000, 0x02000000, 0x03000000]
|
||||
M_ADDR_WIDTH = [24, 24, 24, 24]
|
||||
M_CONNECT_READ = [0b1111, 0b1111, 0b1111, 0b1111]
|
||||
M_CONNECT_WRITE = [0b1111, 0b1111, 0b1111, 0b1111]
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
s_axi_awid_list = [Signal(intbv(0)[ID_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_axi_awaddr_list = [Signal(intbv(0)[ADDR_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_axi_awlen_list = [Signal(intbv(0)[8:]) for i in range(S_COUNT)]
|
||||
s_axi_awsize_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)]
|
||||
s_axi_awburst_list = [Signal(intbv(0)[2:]) for i in range(S_COUNT)]
|
||||
s_axi_awlock_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_axi_awcache_list = [Signal(intbv(0)[4:]) for i in range(S_COUNT)]
|
||||
s_axi_awprot_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)]
|
||||
s_axi_awqos_list = [Signal(intbv(0)[4:]) for i in range(S_COUNT)]
|
||||
s_axi_awregion_list = [Signal(intbv(0)[4:]) for i in range(S_COUNT)]
|
||||
s_axi_awuser_list = [Signal(intbv(0)[AWUSER_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_axi_awvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_axi_wdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_axi_wstrb_list = [Signal(intbv(0)[STRB_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_axi_wlast_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_axi_wuser_list = [Signal(intbv(0)[WUSER_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_axi_wvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_axi_bready_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_axi_arid_list = [Signal(intbv(0)[ID_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_axi_araddr_list = [Signal(intbv(0)[ADDR_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_axi_arlen_list = [Signal(intbv(0)[8:]) for i in range(S_COUNT)]
|
||||
s_axi_arsize_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)]
|
||||
s_axi_arburst_list = [Signal(intbv(0)[2:]) for i in range(S_COUNT)]
|
||||
s_axi_arlock_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_axi_arcache_list = [Signal(intbv(0)[4:]) for i in range(S_COUNT)]
|
||||
s_axi_arprot_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)]
|
||||
s_axi_arqos_list = [Signal(intbv(0)[4:]) for i in range(S_COUNT)]
|
||||
s_axi_arregion_list = [Signal(intbv(0)[4:]) for i in range(S_COUNT)]
|
||||
s_axi_aruser_list = [Signal(intbv(0)[ARUSER_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_axi_arvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_axi_rready_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
m_axi_awready_list = [Signal(bool(0)) for i in range(M_COUNT)]
|
||||
m_axi_wready_list = [Signal(bool(0)) for i in range(M_COUNT)]
|
||||
m_axi_bid_list = [Signal(intbv(0)[ID_WIDTH:]) for i in range(M_COUNT)]
|
||||
m_axi_bresp_list = [Signal(intbv(0)[2:]) for i in range(M_COUNT)]
|
||||
m_axi_buser_list = [Signal(intbv(0)[BUSER_WIDTH:]) for i in range(M_COUNT)]
|
||||
m_axi_bvalid_list = [Signal(bool(0)) for i in range(M_COUNT)]
|
||||
m_axi_arready_list = [Signal(bool(0)) for i in range(M_COUNT)]
|
||||
m_axi_rid_list = [Signal(intbv(0)[ID_WIDTH:]) for i in range(M_COUNT)]
|
||||
m_axi_rdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(M_COUNT)]
|
||||
m_axi_rresp_list = [Signal(intbv(0)[2:]) for i in range(M_COUNT)]
|
||||
m_axi_rlast_list = [Signal(bool(0)) for i in range(M_COUNT)]
|
||||
m_axi_ruser_list = [Signal(intbv(0)[RUSER_WIDTH:]) for i in range(M_COUNT)]
|
||||
m_axi_rvalid_list = [Signal(bool(0)) for i in range(M_COUNT)]
|
||||
|
||||
s_axi_awid = ConcatSignal(*reversed(s_axi_awid_list))
|
||||
s_axi_awaddr = ConcatSignal(*reversed(s_axi_awaddr_list))
|
||||
s_axi_awlen = ConcatSignal(*reversed(s_axi_awlen_list))
|
||||
s_axi_awsize = ConcatSignal(*reversed(s_axi_awsize_list))
|
||||
s_axi_awburst = ConcatSignal(*reversed(s_axi_awburst_list))
|
||||
s_axi_awlock = ConcatSignal(*reversed(s_axi_awlock_list))
|
||||
s_axi_awcache = ConcatSignal(*reversed(s_axi_awcache_list))
|
||||
s_axi_awprot = ConcatSignal(*reversed(s_axi_awprot_list))
|
||||
s_axi_awqos = ConcatSignal(*reversed(s_axi_awqos_list))
|
||||
s_axi_awregion = ConcatSignal(*reversed(s_axi_awregion_list))
|
||||
s_axi_awuser = ConcatSignal(*reversed(s_axi_awuser_list))
|
||||
s_axi_awvalid = ConcatSignal(*reversed(s_axi_awvalid_list))
|
||||
s_axi_wdata = ConcatSignal(*reversed(s_axi_wdata_list))
|
||||
s_axi_wstrb = ConcatSignal(*reversed(s_axi_wstrb_list))
|
||||
s_axi_wlast = ConcatSignal(*reversed(s_axi_wlast_list))
|
||||
s_axi_wuser = ConcatSignal(*reversed(s_axi_wuser_list))
|
||||
s_axi_wvalid = ConcatSignal(*reversed(s_axi_wvalid_list))
|
||||
s_axi_bready = ConcatSignal(*reversed(s_axi_bready_list))
|
||||
s_axi_arid = ConcatSignal(*reversed(s_axi_arid_list))
|
||||
s_axi_araddr = ConcatSignal(*reversed(s_axi_araddr_list))
|
||||
s_axi_arlen = ConcatSignal(*reversed(s_axi_arlen_list))
|
||||
s_axi_arsize = ConcatSignal(*reversed(s_axi_arsize_list))
|
||||
s_axi_arburst = ConcatSignal(*reversed(s_axi_arburst_list))
|
||||
s_axi_arlock = ConcatSignal(*reversed(s_axi_arlock_list))
|
||||
s_axi_arcache = ConcatSignal(*reversed(s_axi_arcache_list))
|
||||
s_axi_arprot = ConcatSignal(*reversed(s_axi_arprot_list))
|
||||
s_axi_arqos = ConcatSignal(*reversed(s_axi_arqos_list))
|
||||
s_axi_arregion = ConcatSignal(*reversed(s_axi_arregion_list))
|
||||
s_axi_aruser = ConcatSignal(*reversed(s_axi_aruser_list))
|
||||
s_axi_arvalid = ConcatSignal(*reversed(s_axi_arvalid_list))
|
||||
s_axi_rready = ConcatSignal(*reversed(s_axi_rready_list))
|
||||
m_axi_awready = ConcatSignal(*reversed(m_axi_awready_list))
|
||||
m_axi_wready = ConcatSignal(*reversed(m_axi_wready_list))
|
||||
m_axi_bid = ConcatSignal(*reversed(m_axi_bid_list))
|
||||
m_axi_bresp = ConcatSignal(*reversed(m_axi_bresp_list))
|
||||
m_axi_buser = ConcatSignal(*reversed(m_axi_buser_list))
|
||||
m_axi_bvalid = ConcatSignal(*reversed(m_axi_bvalid_list))
|
||||
m_axi_arready = ConcatSignal(*reversed(m_axi_arready_list))
|
||||
m_axi_rid = ConcatSignal(*reversed(m_axi_rid_list))
|
||||
m_axi_rdata = ConcatSignal(*reversed(m_axi_rdata_list))
|
||||
m_axi_rresp = ConcatSignal(*reversed(m_axi_rresp_list))
|
||||
m_axi_rlast = ConcatSignal(*reversed(m_axi_rlast_list))
|
||||
m_axi_ruser = ConcatSignal(*reversed(m_axi_ruser_list))
|
||||
m_axi_rvalid = ConcatSignal(*reversed(m_axi_rvalid_list))
|
||||
|
||||
# Outputs
|
||||
s_axi_awready = Signal(intbv(0)[S_COUNT:])
|
||||
s_axi_wready = Signal(intbv(0)[S_COUNT:])
|
||||
s_axi_bid = Signal(intbv(0)[S_COUNT*ID_WIDTH:])
|
||||
s_axi_bresp = Signal(intbv(0)[S_COUNT*2:])
|
||||
s_axi_buser = Signal(intbv(0)[S_COUNT*BUSER_WIDTH:])
|
||||
s_axi_bvalid = Signal(intbv(0)[S_COUNT:])
|
||||
s_axi_arready = Signal(intbv(0)[S_COUNT:])
|
||||
s_axi_rid = Signal(intbv(0)[S_COUNT*ID_WIDTH:])
|
||||
s_axi_rdata = Signal(intbv(0)[S_COUNT*DATA_WIDTH:])
|
||||
s_axi_rresp = Signal(intbv(0)[S_COUNT*2:])
|
||||
s_axi_rlast = Signal(intbv(0)[S_COUNT:])
|
||||
s_axi_ruser = Signal(intbv(0)[S_COUNT*RUSER_WIDTH:])
|
||||
s_axi_rvalid = Signal(intbv(0)[S_COUNT:])
|
||||
m_axi_awid = Signal(intbv(0)[M_COUNT*ID_WIDTH:])
|
||||
m_axi_awaddr = Signal(intbv(0)[M_COUNT*ADDR_WIDTH:])
|
||||
m_axi_awlen = Signal(intbv(0)[M_COUNT*8:])
|
||||
m_axi_awsize = Signal(intbv(0)[M_COUNT*3:])
|
||||
m_axi_awburst = Signal(intbv(0)[M_COUNT*2:])
|
||||
m_axi_awlock = Signal(intbv(0)[M_COUNT:])
|
||||
m_axi_awcache = Signal(intbv(0)[M_COUNT*4:])
|
||||
m_axi_awprot = Signal(intbv(0)[M_COUNT*3:])
|
||||
m_axi_awqos = Signal(intbv(0)[M_COUNT*4:])
|
||||
m_axi_awregion = Signal(intbv(0)[M_COUNT*4:])
|
||||
m_axi_awuser = Signal(intbv(0)[M_COUNT*AWUSER_WIDTH:])
|
||||
m_axi_awvalid = Signal(intbv(0)[M_COUNT:])
|
||||
m_axi_wdata = Signal(intbv(0)[M_COUNT*DATA_WIDTH:])
|
||||
m_axi_wstrb = Signal(intbv(0)[M_COUNT*STRB_WIDTH:])
|
||||
m_axi_wlast = Signal(intbv(0)[M_COUNT:])
|
||||
m_axi_wuser = Signal(intbv(0)[M_COUNT*WUSER_WIDTH:])
|
||||
m_axi_wvalid = Signal(intbv(0)[M_COUNT:])
|
||||
m_axi_bready = Signal(intbv(0)[M_COUNT:])
|
||||
m_axi_arid = Signal(intbv(0)[M_COUNT*ID_WIDTH:])
|
||||
m_axi_araddr = Signal(intbv(0)[M_COUNT*ADDR_WIDTH:])
|
||||
m_axi_arlen = Signal(intbv(0)[M_COUNT*8:])
|
||||
m_axi_arsize = Signal(intbv(0)[M_COUNT*3:])
|
||||
m_axi_arburst = Signal(intbv(0)[M_COUNT*2:])
|
||||
m_axi_arlock = Signal(intbv(0)[M_COUNT:])
|
||||
m_axi_arcache = Signal(intbv(0)[M_COUNT*4:])
|
||||
m_axi_arprot = Signal(intbv(0)[M_COUNT*3:])
|
||||
m_axi_arqos = Signal(intbv(0)[M_COUNT*4:])
|
||||
m_axi_arregion = Signal(intbv(0)[M_COUNT*4:])
|
||||
m_axi_aruser = Signal(intbv(0)[M_COUNT*ARUSER_WIDTH:])
|
||||
m_axi_arvalid = Signal(intbv(0)[M_COUNT:])
|
||||
m_axi_rready = Signal(intbv(0)[M_COUNT:])
|
||||
|
||||
s_axi_awready_list = [s_axi_awready(i) for i in range(S_COUNT)]
|
||||
s_axi_wready_list = [s_axi_wready(i) for i in range(S_COUNT)]
|
||||
s_axi_bid_list = [s_axi_bid((i+1)*ID_WIDTH, i*ID_WIDTH) for i in range(S_COUNT)]
|
||||
s_axi_bresp_list = [s_axi_bresp((i+1)*2, i*2) for i in range(S_COUNT)]
|
||||
s_axi_buser_list = [s_axi_buser((i+1)*BUSER_WIDTH, i*BUSER_WIDTH) for i in range(S_COUNT)]
|
||||
s_axi_bvalid_list = [s_axi_bvalid(i) for i in range(S_COUNT)]
|
||||
s_axi_arready_list = [s_axi_arready(i) for i in range(S_COUNT)]
|
||||
s_axi_rid_list = [s_axi_rid((i+1)*ID_WIDTH, i*ID_WIDTH) for i in range(S_COUNT)]
|
||||
s_axi_rdata_list = [s_axi_rdata((i+1)*DATA_WIDTH, i*DATA_WIDTH) for i in range(S_COUNT)]
|
||||
s_axi_rresp_list = [s_axi_rresp((i+1)*2, i*2) for i in range(S_COUNT)]
|
||||
s_axi_rlast_list = [s_axi_rlast(i) for i in range(S_COUNT)]
|
||||
s_axi_ruser_list = [s_axi_ruser((i+1)*RUSER_WIDTH, i*RUSER_WIDTH) for i in range(S_COUNT)]
|
||||
s_axi_rvalid_list = [s_axi_rvalid(i) for i in range(S_COUNT)]
|
||||
m_axi_awid_list = [m_axi_awid((i+1)*ID_WIDTH, i*ID_WIDTH) for i in range(M_COUNT)]
|
||||
m_axi_awaddr_list = [m_axi_awaddr((i+1)*ADDR_WIDTH, i*ADDR_WIDTH) for i in range(M_COUNT)]
|
||||
m_axi_awlen_list = [m_axi_awlen((i+1)*8, i*8) for i in range(M_COUNT)]
|
||||
m_axi_awsize_list = [m_axi_awsize((i+1)*3, i*3) for i in range(M_COUNT)]
|
||||
m_axi_awburst_list = [m_axi_awburst((i+1)*2, i*2) for i in range(M_COUNT)]
|
||||
m_axi_awlock_list = [m_axi_awlock(i) for i in range(M_COUNT)]
|
||||
m_axi_awcache_list = [m_axi_awcache((i+1)*4, i*4) for i in range(M_COUNT)]
|
||||
m_axi_awprot_list = [m_axi_awprot((i+1)*3, i*3) for i in range(M_COUNT)]
|
||||
m_axi_awqos_list = [m_axi_awqos((i+1)*4, i*4) for i in range(M_COUNT)]
|
||||
m_axi_awregion_list = [m_axi_awregion((i+1)*4, i*4) for i in range(M_COUNT)]
|
||||
m_axi_awuser_list = [m_axi_awuser((i+1)*AWUSER_WIDTH, i*AWUSER_WIDTH) for i in range(M_COUNT)]
|
||||
m_axi_awvalid_list = [m_axi_awvalid(i) for i in range(M_COUNT)]
|
||||
m_axi_wdata_list = [m_axi_wdata((i+1)*DATA_WIDTH, i*DATA_WIDTH) for i in range(M_COUNT)]
|
||||
m_axi_wstrb_list = [m_axi_wstrb((i+1)*STRB_WIDTH, i*STRB_WIDTH) for i in range(M_COUNT)]
|
||||
m_axi_wlast_list = [m_axi_wlast(i) for i in range(M_COUNT)]
|
||||
m_axi_wuser_list = [m_axi_wuser((i+1)*WUSER_WIDTH, i*WUSER_WIDTH) for i in range(M_COUNT)]
|
||||
m_axi_wvalid_list = [m_axi_wvalid(i) for i in range(M_COUNT)]
|
||||
m_axi_bready_list = [m_axi_bready(i) for i in range(M_COUNT)]
|
||||
m_axi_arid_list = [m_axi_arid((i+1)*ID_WIDTH, i*ID_WIDTH) for i in range(M_COUNT)]
|
||||
m_axi_araddr_list = [m_axi_araddr((i+1)*ADDR_WIDTH, i*ADDR_WIDTH) for i in range(M_COUNT)]
|
||||
m_axi_arlen_list = [m_axi_arlen((i+1)*8, i*8) for i in range(M_COUNT)]
|
||||
m_axi_arsize_list = [m_axi_arsize((i+1)*3, i*3) for i in range(M_COUNT)]
|
||||
m_axi_arburst_list = [m_axi_arburst((i+1)*2, i*2) for i in range(M_COUNT)]
|
||||
m_axi_arlock_list = [m_axi_arlock(i) for i in range(M_COUNT)]
|
||||
m_axi_arcache_list = [m_axi_arcache((i+1)*4, i*4) for i in range(M_COUNT)]
|
||||
m_axi_arprot_list = [m_axi_arprot((i+1)*3, i*3) for i in range(M_COUNT)]
|
||||
m_axi_arqos_list = [m_axi_arqos((i+1)*4, i*4) for i in range(M_COUNT)]
|
||||
m_axi_arregion_list = [m_axi_arregion((i+1)*4, i*4) for i in range(M_COUNT)]
|
||||
m_axi_aruser_list = [m_axi_aruser((i+1)*ARUSER_WIDTH, i*ARUSER_WIDTH) for i in range(M_COUNT)]
|
||||
m_axi_arvalid_list = [m_axi_arvalid(i) for i in range(M_COUNT)]
|
||||
m_axi_rready_list = [m_axi_rready(i) for i in range(M_COUNT)]
|
||||
|
||||
# AXI4 masters
|
||||
axi_master_inst_list = []
|
||||
axi_master_pause_list = []
|
||||
axi_master_logic = []
|
||||
|
||||
for k in range(S_COUNT):
|
||||
m = axi.AXIMaster()
|
||||
p = Signal(bool(False))
|
||||
|
||||
axi_master_inst_list.append(m)
|
||||
axi_master_pause_list.append(p)
|
||||
|
||||
axi_master_logic.append(m.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
m_axi_awid=s_axi_awid_list[k],
|
||||
m_axi_awaddr=s_axi_awaddr_list[k],
|
||||
m_axi_awlen=s_axi_awlen_list[k],
|
||||
m_axi_awsize=s_axi_awsize_list[k],
|
||||
m_axi_awburst=s_axi_awburst_list[k],
|
||||
m_axi_awlock=s_axi_awlock_list[k],
|
||||
m_axi_awcache=s_axi_awcache_list[k],
|
||||
m_axi_awprot=s_axi_awprot_list[k],
|
||||
m_axi_awqos=s_axi_awqos_list[k],
|
||||
m_axi_awregion=s_axi_awregion_list[k],
|
||||
m_axi_awvalid=s_axi_awvalid_list[k],
|
||||
m_axi_awready=s_axi_awready_list[k],
|
||||
m_axi_wdata=s_axi_wdata_list[k],
|
||||
m_axi_wstrb=s_axi_wstrb_list[k],
|
||||
m_axi_wlast=s_axi_wlast_list[k],
|
||||
m_axi_wvalid=s_axi_wvalid_list[k],
|
||||
m_axi_wready=s_axi_wready_list[k],
|
||||
m_axi_bid=s_axi_bid_list[k],
|
||||
m_axi_bresp=s_axi_bresp_list[k],
|
||||
m_axi_bvalid=s_axi_bvalid_list[k],
|
||||
m_axi_bready=s_axi_bready_list[k],
|
||||
m_axi_arid=s_axi_arid_list[k],
|
||||
m_axi_araddr=s_axi_araddr_list[k],
|
||||
m_axi_arlen=s_axi_arlen_list[k],
|
||||
m_axi_arsize=s_axi_arsize_list[k],
|
||||
m_axi_arburst=s_axi_arburst_list[k],
|
||||
m_axi_arlock=s_axi_arlock_list[k],
|
||||
m_axi_arcache=s_axi_arcache_list[k],
|
||||
m_axi_arprot=s_axi_arprot_list[k],
|
||||
m_axi_arqos=s_axi_arqos_list[k],
|
||||
m_axi_arregion=s_axi_arregion_list[k],
|
||||
m_axi_arvalid=s_axi_arvalid_list[k],
|
||||
m_axi_arready=s_axi_arready_list[k],
|
||||
m_axi_rid=s_axi_rid_list[k],
|
||||
m_axi_rdata=s_axi_rdata_list[k],
|
||||
m_axi_rresp=s_axi_rresp_list[k],
|
||||
m_axi_rlast=s_axi_rlast_list[k],
|
||||
m_axi_rvalid=s_axi_rvalid_list[k],
|
||||
m_axi_rready=s_axi_rready_list[k],
|
||||
pause=p,
|
||||
name='master_%d' % k
|
||||
))
|
||||
|
||||
# AXI4 RAM models
|
||||
axi_ram_inst_list = []
|
||||
axi_ram_pause_list = []
|
||||
axi_ram_logic = []
|
||||
|
||||
for k in range(M_COUNT):
|
||||
r = axi.AXIRam(2**16)
|
||||
p = Signal(bool(False))
|
||||
|
||||
axi_ram_inst_list.append(r)
|
||||
axi_ram_pause_list.append(p)
|
||||
|
||||
axi_ram_logic.append(r.create_port(
|
||||
clk,
|
||||
s_axi_awid=m_axi_awid_list[k],
|
||||
s_axi_awaddr=m_axi_awaddr_list[k],
|
||||
s_axi_awlen=m_axi_awlen_list[k],
|
||||
s_axi_awsize=m_axi_awsize_list[k],
|
||||
s_axi_awburst=m_axi_awburst_list[k],
|
||||
s_axi_awlock=m_axi_awlock_list[k],
|
||||
s_axi_awcache=m_axi_awcache_list[k],
|
||||
s_axi_awprot=m_axi_awprot_list[k],
|
||||
s_axi_awvalid=m_axi_awvalid_list[k],
|
||||
s_axi_awready=m_axi_awready_list[k],
|
||||
s_axi_wdata=m_axi_wdata_list[k],
|
||||
s_axi_wstrb=m_axi_wstrb_list[k],
|
||||
s_axi_wlast=m_axi_wlast_list[k],
|
||||
s_axi_wvalid=m_axi_wvalid_list[k],
|
||||
s_axi_wready=m_axi_wready_list[k],
|
||||
s_axi_bid=m_axi_bid_list[k],
|
||||
s_axi_bresp=m_axi_bresp_list[k],
|
||||
s_axi_bvalid=m_axi_bvalid_list[k],
|
||||
s_axi_bready=m_axi_bready_list[k],
|
||||
s_axi_arid=m_axi_arid_list[k],
|
||||
s_axi_araddr=m_axi_araddr_list[k],
|
||||
s_axi_arlen=m_axi_arlen_list[k],
|
||||
s_axi_arsize=m_axi_arsize_list[k],
|
||||
s_axi_arburst=m_axi_arburst_list[k],
|
||||
s_axi_arlock=m_axi_arlock_list[k],
|
||||
s_axi_arcache=m_axi_arcache_list[k],
|
||||
s_axi_arprot=m_axi_arprot_list[k],
|
||||
s_axi_arvalid=m_axi_arvalid_list[k],
|
||||
s_axi_arready=m_axi_arready_list[k],
|
||||
s_axi_rid=m_axi_rid_list[k],
|
||||
s_axi_rdata=m_axi_rdata_list[k],
|
||||
s_axi_rresp=m_axi_rresp_list[k],
|
||||
s_axi_rlast=m_axi_rlast_list[k],
|
||||
s_axi_rvalid=m_axi_rvalid_list[k],
|
||||
s_axi_rready=m_axi_rready_list[k],
|
||||
pause=p,
|
||||
name='ram_%d' % k
|
||||
))
|
||||
|
||||
# DUT
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
|
||||
dut = Cosimulation(
|
||||
"vvp -m myhdl %s.vvp -lxt2" % testbench,
|
||||
clk=clk,
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
s_axi_awid=s_axi_awid,
|
||||
s_axi_awaddr=s_axi_awaddr,
|
||||
s_axi_awlen=s_axi_awlen,
|
||||
s_axi_awsize=s_axi_awsize,
|
||||
s_axi_awburst=s_axi_awburst,
|
||||
s_axi_awlock=s_axi_awlock,
|
||||
s_axi_awcache=s_axi_awcache,
|
||||
s_axi_awprot=s_axi_awprot,
|
||||
s_axi_awqos=s_axi_awqos,
|
||||
s_axi_awregion=s_axi_awregion,
|
||||
s_axi_awuser=s_axi_awuser,
|
||||
s_axi_awvalid=s_axi_awvalid,
|
||||
s_axi_awready=s_axi_awready,
|
||||
s_axi_wdata=s_axi_wdata,
|
||||
s_axi_wstrb=s_axi_wstrb,
|
||||
s_axi_wlast=s_axi_wlast,
|
||||
s_axi_wuser=s_axi_wuser,
|
||||
s_axi_wvalid=s_axi_wvalid,
|
||||
s_axi_wready=s_axi_wready,
|
||||
s_axi_bid=s_axi_bid,
|
||||
s_axi_bresp=s_axi_bresp,
|
||||
s_axi_buser=s_axi_buser,
|
||||
s_axi_bvalid=s_axi_bvalid,
|
||||
s_axi_bready=s_axi_bready,
|
||||
s_axi_arid=s_axi_arid,
|
||||
s_axi_araddr=s_axi_araddr,
|
||||
s_axi_arlen=s_axi_arlen,
|
||||
s_axi_arsize=s_axi_arsize,
|
||||
s_axi_arburst=s_axi_arburst,
|
||||
s_axi_arlock=s_axi_arlock,
|
||||
s_axi_arcache=s_axi_arcache,
|
||||
s_axi_arprot=s_axi_arprot,
|
||||
s_axi_arqos=s_axi_arqos,
|
||||
s_axi_arregion=s_axi_arregion,
|
||||
s_axi_aruser=s_axi_aruser,
|
||||
s_axi_arvalid=s_axi_arvalid,
|
||||
s_axi_arready=s_axi_arready,
|
||||
s_axi_rid=s_axi_rid,
|
||||
s_axi_rdata=s_axi_rdata,
|
||||
s_axi_rresp=s_axi_rresp,
|
||||
s_axi_rlast=s_axi_rlast,
|
||||
s_axi_ruser=s_axi_ruser,
|
||||
s_axi_rvalid=s_axi_rvalid,
|
||||
s_axi_rready=s_axi_rready,
|
||||
m_axi_awid=m_axi_awid,
|
||||
m_axi_awaddr=m_axi_awaddr,
|
||||
m_axi_awlen=m_axi_awlen,
|
||||
m_axi_awsize=m_axi_awsize,
|
||||
m_axi_awburst=m_axi_awburst,
|
||||
m_axi_awlock=m_axi_awlock,
|
||||
m_axi_awcache=m_axi_awcache,
|
||||
m_axi_awprot=m_axi_awprot,
|
||||
m_axi_awqos=m_axi_awqos,
|
||||
m_axi_awregion=m_axi_awregion,
|
||||
m_axi_awuser=m_axi_awuser,
|
||||
m_axi_awvalid=m_axi_awvalid,
|
||||
m_axi_awready=m_axi_awready,
|
||||
m_axi_wdata=m_axi_wdata,
|
||||
m_axi_wstrb=m_axi_wstrb,
|
||||
m_axi_wlast=m_axi_wlast,
|
||||
m_axi_wuser=m_axi_wuser,
|
||||
m_axi_wvalid=m_axi_wvalid,
|
||||
m_axi_wready=m_axi_wready,
|
||||
m_axi_bid=m_axi_bid,
|
||||
m_axi_bresp=m_axi_bresp,
|
||||
m_axi_buser=m_axi_buser,
|
||||
m_axi_bvalid=m_axi_bvalid,
|
||||
m_axi_bready=m_axi_bready,
|
||||
m_axi_arid=m_axi_arid,
|
||||
m_axi_araddr=m_axi_araddr,
|
||||
m_axi_arlen=m_axi_arlen,
|
||||
m_axi_arsize=m_axi_arsize,
|
||||
m_axi_arburst=m_axi_arburst,
|
||||
m_axi_arlock=m_axi_arlock,
|
||||
m_axi_arcache=m_axi_arcache,
|
||||
m_axi_arprot=m_axi_arprot,
|
||||
m_axi_arqos=m_axi_arqos,
|
||||
m_axi_arregion=m_axi_arregion,
|
||||
m_axi_aruser=m_axi_aruser,
|
||||
m_axi_arvalid=m_axi_arvalid,
|
||||
m_axi_arready=m_axi_arready,
|
||||
m_axi_rid=m_axi_rid,
|
||||
m_axi_rdata=m_axi_rdata,
|
||||
m_axi_rresp=m_axi_rresp,
|
||||
m_axi_rlast=m_axi_rlast,
|
||||
m_axi_ruser=m_axi_ruser,
|
||||
m_axi_rvalid=m_axi_rvalid,
|
||||
m_axi_rready=m_axi_rready
|
||||
)
|
||||
|
||||
@always(delay(4))
|
||||
def clkgen():
|
||||
clk.next = not clk
|
||||
|
||||
def wait_normal():
|
||||
while not all([axi_master_inst_list[k].idle() for k in range(S_COUNT)]):
|
||||
yield clk.posedge
|
||||
|
||||
def wait_pause_master():
|
||||
while not all([axi_master_inst_list[k].idle() for k in range(S_COUNT)]):
|
||||
for k in range(S_COUNT):
|
||||
axi_master_pause_list[k].next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
for k in range(S_COUNT):
|
||||
axi_master_pause_list[k].next = False
|
||||
yield clk.posedge
|
||||
|
||||
def wait_pause_slave():
|
||||
while not all([axi_master_inst_list[k].idle() for k in range(S_COUNT)]):
|
||||
for k in range(M_COUNT):
|
||||
axi_ram_pause_list[k].next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
for k in range(M_COUNT):
|
||||
axi_ram_pause_list[k].next = False
|
||||
yield clk.posedge
|
||||
|
||||
@instance
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
rst.next = 1
|
||||
yield clk.posedge
|
||||
rst.next = 0
|
||||
yield clk.posedge
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
|
||||
# testbench stimulus
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: write")
|
||||
current_test.next = 1
|
||||
|
||||
addr = 4
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
|
||||
axi_master_inst_list[0].init_write(addr, test_data)
|
||||
|
||||
yield axi_master_inst_list[0].wait()
|
||||
yield clk.posedge
|
||||
|
||||
data = axi_ram_inst_list[0].read_mem(addr&0xffffff80, 32)
|
||||
for i in range(0, len(data), 16):
|
||||
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
|
||||
|
||||
assert axi_ram_inst_list[0].read_mem(addr, len(test_data)) == test_data
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 2: read")
|
||||
current_test.next = 2
|
||||
|
||||
addr = 4
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
|
||||
axi_ram_inst_list[0].write_mem(addr, test_data)
|
||||
|
||||
axi_master_inst_list[0].init_read(addr, len(test_data))
|
||||
|
||||
yield axi_master_inst_list[0].wait()
|
||||
yield clk.posedge
|
||||
|
||||
data = axi_master_inst_list[0].get_read_data()
|
||||
assert data[0] == addr
|
||||
assert data[1] == test_data
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 3: one to many")
|
||||
current_test.next = 3
|
||||
|
||||
addr = 4
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
|
||||
for k in range(S_COUNT):
|
||||
axi_master_inst_list[0].init_write(addr+M_BASE_ADDR[k], test_data)
|
||||
|
||||
yield axi_master_inst_list[0].wait()
|
||||
yield clk.posedge
|
||||
|
||||
for k in range(S_COUNT):
|
||||
data = axi_ram_inst_list[k].read_mem(addr&0xffffff80, 32)
|
||||
for i in range(0, len(data), 16):
|
||||
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
|
||||
|
||||
for k in range(S_COUNT):
|
||||
assert axi_ram_inst_list[k].read_mem(addr, len(test_data)) == test_data
|
||||
|
||||
for k in range(S_COUNT):
|
||||
axi_master_inst_list[0].init_read(addr+M_BASE_ADDR[k], len(test_data))
|
||||
|
||||
yield axi_master_inst_list[0].wait()
|
||||
yield clk.posedge
|
||||
|
||||
for k in range(S_COUNT):
|
||||
data = axi_master_inst_list[0].get_read_data()
|
||||
assert data[0] == addr+M_BASE_ADDR[k]
|
||||
assert data[1] == test_data
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 4: many to one")
|
||||
current_test.next = 4
|
||||
|
||||
for k in range(M_COUNT):
|
||||
axi_master_inst_list[k].init_write(k*4, bytearray([(k+1)*17]*4))
|
||||
|
||||
for k in range(M_COUNT):
|
||||
yield axi_master_inst_list[k].wait()
|
||||
yield clk.posedge
|
||||
|
||||
data = axi_ram_inst_list[0].read_mem(addr&0xffffff80, 32)
|
||||
for i in range(0, len(data), 16):
|
||||
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
|
||||
|
||||
for k in range(M_COUNT):
|
||||
assert axi_ram_inst_list[0].read_mem(k*4, 4) == bytearray([(k+1)*17]*4)
|
||||
|
||||
for k in range(M_COUNT):
|
||||
axi_master_inst_list[k].init_read(k*4, 4)
|
||||
|
||||
for k in range(M_COUNT):
|
||||
yield axi_master_inst_list[k].wait()
|
||||
yield clk.posedge
|
||||
|
||||
for k in range(M_COUNT):
|
||||
data = axi_master_inst_list[k].get_read_data()
|
||||
assert data[0] == k*4
|
||||
assert data[1] == bytearray([(k+1)*17]*4)
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 5: various writes")
|
||||
current_test.next = 5
|
||||
|
||||
for length in list(range(1,8))+[1024]:
|
||||
for offset in list(range(4,8))+[4096-4]:
|
||||
for wait in wait_normal, wait_pause_master, wait_pause_slave:
|
||||
print("length %d, offset %d"% (length, offset))
|
||||
#addr = 256*(16*offset+length)+offset
|
||||
addr = offset
|
||||
test_data = bytearray([x%256 for x in range(length)])
|
||||
|
||||
axi_ram_inst_list[0].write_mem(addr&0xffffff80, b'\xAA'*(length+256))
|
||||
axi_master_inst_list[0].init_write(addr, test_data)
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
|
||||
data = axi_ram_inst_list[0].read_mem(addr&0xffffff80, 32)
|
||||
for i in range(0, len(data), 16):
|
||||
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
|
||||
|
||||
assert axi_ram_inst_list[0].read_mem(addr, length) == test_data
|
||||
assert axi_ram_inst_list[0].read_mem(addr-1, 1) == b'\xAA'
|
||||
assert axi_ram_inst_list[0].read_mem(addr+length, 1) == b'\xAA'
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 6: various reads")
|
||||
current_test.next = 6
|
||||
|
||||
for length in list(range(1,8))+[1024]:
|
||||
for offset in list(range(4,8))+[4096-4]:
|
||||
for wait in wait_normal, wait_pause_master, wait_pause_slave:
|
||||
print("length %d, offset %d"% (length, offset))
|
||||
#addr = 256*(16*offset+length)+offset
|
||||
addr = offset
|
||||
test_data = bytearray([x%256 for x in range(length)])
|
||||
|
||||
axi_ram_inst_list[0].write_mem(addr, test_data)
|
||||
|
||||
axi_master_inst_list[0].init_read(addr, length)
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
|
||||
data = axi_master_inst_list[0].get_read_data()
|
||||
assert data[0] == addr
|
||||
assert data[1] == test_data
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 7: concurrent operations")
|
||||
current_test.next = 7
|
||||
|
||||
for count in [1, 2, 4, 8]:
|
||||
for stride in [2, 3, 5, 7]:
|
||||
for wait in wait_normal, wait_pause_master, wait_pause_slave:
|
||||
print("count %d, stride %d"% (count, stride))
|
||||
|
||||
for k in range(S_COUNT):
|
||||
for l in range(count):
|
||||
ram = ((k*61+l)*stride)%M_COUNT
|
||||
offset = k*256+l*4
|
||||
axi_ram_inst_list[ram].write_mem(offset, b'\xAA'*4)
|
||||
axi_master_inst_list[k].init_write(M_BASE_ADDR[ram]+offset, bytearray([0xaa, k, l, 0xaa]))
|
||||
|
||||
ram = ((k*61+l+67)*stride)%M_COUNT
|
||||
offset = k*256+l*4
|
||||
axi_ram_inst_list[ram].write_mem(offset+0x8000, bytearray([0xaa, k, l, 0xaa]))
|
||||
axi_master_inst_list[k].init_read(M_BASE_ADDR[ram]+offset+0x8000, 4)
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
|
||||
for k in range(S_COUNT):
|
||||
for l in range(count):
|
||||
ram = ((k*61+l)*stride)%M_COUNT
|
||||
offset = k*256+l*4
|
||||
axi_ram_inst_list[ram].read_mem(offset, 4) == bytearray([0xaa, k, l, 0xaa])
|
||||
|
||||
ram = ((k*61+l+67)*stride)%M_COUNT
|
||||
offset = k*256+l*4
|
||||
data = axi_master_inst_list[k].get_read_data()
|
||||
assert data[0] == M_BASE_ADDR[ram]+offset+0x8000
|
||||
assert data[1] == bytearray([0xaa, k, l, 0xaa])
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 8: bad write")
|
||||
current_test.next = 8
|
||||
|
||||
axi_master_inst_list[0].init_write(0xff000000, b'\xDE\xAD\xBE\xEF')
|
||||
|
||||
yield axi_master_inst_list[0].wait()
|
||||
yield clk.posedge
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 2: bad read")
|
||||
current_test.next = 2
|
||||
|
||||
axi_master_inst_list[0].init_read(0xff000000, 4)
|
||||
|
||||
yield axi_master_inst_list[0].wait()
|
||||
yield clk.posedge
|
||||
|
||||
data = axi_master_inst_list[0].get_read_data()
|
||||
assert data[0] == 0xff000000
|
||||
|
||||
yield delay(100)
|
||||
|
||||
raise StopSimulation
|
||||
|
||||
return instances()
|
||||
|
||||
def test_bench():
|
||||
sim = Simulation(bench())
|
||||
sim.run()
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("Running test...")
|
||||
test_bench()
|
||||
372
tb/test_axi_interconnect_4x4.v
Normal file
372
tb/test_axi_interconnect_4x4.v
Normal file
@ -0,0 +1,372 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for axi_interconnect
|
||||
*/
|
||||
module test_axi_interconnect_4x4;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 32;
|
||||
parameter ADDR_WIDTH = 32;
|
||||
parameter STRB_WIDTH = (DATA_WIDTH/8);
|
||||
parameter ID_WIDTH = 8;
|
||||
parameter AWUSER_ENABLE = 0;
|
||||
parameter AWUSER_WIDTH = 1;
|
||||
parameter WUSER_ENABLE = 0;
|
||||
parameter WUSER_WIDTH = 1;
|
||||
parameter BUSER_ENABLE = 0;
|
||||
parameter BUSER_WIDTH = 1;
|
||||
parameter ARUSER_ENABLE = 0;
|
||||
parameter ARUSER_WIDTH = 1;
|
||||
parameter RUSER_ENABLE = 0;
|
||||
parameter RUSER_WIDTH = 1;
|
||||
parameter FORWARD_ID = 1;
|
||||
parameter S_COUNT = 4;
|
||||
parameter M_COUNT = 4;
|
||||
parameter M_BASE_ADDR = {32'h03000000, 32'h02000000, 32'h01000000, 32'h00000000};
|
||||
parameter M_ADDR_WIDTH = {32'd24, 32'd24, 32'd24, 32'd24};
|
||||
parameter M_CONNECT_READ = {4'b1111, 4'b1111, 4'b1111, 4'b1111};
|
||||
parameter M_CONNECT_WRITE = {4'b1111, 4'b1111, 4'b1111, 4'b1111};
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [S_COUNT*ID_WIDTH-1:0] s_axi_awid = 0;
|
||||
reg [S_COUNT*ADDR_WIDTH-1:0] s_axi_awaddr = 0;
|
||||
reg [S_COUNT*8-1:0] s_axi_awlen = 0;
|
||||
reg [S_COUNT*3-1:0] s_axi_awsize = 0;
|
||||
reg [S_COUNT*2-1:0] s_axi_awburst = 0;
|
||||
reg [S_COUNT-1:0] s_axi_awlock = 0;
|
||||
reg [S_COUNT*4-1:0] s_axi_awcache = 0;
|
||||
reg [S_COUNT*3-1:0] s_axi_awprot = 0;
|
||||
reg [S_COUNT*4-1:0] s_axi_awqos = 0;
|
||||
reg [S_COUNT*4-1:0] s_axi_awregion = 0;
|
||||
reg [S_COUNT*AWUSER_WIDTH-1:0] s_axi_awuser = 0;
|
||||
reg [S_COUNT-1:0] s_axi_awvalid = 0;
|
||||
reg [S_COUNT*DATA_WIDTH-1:0] s_axi_wdata = 0;
|
||||
reg [S_COUNT*STRB_WIDTH-1:0] s_axi_wstrb = 0;
|
||||
reg [S_COUNT-1:0] s_axi_wlast = 0;
|
||||
reg [S_COUNT*WUSER_WIDTH-1:0] s_axi_wuser = 0;
|
||||
reg [S_COUNT-1:0] s_axi_wvalid = 0;
|
||||
reg [S_COUNT-1:0] s_axi_bready = 0;
|
||||
reg [S_COUNT*ID_WIDTH-1:0] s_axi_arid = 0;
|
||||
reg [S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr = 0;
|
||||
reg [S_COUNT*8-1:0] s_axi_arlen = 0;
|
||||
reg [S_COUNT*3-1:0] s_axi_arsize = 0;
|
||||
reg [S_COUNT*2-1:0] s_axi_arburst = 0;
|
||||
reg [S_COUNT-1:0] s_axi_arlock = 0;
|
||||
reg [S_COUNT*4-1:0] s_axi_arcache = 0;
|
||||
reg [S_COUNT*3-1:0] s_axi_arprot = 0;
|
||||
reg [S_COUNT*4-1:0] s_axi_arqos = 0;
|
||||
reg [S_COUNT*4-1:0] s_axi_arregion = 0;
|
||||
reg [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser = 0;
|
||||
reg [S_COUNT-1:0] s_axi_arvalid = 0;
|
||||
reg [S_COUNT-1:0] s_axi_rready = 0;
|
||||
reg [M_COUNT-1:0] m_axi_awready = 0;
|
||||
reg [M_COUNT-1:0] m_axi_wready = 0;
|
||||
reg [M_COUNT*ID_WIDTH-1:0] m_axi_bid = 0;
|
||||
reg [M_COUNT*2-1:0] m_axi_bresp = 0;
|
||||
reg [M_COUNT*BUSER_WIDTH-1:0] m_axi_buser = 0;
|
||||
reg [M_COUNT-1:0] m_axi_bvalid = 0;
|
||||
reg [M_COUNT-1:0] m_axi_arready = 0;
|
||||
reg [M_COUNT*ID_WIDTH-1:0] m_axi_rid = 0;
|
||||
reg [M_COUNT*DATA_WIDTH-1:0] m_axi_rdata = 0;
|
||||
reg [M_COUNT*2-1:0] m_axi_rresp = 0;
|
||||
reg [M_COUNT-1:0] m_axi_rlast = 0;
|
||||
reg [M_COUNT*RUSER_WIDTH-1:0] m_axi_ruser = 0;
|
||||
reg [M_COUNT-1:0] m_axi_rvalid = 0;
|
||||
|
||||
// Outputs
|
||||
wire [S_COUNT-1:0] s_axi_awready;
|
||||
wire [S_COUNT-1:0] s_axi_wready;
|
||||
wire [S_COUNT*ID_WIDTH-1:0] s_axi_bid;
|
||||
wire [S_COUNT*2-1:0] s_axi_bresp;
|
||||
wire [S_COUNT*BUSER_WIDTH-1:0] s_axi_buser;
|
||||
wire [S_COUNT-1:0] s_axi_bvalid;
|
||||
wire [S_COUNT-1:0] s_axi_arready;
|
||||
wire [S_COUNT*ID_WIDTH-1:0] s_axi_rid;
|
||||
wire [S_COUNT*DATA_WIDTH-1:0] s_axi_rdata;
|
||||
wire [S_COUNT*2-1:0] s_axi_rresp;
|
||||
wire [S_COUNT-1:0] s_axi_rlast;
|
||||
wire [S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser;
|
||||
wire [S_COUNT-1:0] s_axi_rvalid;
|
||||
wire [M_COUNT*ID_WIDTH-1:0] m_axi_awid;
|
||||
wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_awaddr;
|
||||
wire [M_COUNT*8-1:0] m_axi_awlen;
|
||||
wire [M_COUNT*3-1:0] m_axi_awsize;
|
||||
wire [M_COUNT*2-1:0] m_axi_awburst;
|
||||
wire [M_COUNT-1:0] m_axi_awlock;
|
||||
wire [M_COUNT*4-1:0] m_axi_awcache;
|
||||
wire [M_COUNT*3-1:0] m_axi_awprot;
|
||||
wire [M_COUNT*4-1:0] m_axi_awqos;
|
||||
wire [M_COUNT*4-1:0] m_axi_awregion;
|
||||
wire [M_COUNT*AWUSER_WIDTH-1:0] m_axi_awuser;
|
||||
wire [M_COUNT-1:0] m_axi_awvalid;
|
||||
wire [M_COUNT*DATA_WIDTH-1:0] m_axi_wdata;
|
||||
wire [M_COUNT*STRB_WIDTH-1:0] m_axi_wstrb;
|
||||
wire [M_COUNT-1:0] m_axi_wlast;
|
||||
wire [M_COUNT*WUSER_WIDTH-1:0] m_axi_wuser;
|
||||
wire [M_COUNT-1:0] m_axi_wvalid;
|
||||
wire [M_COUNT-1:0] m_axi_bready;
|
||||
wire [M_COUNT*ID_WIDTH-1:0] m_axi_arid;
|
||||
wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_araddr;
|
||||
wire [M_COUNT*8-1:0] m_axi_arlen;
|
||||
wire [M_COUNT*3-1:0] m_axi_arsize;
|
||||
wire [M_COUNT*2-1:0] m_axi_arburst;
|
||||
wire [M_COUNT-1:0] m_axi_arlock;
|
||||
wire [M_COUNT*4-1:0] m_axi_arcache;
|
||||
wire [M_COUNT*3-1:0] m_axi_arprot;
|
||||
wire [M_COUNT*4-1:0] m_axi_arqos;
|
||||
wire [M_COUNT*4-1:0] m_axi_arregion;
|
||||
wire [M_COUNT*ARUSER_WIDTH-1:0] m_axi_aruser;
|
||||
wire [M_COUNT-1:0] m_axi_arvalid;
|
||||
wire [M_COUNT-1:0] m_axi_rready;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(
|
||||
clk,
|
||||
rst,
|
||||
current_test,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awregion,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arregion,
|
||||
s_axi_aruser,
|
||||
s_axi_arvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awready,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rid,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_ruser,
|
||||
m_axi_rvalid
|
||||
);
|
||||
$to_myhdl(
|
||||
s_axi_awready,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_ruser,
|
||||
s_axi_rvalid,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awregion,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_bready,
|
||||
m_axi_arid,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arsize,
|
||||
m_axi_arburst,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arqos,
|
||||
m_axi_arregion,
|
||||
m_axi_aruser,
|
||||
m_axi_arvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_axi_interconnect_4x4.lxt");
|
||||
$dumpvars(0, test_axi_interconnect_4x4);
|
||||
end
|
||||
|
||||
axi_interconnect #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ADDR_WIDTH(ADDR_WIDTH),
|
||||
.STRB_WIDTH(STRB_WIDTH),
|
||||
.ID_WIDTH(ID_WIDTH),
|
||||
.AWUSER_ENABLE(AWUSER_ENABLE),
|
||||
.AWUSER_WIDTH(AWUSER_WIDTH),
|
||||
.WUSER_ENABLE(WUSER_ENABLE),
|
||||
.WUSER_WIDTH(WUSER_WIDTH),
|
||||
.BUSER_ENABLE(BUSER_ENABLE),
|
||||
.BUSER_WIDTH(BUSER_WIDTH),
|
||||
.ARUSER_ENABLE(ARUSER_ENABLE),
|
||||
.ARUSER_WIDTH(ARUSER_WIDTH),
|
||||
.RUSER_ENABLE(RUSER_ENABLE),
|
||||
.RUSER_WIDTH(RUSER_WIDTH),
|
||||
.FORWARD_ID(FORWARD_ID),
|
||||
.S_COUNT(S_COUNT),
|
||||
.M_COUNT(M_COUNT),
|
||||
.M_BASE_ADDR(M_BASE_ADDR),
|
||||
.M_ADDR_WIDTH(M_ADDR_WIDTH),
|
||||
.M_CONNECT_READ(M_CONNECT_READ),
|
||||
.M_CONNECT_WRITE(M_CONNECT_WRITE)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awregion(s_axi_awregion),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_arregion(s_axi_arregion),
|
||||
.s_axi_aruser(s_axi_aruser),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(s_axi_ruser),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awregion(m_axi_awregion),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(m_axi_arid),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arsize(m_axi_arsize),
|
||||
.m_axi_arburst(m_axi_arburst),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_arregion(m_axi_arregion),
|
||||
.m_axi_aruser(m_axi_aruser),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(m_axi_rid),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_ruser(m_axi_ruser),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
|
||||
endmodule
|
||||
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Reference in New Issue
Block a user