diff --git a/example/common/tb/example_core_pcie/test_example_core_pcie.py b/example/common/tb/example_core_pcie/test_example_core_pcie.py
index 2c5256c05..e3f7fcaf0 100644
--- a/example/common/tb/example_core_pcie/test_example_core_pcie.py
+++ b/example/common/tb/example_core_pcie/test_example_core_pcie.py
@@ -35,7 +35,6 @@ from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Timer
 
 from cocotbext.pcie.core import RootComplex
-from cocotbext.axi.utils import hexdump_str
 
 try:
     from pcie_if import PcieIfDevice, PcieIfRxBus, PcieIfTxBus
@@ -76,9 +75,9 @@ class TB(object):
             rd_req_tx_seq_num=dut.s_axis_rd_req_tx_seq_num,
             rd_req_tx_seq_num_valid=dut.s_axis_rd_req_tx_seq_num_valid,
 
-            cfg_max_payload=dut.max_payload_size,
             rx_cpl_tlp_bus=PcieIfRxBus.from_prefix(dut, "rx_cpl_tlp"),
 
+            cfg_max_payload=dut.max_payload_size,
             cfg_max_read_req=dut.max_read_request_size,
             cfg_ext_tag_enable=dut.ext_tag_enable,
 
@@ -93,8 +92,8 @@ class TB(object):
 
         self.dev.functions[0].msi_multiple_message_capable = 5
 
-        self.dev.functions[0].configure_bar(0, 2**24)
-        self.dev.functions[0].configure_bar(2, 2**24)
+        self.dev.functions[0].configure_bar(0, 2**len(dut.axil_ctrl_awaddr))
+        self.dev.functions[0].configure_bar(2, 2**len(dut.axi_ram_awaddr))
 
         dut.bus_num.setimmediatevalue(0)
 
diff --git a/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py b/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py
index 76212fb9e..9680b297e 100644
--- a/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py
+++ b/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py
@@ -34,7 +34,6 @@ from cocotb.triggers import RisingEdge, FallingEdge, Timer
 
 from cocotbext.pcie.core import RootComplex
 from cocotbext.pcie.intel.s10 import S10PcieDevice, S10RxBus, S10TxBus
-from cocotbext.axi.utils import hexdump_str
 
 
 class TB(object):
@@ -159,8 +158,8 @@ class TB(object):
 
         self.dev.functions[0].msi_multiple_message_capable = 5
 
-        self.dev.functions[0].configure_bar(0, 2**24)
-        self.dev.functions[0].configure_bar(2, 2**24)
+        self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_awaddr))
+        self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axi_ram_awaddr))
 
     async def init(self):
 
diff --git a/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py b/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py
index 4ba7dd0ce..f1d4c8e08 100644
--- a/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py
+++ b/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py
@@ -35,7 +35,6 @@ from cocotb.triggers import RisingEdge, FallingEdge, Timer
 from cocotbext.axi import AxiStreamBus
 from cocotbext.pcie.core import RootComplex
 from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
-from cocotbext.axi.utils import hexdump_str
 
 
 class TB(object):
@@ -235,8 +234,8 @@ class TB(object):
 
         self.dev.functions[0].msi_multiple_message_capable = 5
 
-        self.dev.functions[0].configure_bar(0, 2**24)
-        self.dev.functions[0].configure_bar(2, 2**24)
+        self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_awaddr))
+        self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axi_ram_awaddr))
 
         # monitor error outputs
         self.status_error_cor_asserted = False