FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

Testbench cleanup

Browse Source
This commit is contained in:
Alex Forencich 2021-11-18 13:45:55 -08:00
parent 419ee057c8
commit a330c6e7f0
3 changed files with 7 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
example/common/tb/example_core_pcie/test_example_core_pcie.py
View File

@ -35,7 +35,6 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotbext.pcie.core import RootComplex
from cocotbext.axi.utils import hexdump_str
try:
from pcie_if import PcieIfDevice, PcieIfRxBus, PcieIfTxBus
@ -76,9 +75,9 @@ class TB(object):
rd_req_tx_seq_num=dut.s_axis_rd_req_tx_seq_num,
rd_req_tx_seq_num_valid=dut.s_axis_rd_req_tx_seq_num_valid,
cfg_max_payload=dut.max_payload_size,
rx_cpl_tlp_bus=PcieIfRxBus.from_prefix(dut, "rx_cpl_tlp"),
cfg_max_payload=dut.max_payload_size,
cfg_max_read_req=dut.max_read_request_size,
cfg_ext_tag_enable=dut.ext_tag_enable,
@ -93,8 +92,8 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**24)
self.dev.functions[0].configure_bar(2, 2**24)
self.dev.functions[0].configure_bar(0, 2**len(dut.axil_ctrl_awaddr))
self.dev.functions[0].configure_bar(2, 2**len(dut.axi_ram_awaddr))
dut.bus_num.setimmediatevalue(0)

5
example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py
View File

@ -34,7 +34,6 @@ from cocotb.triggers import RisingEdge, FallingEdge, Timer
from cocotbext.pcie.core import RootComplex
from cocotbext.pcie.intel.s10 import S10PcieDevice, S10RxBus, S10TxBus
from cocotbext.axi.utils import hexdump_str
class TB(object):
@ -159,8 +158,8 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**24)
self.dev.functions[0].configure_bar(2, 2**24)
self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_awaddr))
self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axi_ram_awaddr))
async def init(self):

5
example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py
View File

@ -35,7 +35,6 @@ from cocotb.triggers import RisingEdge, FallingEdge, Timer
from cocotbext.axi import AxiStreamBus
from cocotbext.pcie.core import RootComplex
from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
from cocotbext.axi.utils import hexdump_str
class TB(object):
@ -235,8 +234,8 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**24)
self.dev.functions[0].configure_bar(2, 2**24)
self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_awaddr))
self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axi_ram_awaddr))
# monitor error outputs
self.status_error_cor_asserted = False