FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

Memory writes don't get assigned tags

Browse Source
This commit is contained in:
Alex Forencich 2018-10-14 20:30:44 -07:00
parent 0e601554cb
commit a4e2a65902
1 changed files with 0 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
tb/pcie.py
View File

@ -1999,7 +1999,6 @@ class Function(PMCapability, PCIECapability):
else:
tlp.fmt_type = TLP_MEM_WRITE
tlp.requester_id = self.get_id()
tlp.tag = self.current_tag
first_pad = addr % 4
byte_length = len(data)-n
@ -2007,8 +2006,6 @@ class Function(PMCapability, PCIECapability):
byte_length = min(byte_length, 0x1000 - (addr & 0xfff)) # 4k align
tlp.set_be_data(addr, data[n:n+byte_length])
self.current_tag = (self.current_tag % 31) + 1
yield self.send(tlp)
n += byte_length
@ -3622,7 +3619,6 @@ class RootComplex(Switch):
else:
tlp.fmt_type = TLP_MEM_WRITE
tlp.requester_id = PcieId(0, 0, 0)
tlp.tag = self.current_tag
first_pad = addr % 4
byte_length = len(data)-n
@ -3630,8 +3626,6 @@ class RootComplex(Switch):
byte_length = min(byte_length, 0x1000 - (addr & 0xfff)) # 4k align
tlp.set_be_data(addr, data[n:n+byte_length])
self.current_tag = (self.current_tag % 31) + 1
yield self.send(tlp)
n += byte_length