FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

Update testbenches for new version of cocotbext-pcie

Browse Source
This commit is contained in:
Alex Forencich 2022-06-05 00:24:42 -07:00
parent 21b0f014a5
commit a5d7833bd9
30 changed files with 105 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -82,8 +82,10 @@ class TB(object):
# pcie_link_width=16, # pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -82,8 +82,10 @@ class TB(object):
# pcie_link_width=16, # pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -82,8 +82,10 @@ class TB(object):
# pcie_link_width=16, # pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -82,8 +82,10 @@ class TB(object):
# pcie_link_width=16, # pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

2
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -81,7 +81,7 @@ class TB(object):
pcie_link_width=8, pcie_link_width=8,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
straddle=False, rc_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,

2
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -81,7 +81,7 @@ class TB(object):
pcie_link_width=8, pcie_link_width=8,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
straddle=False, rc_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,

2
fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -81,7 +81,7 @@ class TB(object):
pcie_link_width=8, pcie_link_width=8,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
straddle=False, rc_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,

6
fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=8, pcie_link_width=8,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=8, pcie_link_width=8,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

2
fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -81,7 +81,7 @@ class TB(object):
pcie_link_width=8, pcie_link_width=8,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
straddle=False, rc_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,

6
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=4, pcie_link_width=4,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

6
fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -81,8 +81,10 @@ class TB(object):
pcie_link_width=16, pcie_link_width=16,
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
cq_cc_straddle=False, cq_straddle=False,
rq_rc_straddle=False, cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
pf_count=1, pf_count=1,
max_payload_size=1024, max_payload_size=1024,

2
tox.ini
View File

@ -18,7 +18,7 @@ deps =
cocotb-test == 0.2.1 cocotb-test == 0.2.1
cocotbext-axi == 0.1.18 cocotbext-axi == 0.1.18
cocotbext-eth == 0.1.18 cocotbext-eth == 0.1.18
cocotbext-pcie == 0.2.0 cocotbext-pcie == 0.2.2
scapy == 2.4.5 scapy == 2.4.5
commands = commands =