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Add support for writing immediate data to DMA IF modules

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This commit is contained in:
Alex Forencich 2022-04-04 12:40:42 -07:00
parent 34fe24287d
commit a5dcb3d27c
12 changed files with 339 additions and 14 deletions
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10
rtl/dma_if_axi.v
View File

@ -55,6 +55,10 @@ module dma_if_axi #
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8,
// RAM segment address width
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
// Immediate enable
parameter IMM_ENABLE = 0,
// Immediate width
parameter IMM_WIDTH = 32,
// Length field width
parameter LEN_WIDTH = 16,
// Tag field width
@ -135,6 +139,8 @@ module dma_if_axi #
input wire [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr,
input wire [RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel,
input wire [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr,
input wire [IMM_WIDTH-1:0] s_axis_write_desc_imm,
input wire s_axis_write_desc_imm_en,
input wire [LEN_WIDTH-1:0] s_axis_write_desc_len,
input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag,
input wire s_axis_write_desc_valid,
@ -310,6 +316,8 @@ dma_if_axi_wr #(
.RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
.RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.IMM_ENABLE(IMM_ENABLE),
.IMM_WIDTH(IMM_WIDTH),
.LEN_WIDTH(LEN_WIDTH),
.TAG_WIDTH(TAG_WIDTH),
.OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
@ -348,6 +356,8 @@ dma_if_axi_wr_inst (
.s_axis_write_desc_axi_addr(s_axis_write_desc_axi_addr),
.s_axis_write_desc_ram_sel(s_axis_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(s_axis_write_desc_ram_addr),
.s_axis_write_desc_imm(s_axis_write_desc_imm),
.s_axis_write_desc_imm_en(s_axis_write_desc_imm_en),
.s_axis_write_desc_len(s_axis_write_desc_len),
.s_axis_write_desc_tag(s_axis_write_desc_tag),
.s_axis_write_desc_valid(s_axis_write_desc_valid),

72
rtl/dma_if_axi_wr.v
View File

@ -55,6 +55,10 @@ module dma_if_axi_wr #
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8,
// RAM segment address width
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
// Immediate enable
parameter IMM_ENABLE = 0,
// Immediate width
parameter IMM_WIDTH = 32,
// Length field width
parameter LEN_WIDTH = 16,
// Tag field width
@ -97,6 +101,8 @@ module dma_if_axi_wr #
input wire [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr,
input wire [RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel,
input wire [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr,
input wire [IMM_WIDTH-1:0] s_axis_write_desc_imm,
input wire s_axis_write_desc_imm_en,
input wire [LEN_WIDTH-1:0] s_axis_write_desc_len,
input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag,
input wire s_axis_write_desc_valid,
@ -211,6 +217,11 @@ initial begin
$error("Error: AXI_ID_WIDTH insufficient for requested OP_TABLE_SIZE (instance %m)");
$finish;
end
if (IMM_ENABLE && IMM_WIDTH > AXI_DATA_WIDTH) begin
$error("Error: IMM_WIDTH must not be larger than the AXI interface width (instance %m)");
$finish;
end
end
localparam [1:0]
@ -258,6 +269,8 @@ reg read_cmd_ready;
reg [AXI_ADDR_WIDTH-1:0] req_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, req_axi_addr_next;
reg [RAM_SEL_WIDTH-1:0] ram_sel_reg = {RAM_SEL_WIDTH{1'b0}}, ram_sel_next;
reg [RAM_ADDR_WIDTH-1:0] ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, ram_addr_next;
reg [IMM_WIDTH-1:0] imm_reg = {IMM_WIDTH{1'b0}}, imm_next;
reg imm_en_reg = 1'b0, imm_en_next;
reg [LEN_WIDTH-1:0] op_count_reg = {LEN_WIDTH{1'b0}}, op_count_next;
reg zero_len_reg = 1'b0, zero_len_next;
reg [LEN_WIDTH-1:0] tr_count_reg = {LEN_WIDTH{1'b0}}, tr_count_next;
@ -267,6 +280,7 @@ reg [TAG_WIDTH-1:0] tag_reg = {TAG_WIDTH{1'b0}}, tag_next;
reg [AXI_ADDR_WIDTH-1:0] read_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, read_axi_addr_next;
reg [RAM_SEL_WIDTH-1:0] read_ram_sel_reg = {RAM_SEL_WIDTH{1'b0}}, read_ram_sel_next;
reg [RAM_ADDR_WIDTH-1:0] read_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, read_ram_addr_next;
reg read_imm_en_reg = 1'b0, read_imm_en_next;
reg [LEN_WIDTH-1:0] read_len_reg = {LEN_WIDTH{1'b0}}, read_len_next;
reg [RAM_SEG_COUNT-1:0] read_ram_mask_reg = {RAM_SEG_COUNT{1'b0}}, read_ram_mask_next;
reg [RAM_SEG_COUNT-1:0] read_ram_mask_0_reg = {RAM_SEG_COUNT{1'b0}}, read_ram_mask_0_next;
@ -279,6 +293,8 @@ reg [RAM_OFFSET_WIDTH-1:0] start_offset_reg = {RAM_OFFSET_WIDTH{1'b0}}, start_of
reg [RAM_OFFSET_WIDTH-1:0] end_offset_reg = {RAM_OFFSET_WIDTH{1'b0}}, end_offset_next;
reg [AXI_ADDR_WIDTH-1:0] axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, axi_addr_next;
reg [IMM_WIDTH-1:0] axi_imm_reg = {IMM_WIDTH{1'b0}}, axi_imm_next;
reg axi_imm_en_reg = 1'b0, axi_imm_en_next;
reg [12:0] axi_len_reg = 13'd0, axi_len_next;
reg axi_zero_len_reg = 1'b0, axi_zero_len_next;
reg [RAM_OFFSET_WIDTH-1:0] offset_reg = {RAM_OFFSET_WIDTH{1'b0}}, offset_next;
@ -292,6 +308,7 @@ reg last_cycle_reg = 1'b0, last_cycle_next;
reg [AXI_ADDR_WIDTH-1:0] read_cmd_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, read_cmd_axi_addr_next;
reg [RAM_SEL_WIDTH-1:0] read_cmd_ram_sel_reg = {RAM_SEL_WIDTH{1'b0}}, read_cmd_ram_sel_next;
reg [RAM_ADDR_WIDTH-1:0] read_cmd_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, read_cmd_ram_addr_next;
reg read_cmd_imm_en_reg = 1'b0, read_cmd_imm_en_next;
reg [12:0] read_cmd_len_reg = 13'd0, read_cmd_len_next;
reg [CYCLE_COUNT_WIDTH-1:0] read_cmd_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, read_cmd_cycle_count_next;
reg read_cmd_last_cycle_reg = 1'b0, read_cmd_last_cycle_next;
@ -385,6 +402,8 @@ assign stat_wr_tx_stall = stat_wr_tx_stall_reg;
// operation tag management
reg [OP_TAG_WIDTH+1-1:0] op_table_start_ptr_reg = 0;
reg [AXI_ADDR_WIDTH-1:0] op_table_start_axi_addr;
reg [IMM_WIDTH-1:0] op_table_start_imm;
reg op_table_start_imm_en;
reg [11:0] op_table_start_len;
reg op_table_start_zero_len;
reg [CYCLE_COUNT_WIDTH-1:0] op_table_start_cycle_count;
@ -407,6 +426,10 @@ reg [2**OP_TAG_WIDTH-1:0] op_table_write_complete = 0;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [AXI_ADDR_WIDTH-1:0] op_table_axi_addr[2**OP_TAG_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [IMM_WIDTH-1:0] op_table_imm[2**OP_TAG_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg op_table_imm_en[2**OP_TAG_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [11:0] op_table_len[2**OP_TAG_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg op_table_zero_len[2**OP_TAG_WIDTH-1:0];
@ -426,6 +449,8 @@ integer i;
initial begin
for (i = 0; i < 2**OP_TAG_WIDTH; i = i + 1) begin
op_table_axi_addr[i] = 0;
op_table_imm[i] = 0;
op_table_imm_en[i] = 0;
op_table_len[i] = 0;
op_table_zero_len[i] = 1'b0;
op_table_cycle_count[i] = 0;
@ -454,6 +479,8 @@ always @* begin
req_axi_addr_next = req_axi_addr_reg;
ram_sel_next = ram_sel_reg;
ram_addr_next = ram_addr_reg;
imm_next = imm_reg;
imm_en_next = imm_en_reg;
op_count_next = op_count_reg;
zero_len_next = zero_len_reg;
tr_count_next = tr_count_reg;
@ -462,12 +489,15 @@ always @* begin
read_cmd_axi_addr_next = read_cmd_axi_addr_reg;
read_cmd_ram_sel_next = read_cmd_ram_sel_reg;
read_cmd_ram_addr_next = read_cmd_ram_addr_reg;
read_cmd_imm_en_next = read_cmd_imm_en_reg;
read_cmd_len_next = read_cmd_len_reg;
read_cmd_cycle_count_next = read_cmd_cycle_count_reg;
read_cmd_last_cycle_next = read_cmd_last_cycle_reg;
read_cmd_valid_next = read_cmd_valid_reg && !read_cmd_ready;
op_table_start_axi_addr = req_axi_addr_reg;
op_table_start_imm = imm_reg;
op_table_start_imm_en = imm_en_reg;
op_table_start_len = 0;
op_table_start_zero_len = zero_len_reg;
op_table_start_cycle_count = 0;
@ -483,8 +513,15 @@ always @* begin
s_axis_write_desc_ready_next = !op_table_active[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] && ($unsigned(op_table_start_ptr_reg - op_table_finish_ptr_reg) < 2**OP_TAG_WIDTH) && enable;
req_axi_addr_next = s_axis_write_desc_axi_addr;
ram_sel_next = s_axis_write_desc_ram_sel;
ram_addr_next = s_axis_write_desc_ram_addr;
if (IMM_ENABLE && s_axis_write_desc_imm_en) begin
ram_sel_next = 0;
ram_addr_next = 0;
end else begin
ram_sel_next = s_axis_write_desc_ram_sel;
ram_addr_next = s_axis_write_desc_ram_addr;
end
imm_next = s_axis_write_desc_imm;
imm_en_next = IMM_ENABLE && s_axis_write_desc_imm_en;
if (s_axis_write_desc_len == 0) begin
// zero-length operation
op_count_next = 1;
@ -533,6 +570,7 @@ always @* begin
read_cmd_axi_addr_next = req_axi_addr_reg;
read_cmd_ram_sel_next = ram_sel_reg;
read_cmd_ram_addr_next = ram_addr_reg;
read_cmd_imm_en_next = imm_en_reg;
read_cmd_len_next = tr_word_count_next;
read_cmd_cycle_count_next = (tr_word_count_next + (req_axi_addr_reg & OFFSET_MASK) - 1) >> AXI_BURST_SIZE;
op_table_start_cycle_count = read_cmd_cycle_count_next;
@ -544,6 +582,8 @@ always @* begin
op_count_next = op_count_reg - tr_word_count_next;
op_table_start_axi_addr = req_axi_addr_reg;
op_table_start_imm = imm_reg;
op_table_start_imm_en = imm_en_reg;
op_table_start_len = tr_word_count_next;
op_table_start_zero_len = zero_len_reg;
op_table_start_offset = (req_axi_addr_reg & OFFSET_MASK)-ram_addr_reg[RAM_OFFSET_WIDTH-1:0];
@ -600,6 +640,7 @@ always @* begin
read_axi_addr_next = read_axi_addr_reg;
read_ram_sel_next = read_ram_sel_reg;
read_ram_addr_next = read_ram_addr_reg;
read_imm_en_next = read_imm_en_reg;
read_len_next = read_len_reg;
read_ram_mask_next = read_ram_mask_reg;
read_ram_mask_0_next = read_ram_mask_0_reg;
@ -622,6 +663,7 @@ always @* begin
read_axi_addr_next = read_cmd_axi_addr_reg;
read_ram_sel_next = read_cmd_ram_sel_reg;
read_ram_addr_next = read_cmd_ram_addr_reg;
read_imm_en_next = read_cmd_imm_en_reg;
read_len_next = read_cmd_len_reg;
read_cycle_count_next = read_cmd_cycle_count_reg;
read_last_cycle_next = read_cmd_last_cycle_reg;
@ -667,14 +709,14 @@ always @* begin
if (read_ram_mask_reg[i]) begin
ram_rd_cmd_sel_next[i*RAM_SEL_WIDTH +: RAM_SEL_WIDTH] = read_ram_sel_reg;
ram_rd_cmd_addr_next[i*RAM_SEG_ADDR_WIDTH +: RAM_SEG_ADDR_WIDTH] = read_ram_addr_reg[RAM_ADDR_WIDTH-1:RAM_ADDR_WIDTH-RAM_SEG_ADDR_WIDTH];
ram_rd_cmd_valid_next[i] = 1'b1;
ram_rd_cmd_valid_next[i] = !(IMM_ENABLE && read_imm_en_reg);
end
if (read_ram_mask_1_reg[i]) begin
ram_rd_cmd_addr_next[i*RAM_SEG_ADDR_WIDTH +: RAM_SEG_ADDR_WIDTH] = read_ram_addr_reg[RAM_ADDR_WIDTH-1:RAM_ADDR_WIDTH-RAM_SEG_ADDR_WIDTH]+1;
end
end
mask_fifo_wr_mask = read_ram_mask_reg;
mask_fifo_wr_mask = (IMM_ENABLE && read_imm_en_reg) ? 0 : read_ram_mask_reg;
mask_fifo_we = 1'b1;
if (read_len_next > AXI_STRB_WIDTH) begin
@ -703,6 +745,7 @@ always @* begin
read_axi_addr_next = read_cmd_axi_addr_reg;
read_ram_sel_next = read_cmd_ram_sel_reg;
read_ram_addr_next = read_cmd_ram_addr_reg;
read_imm_en_next = read_cmd_imm_en_reg;
read_len_next = read_cmd_len_reg;
read_cycle_count_next = read_cmd_cycle_count_reg;
read_last_cycle_next = read_cmd_last_cycle_reg;
@ -752,6 +795,8 @@ always @* begin
stat_wr_req_finish_valid_next = 1'b0;
axi_addr_next = axi_addr_reg;
axi_imm_next = axi_imm_reg;
axi_imm_en_next = axi_imm_en_reg;
axi_len_next = axi_len_reg;
axi_zero_len_next = axi_zero_len_reg;
offset_next = offset_reg;
@ -773,8 +818,8 @@ always @* begin
m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_awready;
m_axi_bready_next = 1'b0;
m_axi_wdata_int = 0;
m_axi_wstrb_int = 0;
m_axi_wdata_int = ((IMM_ENABLE && axi_imm_en_reg) ? {2{{RAM_DATA_WIDTH{1'b0}} | axi_imm_reg}} : {2{ram_rd_resp_data}}) >> (RAM_DATA_WIDTH-offset_reg*AXI_WORD_SIZE);
m_axi_wstrb_int = strb_offset_mask_reg;
m_axi_wlast_int = 1'b0;
m_axi_wvalid_int = 1'b0;
@ -785,6 +830,8 @@ always @* begin
ram_rd_resp_ready_cmb = {RAM_SEG_COUNT{1'b0}};
axi_addr_next = op_table_axi_addr[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
axi_imm_next = op_table_imm[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
axi_imm_en_next = op_table_imm_en[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
axi_len_next = op_table_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
axi_zero_len_next = op_table_zero_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
offset_next = op_table_offset[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
@ -819,8 +866,9 @@ always @* begin
offset_next = offset_reg + AXI_STRB_WIDTH;
strb_offset_mask_next = {AXI_STRB_WIDTH{1'b1}};
m_axi_wdata_int = {2{ram_rd_resp_data}} >> (RAM_DATA_WIDTH-offset_reg*AXI_WORD_SIZE);
m_axi_wdata_int = ((IMM_ENABLE && axi_imm_en_reg) ? {2{{RAM_DATA_WIDTH{1'b0}} | axi_imm_reg}} : {2{ram_rd_resp_data}}) >> (RAM_DATA_WIDTH-offset_reg*AXI_WORD_SIZE);
m_axi_wstrb_int = strb_offset_mask_reg;
m_axi_wlast_int = 1'b0;
m_axi_wvalid_int = 1'b1;
if (last_cycle_reg) begin
@ -834,6 +882,8 @@ always @* begin
// skip idle state if possible
axi_addr_next = op_table_axi_addr[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
axi_imm_next = op_table_imm[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
axi_imm_en_next = op_table_imm_en[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
axi_len_next = op_table_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
axi_zero_len_next = op_table_zero_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
offset_next = op_table_offset[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
@ -959,6 +1009,8 @@ always @(posedge clk) begin
req_axi_addr_reg <= req_axi_addr_next;
ram_sel_reg <= ram_sel_next;
ram_addr_reg <= ram_addr_next;
imm_reg <= imm_next;
imm_en_reg <= imm_en_next;
op_count_reg <= op_count_next;
zero_len_reg <= zero_len_next;
tr_count_reg <= tr_count_next;
@ -968,6 +1020,7 @@ always @(posedge clk) begin
read_axi_addr_reg <= read_axi_addr_next;
read_ram_sel_reg <= read_ram_sel_next;
read_ram_addr_reg <= read_ram_addr_next;
read_imm_en_reg <= read_imm_en_next;
read_len_reg <= read_len_next;
read_ram_mask_reg <= read_ram_mask_next;
read_ram_mask_0_reg <= read_ram_mask_0_next;
@ -980,6 +1033,8 @@ always @(posedge clk) begin
end_offset_reg <= end_offset_next;
axi_addr_reg <= axi_addr_next;
axi_imm_reg <= axi_imm_next;
axi_imm_en_reg <= axi_imm_en_next;
axi_len_reg <= axi_len_next;
axi_zero_len_reg <= axi_zero_len_next;
offset_reg <= offset_next;
@ -993,6 +1048,7 @@ always @(posedge clk) begin
read_cmd_axi_addr_reg <= read_cmd_axi_addr_next;
read_cmd_ram_sel_reg <= read_cmd_ram_sel_next;
read_cmd_ram_addr_reg <= read_cmd_ram_addr_next;
read_cmd_imm_en_reg <= read_cmd_imm_en_next;
read_cmd_len_reg <= read_cmd_len_next;
read_cmd_cycle_count_reg <= read_cmd_cycle_count_next;
read_cmd_last_cycle_reg <= read_cmd_last_cycle_next;
@ -1040,6 +1096,8 @@ always @(posedge clk) begin
op_table_active[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= 1'b1;
op_table_write_complete[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= 1'b0;
op_table_axi_addr[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= op_table_start_axi_addr;
op_table_imm[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= op_table_start_imm;
op_table_imm_en[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= op_table_start_imm_en;
op_table_len[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= op_table_start_len;
op_table_zero_len[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= op_table_start_zero_len;
op_table_cycle_count[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= op_table_start_cycle_count;

26
rtl/dma_if_desc_mux.v
View File

@ -46,6 +46,10 @@ module dma_if_desc_mux #
parameter RAM_ADDR_WIDTH = 16,
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// Immediate enable
parameter IMM_ENABLE = 0,
// Immediate width
parameter IMM_WIDTH = 32,
// Length field width
parameter LEN_WIDTH = 16,
// Input tag field width
@ -68,6 +72,8 @@ module dma_if_desc_mux #
output wire [DMA_ADDR_WIDTH-1:0] m_axis_desc_dma_addr,
output wire [M_RAM_SEL_WIDTH-1:0] m_axis_desc_ram_sel,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_desc_ram_addr,
output wire [IMM_WIDTH-1:0] m_axis_desc_imm,
output wire m_axis_desc_imm_en,
output wire [LEN_WIDTH-1:0] m_axis_desc_len,
output wire [M_TAG_WIDTH-1:0] m_axis_desc_tag,
output wire m_axis_desc_valid,
@ -86,6 +92,8 @@ module dma_if_desc_mux #
input wire [PORTS*DMA_ADDR_WIDTH-1:0] s_axis_desc_dma_addr,
input wire [PORTS*S_RAM_SEL_WIDTH-1:0] s_axis_desc_ram_sel,
input wire [PORTS*RAM_ADDR_WIDTH-1:0] s_axis_desc_ram_addr,
input wire [PORTS*IMM_WIDTH-1:0] s_axis_desc_imm,
input wire [PORTS-1:0] s_axis_desc_imm_en,
input wire [PORTS*LEN_WIDTH-1:0] s_axis_desc_len,
input wire [PORTS*S_TAG_WIDTH-1:0] s_axis_desc_tag,
input wire [PORTS-1:0] s_axis_desc_valid,
@ -136,6 +144,8 @@ wire [CL_PORTS-1:0] grant_encoded;
reg [DMA_ADDR_WIDTH-1:0] m_axis_desc_dma_addr_int;
reg [M_RAM_SEL_WIDTH-1:0] m_axis_desc_ram_sel_int;
reg [RAM_ADDR_WIDTH-1:0] m_axis_desc_ram_addr_int;
reg [IMM_WIDTH-1:0] m_axis_desc_imm_int;
reg m_axis_desc_imm_en_int;
reg [LEN_WIDTH-1:0] m_axis_desc_len_int;
reg [M_TAG_WIDTH-1:0] m_axis_desc_tag_int;
reg m_axis_desc_valid_int;
@ -148,6 +158,8 @@ assign s_axis_desc_ready = (m_axis_desc_ready_int_reg && grant_valid) << grant_e
wire [DMA_ADDR_WIDTH-1:0] current_s_desc_dma_addr = s_axis_desc_dma_addr[grant_encoded*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH];
wire [S_RAM_SEL_WIDTH-1:0] current_s_desc_ram_sel = s_axis_desc_ram_sel[grant_encoded*S_RAM_SEL_WIDTH +: S_RAM_SEL_WIDTH_INT];
wire [RAM_ADDR_WIDTH-1:0] current_s_desc_ram_addr = s_axis_desc_ram_addr[grant_encoded*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH];
wire [IMM_WIDTH-1:0] current_s_desc_imm = s_axis_desc_imm[grant_encoded*IMM_WIDTH +: IMM_WIDTH];
wire current_s_desc_imm_en = s_axis_desc_imm_en[grant_encoded];
wire [LEN_WIDTH-1:0] current_s_desc_len = s_axis_desc_len[grant_encoded*LEN_WIDTH +: LEN_WIDTH];
wire [S_TAG_WIDTH-1:0] current_s_desc_tag = s_axis_desc_tag[grant_encoded*S_TAG_WIDTH +: S_TAG_WIDTH];
wire current_s_desc_valid = s_axis_desc_valid[grant_encoded];
@ -182,6 +194,8 @@ always @* begin
m_axis_desc_ram_sel_int[M_RAM_SEL_WIDTH-1:M_RAM_SEL_WIDTH-CL_PORTS] = grant_encoded;
end
m_axis_desc_ram_addr_int = current_s_desc_ram_addr;
m_axis_desc_imm_int = current_s_desc_imm;
m_axis_desc_imm_en_int = current_s_desc_imm_en;
m_axis_desc_len_int = current_s_desc_len;
m_axis_desc_tag_int = {grant_encoded, current_s_desc_tag};
m_axis_desc_valid_int = current_s_desc_valid && m_axis_desc_ready_int_reg && grant_valid;
@ -191,6 +205,8 @@ end
reg [DMA_ADDR_WIDTH-1:0] m_axis_desc_dma_addr_reg = {DMA_ADDR_WIDTH{1'b0}};
reg [M_RAM_SEL_WIDTH-1:0] m_axis_desc_ram_sel_reg = {M_RAM_SEL_WIDTH{1'b0}};
reg [RAM_ADDR_WIDTH-1:0] m_axis_desc_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}};
reg [IMM_WIDTH-1:0] m_axis_desc_imm_reg = {IMM_WIDTH{1'b0}};
reg m_axis_desc_imm_en_reg = 1'b0;
reg [LEN_WIDTH-1:0] m_axis_desc_len_reg = {LEN_WIDTH{1'b0}};
reg [M_TAG_WIDTH-1:0] m_axis_desc_tag_reg = {M_TAG_WIDTH{1'b0}};
reg m_axis_desc_valid_reg = 1'b0, m_axis_desc_valid_next;
@ -198,6 +214,8 @@ reg m_axis_desc_valid_reg = 1'b0, m_axis_desc_valid_ne
reg [DMA_ADDR_WIDTH-1:0] temp_m_axis_desc_dma_addr_reg = {DMA_ADDR_WIDTH{1'b0}};
reg [M_RAM_SEL_WIDTH-1:0] temp_m_axis_desc_ram_sel_reg = {M_RAM_SEL_WIDTH{1'b0}};
reg [RAM_ADDR_WIDTH-1:0] temp_m_axis_desc_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}};
reg [IMM_WIDTH-1:0] temp_m_axis_desc_imm_reg = {IMM_WIDTH{1'b0}};
reg temp_m_axis_desc_imm_en_reg = 1'b0;
reg [LEN_WIDTH-1:0] temp_m_axis_desc_len_reg = {LEN_WIDTH{1'b0}};
reg [M_TAG_WIDTH-1:0] temp_m_axis_desc_tag_reg = {M_TAG_WIDTH{1'b0}};
reg temp_m_axis_desc_valid_reg = 1'b0, temp_m_axis_desc_valid_next;
@ -210,6 +228,8 @@ reg store_axis_temp_to_output;
assign m_axis_desc_dma_addr = m_axis_desc_dma_addr_reg;
assign m_axis_desc_ram_sel = m_axis_desc_ram_sel_reg;
assign m_axis_desc_ram_addr = m_axis_desc_ram_addr_reg;
assign m_axis_desc_imm = IMM_ENABLE ? m_axis_desc_imm_reg : {IMM_WIDTH{1'b0}};
assign m_axis_desc_imm_en = IMM_ENABLE ? m_axis_desc_imm_en_reg : 1'b0;
assign m_axis_desc_len = m_axis_desc_len_reg;
assign m_axis_desc_tag = m_axis_desc_tag_reg;
assign m_axis_desc_valid = m_axis_desc_valid_reg;
@ -261,12 +281,16 @@ always @(posedge clk) begin
m_axis_desc_dma_addr_reg <= m_axis_desc_dma_addr_int;
m_axis_desc_ram_sel_reg <= m_axis_desc_ram_sel_int;
m_axis_desc_ram_addr_reg <= m_axis_desc_ram_addr_int;
m_axis_desc_imm_reg <= m_axis_desc_imm_int;
m_axis_desc_imm_en_reg <= m_axis_desc_imm_en_int;
m_axis_desc_len_reg <= m_axis_desc_len_int;
m_axis_desc_tag_reg <= m_axis_desc_tag_int;
end else if (store_axis_temp_to_output) begin
m_axis_desc_dma_addr_reg <= temp_m_axis_desc_dma_addr_reg;
m_axis_desc_ram_sel_reg <= temp_m_axis_desc_ram_sel_reg;
m_axis_desc_ram_addr_reg <= temp_m_axis_desc_ram_addr_reg;
m_axis_desc_imm_reg <= temp_m_axis_desc_imm_reg;
m_axis_desc_imm_en_reg <= temp_m_axis_desc_imm_en_reg;
m_axis_desc_len_reg <= temp_m_axis_desc_len_reg;
m_axis_desc_tag_reg <= temp_m_axis_desc_tag_reg;
end
@ -275,6 +299,8 @@ always @(posedge clk) begin
temp_m_axis_desc_dma_addr_reg <= m_axis_desc_dma_addr_int;
temp_m_axis_desc_ram_sel_reg <= m_axis_desc_ram_sel_int;
temp_m_axis_desc_ram_addr_reg <= m_axis_desc_ram_addr_int;
temp_m_axis_desc_imm_reg <= m_axis_desc_imm_int;
temp_m_axis_desc_imm_en_reg <= m_axis_desc_imm_en_int;
temp_m_axis_desc_len_reg <= m_axis_desc_len_int;
temp_m_axis_desc_tag_reg <= m_axis_desc_tag_int;
end

14
rtl/dma_if_mux.v
View File

@ -52,6 +52,10 @@ module dma_if_mux #
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// Immediate enable
parameter IMM_ENABLE = 0,
// Immediate width
parameter IMM_WIDTH = 32,
// Length field width
parameter LEN_WIDTH = 16,
// Input tag field width
@ -92,6 +96,8 @@ module dma_if_mux #
output wire [DMA_ADDR_WIDTH-1:0] m_axis_write_desc_dma_addr,
output wire [M_RAM_SEL_WIDTH-1:0] m_axis_write_desc_ram_sel,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_write_desc_ram_addr,
output wire [IMM_WIDTH-1:0] m_axis_write_desc_imm,
output wire m_axis_write_desc_imm_en,
output wire [LEN_WIDTH-1:0] m_axis_write_desc_len,
output wire [M_TAG_WIDTH-1:0] m_axis_write_desc_tag,
output wire m_axis_write_desc_valid,
@ -128,6 +134,8 @@ module dma_if_mux #
input wire [PORTS*DMA_ADDR_WIDTH-1:0] s_axis_write_desc_dma_addr,
input wire [PORTS*S_RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel,
input wire [PORTS*RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr,
input wire [PORTS*IMM_WIDTH-1:0] s_axis_write_desc_imm,
input wire [PORTS-1:0] s_axis_write_desc_imm_en,
input wire [PORTS*LEN_WIDTH-1:0] s_axis_write_desc_len,
input wire [PORTS*S_TAG_WIDTH-1:0] s_axis_write_desc_tag,
input wire [PORTS-1:0] s_axis_write_desc_valid,
@ -266,6 +274,8 @@ dma_if_mux_wr #(
.M_RAM_SEL_WIDTH(M_RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.IMM_ENABLE(IMM_ENABLE),
.IMM_WIDTH(IMM_WIDTH),
.LEN_WIDTH(LEN_WIDTH),
.S_TAG_WIDTH(S_TAG_WIDTH),
.M_TAG_WIDTH(M_TAG_WIDTH),
@ -282,6 +292,8 @@ dma_if_mux_wr_inst (
.m_axis_write_desc_dma_addr(m_axis_write_desc_dma_addr),
.m_axis_write_desc_ram_sel(m_axis_write_desc_ram_sel),
.m_axis_write_desc_ram_addr(m_axis_write_desc_ram_addr),
.m_axis_write_desc_imm(m_axis_write_desc_imm),
.m_axis_write_desc_imm_en(m_axis_write_desc_imm_en),
.m_axis_write_desc_len(m_axis_write_desc_len),
.m_axis_write_desc_tag(m_axis_write_desc_tag),
.m_axis_write_desc_valid(m_axis_write_desc_valid),
@ -300,6 +312,8 @@ dma_if_mux_wr_inst (
.s_axis_write_desc_dma_addr(s_axis_write_desc_dma_addr),
.s_axis_write_desc_ram_sel(s_axis_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(s_axis_write_desc_ram_addr),
.s_axis_write_desc_imm(s_axis_write_desc_imm),
.s_axis_write_desc_imm_en(s_axis_write_desc_imm_en),
.s_axis_write_desc_len(s_axis_write_desc_len),
.s_axis_write_desc_tag(s_axis_write_desc_tag),
.s_axis_write_desc_valid(s_axis_write_desc_valid),

5
rtl/dma_if_mux_rd.v
View File

@ -134,6 +134,7 @@ dma_if_desc_mux #(
.M_RAM_SEL_WIDTH(M_RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.IMM_ENABLE(0),
.LEN_WIDTH(LEN_WIDTH),
.S_TAG_WIDTH(S_TAG_WIDTH),
.M_TAG_WIDTH(M_TAG_WIDTH),
@ -150,6 +151,8 @@ dma_if_desc_mux_inst (
.m_axis_desc_dma_addr(m_axis_read_desc_dma_addr),
.m_axis_desc_ram_sel(m_axis_read_desc_ram_sel),
.m_axis_desc_ram_addr(m_axis_read_desc_ram_addr),
.m_axis_desc_imm(),
.m_axis_desc_imm_en(),
.m_axis_desc_len(m_axis_read_desc_len),
.m_axis_desc_tag(m_axis_read_desc_tag),
.m_axis_desc_valid(m_axis_read_desc_valid),
@ -168,6 +171,8 @@ dma_if_desc_mux_inst (
.s_axis_desc_dma_addr(s_axis_read_desc_dma_addr),
.s_axis_desc_ram_sel(s_axis_read_desc_ram_sel),
.s_axis_desc_ram_addr(s_axis_read_desc_ram_addr),
.s_axis_desc_imm(32'd0),
.s_axis_desc_imm_en(1'b0),
.s_axis_desc_len(s_axis_read_desc_len),
.s_axis_desc_tag(s_axis_read_desc_tag),
.s_axis_desc_valid(s_axis_read_desc_valid),

14
rtl/dma_if_mux_wr.v
View File

@ -52,6 +52,10 @@ module dma_if_mux_wr #
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// Immediate enable
parameter IMM_ENABLE = 0,
// Immediate width
parameter IMM_WIDTH = 32,
// Length field width
parameter LEN_WIDTH = 16,
// Input tag field width
@ -74,6 +78,8 @@ module dma_if_mux_wr #
output wire [DMA_ADDR_WIDTH-1:0] m_axis_write_desc_dma_addr,
output wire [M_RAM_SEL_WIDTH-1:0] m_axis_write_desc_ram_sel,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_write_desc_ram_addr,
output wire [IMM_WIDTH-1:0] m_axis_write_desc_imm,
output wire m_axis_write_desc_imm_en,
output wire [LEN_WIDTH-1:0] m_axis_write_desc_len,
output wire [M_TAG_WIDTH-1:0] m_axis_write_desc_tag,
output wire m_axis_write_desc_valid,
@ -92,6 +98,8 @@ module dma_if_mux_wr #
input wire [PORTS*DMA_ADDR_WIDTH-1:0] s_axis_write_desc_dma_addr,
input wire [PORTS*S_RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel,
input wire [PORTS*RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr,
input wire [PORTS*IMM_WIDTH-1:0] s_axis_write_desc_imm,
input wire [PORTS-1:0] s_axis_write_desc_imm_en,
input wire [PORTS*LEN_WIDTH-1:0] s_axis_write_desc_len,
input wire [PORTS*S_TAG_WIDTH-1:0] s_axis_write_desc_tag,
input wire [PORTS-1:0] s_axis_write_desc_valid,
@ -134,6 +142,8 @@ dma_if_desc_mux #(
.M_RAM_SEL_WIDTH(M_RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.IMM_ENABLE(IMM_ENABLE),
.IMM_WIDTH(IMM_WIDTH),
.LEN_WIDTH(LEN_WIDTH),
.S_TAG_WIDTH(S_TAG_WIDTH),
.M_TAG_WIDTH(M_TAG_WIDTH),
@ -150,6 +160,8 @@ dma_if_desc_mux_inst (
.m_axis_desc_dma_addr(m_axis_write_desc_dma_addr),
.m_axis_desc_ram_sel(m_axis_write_desc_ram_sel),
.m_axis_desc_ram_addr(m_axis_write_desc_ram_addr),
.m_axis_desc_imm(m_axis_write_desc_imm),
.m_axis_desc_imm_en(m_axis_write_desc_imm_en),
.m_axis_desc_len(m_axis_write_desc_len),
.m_axis_desc_tag(m_axis_write_desc_tag),
.m_axis_desc_valid(m_axis_write_desc_valid),
@ -168,6 +180,8 @@ dma_if_desc_mux_inst (
.s_axis_desc_dma_addr(s_axis_write_desc_dma_addr),
.s_axis_desc_ram_sel(s_axis_write_desc_ram_sel),
.s_axis_desc_ram_addr(s_axis_write_desc_ram_addr),
.s_axis_desc_imm(s_axis_write_desc_imm),
.s_axis_desc_imm_en(s_axis_write_desc_imm_en),
.s_axis_desc_len(s_axis_write_desc_len),
.s_axis_desc_tag(s_axis_write_desc_tag),
.s_axis_desc_valid(s_axis_write_desc_valid),

10
rtl/dma_if_pcie.v
View File

@ -63,6 +63,10 @@ module dma_if_pcie #
parameter PCIE_ADDR_WIDTH = 64,
// PCIe tag count
parameter PCIE_TAG_COUNT = 256,
// Immediate enable
parameter IMM_ENABLE = 0,
// Immediate width
parameter IMM_WIDTH = 32,
// Length field width
parameter LEN_WIDTH = 16,
// Tag field width
@ -160,6 +164,8 @@ module dma_if_pcie #
input wire [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr,
input wire [RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel,
input wire [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr,
input wire [IMM_WIDTH-1:0] s_axis_write_desc_imm,
input wire s_axis_write_desc_imm_en,
input wire [LEN_WIDTH-1:0] s_axis_write_desc_len,
input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag,
input wire s_axis_write_desc_valid,
@ -385,6 +391,8 @@ dma_if_pcie_wr #(
.RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.IMM_ENABLE(IMM_ENABLE),
.IMM_WIDTH(IMM_WIDTH),
.LEN_WIDTH(LEN_WIDTH),
.TAG_WIDTH(TAG_WIDTH),
.OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
@ -426,6 +434,8 @@ dma_if_pcie_wr_inst (
.s_axis_write_desc_pcie_addr(s_axis_write_desc_pcie_addr),
.s_axis_write_desc_ram_sel(s_axis_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(s_axis_write_desc_ram_addr),
.s_axis_write_desc_imm(s_axis_write_desc_imm),
.s_axis_write_desc_imm_en(s_axis_write_desc_imm_en),
.s_axis_write_desc_len(s_axis_write_desc_len),
.s_axis_write_desc_tag(s_axis_write_desc_tag),
.s_axis_write_desc_valid(s_axis_write_desc_valid),

67
rtl/dma_if_pcie_wr.v
View File

@ -61,6 +61,10 @@ module dma_if_pcie_wr #
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
// PCIe address width
parameter PCIE_ADDR_WIDTH = 64,
// Immediate enable
parameter IMM_ENABLE = 0,
// Immediate width
parameter IMM_WIDTH = 32,
// Length field width
parameter LEN_WIDTH = 16,
// Tag field width
@ -108,6 +112,8 @@ module dma_if_pcie_wr #
input wire [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr,
input wire [RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel,
input wire [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr,
input wire [IMM_WIDTH-1:0] s_axis_write_desc_imm,
input wire s_axis_write_desc_imm_en,
input wire [LEN_WIDTH-1:0] s_axis_write_desc_len,
input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag,
input wire s_axis_write_desc_valid,
@ -230,6 +236,11 @@ initial begin
$error("Error: RAM_ADDR_WIDTH does not match RAM configuration (instance %m)");
$finish;
end
if (IMM_ENABLE && IMM_WIDTH > TLP_DATA_WIDTH) begin
$error("Error: IMM_WIDTH must not be larger than the PCIe interface width (instance %m)");
$finish;
end
end
localparam [2:0]
@ -265,6 +276,8 @@ reg read_cmd_ready;
reg [PCIE_ADDR_WIDTH-1:0] pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, pcie_addr_next;
reg [RAM_SEL_WIDTH-1:0] ram_sel_reg = {RAM_SEL_WIDTH{1'b0}}, ram_sel_next;
reg [RAM_ADDR_WIDTH-1:0] ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, ram_addr_next;
reg [IMM_WIDTH-1:0] imm_reg = {IMM_WIDTH{1'b0}}, imm_next;
reg imm_en_reg = 1'b0, imm_en_next;
reg [LEN_WIDTH-1:0] op_count_reg = {LEN_WIDTH{1'b0}}, op_count_next;
reg [LEN_WIDTH-1:0] tr_count_reg = {LEN_WIDTH{1'b0}}, tr_count_next;
reg [12:0] tlp_count_reg = 13'd0, tlp_count_next;
@ -274,6 +287,7 @@ reg zero_len_reg = 1'b0, zero_len_next;
reg [PCIE_ADDR_WIDTH-1:0] read_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, read_pcie_addr_next;
reg [RAM_SEL_WIDTH-1:0] read_ram_sel_reg = {RAM_SEL_WIDTH{1'b0}}, read_ram_sel_next;
reg [RAM_ADDR_WIDTH-1:0] read_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, read_ram_addr_next;
reg read_imm_en_reg = 1'b0, read_imm_en_next;
reg [LEN_WIDTH-1:0] read_len_reg = {LEN_WIDTH{1'b0}}, read_len_next;
reg [RAM_SEG_COUNT-1:0] read_ram_mask_reg = {RAM_SEG_COUNT{1'b0}}, read_ram_mask_next;
reg [RAM_SEG_COUNT-1:0] read_ram_mask_0_reg = {RAM_SEG_COUNT{1'b0}}, read_ram_mask_0_next;
@ -286,6 +300,8 @@ reg [RAM_OFFSET_WIDTH-1:0] start_offset_reg = {RAM_OFFSET_WIDTH{1'b0}}, start_of
reg [RAM_OFFSET_WIDTH-1:0] end_offset_reg = {RAM_OFFSET_WIDTH{1'b0}}, end_offset_next;
reg [PCIE_ADDR_WIDTH-1:0] tlp_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, tlp_addr_next;
reg [IMM_WIDTH-1:0] tlp_imm_reg = {IMM_WIDTH{1'b0}}, tlp_imm_next;
reg tlp_imm_en_reg = 1'b0, tlp_imm_en_next;
reg [11:0] tlp_len_reg = 12'd0, tlp_len_next;
reg tlp_zero_len_reg = 1'b0, tlp_zero_len_next;
reg [RAM_OFFSET_WIDTH-1:0] offset_reg = {RAM_OFFSET_WIDTH{1'b0}}, offset_next;
@ -299,6 +315,7 @@ reg tlp_frame_reg = 1'b0, tlp_frame_next;
reg [PCIE_ADDR_WIDTH-1:0] read_cmd_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, read_cmd_pcie_addr_next;
reg [RAM_SEL_WIDTH-1:0] read_cmd_ram_sel_reg = {RAM_SEL_WIDTH{1'b0}}, read_cmd_ram_sel_next;
reg [RAM_ADDR_WIDTH-1:0] read_cmd_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, read_cmd_ram_addr_next;
reg read_cmd_imm_en_reg = 1'b0, read_cmd_imm_en_next;
reg [11:0] read_cmd_len_reg = 12'd0, read_cmd_len_next;
reg [CYCLE_COUNT_WIDTH-1:0] read_cmd_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, read_cmd_cycle_count_next;
reg read_cmd_last_cycle_reg = 1'b0, read_cmd_last_cycle_next;
@ -395,6 +412,8 @@ assign stat_wr_tx_stall = stat_wr_tx_stall_reg;
// operation tag management
reg [OP_TAG_WIDTH+1-1:0] op_table_start_ptr_reg = 0;
reg [PCIE_ADDR_WIDTH-1:0] op_table_start_pcie_addr;
reg [IMM_WIDTH-1:0] op_table_start_imm;
reg op_table_start_imm_en;
reg [11:0] op_table_start_len;
reg op_table_start_zero_len;
reg [9:0] op_table_start_dword_len;
@ -415,6 +434,10 @@ reg [2**OP_TAG_WIDTH-1:0] op_table_tx_done = 0;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [PCIE_ADDR_WIDTH-1:0] op_table_pcie_addr[2**OP_TAG_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [IMM_WIDTH-1:0] op_table_imm[2**OP_TAG_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg op_table_imm_en[2**OP_TAG_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [11:0] op_table_len[2**OP_TAG_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg op_table_zero_len[2**OP_TAG_WIDTH-1:0];
@ -434,6 +457,8 @@ integer i;
initial begin
for (i = 0; i < 2**OP_TAG_WIDTH; i = i + 1) begin
op_table_pcie_addr[i] = 0;
op_table_imm[i] = 0;
op_table_imm_en[i] = 0;
op_table_len[i] = 0;
op_table_zero_len[i] = 0;
op_table_dword_len[i] = 0;
@ -463,6 +488,8 @@ always @* begin
pcie_addr_next = pcie_addr_reg;
ram_sel_next = ram_sel_reg;
ram_addr_next = ram_addr_reg;
imm_next = imm_reg;
imm_en_next = imm_en_reg;
op_count_next = op_count_reg;
tr_count_next = tr_count_reg;
tlp_count_next = tlp_count_reg;
@ -472,12 +499,15 @@ always @* begin
read_cmd_pcie_addr_next = read_cmd_pcie_addr_reg;
read_cmd_ram_sel_next = read_cmd_ram_sel_reg;
read_cmd_ram_addr_next = read_cmd_ram_addr_reg;
read_cmd_imm_en_next = read_cmd_imm_en_reg;
read_cmd_len_next = read_cmd_len_reg;
read_cmd_cycle_count_next = read_cmd_cycle_count_reg;
read_cmd_last_cycle_next = read_cmd_last_cycle_reg;
read_cmd_valid_next = read_cmd_valid_reg && !read_cmd_ready;
op_table_start_pcie_addr = pcie_addr_reg;
op_table_start_imm = imm_reg;
op_table_start_imm_en = imm_en_reg;
op_table_start_len = tlp_count_reg;
op_table_start_zero_len = zero_len_reg;
op_table_start_dword_len = (tlp_count_reg + pcie_addr_reg[1:0] + 3) >> 2;
@ -494,8 +524,15 @@ always @* begin
s_axis_write_desc_ready_next = !op_table_active[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] && ($unsigned(op_table_start_ptr_reg - op_table_finish_ptr_reg) < 2**OP_TAG_WIDTH) && enable;
pcie_addr_next = s_axis_write_desc_pcie_addr;
ram_sel_next = s_axis_write_desc_ram_sel;
ram_addr_next = s_axis_write_desc_ram_addr;
if (IMM_ENABLE && s_axis_write_desc_imm_en) begin
ram_sel_next = 0;
ram_addr_next = 0;
end else begin
ram_sel_next = s_axis_write_desc_ram_sel;
ram_addr_next = s_axis_write_desc_ram_addr;
end
imm_next = s_axis_write_desc_imm;
imm_en_next = IMM_ENABLE && s_axis_write_desc_imm_en;
if (s_axis_write_desc_len == 0) begin
// zero-length operation
op_count_next = 1;
@ -544,6 +581,7 @@ always @* begin
read_cmd_pcie_addr_next = pcie_addr_reg;
read_cmd_ram_sel_next = ram_sel_reg;
read_cmd_ram_addr_next = ram_addr_reg;
read_cmd_imm_en_next = imm_en_reg;
read_cmd_len_next = tlp_count_reg;
read_cmd_cycle_count_next = (tlp_count_reg + pcie_addr_reg[1:0] - 1) >> $clog2(TLP_DATA_WIDTH_BYTES);
op_table_start_cycle_count = read_cmd_cycle_count_next;
@ -555,6 +593,8 @@ always @* begin
op_count_next = op_count_reg - tlp_count_reg;
op_table_start_pcie_addr = pcie_addr_reg;
op_table_start_imm = imm_reg;
op_table_start_imm_en = imm_en_reg;
op_table_start_len = tlp_count_reg;
op_table_start_zero_len = zero_len_reg;
op_table_start_dword_len = (tlp_count_reg + pcie_addr_reg[1:0] + 3) >> 2;
@ -614,6 +654,7 @@ always @* begin
read_pcie_addr_next = read_pcie_addr_reg;
read_ram_sel_next = read_ram_sel_reg;
read_ram_addr_next = read_ram_addr_reg;
read_imm_en_next = read_imm_en_reg;
read_len_next = read_len_reg;
read_ram_mask_next = read_ram_mask_reg;
read_ram_mask_0_next = read_ram_mask_0_reg;
@ -636,6 +677,7 @@ always @* begin
read_pcie_addr_next = read_cmd_pcie_addr_reg;
read_ram_sel_next = read_cmd_ram_sel_reg;
read_ram_addr_next = read_cmd_ram_addr_reg;
read_imm_en_next = read_cmd_imm_en_reg;
read_len_next = read_cmd_len_reg;
read_cycle_count_next = read_cmd_cycle_count_reg;
read_last_cycle_next = read_cmd_last_cycle_reg;
@ -681,14 +723,14 @@ always @* begin
if (read_ram_mask_reg[i]) begin
ram_rd_cmd_sel_next[i*RAM_SEL_WIDTH +: RAM_SEL_WIDTH] = read_ram_sel_reg;
ram_rd_cmd_addr_next[i*RAM_SEG_ADDR_WIDTH +: RAM_SEG_ADDR_WIDTH] = read_ram_addr_reg[RAM_ADDR_WIDTH-1:RAM_ADDR_WIDTH-RAM_SEG_ADDR_WIDTH];
ram_rd_cmd_valid_next[i] = 1'b1;
ram_rd_cmd_valid_next[i] = !(IMM_ENABLE && read_imm_en_reg);
end
if (read_ram_mask_1_reg[i]) begin
ram_rd_cmd_addr_next[i*RAM_SEG_ADDR_WIDTH +: RAM_SEG_ADDR_WIDTH] = read_ram_addr_reg[RAM_ADDR_WIDTH-1:RAM_ADDR_WIDTH-RAM_SEG_ADDR_WIDTH]+1;
end
end
mask_fifo_wr_mask = read_ram_mask_reg;
mask_fifo_wr_mask = (IMM_ENABLE && read_imm_en_reg) ? 0 : read_ram_mask_reg;
mask_fifo_we = 1'b1;
if (read_len_next > TLP_DATA_WIDTH_BYTES) begin
@ -718,6 +760,7 @@ always @* begin
read_pcie_addr_next = read_cmd_pcie_addr_reg;
read_ram_sel_next = read_cmd_ram_sel_reg;
read_ram_addr_next = read_cmd_ram_addr_reg;
read_imm_en_next = read_cmd_imm_en_reg;
read_len_next = read_cmd_len_reg;
read_cycle_count_next = read_cmd_cycle_count_reg;
read_last_cycle_next = read_cmd_last_cycle_reg;
@ -769,6 +812,8 @@ always @* begin
stat_wr_req_finish_valid_next = 1'b0;
tlp_addr_next = tlp_addr_reg;
tlp_imm_next = tlp_imm_reg;
tlp_imm_en_next = tlp_imm_en_reg;
tlp_len_next = tlp_len_reg;
tlp_zero_len_next = tlp_zero_len_reg;
dword_count_next = dword_count_reg;
@ -839,6 +884,8 @@ always @* begin
tlp_frame_next = 1'b0;
tlp_addr_next = op_table_pcie_addr[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
tlp_imm_next = op_table_imm[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
tlp_imm_en_next = op_table_imm_en[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
tlp_len_next = op_table_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
tlp_zero_len_next = op_table_zero_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
dword_count_next = op_table_dword_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
@ -857,7 +904,7 @@ always @* begin
// transfer state, transfer data
if (!tx_wr_req_tlp_valid_reg || tx_wr_req_tlp_ready) begin
tx_wr_req_tlp_data_next = {2{ram_rd_resp_data}} >> (RAM_DATA_WIDTH-offset_reg*8);
tx_wr_req_tlp_data_next = ((IMM_ENABLE && tlp_imm_en_reg) ? {2{{RAM_DATA_WIDTH{1'b0}} | tlp_imm_reg}} : {2{ram_rd_resp_data}}) >> (RAM_DATA_WIDTH-offset_reg*8);
if (dword_count_reg >= TLP_STRB_WIDTH) begin
tx_wr_req_tlp_strb_next = {TLP_STRB_WIDTH{1'b1}};
end else begin
@ -895,6 +942,8 @@ always @* begin
// skip idle state if possible
tlp_addr_next = op_table_pcie_addr[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
tlp_imm_next = op_table_imm[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
tlp_imm_en_next = op_table_imm_en[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
tlp_len_next = op_table_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
tlp_zero_len_next = op_table_zero_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
dword_count_next = op_table_dword_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
@ -977,6 +1026,8 @@ always @(posedge clk) begin
pcie_addr_reg <= pcie_addr_next;
ram_sel_reg <= ram_sel_next;
ram_addr_reg <= ram_addr_next;
imm_reg <= imm_next;
imm_en_reg <= imm_en_next;
op_count_reg <= op_count_next;
tr_count_reg <= tr_count_next;
tlp_count_reg <= tlp_count_next;
@ -986,6 +1037,7 @@ always @(posedge clk) begin
read_pcie_addr_reg <= read_pcie_addr_next;
read_ram_sel_reg <= read_ram_sel_next;
read_ram_addr_reg <= read_ram_addr_next;
read_imm_en_reg <= read_imm_en_next;
read_len_reg <= read_len_next;
read_ram_mask_reg <= read_ram_mask_next;
read_ram_mask_0_reg <= read_ram_mask_0_next;
@ -998,6 +1050,8 @@ always @(posedge clk) begin
end_offset_reg <= end_offset_next;
tlp_addr_reg <= tlp_addr_next;
tlp_imm_reg <= tlp_imm_next;
tlp_imm_en_reg <= tlp_imm_en_next;
tlp_len_reg <= tlp_len_next;
tlp_zero_len_reg <= tlp_zero_len_next;
dword_count_reg <= dword_count_next;
@ -1011,6 +1065,7 @@ always @(posedge clk) begin
read_cmd_pcie_addr_reg <= read_cmd_pcie_addr_next;
read_cmd_ram_sel_reg <= read_cmd_ram_sel_next;
read_cmd_ram_addr_reg <= read_cmd_ram_addr_next;
read_cmd_imm_en_reg <= read_cmd_imm_en_next;
read_cmd_len_reg <= read_cmd_len_next;
read_cmd_cycle_count_reg <= read_cmd_cycle_count_next;
read_cmd_last_cycle_reg <= read_cmd_last_cycle_next;
@ -1066,6 +1121,8 @@ always @(posedge clk) begin
op_table_active[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= 1'b1;
op_table_tx_done[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= 1'b0;
op_table_pcie_addr[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= op_table_start_pcie_addr;
op_table_imm[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= op_table_start_imm;
op_table_imm_en[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= op_table_start_imm_en;
op_table_len[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= op_table_start_len;
op_table_zero_len[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= op_table_start_zero_len;
op_table_dword_len[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= op_table_start_dword_len;

6
tb/dma_if_axi_wr/Makefile
View File

@ -42,6 +42,8 @@ export PARAM_RAM_SEG_COUNT ?= 2
export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) )
export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 )
export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_IMM_ENABLE ?= 1
export PARAM_IMM_WIDTH ?= $(PARAM_AXI_DATA_WIDTH)
export PARAM_LEN_WIDTH ?= 16
export PARAM_TAG_WIDTH ?= 8
export PARAM_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
@ -60,6 +62,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).IMM_ENABLE=$(PARAM_IMM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).IMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).OP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
@ -82,6 +86,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GRAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH)
COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH)
COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH)
COMPILE_ARGS += -GIMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -GIMM_ENABLE=$(PARAM_IMM_ENABLE)
COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GOP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)

57
tb/dma_if_axi_wr/test_dma_if_axi_wr.py
View File

@ -50,7 +50,7 @@ except ImportError:
del sys.path[0]
DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc",
signals=["axi_addr", "ram_addr", "ram_sel", "len", "tag", "valid", "ready"]
signals=["axi_addr", "ram_addr", "ram_sel", "imm", "imm_en", "len", "tag", "valid", "ready"]
)
DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus",
@ -153,6 +153,54 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await RisingEdge(dut.clk)
async def run_test_write_imm(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
axi_byte_lanes = tb.axi_ram.byte_lanes
tag_count = 2**len(tb.write_desc_source.bus.tag)
cur_tag = 1
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
await tb.cycle_reset()
tb.dut.enable.value = 1
for length in list(range(1, len(dut.s_axis_write_desc_imm) // 8)):
# for axi_offset in axi_offsets:
for axi_offset in list(range(axi_byte_lanes+1))+list(range(4096-axi_byte_lanes, 4096)):
tb.log.info("length %d, axi_offset %d", length, axi_offset)
axi_addr = axi_offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
imm = int.from_bytes(test_data, 'little')
tb.axi_ram.write(axi_addr-128, b'\xaa'*(len(test_data)+256))
tb.log.debug("Immediate: 0x%x", imm)
desc = DescTransaction(axi_addr=axi_addr, ram_addr=0, ram_sel=0, imm=imm, imm_en=1, len=len(test_data), tag=cur_tag)
await tb.write_desc_source.send(desc)
status = await tb.write_desc_status_sink.recv()
tb.log.info("status: %s", status)
assert int(status.tag) == cur_tag
assert int(status.error) == 0
tb.log.debug("%s", tb.axi_ram.hexdump_str((axi_addr & ~0xf)-16, (((axi_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
assert tb.axi_ram.read(axi_addr-1, len(test_data)+2) == b'\xaa'+test_data+b'\xaa'
cur_tag = (cur_tag + 1) % tag_count
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
@ -164,6 +212,11 @@ if cocotb.SIM_NAME:
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
factory = TestFactory(run_test_write_imm)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
@ -201,6 +254,8 @@ def test_dma_if_axi_wr(request, axi_data_width):
parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width
parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width
parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width
parameters['IMM_ENABLE'] = 1
parameters['IMM_WIDTH'] = parameters['AXI_DATA_WIDTH']
parameters['LEN_WIDTH'] = 16
parameters['TAG_WIDTH'] = 8
parameters['OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']

6
tb/dma_if_pcie_wr/Makefile
View File

@ -46,6 +46,8 @@ export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* $(PARA
export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 )
export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_PCIE_ADDR_WIDTH ?= 64
export PARAM_IMM_ENABLE ?= 1
export PARAM_IMM_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* $(PARAM_TLP_SEG_DATA_WIDTH) )
export PARAM_LEN_WIDTH ?= 20
export PARAM_TAG_WIDTH ?= 8
export PARAM_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" )
@ -70,6 +72,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_ADDR_WIDTH=$(PARAM_PCIE_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).IMM_ENABLE=$(PARAM_IMM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).IMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).OP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
@ -98,6 +102,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH)
COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH)
COMPILE_ARGS += -GPCIE_ADDR_WIDTH=$(PARAM_PCIE_ADDR_WIDTH)
COMPILE_ARGS += -GIMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -GIMM_ENABLE=$(PARAM_IMM_ENABLE)
COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GOP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)

66
tb/dma_if_pcie_wr/test_dma_if_pcie_wr.py
View File

@ -53,7 +53,7 @@ except ImportError:
del sys.path[0]
DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc",
signals=["pcie_addr", "ram_addr", "ram_sel", "len", "tag", "valid", "ready"]
signals=["pcie_addr", "ram_addr", "ram_sel", "imm", "imm_en", "len", "tag", "valid", "ready"]
)
DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus",
@ -184,6 +184,64 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await RisingEdge(dut.clk)
async def run_test_write_imm(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
if os.getenv("PCIE_OFFSET") is None:
pcie_offsets = list(range(4))+list(range(4096-4, 4096))
else:
pcie_offsets = [int(os.getenv("PCIE_OFFSET"))]
byte_lanes = tb.dma_ram.byte_lanes
tag_count = 2**len(tb.write_desc_source.bus.tag)
cur_tag = 1
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
await tb.cycle_reset()
await tb.rc.enumerate(enable_bus_mastering=True)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.enable <= 1
for length in list(range(0, len(dut.s_axis_write_desc_imm) // 8 + 1)):
for pcie_offset in pcie_offsets:
tb.log.info("length %d, pcie_offset %d", length, pcie_offset)
pcie_addr = pcie_offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
imm = int.from_bytes(test_data, 'little')
mem[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
tb.log.debug("Immediate: 0x%x", imm)
desc = DescTransaction(pcie_addr=mem_base+pcie_addr, ram_addr=0, ram_sel=0, imm=imm, imm_en=1, len=len(test_data), tag=cur_tag)
await tb.write_desc_source.send(desc)
status = await tb.write_desc_status_sink.recv()
await Timer(100 + (length // byte_lanes), 'ns')
tb.log.info("status: %s", status)
assert int(status.tag) == cur_tag
assert int(status.error) == 0
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
assert mem[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
cur_tag = (cur_tag + 1) % tag_count
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
@ -194,6 +252,10 @@ if cocotb.SIM_NAME:
factory.add_option(("idle_inserter", "backpressure_inserter"), [(None, None), (cycle_pause, cycle_pause)])
factory.generate_tests()
factory = TestFactory(run_test_write_imm)
factory.add_option(("idle_inserter", "backpressure_inserter"), [(None, None), (cycle_pause, cycle_pause)])
factory.generate_tests()
# cocotb-test
@ -241,6 +303,8 @@ def test_dma_if_pcie_wr(request, pcie_data_width, pcie_offset):
parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width
parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width
parameters['PCIE_ADDR_WIDTH'] = 64
parameters['IMM_ENABLE'] = 1
parameters['IMM_WIDTH'] = parameters['TLP_SEG_COUNT'] * parameters['TLP_SEG_DATA_WIDTH']
parameters['LEN_WIDTH'] = 20
parameters['TAG_WIDTH'] = 8
parameters['OP_TABLE_SIZE'] = 2**(parameters['TX_SEQ_NUM_WIDTH']-1)