From a6c4b8b1b7520528ed29e9e5d146390258630f21 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 21 Jul 2019 15:27:01 -0700 Subject: [PATCH] Change board IDs --- fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v | 2 +- fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v | 2 +- modules/mqnic/mqnic_hw.h | 4 ++-- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index d837bac53..018ce06cc 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -277,7 +277,7 @@ parameter PTP_PERIOD_FNS = 32'd0; // FW and board IDs parameter FW_ID = 32'd0; parameter FW_VER = {16'd0, 16'd1}; -parameter BOARD_ID = {16'h4144, 16'h0001}; +parameter BOARD_ID = {16'h4144, 16'h9003}; parameter BOARD_VER = {16'd0, 16'd1}; // Structural parameters diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v index b0ab07cde..09aa76069 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -215,7 +215,7 @@ parameter PTP_PERIOD_FNS = 32'd0; // FW and board IDs parameter FW_ID = 32'd0; parameter FW_VER = {16'd0, 16'd1}; -parameter BOARD_ID = {16'h1ce4, 16'h0001}; +parameter BOARD_ID = {16'h1ce4, 16'h800a}; parameter BOARD_VER = {16'd0, 16'd1}; // Structural parameters diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index aff64065b..266f4a148 100644 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -277,7 +277,7 @@ parameter PTP_PERIOD_FNS = 32'd0; // FW and board IDs parameter FW_ID = 32'd0; parameter FW_VER = {16'd0, 16'd1}; -parameter BOARD_ID = {16'h4144, 16'h0001}; +parameter BOARD_ID = {16'h4144, 16'h9003}; parameter BOARD_VER = {16'd0, 16'd1}; // Structural parameters diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v index 5745326ab..f31931918 100644 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -215,7 +215,7 @@ parameter PTP_PERIOD_FNS = 32'd0; // FW and board IDs parameter FW_ID = 32'd0; parameter FW_VER = {16'd0, 16'd1}; -parameter BOARD_ID = {16'h1ce4, 16'h0001}; +parameter BOARD_ID = {16'h1ce4, 16'h800a}; parameter BOARD_VER = {16'd0, 16'd1}; // Structural parameters diff --git a/modules/mqnic/mqnic_hw.h b/modules/mqnic/mqnic_hw.h index 4820ee785..c29196805 100644 --- a/modules/mqnic/mqnic_hw.h +++ b/modules/mqnic/mqnic_hw.h @@ -42,8 +42,8 @@ either expressed or implied, of The Regents of the University of California. #define MQNIC_MAX_RX_RINGS 256 #define MQNIC_MAX_RX_CPL_RINGS 256 -#define MQNIC_BOARD_ID_EXANIC_X10 0x1ce40001 -#define MQNIC_BOARD_ID_ADM_PCIE_9V3 0x41440001 +#define MQNIC_BOARD_ID_EXANIC_X10 0x1ce4800a +#define MQNIC_BOARD_ID_ADM_PCIE_9V3 0x41449003 // NIC CSRs #define MQNIC_REG_FW_ID 0x0000