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Add FPGA ID code for userspace tools
This commit is contained in:
Alex Forencich
parent
2a137bccbd
commit
a7241bc597
138
utils/fpga_id.c
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138
utils/fpga_id.c
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/*
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Copyright 2020, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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#include "fpga_id.h"
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struct fpga_id {
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int id;
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char part[16];
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};
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const struct fpga_id fpga_id_list[] =
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{
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// Artix 7
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{FPGA_ID_XC7A15T, "XC7A15T"},
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{FPGA_ID_XC7A35T, "XC7A35T"},
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{FPGA_ID_XC7A50T, "XC7A50T"},
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{FPGA_ID_XC7A75T, "XC7A75T"},
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{FPGA_ID_XC7A100T, "XC7A100T"},
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{FPGA_ID_XC7A200T, "XC7A200T"},
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// Kintex 7
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{FPGA_ID_XC7K70T, "XC7K70T"},
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{FPGA_ID_XC7K160T, "XC7K160T"},
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{FPGA_ID_XC7K325T, "XC7K325T"},
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{FPGA_ID_XC7K355T, "XC7K355T"},
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{FPGA_ID_XC7K410T, "XC7K410T"},
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{FPGA_ID_XC7K420T, "XC7K420T"},
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{FPGA_ID_XC7K480T, "XC7K480T"},
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// Virtex 7
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{FPGA_ID_XC7V585T, "XC7V585T"},
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{FPGA_ID_XC7V2000T, "XC7V2000T"},
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{FPGA_ID_XC7VX330T, "XC7VX330T"},
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{FPGA_ID_XC7VX415T, "XC7VX415T"},
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{FPGA_ID_XC7VX485T, "XC7VX485T"},
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{FPGA_ID_XC7VX550T, "XC7VX550T"},
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{FPGA_ID_XC7VX690T, "XC7VX690T"},
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{FPGA_ID_XC7VX980T, "XC7VX980T"},
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{FPGA_ID_XC7VX1140T, "XC7VX1140T"},
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{FPGA_ID_XC7VH580T, "XC7VH580T"},
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{FPGA_ID_XC7VH870T, "XC7VH870T"},
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// Kintex Ultrascale
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{FPGA_ID_XCKU025, "XCKU025"},
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{FPGA_ID_XCKU035, "XCKU035"},
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{FPGA_ID_XCKU040, "XCKU040"},
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{FPGA_ID_XCKU060, "XCKU060"},
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{FPGA_ID_XCKU085, "XCKU085"},
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{FPGA_ID_XCKU095, "XCKU095"},
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{FPGA_ID_XCKU115, "XCKU115"},
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// Virtex Ultrascale
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{FPGA_ID_XCVU065, "XCVU065"},
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{FPGA_ID_XCVU080, "XCVU080"},
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{FPGA_ID_XCVU095, "XCVU095"},
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{FPGA_ID_XCVU125, "XCVU125"},
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{FPGA_ID_XCVU160, "XCVU160"},
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{FPGA_ID_XCVU190, "XCVU190"},
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{FPGA_ID_XCVU440, "XCVU440"},
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// Kintex Ultrascale+
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{FPGA_ID_XCKU3P, "XCKU3P"},
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{FPGA_ID_XCKU5P, "XCKU5P"},
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{FPGA_ID_XCKU9P, "XCKU9P"},
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{FPGA_ID_XCKU11P, "XCKU11P"},
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{FPGA_ID_XCKU13P, "XCKU13P"},
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{FPGA_ID_XCKU15P, "XCKU15P"},
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// Virtex Ultrascale+
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{FPGA_ID_XCVU3P, "XCVU3P"},
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{FPGA_ID_XCVU5P, "XCVU5P"},
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{FPGA_ID_XCVU7P, "XCVU7P"},
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{FPGA_ID_XCVU9P, "XCVU9P"},
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{FPGA_ID_XCVU11P, "XCVU11P"},
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{FPGA_ID_XCVU13P, "XCVU13P"},
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// Zynq Ultrascale+
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{FPGA_ID_XCZU2, "XCZU2"},
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{FPGA_ID_XCZU3, "XCZU3"},
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{FPGA_ID_XCZU4, "XCZU4"},
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{FPGA_ID_XCZU5, "XCZU5"},
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{FPGA_ID_XCZU6, "XCZU6"},
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{FPGA_ID_XCZU7, "XCZU7"},
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{FPGA_ID_XCZU9, "XCZU9"},
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{FPGA_ID_XCZU11, "XCZU11"},
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{FPGA_ID_XCZU15, "XCZU15"},
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{FPGA_ID_XCZU17, "XCZU17"},
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{FPGA_ID_XCZU19, "XCZU19"},
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{FPGA_ID_XCZU21, "XCZU21"},
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{FPGA_ID_XCZU25, "XCZU25"},
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{FPGA_ID_XCZU27, "XCZU27"},
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{FPGA_ID_XCZU28, "XCZU28"},
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{FPGA_ID_XCZU29, "XCZU29"},
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// Alveo
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{FPGA_ID_XCU50, "XCU50"},
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{FPGA_ID_XCU200, "XCU200"},
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{FPGA_ID_XCU250, "XCU250"},
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{FPGA_ID_XCU280, "XCU280"},
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{0, ""}
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};
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const char *get_fpga_part(int id)
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{
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const struct fpga_id *ptr = fpga_id_list;
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id = id & 0x0fffffff; // mask off version
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while (ptr->id && ptr->id != id)
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{
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ptr++;
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}
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return ptr->part;
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}
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119
utils/fpga_id.h
Normal file
119
utils/fpga_id.h
Normal file
@ -0,0 +1,119 @@
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/*
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Copyright 2020, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
|
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1. Redistributions of source code must retain the above copyright notice,
|
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this list of conditions and the following disclaimer.
|
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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#ifndef FPGA_ID_H
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#define FPGA_ID_H
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// Artix 7
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#define FPGA_ID_XC7A15T 0x362D093
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#define FPGA_ID_XC7A35T 0x362D093
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#define FPGA_ID_XC7A50T 0x362C093
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#define FPGA_ID_XC7A75T 0x3632093
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#define FPGA_ID_XC7A100T 0x3631093
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#define FPGA_ID_XC7A200T 0x3636093
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// Kintex 7
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#define FPGA_ID_XC7K70T 0x3647093
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#define FPGA_ID_XC7K160T 0x364C093
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#define FPGA_ID_XC7K325T 0x3651093
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#define FPGA_ID_XC7K355T 0x3747093
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#define FPGA_ID_XC7K410T 0x3656093
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#define FPGA_ID_XC7K420T 0x3752093
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#define FPGA_ID_XC7K480T 0x3751093
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// Virtex 7
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#define FPGA_ID_XC7V585T 0x3671093
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#define FPGA_ID_XC7V2000T 0x36B3093
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#define FPGA_ID_XC7VX330T 0x3667093
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#define FPGA_ID_XC7VX415T 0x3682093
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#define FPGA_ID_XC7VX485T 0x3687093
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#define FPGA_ID_XC7VX550T 0x3692093
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#define FPGA_ID_XC7VX690T 0x3691093
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#define FPGA_ID_XC7VX980T 0x3696093
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#define FPGA_ID_XC7VX1140T 0x36D5093
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#define FPGA_ID_XC7VH580T 0x36D9093
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#define FPGA_ID_XC7VH870T 0x36DB093
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// Kintex Ultrascale
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#define FPGA_ID_XCKU025 0x3824093
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#define FPGA_ID_XCKU035 0x3823093
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#define FPGA_ID_XCKU040 0x3822093
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#define FPGA_ID_XCKU060 0x3919093
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#define FPGA_ID_XCKU085 0x380F093
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#define FPGA_ID_XCKU095 0x3844093
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#define FPGA_ID_XCKU115 0x390D093
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// Virtex Ultrascale
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#define FPGA_ID_XCVU065 0x3939093
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#define FPGA_ID_XCVU080 0x3843093
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#define FPGA_ID_XCVU095 0x3842093
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#define FPGA_ID_XCVU125 0x392D093
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#define FPGA_ID_XCVU160 0x3933093
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#define FPGA_ID_XCVU190 0x3931093
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#define FPGA_ID_XCVU440 0x396D093
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// Kintex Ultrascale+
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#define FPGA_ID_XCKU3P 0x4A63093
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#define FPGA_ID_XCKU5P 0x4A62093
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#define FPGA_ID_XCKU9P 0x484A093
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#define FPGA_ID_XCKU11P 0x4A4E093
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#define FPGA_ID_XCKU13P 0x4A52093
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#define FPGA_ID_XCKU15P 0x4A56093
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// Virtex Ultrascale+
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#define FPGA_ID_XCVU3P 0x4B39093
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#define FPGA_ID_XCVU5P 0x4B2B093
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#define FPGA_ID_XCVU7P 0x4B29093
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#define FPGA_ID_XCVU9P 0x4B31093
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#define FPGA_ID_XCVU11P 0x4B49093
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#define FPGA_ID_XCVU13P 0x4B51093
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// Zynq Ultrascale+
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#define FPGA_ID_XCZU2 0x4711093
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#define FPGA_ID_XCZU3 0x4710093
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#define FPGA_ID_XCZU4 0x4721093
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#define FPGA_ID_XCZU5 0x4720093
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#define FPGA_ID_XCZU6 0x4739093
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#define FPGA_ID_XCZU7 0x4730093
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#define FPGA_ID_XCZU9 0x4738093
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#define FPGA_ID_XCZU11 0x4740093
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#define FPGA_ID_XCZU15 0x4750093
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#define FPGA_ID_XCZU17 0x4759093
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#define FPGA_ID_XCZU19 0x4758093
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#define FPGA_ID_XCZU21 0x47E1093
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#define FPGA_ID_XCZU25 0x47E5093
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#define FPGA_ID_XCZU27 0x47E4093
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#define FPGA_ID_XCZU28 0x47E0093
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#define FPGA_ID_XCZU29 0x47E2093
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// Alveo
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#define FPGA_ID_XCU50 0x4B77093
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#define FPGA_ID_XCU200 0x4B37093
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#define FPGA_ID_XCU250 0x4B57093
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#define FPGA_ID_XCU280 0x4B7D093
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const char *get_fpga_part(int id);
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#endif /* FPGA_ID_H */
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