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Pipeline RAM output in RAM switch

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This commit is contained in:
Alex Forencich 2020-09-03 15:55:45 -07:00
parent ae10935a93
commit a7689b6772
7 changed files with 33 additions and 12 deletions
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30
rtl/axis_ram_switch.v
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@ -93,7 +93,9 @@ module axis_ram_switch #
// arbitration type: "PRIORITY" or "ROUND_ROBIN" // arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "ROUND_ROBIN", parameter ARB_TYPE = "ROUND_ROBIN",
// LSB priority: "LOW", "HIGH" // LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH" parameter LSB_PRIORITY = "HIGH",
// RAM read data output pipeline stages
parameter RAM_PIPELINE = 2
) )
( (
input wire clk, input wire clk,
@ -217,8 +219,8 @@ end
// Shared RAM // Shared RAM
reg [DATA_WIDTH-1:0] mem[(2**RAM_ADDR_WIDTH)-1:0]; reg [DATA_WIDTH-1:0] mem[(2**RAM_ADDR_WIDTH)-1:0];
reg [DATA_WIDTH-1:0] mem_read_data_reg; reg [DATA_WIDTH-1:0] mem_read_data_reg[RAM_PIPELINE-1:0];
reg [M_COUNT-1:0] mem_read_data_valid_reg; reg [M_COUNT-1:0] mem_read_data_valid_reg[RAM_PIPELINE-1:0];
wire [S_COUNT*DATA_WIDTH-1:0] port_ram_wr_data; wire [S_COUNT*DATA_WIDTH-1:0] port_ram_wr_data;
wire [S_COUNT*RAM_ADDR_WIDTH-1:0] port_ram_wr_addr; wire [S_COUNT*RAM_ADDR_WIDTH-1:0] port_ram_wr_addr;
@ -231,8 +233,8 @@ wire [M_COUNT-1:0] port_ram_rd_ack;
wire [M_COUNT*DATA_WIDTH-1:0] port_ram_rd_data; wire [M_COUNT*DATA_WIDTH-1:0] port_ram_rd_data;
wire [M_COUNT-1:0] port_ram_rd_data_valid; wire [M_COUNT-1:0] port_ram_rd_data_valid;
assign port_ram_rd_data = {M_COUNT{mem_read_data_reg}}; assign port_ram_rd_data = {M_COUNT{mem_read_data_reg[RAM_PIPELINE-1]}};
assign port_ram_rd_data_valid = mem_read_data_valid_reg; assign port_ram_rd_data_valid = mem_read_data_valid_reg[RAM_PIPELINE-1];
wire [CL_S_COUNT-1:0] ram_wr_sel; wire [CL_S_COUNT-1:0] ram_wr_sel;
wire ram_wr_en; wire ram_wr_en;
@ -306,16 +308,26 @@ end
endgenerate endgenerate
integer s;
always @(posedge clk) begin always @(posedge clk) begin
mem_read_data_valid_reg <= 0; mem_read_data_valid_reg[0] <= 0;
for (s = RAM_PIPELINE-1; s > 0; s = s - 1) begin
mem_read_data_reg[s] <= mem_read_data_reg[s-1];
mem_read_data_valid_reg[s] <= mem_read_data_valid_reg[s-1];
end
if (ram_rd_en) begin if (ram_rd_en) begin
mem_read_data_reg <= mem[port_ram_rd_addr[ram_rd_sel*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]]; mem_read_data_reg[0] <= mem[port_ram_rd_addr[ram_rd_sel*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]];
mem_read_data_valid_reg <= 1 << ram_rd_sel; mem_read_data_valid_reg[0] <= 1 << ram_rd_sel;
end end
if (rst) begin if (rst) begin
mem_read_data_valid_reg <= 0; mem_read_data_valid_reg[0] <= 0;
for (s = 0; s < RAM_PIPELINE; s = s + 1) begin
mem_read_data_valid_reg[s] <= 0;
end
end end
end end

1
tb/test_axis_ram_switch_1x4_256_64.py
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@ -72,6 +72,7 @@ def bench():
M_CONNECT = [0b1111]*M_COUNT M_CONNECT = [0b1111]*M_COUNT
ARB_TYPE = "ROUND_ROBIN" ARB_TYPE = "ROUND_ROBIN"
LSB_PRIORITY = "HIGH" LSB_PRIORITY = "HIGH"
RAM_PIPELINE = 2
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))

4
tb/test_axis_ram_switch_1x4_256_64.v
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@ -56,6 +56,7 @@ parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}; parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter ARB_TYPE = "ROUND_ROBIN"; parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH"; parameter LSB_PRIORITY = "HIGH";
parameter RAM_PIPELINE = 2;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -142,7 +143,8 @@ axis_ram_switch #(
.M_TOP(M_TOP), .M_TOP(M_TOP),
.M_CONNECT(M_CONNECT), .M_CONNECT(M_CONNECT),
.ARB_TYPE(ARB_TYPE), .ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY) .LSB_PRIORITY(LSB_PRIORITY),
.RAM_PIPELINE(RAM_PIPELINE)
) )
UUT ( UUT (
.clk(clk), .clk(clk),

1
tb/test_axis_ram_switch_4x1_64_256.py
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@ -72,6 +72,7 @@ def bench():
M_CONNECT = [0b1111]*M_COUNT M_CONNECT = [0b1111]*M_COUNT
ARB_TYPE = "ROUND_ROBIN" ARB_TYPE = "ROUND_ROBIN"
LSB_PRIORITY = "HIGH" LSB_PRIORITY = "HIGH"
RAM_PIPELINE = 2
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))

4
tb/test_axis_ram_switch_4x1_64_256.v
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@ -56,6 +56,7 @@ parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}; parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter ARB_TYPE = "ROUND_ROBIN"; parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH"; parameter LSB_PRIORITY = "HIGH";
parameter RAM_PIPELINE = 2;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -142,7 +143,8 @@ axis_ram_switch #(
.M_TOP(M_TOP), .M_TOP(M_TOP),
.M_CONNECT(M_CONNECT), .M_CONNECT(M_CONNECT),
.ARB_TYPE(ARB_TYPE), .ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY) .LSB_PRIORITY(LSB_PRIORITY),
.RAM_PIPELINE(RAM_PIPELINE)
) )
UUT ( UUT (
.clk(clk), .clk(clk),

1
tb/test_axis_ram_switch_4x4_64_64.py
View File

@ -70,6 +70,7 @@ def bench():
M_CONNECT = [0b1111]*M_COUNT M_CONNECT = [0b1111]*M_COUNT
ARB_TYPE = "ROUND_ROBIN" ARB_TYPE = "ROUND_ROBIN"
LSB_PRIORITY = "HIGH" LSB_PRIORITY = "HIGH"
RAM_PIPELINE = 2
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))

4
tb/test_axis_ram_switch_4x4_64_64.v
View File

@ -56,6 +56,7 @@ parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}; parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter ARB_TYPE = "ROUND_ROBIN"; parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH"; parameter LSB_PRIORITY = "HIGH";
parameter RAM_PIPELINE = 2;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -142,7 +143,8 @@ axis_ram_switch #(
.M_TOP(M_TOP), .M_TOP(M_TOP),
.M_CONNECT(M_CONNECT), .M_CONNECT(M_CONNECT),
.ARB_TYPE(ARB_TYPE), .ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY) .LSB_PRIORITY(LSB_PRIORITY),
.RAM_PIPELINE(RAM_PIPELINE)
) )
UUT ( UUT (
.clk(clk), .clk(clk),