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fpga/common/tb: Fix testbench parameters in mqnic_core_axi testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-06-24 00:56:47 -07:00
parent 045b0c1c68
commit a7e4c9e6eb
2 changed files with 4 additions and 2 deletions
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3
fpga/common/tb/mqnic_core_axi/Makefile
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@ -222,7 +222,8 @@ export PARAM_DMA_TAG_WIDTH := 16
export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
export PARAM_RAM_PIPELINE := 2
export PARAM_AXI_DMA_MAX_BURST_LEN := 16
export PARAM_AXI_DMA_USE_ID := 1
export PARAM_AXI_DMA_READ_USE_ID := 0
export PARAM_AXI_DMA_WRITE_USE_ID := 1
export PARAM_AXI_DMA_READ_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_AXI_ID_WIDTH) ))" )
export PARAM_AXI_DMA_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_AXI_ID_WIDTH) ))" )

3
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -737,7 +737,8 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
parameters['RAM_PIPELINE'] = 2
parameters['AXI_DMA_MAX_BURST_LEN'] = 16
parameters['AXI_DMA_USE_ID'] = 1
parameters['AXI_DMA_READ_USE_ID'] = 0
parameters['AXI_DMA_WRITE_USE_ID'] = 1
parameters['AXI_DMA_READ_OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']
parameters['AXI_DMA_WRITE_OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']