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Change block parameter

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This commit is contained in:
Alex Forencich 2014-11-13 02:01:07 -08:00
parent a1633f27d8
commit a8970e6e75
5 changed files with 26 additions and 6 deletions
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10
rtl/arbiter.v
View File

@ -34,7 +34,7 @@ module arbiter #
parameter PORTS = 4,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter TYPE = "PRIORITY",
// block until request deassert: "TRUE" or "FALSE"
// block type: "NONE", "REQUEST", "ACKNOWLEDGE"
parameter BLOCK = "TRUE"
)
(
@ -42,6 +42,7 @@ module arbiter #
input wire rst,
input wire [PORTS-1:0] request,
input wire [PORTS-1:0] acknowledge,
output wire [PORTS-1:0] grant,
output wire grant_valid,
@ -92,11 +93,16 @@ always @* begin
grant_encoded_next = 0;
mask_next = mask_reg;
if (BLOCK == "TRUE" && grant_reg & request) begin
if (BLOCK == "REQUEST" && grant_reg & request) begin
// granted request still asserted; hold it
grant_valid_next = grant_valid_reg;
grant_next = grant_reg;
grant_encoded_next = grant_encoded_reg;
end else if (BLOCK == "ACKNOWLEDGE" && grant_valid && !(grant_reg & acknowledge)) begin
// granted request not yet acknowledged; hold it
grant_valid_next = grant_valid_reg;
grant_next = grant_reg;
grant_encoded_next = grant_encoded_reg;
end else if (request_valid) begin
if (TYPE == "PRIORITY") begin
grant_valid_next = 1;

4
tb/test_arbiter.py
View File

@ -43,6 +43,7 @@ def dut_arbiter(clk,
current_test,
request,
acknowledge,
grant,
grant_valid,
@ -56,6 +57,7 @@ def dut_arbiter(clk,
current_test=current_test,
request=request,
acknowledge=acknowledge,
grant=grant,
grant_valid=grant_valid,
@ -69,6 +71,7 @@ def bench():
current_test = Signal(intbv(0)[8:])
request = Signal(intbv(0)[32:])
acknowledge = Signal(intbv(0)[32:])
# Outputs
grant = Signal(intbv(0)[32:])
@ -81,6 +84,7 @@ def bench():
current_test,
request,
acknowledge,
grant,
grant_valid,

7
tb/test_arbiter.v
View File

@ -31,7 +31,7 @@ module test_arbiter;
// parameters
localparam PORTS = 32;
localparam TYPE = "PRIORITY";
localparam BLOCK = "TRUE";
localparam BLOCK = "REQUEST";
// Inputs
reg clk = 0;
@ -39,6 +39,7 @@ reg rst = 0;
reg [7:0] current_test = 0;
reg [PORTS-1:0] request = 0;
reg [PORTS-1:0] acknowledge = 0;
// Outputs
wire [PORTS-1:0] grant;
@ -50,7 +51,8 @@ initial begin
$from_myhdl(clk,
rst,
current_test,
request);
request,
acknowledge);
$to_myhdl(grant,
grant_valid,
grant_encoded);
@ -69,6 +71,7 @@ UUT (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)

4
tb/test_arbiter_rr.py
View File

@ -43,6 +43,7 @@ def dut_arbiter_rr(clk,
current_test,
request,
acknowledge,
grant,
grant_valid,
@ -56,6 +57,7 @@ def dut_arbiter_rr(clk,
current_test=current_test,
request=request,
acknowledge=acknowledge,
grant=grant,
grant_valid=grant_valid,
@ -69,6 +71,7 @@ def bench():
current_test = Signal(intbv(0)[8:])
request = Signal(intbv(0)[32:])
acknowledge = Signal(intbv(0)[32:])
# Outputs
grant = Signal(intbv(0)[32:])
@ -81,6 +84,7 @@ def bench():
current_test,
request,
acknowledge,
grant,
grant_valid,

7
tb/test_arbiter_rr.v
View File

@ -31,7 +31,7 @@ module test_arbiter_rr;
// parameters
localparam PORTS = 32;
localparam TYPE = "ROUND_ROBIN";
localparam BLOCK = "TRUE";
localparam BLOCK = "REQUEST";
// Inputs
reg clk = 0;
@ -39,6 +39,7 @@ reg rst = 0;
reg [7:0] current_test = 0;
reg [PORTS-1:0] request = 0;
reg [PORTS-1:0] acknowledge = 0;
// Outputs
wire [PORTS-1:0] grant;
@ -50,7 +51,8 @@ initial begin
$from_myhdl(clk,
rst,
current_test,
request);
request,
acknowledge);
$to_myhdl(grant,
grant_valid,
grant_encoded);
@ -69,6 +71,7 @@ UUT (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)