FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

Reorder includes

Browse Source
This commit is contained in:
Alex Forencich 2014-11-20 23:51:24 -08:00
parent 2ae3581144
commit a8bb020839
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tb/test_ip.py
View File

@ -35,9 +35,9 @@ module = 'ip'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("../rtl/ip_eth_rx.v")
srcs.append("../rtl/ip_eth_tx.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)

2
tb/test_ip_64.py
View File

@ -35,9 +35,9 @@ module = 'ip_64'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("../rtl/ip_eth_rx_64.v")
srcs.append("../rtl/ip_eth_tx_64.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)