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fpga/common: Fix GT wrapper timing constraints when DRP interface is tied off

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-07-17 18:43:07 -07:00
parent ed4a26e2cb
commit a99815800b
2 changed files with 12 additions and 4 deletions
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8
fpga/common/syn/vivado/cmac_gty_ch_wrapper.tcl
View File

@ -42,8 +42,12 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == cmac_gty_ch_wrapper ||
constrain_sync_chain $inst "gt_txprbsforceerr_drp_reg_reg" "gt_txprbsforceerr_sync_1_reg_reg" "gt_txprbsforceerr_sync_2_reg_reg"
constrain_sync_chain $inst "gt_txpolarity_drp_reg_reg" "gt_txpolarity_sync_reg_reg"
constrain_sync_chain $inst "gt_txinhibit_drp_reg_reg" "gt_txinhibit_sync_reg_reg"
set_false_path -from [get_cells "$inst/gt_tx_pd_reg_reg"]
set_false_path -from [get_cells "$inst/gt_txelecidle_reg_reg"]
set driver_ffs [get_cells -hier "gt_tx_pd_reg_reg gt_txelecidle_reg_reg" -filter "PARENT == $inst"]
if {[llength $driver_ffs]} {
set_false_path -from $driver_ffs
}
# RX
constrain_sync_chain $inst "gt_rxpolarity_drp_reg_reg" "gt_rxpolarity_sync_reg_reg"

8
fpga/common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
View File

@ -39,8 +39,12 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_xcvr_phy_10g_gty_wr
constrain_sync_chain $inst "gt_txprbsforceerr_drp_reg_reg" "gt_txprbsforceerr_sync_1_reg_reg" "gt_txprbsforceerr_sync_2_reg_reg"
constrain_sync_chain $inst "gt_txpolarity_drp_reg_reg" "gt_txpolarity_sync_reg_reg"
constrain_sync_chain $inst "gt_txinhibit_drp_reg_reg" "gt_txinhibit_sync_reg_reg"
set_false_path -from [get_cells $inst/gt_tx_pd_reg_reg]
set_false_path -from [get_cells $inst/gt_txelecidle_reg_reg]
set driver_ffs [get_cells -hier "gt_tx_pd_reg_reg gt_txelecidle_reg_reg" -filter "PARENT == $inst"]
if {[llength $driver_ffs]} {
set_false_path -from $driver_ffs
}
# RX
constrain_sync_chain $inst "gt_rxpolarity_drp_reg_reg" "gt_rxpolarity_sync_reg_reg"