diff --git a/fpga/lib/eth/README.md b/fpga/lib/eth/README.md index 612296390..9e7a73fe1 100644 --- a/fpga/lib/eth/README.md +++ b/fpga/lib/eth/README.md @@ -11,8 +11,9 @@ processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA -module. Also includes full MyHDL testbench with intelligent bus cosimulation -endpoints. +module. Includes various PTP related components for implementing systems that +require precise time synchronization. Also includes full MyHDL testbench with +intelligent bus cosimulation endpoints. For IP and ARP support only, use ip_complete (1G) or ip_complete_64 (10G/25G). @@ -24,6 +25,11 @@ interfaces and with/without FIFOs. Top level 10G/25G PCS/PMA PHY module is eth_phy_10g. Top level 10G/25G MAC/PCS/PMA combination module is eth_mac_phy_10g. +PTP components include a configurable PTP clock (ptp_clock), a PTP clock CDC +module (ptp_clock_cdc) for transferring PTP time across clock domains, and a +configurable PTP period output module for precisely generating arbitrary +frequencies from PTP time. + ## Documentation ### arp module @@ -280,6 +286,22 @@ PTP clock module with PPS output. Generates both 64 bit and 96 bit timestamp formats. Fine frequeny adjustment supported with configurable fractional nanoseconds field. +### ptp_clock_cdc module + +PTP clock CDC module with PPS output. Use this module to transfer and deskew a +free-running PTP clock across clock domains. Currently supports 96 bit +timestamps. + +### ptp_ts_extract module + +PTP timestamp extract module. Use this module to extract a PTP timestamp +embedded in the tuser sideband signal of an AXI stream interface. + +### ptp_perout module + +PTP period output module. Generates a pulse output, configurable in absolute +start time, period, and width, based on PTP time from a PTP clock. + ### rgmii_phy_if module RGMII PHY interface and clocking logic. @@ -433,6 +455,9 @@ and data lines. rtl/mii_phy_if.v : MII PHY interface rtl/oddr.v : Generic DDR output register rtl/ptp_clock.v : PTP clock + rtl/ptp_clock_cdc.v : PTP clock CDC + rtl/ptp_ts_extract.v : PTP timestamp extract + rtl/ptp_perout.v : PTP period out rtl/rgmii_phy_if.v : RGMII PHY interface rtl/ssio_ddr_in.v : Generic source synchronous IO DDR input module rtl/ssio_ddr_in_diff.v : Generic source synchronous IO DDR differential input module diff --git a/fpga/lib/eth/rtl/ptp_clock_cdc.v b/fpga/lib/eth/rtl/ptp_clock_cdc.v new file mode 100644 index 000000000..baac193a4 --- /dev/null +++ b/fpga/lib/eth/rtl/ptp_clock_cdc.v @@ -0,0 +1,424 @@ +/* + +Copyright (c) 2019 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * PTP clock CDC (clock domain crossing) module + */ +module ptp_clock_cdc # +( + parameter TS_WIDTH = 96, + parameter NS_WIDTH = 4, + parameter FNS_WIDTH = 16, + parameter INPUT_PERIOD_NS = 4'h6, + parameter INPUT_PERIOD_FNS = 16'h6666, + parameter OUTPUT_PERIOD_NS = 4'h6, + parameter OUTPUT_PERIOD_FNS = 16'h6666, + parameter USE_SAMPLE_CLOCK = 1, + parameter LOG_FIFO_DEPTH = 3, + parameter LOG_RATE = 3 +) +( + input wire input_clk, + input wire input_rst, + input wire output_clk, + input wire output_rst, + input wire sample_clk, + + /* + * Timestamp inputs from source PTP clock + */ + input wire [TS_WIDTH-1:0] input_ts, + + /* + * Timestamp outputs + */ + output wire [TS_WIDTH-1:0] output_ts, + output wire output_ts_step, + + /* + * PPS output + */ + output wire output_pps +); + +// bus width assertions +initial begin + if (TS_WIDTH != 96) begin + $error("Error: Timestamp width must be 96"); + $finish; + end +end + +parameter TS_NS_WIDTH = TS_WIDTH == 96 ? 30 : 48; + +parameter FIFO_ADDR_WIDTH = LOG_FIFO_DEPTH+1; +parameter LOG_AVG = 6; +parameter LOG_AVG_SCALE = LOG_AVG+8; +parameter LOG_AVG_SYNC_RATE = LOG_RATE; +parameter WR_PERIOD = ((((INPUT_PERIOD_NS << 16) + INPUT_PERIOD_FNS) + 64'd0) << 16) / ((OUTPUT_PERIOD_NS << 16) + OUTPUT_PERIOD_FNS) / 2**(LOG_RATE+1); + +reg [NS_WIDTH-1:0] period_ns_reg = OUTPUT_PERIOD_NS; +reg [FNS_WIDTH-1:0] period_fns_reg = OUTPUT_PERIOD_FNS; + +reg [47:0] ts_s_reg = 0; +reg [TS_NS_WIDTH-1:0] ts_ns_reg = 0; +reg [FNS_WIDTH-1:0] ts_fns_reg = 0; +reg [TS_NS_WIDTH-1:0] ts_ns_inc_reg = 0; +reg [FNS_WIDTH-1:0] ts_fns_inc_reg = 0; +reg [TS_NS_WIDTH+1-1:0] ts_ns_ovf_reg = {TS_NS_WIDTH{1'b1}}; +reg [FNS_WIDTH-1:0] ts_fns_ovf_reg = {FNS_WIDTH{1'b1}}; + +reg ts_step_reg = 1'b0; + +reg pps_reg = 0; + +reg [FIFO_ADDR_WIDTH:0] wr_ptr_reg = {FIFO_ADDR_WIDTH+1{1'b0}}, wr_ptr_next; +reg [FIFO_ADDR_WIDTH:0] wr_ptr_gray_reg = {FIFO_ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next; +reg [FIFO_ADDR_WIDTH:0] rd_ptr_reg = {FIFO_ADDR_WIDTH+1{1'b0}}, rd_ptr_next; +reg [FIFO_ADDR_WIDTH:0] rd_ptr_gray_reg = {FIFO_ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next; + +reg [FIFO_ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {FIFO_ADDR_WIDTH+1{1'b0}}; +reg [FIFO_ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {FIFO_ADDR_WIDTH+1{1'b0}}; +wire [FIFO_ADDR_WIDTH:0] wr_ptr_sync2; +reg [FIFO_ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {FIFO_ADDR_WIDTH+1{1'b0}}; +reg [FIFO_ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {FIFO_ADDR_WIDTH+1{1'b0}}; +wire [FIFO_ADDR_WIDTH:0] rd_ptr_sync2; + +reg [FIFO_ADDR_WIDTH:0] wr_ptr_gray_sample_sync1_reg = {FIFO_ADDR_WIDTH+1{1'b0}}; +reg [FIFO_ADDR_WIDTH:0] wr_ptr_gray_sample_sync2_reg = {FIFO_ADDR_WIDTH+1{1'b0}}; +wire [FIFO_ADDR_WIDTH:0] wr_ptr_sample_sync2; +reg [FIFO_ADDR_WIDTH:0] rd_ptr_gray_sample_sync1_reg = {FIFO_ADDR_WIDTH+1{1'b0}}; +reg [FIFO_ADDR_WIDTH:0] rd_ptr_gray_sample_sync2_reg = {FIFO_ADDR_WIDTH+1{1'b0}}; +wire [FIFO_ADDR_WIDTH:0] rd_ptr_sample_sync2; + +reg [15:0] wr_acc_reg = 16'd0, wr_acc_next; +reg [15:0] wr_inc_reg = WR_PERIOD, wr_inc_next; +reg [31:0] err_int_reg = 0, err_int_next; + +reg [LOG_RATE-1:0] rd_cnt_reg = {LOG_RATE{1'b0}}, rd_cnt_next; + +reg [LOG_FIFO_DEPTH+LOG_AVG_SCALE+2-1:0] sample_acc_reg = 0; +reg [LOG_FIFO_DEPTH+LOG_AVG_SCALE+2-1:0] sample_avg_reg = 0; +reg [LOG_AVG_SYNC_RATE-1:0] sample_cnt_reg = 0; +reg sample_update_reg = 1'b0; +reg sample_update_sync1_reg = 1'b0; +reg sample_update_sync2_reg = 1'b0; +reg sample_update_sync3_reg = 1'b0; + +reg [TS_WIDTH-1:0] mem[(2**FIFO_ADDR_WIDTH)-1:0]; +reg [TS_WIDTH-1:0] mem_read_data_reg = 0; + +// full when first TWO MSBs do NOT match, but rest matches +// (gray code equivalent of first MSB different but rest same) +wire full = ((wr_ptr_gray_reg[FIFO_ADDR_WIDTH] != rd_ptr_gray_sync2_reg[FIFO_ADDR_WIDTH]) && + (wr_ptr_gray_reg[FIFO_ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[FIFO_ADDR_WIDTH-1]) && + (wr_ptr_gray_reg[FIFO_ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[FIFO_ADDR_WIDTH-2:0])); +// empty when pointers match exactly +wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg; + +wire [FIFO_ADDR_WIDTH:0] wr_depth = wr_ptr_reg - rd_ptr_sync2; +wire [FIFO_ADDR_WIDTH:0] rd_depth = wr_ptr_sync2 - rd_ptr_reg; +wire [FIFO_ADDR_WIDTH:0] sample_depth = wr_ptr_sample_sync2 - rd_ptr_sample_sync2; + +// control signals +reg write; +reg read; + +generate + +if (TS_WIDTH == 96) begin + assign output_ts[95:48] = ts_s_reg; + assign output_ts[47:46] = 2'b00; + assign output_ts[45:16] = ts_ns_reg; + assign output_ts[15:0] = FNS_WIDTH > 16 ? ts_fns_reg >> (FNS_WIDTH-16) : ts_fns_reg << (16-FNS_WIDTH); +end else if (TS_WIDTH == 64) begin + assign output_ts[63:16] = ts_ns_reg; + assign output_ts[15:0] = FNS_WIDTH > 16 ? ts_fns_reg >> (FNS_WIDTH-16) : ts_fns_reg << (16-FNS_WIDTH); +end + +endgenerate + +assign output_ts_step = ts_step_reg; + +assign output_pps = pps_reg; + +generate + + genvar n; + + for (n = 0; n < FIFO_ADDR_WIDTH+1; n = n + 1) begin + assign wr_ptr_sync2[n] = ^wr_ptr_gray_sync2_reg[FIFO_ADDR_WIDTH+1-1:n]; + assign rd_ptr_sync2[n] = ^rd_ptr_gray_sync2_reg[FIFO_ADDR_WIDTH+1-1:n]; + assign wr_ptr_sample_sync2[n] = ^wr_ptr_gray_sample_sync2_reg[FIFO_ADDR_WIDTH+1-1:n]; + assign rd_ptr_sample_sync2[n] = ^rd_ptr_gray_sample_sync2_reg[FIFO_ADDR_WIDTH+1-1:n]; + end + +endgenerate + +// pointer sync +always @(posedge input_clk) begin + rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg; + rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg; +end + +always @(posedge output_clk) begin + wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg; + wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg; +end + +always @(posedge sample_clk) begin + rd_ptr_gray_sample_sync1_reg <= rd_ptr_gray_reg; + rd_ptr_gray_sample_sync2_reg <= rd_ptr_gray_sample_sync1_reg; + wr_ptr_gray_sample_sync1_reg <= wr_ptr_gray_reg; + wr_ptr_gray_sample_sync2_reg <= wr_ptr_gray_sample_sync1_reg; +end + +always @(posedge sample_clk) begin + if (USE_SAMPLE_CLOCK) begin + sample_acc_reg <= sample_acc_reg + ((sample_depth * 2**LOG_AVG_SCALE - sample_acc_reg) >> LOG_AVG); + sample_cnt_reg <= sample_cnt_reg + 1; + + if (sample_cnt_reg == 0) begin + sample_update_reg <= !sample_update_reg; + sample_avg_reg <= sample_acc_reg; + end + end +end + +always @(posedge input_clk) begin + sample_update_sync1_reg <= sample_update_reg; + sample_update_sync2_reg <= sample_update_sync1_reg; + sample_update_sync3_reg <= sample_update_sync2_reg; +end + +reg [LOG_FIFO_DEPTH+LOG_AVG_SCALE+2-1:0] sample_avg_sync_reg = 0; +reg sample_avg_sync_valid_reg = 0; + +always @(posedge input_clk) begin + if (USE_SAMPLE_CLOCK) begin + sample_avg_sync_valid_reg <= 1'b0; + if (sample_update_sync2_reg ^ sample_update_sync3_reg) begin + sample_avg_sync_reg <= sample_avg_reg; + sample_avg_sync_valid_reg <= 1'b1; + end + end else begin + sample_acc_reg <= sample_acc_reg + ((wr_depth * 2**LOG_AVG_SCALE - sample_acc_reg) >> LOG_AVG); + sample_cnt_reg <= sample_cnt_reg + 1; + + sample_avg_sync_valid_reg <= 1'b0; + if (sample_cnt_reg == 0) begin + sample_avg_sync_reg <= sample_acc_reg; + sample_avg_sync_valid_reg <= 1'b1; + end + end +end + +always @* begin + write = 1'b0; + + wr_ptr_next = wr_ptr_reg; + wr_ptr_gray_next = wr_ptr_gray_reg; + + wr_acc_next = wr_acc_reg + wr_inc_reg; + wr_inc_next = wr_inc_reg; + + err_int_next = err_int_reg; + + if (sample_avg_sync_valid_reg) begin + // updated sampled FIFO depth + err_int_next = err_int_reg + (sample_avg_sync_reg - (2**LOG_FIFO_DEPTH * 2**LOG_AVG_SCALE)); + wr_inc_next = WR_PERIOD + (((2**LOG_FIFO_DEPTH * 2**LOG_AVG_SCALE) - sample_avg_sync_reg) >> 8) - ($signed(err_int_reg) >> 13); + if ($signed(wr_inc_next) > $signed(WR_PERIOD*4)) begin + wr_inc_next = WR_PERIOD*4; + end else if ($signed(wr_inc_next) < $signed(WR_PERIOD/4)) begin + wr_inc_next = WR_PERIOD/4; + end + end + + if (!full && wr_acc_reg[15] != wr_acc_next[15]) begin + write = 1'b1; + wr_ptr_next = wr_ptr_reg + 1; + wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1); + end +end + +always @(posedge input_clk) begin + wr_ptr_reg <= wr_ptr_next; + wr_ptr_gray_reg <= wr_ptr_gray_next; + + wr_acc_reg <= wr_acc_next; + wr_inc_reg <= wr_inc_next; + + err_int_reg <= err_int_next; + + if (write) begin + mem[wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= input_ts; + end + + if (input_rst) begin + wr_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}}; + wr_ptr_gray_reg <= {FIFO_ADDR_WIDTH+1{1'b0}}; + wr_acc_reg <= 16'd0; + wr_inc_reg <= WR_PERIOD; + + err_int_reg <= 0; + end +end + +always @* begin + read = 1'b0; + + rd_ptr_next = rd_ptr_reg; + rd_ptr_gray_next = rd_ptr_gray_reg; + + rd_cnt_next = rd_cnt_reg + 1; + + if (!empty && rd_cnt_reg == 0) begin + read = 1'b1; + rd_ptr_next = rd_ptr_reg + 1; + rd_ptr_gray_next = rd_ptr_next ^ (rd_ptr_next >> 1); + end +end + +always @(posedge output_clk) begin + rd_ptr_reg <= rd_ptr_next; + rd_ptr_gray_reg <= rd_ptr_gray_next; + + rd_cnt_reg <= rd_cnt_next; + + if (!empty) begin + mem_read_data_reg <= mem[rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]]; + end + + if (read) begin + + end + + if (output_rst) begin + rd_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}}; + rd_ptr_gray_reg <= {FIFO_ADDR_WIDTH+1{1'b0}}; + rd_cnt_reg <= {LOG_RATE{1'b0}}; + end +end + +reg sec_mismatch_reg = 1'b0; +reg diff_valid_reg = 1'b0; +reg diff_offset_valid_reg = 1'b0; + +reg [30:0] ts_ns_diff_reg = 31'd0; +reg [FNS_WIDTH-1:0] ts_fns_diff_reg = 16'd0; + +reg [48:0] time_err_int_reg = 32'd0; + +always @(posedge output_clk) begin + ts_step_reg <= 0; + + diff_valid_reg <= 1'b0; + diff_offset_valid_reg <= 1'b0; + + // 96 bit timestamp + if (!ts_ns_ovf_reg[30]) begin + // if the overflow lookahead did not borrow, one second has elapsed + // increment seconds field, pre-compute both normal increment and overflow values + {ts_ns_inc_reg, ts_fns_inc_reg} <= {ts_ns_ovf_reg, ts_fns_ovf_reg} + {period_ns_reg, period_fns_reg}; + {ts_ns_ovf_reg, ts_fns_ovf_reg} <= {ts_ns_ovf_reg, ts_fns_ovf_reg} + {period_ns_reg, period_fns_reg} - {31'd1_000_000_000, {FNS_WIDTH{1'b0}}}; + {ts_ns_reg, ts_fns_reg} <= {ts_ns_ovf_reg, ts_fns_ovf_reg}; + ts_s_reg <= ts_s_reg + 1; + end else begin + // no increment seconds field, pre-compute both normal increment and overflow values + {ts_ns_inc_reg, ts_fns_inc_reg} <= {ts_ns_inc_reg, ts_fns_inc_reg} + {period_ns_reg, period_fns_reg}; + {ts_ns_ovf_reg, ts_fns_ovf_reg} <= {ts_ns_inc_reg, ts_fns_inc_reg} + {period_ns_reg, period_fns_reg} - {31'd1_000_000_000, {FNS_WIDTH{1'b0}}}; + {ts_ns_reg, ts_fns_reg} <= {ts_ns_inc_reg, ts_fns_inc_reg}; + ts_s_reg <= ts_s_reg; + end + + // FIFO dequeue + if (read) begin + // dequeue from FIFO + if (mem_read_data_reg[95:48] != ts_s_reg) begin + // seconds field doesn't match + if (!sec_mismatch_reg) begin + // ignore the first time + sec_mismatch_reg <= 1'b1; + end else begin + // two seconds mismatches in a row; step the clock + sec_mismatch_reg <= 1'b0; + + {ts_ns_inc_reg, ts_fns_inc_reg} <= (FNS_WIDTH > 16 ? mem_read_data_reg[45:0] << (FNS_WIDTH-16) : mem_read_data_reg[45:0] >> (16-FNS_WIDTH)) + {period_ns_reg, period_fns_reg}; + {ts_ns_ovf_reg, ts_fns_ovf_reg} <= (FNS_WIDTH > 16 ? mem_read_data_reg[45:0] << (FNS_WIDTH-16) : mem_read_data_reg[45:0] >> (16-FNS_WIDTH)) + {period_ns_reg, period_fns_reg} - {31'd1_000_000_000, {FNS_WIDTH{1'b0}}}; + ts_s_reg <= mem_read_data_reg[95:48]; + ts_ns_reg <= mem_read_data_reg[45:16]; + ts_fns_reg <= FNS_WIDTH > 16 ? mem_read_data_reg[15:0] << (FNS_WIDTH-16) : mem_read_data_reg[15:0] >> (16-FNS_WIDTH); + ts_step_reg <= 1; + end + end else begin + // compute difference + sec_mismatch_reg <= 1'b0; + diff_valid_reg <= 1'b1; + {ts_ns_diff_reg, ts_fns_diff_reg} <= {ts_ns_reg, ts_fns_reg} - (FNS_WIDTH > 16 ? mem_read_data_reg[45:0] << (FNS_WIDTH-16) : mem_read_data_reg[45:0] >> (16-FNS_WIDTH)); + end + end else if (diff_valid_reg) begin + // offset difference by FIFO delay + diff_offset_valid_reg <= 1'b1; + diff_valid_reg <= 1'b0; + {ts_ns_diff_reg, ts_fns_diff_reg} <= {ts_ns_diff_reg, ts_fns_diff_reg} - ({period_ns_reg, period_fns_reg} * 2**(LOG_RATE + LOG_FIFO_DEPTH)); + end else if (diff_offset_valid_reg) begin + // PI control + diff_offset_valid_reg <= 1'b0; + if (($signed({ts_ns_diff_reg, ts_fns_diff_reg}) / 2**10) + ($signed(time_err_int_reg) / 2**16) > 4*2**16) begin + // limit positive adjustment + time_err_int_reg <= 0; + {period_ns_reg, period_fns_reg} <= $signed(OUTPUT_PERIOD_NS*2**16 + OUTPUT_PERIOD_FNS) - ({4'd4, {FNS_WIDTH{1'b0}}}); + end else if (($signed({ts_ns_diff_reg, ts_fns_diff_reg}) / 2**10) + ($signed(time_err_int_reg) / 2**16) < -8*2**16) begin + // limit negative adjustment + time_err_int_reg <= 0; + {period_ns_reg, period_fns_reg} <= $signed(OUTPUT_PERIOD_NS*2**16 + OUTPUT_PERIOD_FNS) + ({4'd8, {FNS_WIDTH{1'b0}}}); + end else begin + time_err_int_reg <= $signed(time_err_int_reg) + $signed({ts_ns_diff_reg, ts_fns_diff_reg}); + {period_ns_reg, period_fns_reg} <= $signed(OUTPUT_PERIOD_NS*2**16 + OUTPUT_PERIOD_FNS) - ($signed({ts_ns_diff_reg, ts_fns_diff_reg}) / 2**10) - ($signed(time_err_int_reg) / 2**16); + end + end + + pps_reg <= !ts_ns_ovf_reg[30]; + + if (output_rst) begin + period_ns_reg <= OUTPUT_PERIOD_NS; + period_fns_reg <= OUTPUT_PERIOD_FNS; + ts_s_reg <= 0; + ts_ns_reg <= 0; + ts_fns_reg <= 0; + ts_ns_inc_reg <= 0; + ts_fns_inc_reg <= 0; + ts_ns_ovf_reg <= 31'h7fffffff; + ts_fns_ovf_reg <= {FNS_WIDTH{1'b1}}; + ts_step_reg <= 0; + pps_reg <= 0; + end +end + +endmodule diff --git a/fpga/lib/eth/rtl/ptp_ts_extract.v b/fpga/lib/eth/rtl/ptp_ts_extract.v new file mode 100644 index 000000000..28ed50462 --- /dev/null +++ b/fpga/lib/eth/rtl/ptp_ts_extract.v @@ -0,0 +1,72 @@ +/* + +Copyright (c) 2019 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * PTP timestamp extract module + */ +module ptp_ts_extract # +( + parameter TS_WIDTH = 96, + parameter TS_OFFSET = 1, + parameter USER_WIDTH = TS_WIDTH+TS_OFFSET +) +( + input wire clk, + input wire rst, + + /* + * AXI stream input + */ + input wire s_axis_tvalid, + input wire s_axis_tready, + input wire s_axis_tlast, + input wire [USER_WIDTH-1:0] s_axis_tuser, + + /* + * Timestamp output + */ + output wire [TS_WIDTH-1:0] m_axis_ts, + output wire m_axis_ts_valid +); + +reg frame_reg = 1'b0; + +assign m_axis_ts = s_axis_tuser >> TS_OFFSET; +assign m_axis_ts_valid = s_axis_tvalid && s_axis_tready && !frame_reg; + +always @(posedge clk) begin + if (s_axis_tvalid && s_axis_tready) begin + frame_reg <= !s_axis_tlast; + end + + if (rst) begin + frame_reg <= 1'b0; + end +end + +endmodule diff --git a/fpga/lib/eth/syn/ptp_clock_cdc.tcl b/fpga/lib/eth/syn/ptp_clock_cdc.tcl new file mode 100644 index 000000000..408b6eb45 --- /dev/null +++ b/fpga/lib/eth/syn/ptp_clock_cdc.tcl @@ -0,0 +1,87 @@ +# Copyright (c) 2019 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# PTP timestamp capture module + +foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == ptp_clock_cdc || REF_NAME == ptp_clock_cdc)}] { + puts "Inserting timing constraints for ptp_clock_cdc instance $inst" + + # get clock periods + set input_clk [get_clocks -of_objects [get_pins $inst/wr_ptr_reg_reg[0]/C]] + set output_clk [get_clocks -of_objects [get_pins $inst/rd_ptr_reg_reg[0]/C]] + + set input_clk_period [get_property -min PERIOD $input_clk] + set output_clk_period [get_property -min PERIOD $output_clk] + + # pointer synchronization + set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/(wr|rd)_ptr_gray_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"] + + set_max_delay -from [get_cells "$inst/rd_ptr_reg_reg[*] $inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells $inst/rd_ptr_gray_sync1_reg_reg[*]] -datapath_only $output_clk_period + set_bus_skew -from [get_cells "$inst/rd_ptr_reg_reg[*] $inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells $inst/rd_ptr_gray_sync1_reg_reg[*]] $input_clk_period + set_max_delay -from [get_cells "$inst/wr_ptr_reg_reg[*] $inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells $inst/wr_ptr_gray_sync1_reg_reg[*]] -datapath_only $input_clk_period + set_bus_skew -from [get_cells "$inst/wr_ptr_reg_reg[*] $inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells $inst/wr_ptr_gray_sync1_reg_reg[*]] $output_clk_period + + # output register (needed for distributed RAM sync write/async read) + set output_reg_ffs [get_cells -quiet "$inst/mem_read_data_reg_reg[*]"] + + if {[llength $output_reg_ffs]} { + set_false_path -from $input_clk -to $output_reg_ffs + } + + # pointer synchronization (depth measurement) + set sync_ffs [get_cells -quiet -hier -regexp ".*/rd_ptr_gray_sample_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set src_clk [get_clocks -of_objects [get_pins $inst/rd_ptr_gray_reg_reg[0]/C]] + set dest_clk [get_clocks -of_objects [get_pins $inst/rd_ptr_gray_sample_sync1_reg_reg[0]/C]] + + set_max_delay -from [get_cells "$inst/rd_ptr_reg_reg[*] $inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells $inst/rd_ptr_gray_sample_sync1_reg_reg[*]] -datapath_only [get_property -min PERIOD $src_clk] + set_bus_skew -from [get_cells "$inst/rd_ptr_reg_reg[*] $inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells $inst/rd_ptr_gray_sample_sync1_reg_reg[*]] [get_property -min PERIOD $dest_clk] + } + + set sync_ffs [get_cells -quiet -hier -regexp ".*/wr_ptr_gray_sample_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set src_clk [get_clocks -of_objects [get_pins $inst/wr_ptr_gray_reg_reg[0]/C]] + set dest_clk [get_clocks -of_objects [get_pins $inst/wr_ptr_gray_sample_sync1_reg_reg[0]/C]] + + set_max_delay -from [get_cells "$inst/wr_ptr_reg_reg[*] $inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells $inst/wr_ptr_gray_sample_sync1_reg_reg[*]] -datapath_only [get_property -min PERIOD $src_clk] + set_bus_skew -from [get_cells "$inst/wr_ptr_reg_reg[*] $inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells $inst/wr_ptr_gray_sample_sync1_reg_reg[*]] [get_property -min PERIOD $dest_clk] + } + + # sample update sync + set sync_ffs [get_cells -quiet -hier -regexp ".*/sample_update_sync\[123\]_reg_reg" -filter "PARENT == $inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set src_clk [get_clocks -of_objects [get_pins $inst/sample_update_reg_reg/C]] + set dest_clk [get_clocks -of_objects [get_pins $inst/sample_update_sync1_reg_reg/C]] + + set_max_delay -from [get_cells $inst/sample_update_reg_reg] -to [get_cells $inst/sample_update_sync1_reg_reg] -datapath_only [get_property -min PERIOD $src_clk] + + set_max_delay -from [get_cells "$inst/sample_avg_reg_reg[*]"] -to [get_cells $inst/sample_avg_sync_reg_reg[*]] -datapath_only [get_property -min PERIOD $src_clk] + set_bus_skew -from [get_cells "$inst/sample_avg_reg_reg[*]"] -to [get_cells $inst/sample_avg_sync_reg_reg[*]] [get_property -min PERIOD $dest_clk] + } +} diff --git a/fpga/lib/eth/tb/test_ptp_clock_cdc_96.py b/fpga/lib/eth/tb/test_ptp_clock_cdc_96.py new file mode 100755 index 000000000..e87d87ade --- /dev/null +++ b/fpga/lib/eth/tb/test_ptp_clock_cdc_96.py @@ -0,0 +1,246 @@ +#!/usr/bin/env python +""" + +Copyright (c) 2019 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +from myhdl import * +import os + +import ptp + +module = 'ptp_clock_cdc' +testbench = 'test_%s_96' % module + +srcs = [] + +srcs.append("../rtl/%s.v" % module) +srcs.append("%s.v" % testbench) + +src = ' '.join(srcs) + +build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) + +def bench(): + + # Parameters + TS_WIDTH = 96 + NS_WIDTH = 4 + FNS_WIDTH = 16 + INPUT_PERIOD_NS = 0x6 + INPUT_PERIOD_FNS = 0x6666 + OUTPUT_PERIOD_NS = 0x6 + OUTPUT_PERIOD_FNS = 0x6666 + USE_SAMPLE_CLOCK = 1 + LOG_FIFO_DEPTH = 3 + LOG_RATE = 3 + + # Inputs + clk = Signal(bool(0)) + rst = Signal(bool(0)) + current_test = Signal(intbv(0)[8:]) + + input_clk = Signal(bool(0)) + input_rst = Signal(bool(0)) + output_clk = Signal(bool(0)) + output_rst = Signal(bool(0)) + sample_clk = Signal(bool(0)) + input_ts = Signal(intbv(0)[96:]) + + # Outputs + output_ts = Signal(intbv(0)[96:]) + output_ts_step = Signal(bool(0)) + output_pps = Signal(bool(0)) + + # PTP clock + ptp_clock = ptp.PtpClock() + + ptp_logic = ptp_clock.create_logic( + input_clk, + input_rst, + ts_96=input_ts + ) + + # DUT + if os.system(build_cmd): + raise Exception("Error running build command") + + dut = Cosimulation( + "vvp -m myhdl %s.vvp -lxt2" % testbench, + clk=clk, + rst=rst, + current_test=current_test, + input_clk=input_clk, + input_rst=input_rst, + output_clk=output_clk, + output_rst=output_rst, + sample_clk=sample_clk, + input_ts=input_ts, + output_ts=output_ts, + output_ts_step=output_ts_step, + output_pps=output_pps + ) + + @always(delay(3200)) + def clkgen(): + clk.next = not clk + input_clk.next = not input_clk + + output_clk_hp = Signal(int(3200)) + + @instance + def clkgen_output(): + while True: + yield delay(int(output_clk_hp)) + output_clk.next = not output_clk + + @always(delay(5000)) + def clkgen_sample(): + sample_clk.next = not sample_clk + + @instance + def check(): + yield delay(100000) + yield clk.posedge + rst.next = 1 + input_rst.next = 1 + output_rst.next = 1 + yield clk.posedge + yield clk.posedge + yield clk.posedge + input_rst.next = 0 + output_rst.next = 0 + yield clk.posedge + yield delay(100000) + yield clk.posedge + + # testbench stimulus + + yield clk.posedge + print("test 1: Same clock speed") + current_test.next = 1 + + yield clk.posedge + + for i in range(20000): + yield clk.posedge + + input_stop_ts = input_ts[96:48] + (input_ts[48:0]/2**16*1e-9) + output_stop_ts = output_ts[96:48] + (output_ts[48:0]/2**16*1e-9) + + print(input_stop_ts-output_stop_ts) + + assert abs(input_stop_ts-output_stop_ts) < 1e-8 + + yield delay(100000) + + yield clk.posedge + print("test 2: Slightly faster") + current_test.next = 2 + + output_clk_hp.next = 3100 + + yield clk.posedge + + for i in range(20000): + yield clk.posedge + + input_stop_ts = input_ts[96:48] + (input_ts[48:0]/2**16*1e-9) + output_stop_ts = output_ts[96:48] + (output_ts[48:0]/2**16*1e-9) + + print(input_stop_ts-output_stop_ts) + + assert abs(input_stop_ts-output_stop_ts) < 1e-8 + + yield delay(100000) + + yield clk.posedge + print("test 3: Slightly slower") + current_test.next = 3 + + output_clk_hp.next = 3300 + + yield clk.posedge + + for i in range(20000): + yield clk.posedge + + input_stop_ts = input_ts[96:48] + (input_ts[48:0]/2**16*1e-9) + output_stop_ts = output_ts[96:48] + (output_ts[48:0]/2**16*1e-9) + + print(input_stop_ts-output_stop_ts) + + assert abs(input_stop_ts-output_stop_ts) < 1e-8 + + yield delay(100000) + + yield clk.posedge + print("test 4: Significantly faster") + current_test.next = 4 + + output_clk_hp.next = 2000 + + yield clk.posedge + + for i in range(20000): + yield clk.posedge + + input_stop_ts = input_ts[96:48] + (input_ts[48:0]/2**16*1e-9) + output_stop_ts = output_ts[96:48] + (output_ts[48:0]/2**16*1e-9) + + print(input_stop_ts-output_stop_ts) + + assert abs(input_stop_ts-output_stop_ts) < 1e-8 + + yield delay(100000) + + yield clk.posedge + print("test 5: Significantly slower") + current_test.next = 5 + + output_clk_hp.next = 5000 + + yield clk.posedge + + for i in range(30000): + yield clk.posedge + + input_stop_ts = input_ts[96:48] + (input_ts[48:0]/2**16*1e-9) + output_stop_ts = output_ts[96:48] + (output_ts[48:0]/2**16*1e-9) + + print(input_stop_ts-output_stop_ts) + + assert abs(input_stop_ts-output_stop_ts) < 1e-8 + + yield delay(100000) + + raise StopSimulation + + return instances() + +def test_bench(): + sim = Simulation(bench()) + sim.run() + +if __name__ == '__main__': + print("Running test...") + test_bench() diff --git a/fpga/lib/eth/tb/test_ptp_clock_cdc_96.v b/fpga/lib/eth/tb/test_ptp_clock_cdc_96.v new file mode 100644 index 000000000..6976cbd76 --- /dev/null +++ b/fpga/lib/eth/tb/test_ptp_clock_cdc_96.v @@ -0,0 +1,111 @@ +/* + +Copyright (c) 2019 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ps / 1fs + +/* + * Testbench for ptp_clock_cdc + */ +module test_ptp_clock_cdc_96; + +// Parameters +parameter TS_WIDTH = 96; +parameter NS_WIDTH = 4; +parameter FNS_WIDTH = 16; +parameter INPUT_PERIOD_NS = 4'h6; +parameter INPUT_PERIOD_FNS = 16'h6666; +parameter OUTPUT_PERIOD_NS = 4'h6; +parameter OUTPUT_PERIOD_FNS = 16'h6666; +parameter USE_SAMPLE_CLOCK = 1; +parameter LOG_FIFO_DEPTH = 3; +parameter LOG_RATE = 3; + +// Inputs +reg clk = 0; +reg rst = 0; +reg [7:0] current_test = 0; + +reg input_clk = 0; +reg input_rst = 0; +reg output_clk = 0; +reg output_rst = 0; +reg sample_clk = 0; +reg [TS_WIDTH-1:0] input_ts = 0; + +// Outputs +wire [TS_WIDTH-1:0] output_ts; +wire output_ts_step; +wire output_pps; + +initial begin + // myhdl integration + $from_myhdl( + clk, + rst, + current_test, + input_clk, + input_rst, + output_clk, + output_rst, + sample_clk, + input_ts + ); + $to_myhdl( + output_ts, + output_ts_step, + output_pps + ); + + // dump file + $dumpfile("test_ptp_clock_cdc_96.lxt"); + $dumpvars(0, test_ptp_clock_cdc_96); +end + +ptp_clock_cdc #( + .TS_WIDTH(TS_WIDTH), + .NS_WIDTH(NS_WIDTH), + .FNS_WIDTH(FNS_WIDTH), + .INPUT_PERIOD_NS(INPUT_PERIOD_NS), + .INPUT_PERIOD_FNS(INPUT_PERIOD_FNS), + .OUTPUT_PERIOD_NS(OUTPUT_PERIOD_NS), + .OUTPUT_PERIOD_FNS(OUTPUT_PERIOD_FNS), + .USE_SAMPLE_CLOCK(USE_SAMPLE_CLOCK), + .LOG_FIFO_DEPTH(LOG_FIFO_DEPTH), + .LOG_RATE(LOG_RATE) +) +UUT ( + .input_clk(input_clk), + .input_rst(input_rst), + .output_clk(output_clk), + .output_rst(output_rst), + .sample_clk(sample_clk), + .input_ts(input_ts), + .output_ts(output_ts), + .output_ts_step(output_ts_step), + .output_pps(output_pps) +); + +endmodule