diff --git a/rtl/eth_mac_10g_fifo.v b/rtl/eth_mac_10g_fifo.v
index 4a393320c..32272cebb 100644
--- a/rtl/eth_mac_10g_fifo.v
+++ b/rtl/eth_mac_10g_fifo.v
@@ -227,8 +227,7 @@ if (TX_PTP_TS_ENABLE) begin : tx_ptp
     
     ptp_clock_cdc #(
         .TS_WIDTH(PTP_TS_WIDTH),
-        .NS_WIDTH(6),
-        .FNS_WIDTH(16)
+        .NS_WIDTH(6)
     )
     tx_ptp_cdc (
         .input_clk(logic_clk),
@@ -303,8 +302,7 @@ if (RX_PTP_TS_ENABLE) begin : rx_ptp
 
     ptp_clock_cdc #(
         .TS_WIDTH(PTP_TS_WIDTH),
-        .NS_WIDTH(6),
-        .FNS_WIDTH(16)
+        .NS_WIDTH(6)
     )
     rx_ptp_cdc (
         .input_clk(logic_clk),
diff --git a/rtl/eth_mac_phy_10g_fifo.v b/rtl/eth_mac_phy_10g_fifo.v
index 9d219d30b..be84e7ac4 100644
--- a/rtl/eth_mac_phy_10g_fifo.v
+++ b/rtl/eth_mac_phy_10g_fifo.v
@@ -256,8 +256,7 @@ if (TX_PTP_TS_ENABLE) begin : tx_ptp
     
     ptp_clock_cdc #(
         .TS_WIDTH(PTP_TS_WIDTH),
-        .NS_WIDTH(6),
-        .FNS_WIDTH(16)
+        .NS_WIDTH(6)
     )
     tx_ptp_cdc (
         .input_clk(logic_clk),
@@ -332,8 +331,7 @@ if (RX_PTP_TS_ENABLE) begin : rx_ptp
 
     ptp_clock_cdc #(
         .TS_WIDTH(PTP_TS_WIDTH),
-        .NS_WIDTH(6),
-        .FNS_WIDTH(16)
+        .NS_WIDTH(6)
     )
     rx_ptp_cdc (
         .input_clk(logic_clk),
diff --git a/rtl/ptp_clock_cdc.v b/rtl/ptp_clock_cdc.v
index 19db941f8..780711156 100644
--- a/rtl/ptp_clock_cdc.v
+++ b/rtl/ptp_clock_cdc.v
@@ -35,7 +35,6 @@ module ptp_clock_cdc #
 (
     parameter TS_WIDTH = 96,
     parameter NS_WIDTH = 4,
-    parameter FNS_WIDTH = 16,
     parameter LOG_RATE = 3,
     parameter PIPELINE_OUTPUT = 0
 )
@@ -77,6 +76,8 @@ initial begin
     end
 end
 
+parameter FNS_WIDTH = 16;
+
 parameter TS_NS_WIDTH = TS_WIDTH == 96 ? 30 : 48;
 
 parameter PHASE_CNT_WIDTH = LOG_RATE;
diff --git a/tb/ptp_clock_cdc/Makefile b/tb/ptp_clock_cdc/Makefile
index 2bf883844..9fdff623b 100644
--- a/tb/ptp_clock_cdc/Makefile
+++ b/tb/ptp_clock_cdc/Makefile
@@ -34,7 +34,6 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 # module parameters
 export PARAM_TS_WIDTH := 96
 export PARAM_NS_WIDTH := 4
-export PARAM_FNS_WIDTH := 16
 export PARAM_LOG_RATE := 3
 export PARAM_PIPELINE_OUTPUT := 0
 
diff --git a/tb/ptp_clock_cdc/test_ptp_clock_cdc.py b/tb/ptp_clock_cdc/test_ptp_clock_cdc.py
index f3839ba33..8782fdbbd 100644
--- a/tb/ptp_clock_cdc/test_ptp_clock_cdc.py
+++ b/tb/ptp_clock_cdc/test_ptp_clock_cdc.py
@@ -243,7 +243,6 @@ def test_ptp_clock_cdc(request, ts_width):
 
     parameters['TS_WIDTH'] = ts_width
     parameters['NS_WIDTH'] = 4
-    parameters['FNS_WIDTH'] = 16
     parameters['LOG_RATE'] = 3
     parameters['PIPELINE_OUTPUT'] = 0