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Fix PHY configuration connections

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-08-25 00:09:38 -07:00
parent fa05d4ff3c
commit aaeeb05ac0
32 changed files with 468 additions and 468 deletions
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8
example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

32
example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -318,8 +318,8 @@ qsfp_0_phy_0_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_0),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -368,8 +368,8 @@ qsfp_0_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -418,8 +418,8 @@ qsfp_0_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -468,8 +468,8 @@ qsfp_0_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 1
@ -573,8 +573,8 @@ qsfp_1_phy_0_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_0),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -623,8 +623,8 @@ qsfp_1_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -673,8 +673,8 @@ qsfp_1_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -723,8 +723,8 @@ qsfp_1_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
assign front_led[0] = qsfp_0_rx_block_lock_0;

8
example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

32
example/AU200/fpga_25g/rtl/fpga.v
View File

@ -428,8 +428,8 @@ qsfp0_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -475,8 +475,8 @@ qsfp0_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -522,8 +522,8 @@ qsfp0_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -569,8 +569,8 @@ qsfp0_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP1
@ -675,8 +675,8 @@ qsfp1_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -722,8 +722,8 @@ qsfp1_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -769,8 +769,8 @@ qsfp1_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -816,8 +816,8 @@ qsfp1_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
fpga_core

8
example/AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

32
example/AU250/fpga_25g/rtl/fpga.v
View File

@ -428,8 +428,8 @@ qsfp0_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -475,8 +475,8 @@ qsfp0_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -522,8 +522,8 @@ qsfp0_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -569,8 +569,8 @@ qsfp0_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP1
@ -675,8 +675,8 @@ qsfp1_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -722,8 +722,8 @@ qsfp1_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -769,8 +769,8 @@ qsfp1_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -816,8 +816,8 @@ qsfp1_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
fpga_core

8
example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

32
example/AU280/fpga_25g/rtl/fpga.v
View File

@ -305,8 +305,8 @@ qsfp0_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -352,8 +352,8 @@ qsfp0_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -399,8 +399,8 @@ qsfp0_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -446,8 +446,8 @@ qsfp0_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP1
@ -549,8 +549,8 @@ qsfp1_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -596,8 +596,8 @@ qsfp1_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -643,8 +643,8 @@ qsfp1_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -690,8 +690,8 @@ qsfp1_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
fpga_core

8
example/AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

16
example/AU50/fpga_25g/rtl/fpga.v
View File

@ -273,8 +273,8 @@ qsfp_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -320,8 +320,8 @@ qsfp_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -367,8 +367,8 @@ qsfp_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -414,8 +414,8 @@ qsfp_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
fpga_core

8
example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -298,8 +298,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

8
example/ExaNIC_X10/fpga/rtl/fpga.v
View File

@ -260,8 +260,8 @@ sfp_1_phy_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp_1_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -307,8 +307,8 @@ sfp_2_phy_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp_2_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
assign sfp_1_led[0] = sfp_1_rx_block_lock;

8
example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -298,8 +298,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

8
example/ExaNIC_X25/fpga_25g/rtl/fpga.v
View File

@ -260,8 +260,8 @@ sfp_1_phy_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp_1_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -307,8 +307,8 @@ sfp_2_phy_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp_2_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
assign sfp_1_led[0] = sfp_1_rx_block_lock;

8
example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

144
example/HTG9200/fpga_25g/rtl/fpga.v
View File

@ -489,8 +489,8 @@ qsfp_1_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -536,8 +536,8 @@ qsfp_1_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -583,8 +583,8 @@ qsfp_1_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -630,8 +630,8 @@ qsfp_1_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 2
@ -732,8 +732,8 @@ qsfp_2_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_2_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -779,8 +779,8 @@ qsfp_2_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_2_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -826,8 +826,8 @@ qsfp_2_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_2_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -873,8 +873,8 @@ qsfp_2_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_2_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 3
@ -975,8 +975,8 @@ qsfp_3_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_3_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1022,8 +1022,8 @@ qsfp_3_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_3_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1069,8 +1069,8 @@ qsfp_3_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_3_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1116,8 +1116,8 @@ qsfp_3_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_3_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 4
@ -1218,8 +1218,8 @@ qsfp_4_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_4_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1265,8 +1265,8 @@ qsfp_4_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_4_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1312,8 +1312,8 @@ qsfp_4_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_4_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1359,8 +1359,8 @@ qsfp_4_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_4_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 5
@ -1461,8 +1461,8 @@ qsfp_5_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_5_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1508,8 +1508,8 @@ qsfp_5_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_5_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1555,8 +1555,8 @@ qsfp_5_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_5_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1602,8 +1602,8 @@ qsfp_5_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_5_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 6
@ -1704,8 +1704,8 @@ qsfp_6_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_6_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1751,8 +1751,8 @@ qsfp_6_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_6_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1798,8 +1798,8 @@ qsfp_6_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_6_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1845,8 +1845,8 @@ qsfp_6_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_6_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 7
@ -1947,8 +1947,8 @@ qsfp_7_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_7_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1994,8 +1994,8 @@ qsfp_7_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_7_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2041,8 +2041,8 @@ qsfp_7_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_7_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2088,8 +2088,8 @@ qsfp_7_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_7_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 8
@ -2190,8 +2190,8 @@ qsfp_8_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_8_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2237,8 +2237,8 @@ qsfp_8_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_8_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2284,8 +2284,8 @@ qsfp_8_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_8_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2331,8 +2331,8 @@ qsfp_8_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_8_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 9
@ -2433,8 +2433,8 @@ qsfp_9_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_9_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2480,8 +2480,8 @@ qsfp_9_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_9_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2527,8 +2527,8 @@ qsfp_9_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_9_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2574,8 +2574,8 @@ qsfp_9_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_9_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
fpga_core

8
example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

240
example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v
View File

@ -601,8 +601,8 @@ qsfp_1_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -648,8 +648,8 @@ qsfp_1_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -695,8 +695,8 @@ qsfp_1_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -742,8 +742,8 @@ qsfp_1_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 2
@ -844,8 +844,8 @@ qsfp_2_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_2_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -891,8 +891,8 @@ qsfp_2_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_2_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -938,8 +938,8 @@ qsfp_2_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_2_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -985,8 +985,8 @@ qsfp_2_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_2_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 3
@ -1087,8 +1087,8 @@ qsfp_3_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_3_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1134,8 +1134,8 @@ qsfp_3_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_3_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1181,8 +1181,8 @@ qsfp_3_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_3_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1228,8 +1228,8 @@ qsfp_3_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_3_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 4
@ -1330,8 +1330,8 @@ qsfp_4_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_4_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1377,8 +1377,8 @@ qsfp_4_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_4_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1424,8 +1424,8 @@ qsfp_4_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_4_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1471,8 +1471,8 @@ qsfp_4_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_4_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 5
@ -1573,8 +1573,8 @@ qsfp_5_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_5_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1620,8 +1620,8 @@ qsfp_5_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_5_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1667,8 +1667,8 @@ qsfp_5_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_5_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1714,8 +1714,8 @@ qsfp_5_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_5_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 6
@ -1816,8 +1816,8 @@ qsfp_6_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_6_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1863,8 +1863,8 @@ qsfp_6_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_6_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1910,8 +1910,8 @@ qsfp_6_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_6_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1957,8 +1957,8 @@ qsfp_6_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_6_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 7
@ -2059,8 +2059,8 @@ qsfp_7_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_7_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2106,8 +2106,8 @@ qsfp_7_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_7_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2153,8 +2153,8 @@ qsfp_7_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_7_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2200,8 +2200,8 @@ qsfp_7_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_7_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 8
@ -2302,8 +2302,8 @@ qsfp_8_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_8_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2349,8 +2349,8 @@ qsfp_8_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_8_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2396,8 +2396,8 @@ qsfp_8_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_8_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2443,8 +2443,8 @@ qsfp_8_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_8_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 9
@ -2545,8 +2545,8 @@ qsfp_9_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_9_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2592,8 +2592,8 @@ qsfp_9_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_9_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2639,8 +2639,8 @@ qsfp_9_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_9_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2686,8 +2686,8 @@ qsfp_9_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_9_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// FMC QSFP 1
@ -2790,8 +2790,8 @@ fmc_qsfp_1_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2837,8 +2837,8 @@ fmc_qsfp_1_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2884,8 +2884,8 @@ fmc_qsfp_1_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2931,8 +2931,8 @@ fmc_qsfp_1_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// FMC QSFP 2
@ -3035,8 +3035,8 @@ fmc_qsfp_2_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -3082,8 +3082,8 @@ fmc_qsfp_2_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -3129,8 +3129,8 @@ fmc_qsfp_2_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -3176,8 +3176,8 @@ fmc_qsfp_2_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// FMC QSFP 3
@ -3280,8 +3280,8 @@ fmc_qsfp_3_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -3327,8 +3327,8 @@ fmc_qsfp_3_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -3374,8 +3374,8 @@ fmc_qsfp_3_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -3421,8 +3421,8 @@ fmc_qsfp_3_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// FMC QSFP 4
@ -3525,8 +3525,8 @@ fmc_qsfp_4_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -3572,8 +3572,8 @@ fmc_qsfp_4_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -3619,8 +3619,8 @@ fmc_qsfp_4_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -3666,8 +3666,8 @@ fmc_qsfp_4_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// FMC QSFP 5
@ -3770,8 +3770,8 @@ fmc_qsfp_5_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -3817,8 +3817,8 @@ fmc_qsfp_5_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -3864,8 +3864,8 @@ fmc_qsfp_5_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -3911,8 +3911,8 @@ fmc_qsfp_5_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// FMC QSFP 6
@ -4015,8 +4015,8 @@ fmc_qsfp_6_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -4062,8 +4062,8 @@ fmc_qsfp_6_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -4109,8 +4109,8 @@ fmc_qsfp_6_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -4156,8 +4156,8 @@ fmc_qsfp_6_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
fpga_core

8
example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

16
example/VCU108/fpga_10g/rtl/fpga.v
View File

@ -368,8 +368,8 @@ qsfp_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -415,8 +415,8 @@ qsfp_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -462,8 +462,8 @@ qsfp_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -509,8 +509,8 @@ qsfp_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// SGMII interface to PHY

8
example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

32
example/VCU118/fpga_25g/rtl/fpga.v
View File

@ -403,8 +403,8 @@ qsfp1_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -453,8 +453,8 @@ qsfp1_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -503,8 +503,8 @@ qsfp1_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -553,8 +553,8 @@ qsfp1_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP2
@ -650,8 +650,8 @@ qsfp2_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp2_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -700,8 +700,8 @@ qsfp2_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp2_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -750,8 +750,8 @@ qsfp2_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp2_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -800,8 +800,8 @@ qsfp2_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp2_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// SGMII interface to PHY

8
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

128
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v
View File

@ -585,8 +585,8 @@ qsfp1_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -635,8 +635,8 @@ qsfp1_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -685,8 +685,8 @@ qsfp1_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -735,8 +735,8 @@ qsfp1_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP2
@ -832,8 +832,8 @@ qsfp2_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp2_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -882,8 +882,8 @@ qsfp2_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp2_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -932,8 +932,8 @@ qsfp2_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp2_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -982,8 +982,8 @@ qsfp2_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp2_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// FMC QSFP1
@ -1086,8 +1086,8 @@ fmcp_qsfp1_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1133,8 +1133,8 @@ fmcp_qsfp1_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1180,8 +1180,8 @@ fmcp_qsfp1_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1227,8 +1227,8 @@ fmcp_qsfp1_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// FMC QSFP2
@ -1331,8 +1331,8 @@ fmcp_qsfp2_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1378,8 +1378,8 @@ fmcp_qsfp2_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1425,8 +1425,8 @@ fmcp_qsfp2_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1472,8 +1472,8 @@ fmcp_qsfp2_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// FMC QSFP3
@ -1576,8 +1576,8 @@ fmcp_qsfp3_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1623,8 +1623,8 @@ fmcp_qsfp3_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1670,8 +1670,8 @@ fmcp_qsfp3_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1717,8 +1717,8 @@ fmcp_qsfp3_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// FMC QSFP4
@ -1821,8 +1821,8 @@ fmcp_qsfp4_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1868,8 +1868,8 @@ fmcp_qsfp4_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1915,8 +1915,8 @@ fmcp_qsfp4_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -1962,8 +1962,8 @@ fmcp_qsfp4_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// FMC QSFP5
@ -2066,8 +2066,8 @@ fmcp_qsfp5_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2113,8 +2113,8 @@ fmcp_qsfp5_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2160,8 +2160,8 @@ fmcp_qsfp5_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2207,8 +2207,8 @@ fmcp_qsfp5_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// FMC QSFP6
@ -2311,8 +2311,8 @@ fmcp_qsfp6_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2358,8 +2358,8 @@ fmcp_qsfp6_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2405,8 +2405,8 @@ fmcp_qsfp6_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -2452,8 +2452,8 @@ fmcp_qsfp6_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// SGMII interface to PHY

8
example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

32
example/VCU1525/fpga_25g/rtl/fpga.v
View File

@ -428,8 +428,8 @@ qsfp0_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -475,8 +475,8 @@ qsfp0_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -522,8 +522,8 @@ qsfp0_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -569,8 +569,8 @@ qsfp0_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP1
@ -675,8 +675,8 @@ qsfp1_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -722,8 +722,8 @@ qsfp1_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -769,8 +769,8 @@ qsfp1_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -816,8 +816,8 @@ qsfp1_phy_4_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
fpga_core

8
example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

16
example/ZCU102/fpga/rtl/fpga.v
View File

@ -343,8 +343,8 @@ sfp0_phy_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp0_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -390,8 +390,8 @@ sfp1_phy_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp1_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -437,8 +437,8 @@ sfp2_phy_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp2_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -484,8 +484,8 @@ sfp3_phy_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp3_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
fpga_core

8
example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

8
example/ZCU106/fpga/rtl/fpga.v
View File

@ -304,8 +304,8 @@ sfp0_phy_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp0_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -351,8 +351,8 @@ sfp1_phy_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp1_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
fpga_core

8
example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -94,8 +94,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
@ -290,8 +290,8 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

32
example/fb2CG/fpga_25g/rtl/fpga.v
View File

@ -364,8 +364,8 @@ qsfp_0_phy_0_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_0),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -411,8 +411,8 @@ qsfp_0_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -458,8 +458,8 @@ qsfp_0_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -505,8 +505,8 @@ qsfp_0_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
// QSFP1
@ -633,8 +633,8 @@ qsfp_1_phy_0_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_0),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -680,8 +680,8 @@ qsfp_1_phy_1_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -727,8 +727,8 @@ qsfp_1_phy_2_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
@ -774,8 +774,8 @@ qsfp_1_phy_3_inst (
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
assign led_green[0] = qsfp_0_rx_block_lock_0;