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Code Issues Projects Releases Wiki Activity

Fix user_clk_frequency setting in testbenches

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This commit is contained in:
Alex Forencich 2020-10-12 23:07:43 -07:00
parent 7706df0d87
commit ac4859d88e
27 changed files with 27 additions and 27 deletions
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2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/test_fpga_core.py
View File

@ -349,7 +349,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -377,7 +377,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py
View File

@ -377,7 +377,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/AU200/fpga_100g/tb/test_fpga_core.py
View File

@ -339,7 +339,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/AU200/fpga_10g/tb/test_fpga_core.py
View File

@ -367,7 +367,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/AU250/fpga_100g/tb/test_fpga_core.py
View File

@ -339,7 +339,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/AU250/fpga_10g/tb/test_fpga_core.py
View File

@ -367,7 +367,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py
View File

@ -322,7 +322,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py
View File

@ -349,7 +349,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/AU50/fpga_100g/tb/test_fpga_core.py
View File

@ -279,7 +279,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py
View File

@ -296,7 +296,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -293,7 +293,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py
View File

@ -295,7 +295,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/NetFPGA_SUME/fpga/tb/test_fpga_core.py
View File

@ -296,7 +296,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -315,7 +315,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/VCU118/fpga_100g/tb/test_fpga_core.py
View File

@ -350,7 +350,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py
View File

@ -377,7 +377,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/VCU1525/fpga_100g/tb/test_fpga_core.py
View File

@ -339,7 +339,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/VCU1525/fpga_10g/tb/test_fpga_core.py
View File

@ -367,7 +367,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/ZCU106/fpga_pcie/tb/test_fpga_core.py
View File

@ -275,7 +275,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 4
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/fb2CG/fpga_100g/tb/test_fpga_core.py
View File

@ -349,7 +349,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/fb2CG/fpga_10g/tb/test_fpga_core.py
View File

@ -377,7 +377,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic/fb2CG/fpga_25g/tb/test_fpga_core.py
View File

@ -377,7 +377,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -377,7 +377,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -294,7 +294,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -316,7 +316,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py
View File

@ -378,7 +378,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5