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lib/mqnic: Add JTAG IDs for Intel Agilex series
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
218f2e2bb3
commit
ac6d523746
@ -232,6 +232,59 @@ const struct fpga_id fpga_id_list[] =
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{FPGA_ID_1SD110P_NL, FPGA_ID_MASK_FULL, "1SD110P(NL)"},
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{FPGA_ID_1SD21BP, FPGA_ID_MASK_FULL, "1SD21BP"},
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{FPGA_ID_1SD280P, FPGA_ID_MASK_FULL, "1SD280P"},
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// Agilex
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{FPGA_ID_AGFA006R16A, FPGA_ID_MASK_FULL, "AGFA006R16A"},
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{FPGA_ID_AGFA008R16A, FPGA_ID_MASK_FULL, "AGFA008R16A"},
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{FPGA_ID_AGFA012R24A, FPGA_ID_MASK_FULL, "AGFA012R24A"},
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{FPGA_ID_AGFA012R24B, FPGA_ID_MASK_FULL, "AGFA012R24B"},
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{FPGA_ID_AGFA014R24AR0, FPGA_ID_MASK_FULL, "AGFA014R24AR0"},
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{FPGA_ID_AGFA014R24A, FPGA_ID_MASK_FULL, "AGFA014R24A"},
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{FPGA_ID_AGFA014R24B, FPGA_ID_MASK_FULL, "AGFA014R24B"},
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{FPGA_ID_AGFA019R25A, FPGA_ID_MASK_FULL, "AGFA019R25A"},
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{FPGA_ID_AGFA022R24C, FPGA_ID_MASK_FULL, "AGFA022R24C"},
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{FPGA_ID_AGFA022R25A, FPGA_ID_MASK_FULL, "AGFA022R25A"},
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{FPGA_ID_AGFA022R31C, FPGA_ID_MASK_FULL, "AGFA022R31C"},
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{FPGA_ID_AGFA023R25AR0, FPGA_ID_MASK_FULL, "AGFA023R25AR0"},
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{FPGA_ID_AGFA023R25A, FPGA_ID_MASK_FULL, "AGFA023R25A"},
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{FPGA_ID_AGFA027R24CR0, FPGA_ID_MASK_FULL, "AGFA027R24CR0"},
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{FPGA_ID_AGFA027R24CR2, FPGA_ID_MASK_FULL, "AGFA027R24CR2"},
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{FPGA_ID_AGFA027R24C, FPGA_ID_MASK_FULL, "AGFA027R24C"},
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{FPGA_ID_AGFA027R25AR0, FPGA_ID_MASK_FULL, "AGFA027R25AR0"},
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{FPGA_ID_AGFA027R25A, FPGA_ID_MASK_FULL, "AGFA027R25A"},
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{FPGA_ID_AGFA027R31C, FPGA_ID_MASK_FULL, "AGFA027R31C"},
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{FPGA_ID_AGFB006R16A, FPGA_ID_MASK_FULL, "AGFB006R16A"},
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{FPGA_ID_AGFB008R16A, FPGA_ID_MASK_FULL, "AGFB008R16A"},
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{FPGA_ID_AGFB012R24A, FPGA_ID_MASK_FULL, "AGFB012R24A"},
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{FPGA_ID_AGFB012R24B, FPGA_ID_MASK_FULL, "AGFB012R24B"},
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{FPGA_ID_AGFB014R24AR0, FPGA_ID_MASK_FULL, "AGFB014R24AR0"},
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{FPGA_ID_AGFB014R24A, FPGA_ID_MASK_FULL, "AGFB014R24A"},
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{FPGA_ID_AGFB014R24B, FPGA_ID_MASK_FULL, "AGFB014R24B"},
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{FPGA_ID_AGFB019R25A, FPGA_ID_MASK_FULL, "AGFB019R25A"},
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{FPGA_ID_AGFB022R24C, FPGA_ID_MASK_FULL, "AGFB022R24C"},
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{FPGA_ID_AGFB022R25A, FPGA_ID_MASK_FULL, "AGFB022R25A"},
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{FPGA_ID_AGFB022R31C, FPGA_ID_MASK_FULL, "AGFB022R31C"},
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{FPGA_ID_AGFB023R25AR0, FPGA_ID_MASK_FULL, "AGFB023R25AR0"},
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{FPGA_ID_AGFB023R25A, FPGA_ID_MASK_FULL, "AGFB023R25A"},
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{FPGA_ID_AGFB027R24CR0, FPGA_ID_MASK_FULL, "AGFB027R24CR0"},
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{FPGA_ID_AGFB027R24CR2, FPGA_ID_MASK_FULL, "AGFB027R24CR2"},
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{FPGA_ID_AGFB027R24C, FPGA_ID_MASK_FULL, "AGFB027R24C"},
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{FPGA_ID_AGFB027R25AR0, FPGA_ID_MASK_FULL, "AGFB027R25AR0"},
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{FPGA_ID_AGFB027R25A, FPGA_ID_MASK_FULL, "AGFB027R25A"},
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{FPGA_ID_AGFB027R31C, FPGA_ID_MASK_FULL, "AGFB027R31C"},
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{FPGA_ID_AGFC019R25A, FPGA_ID_MASK_FULL, "AGFC019R25A"},
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{FPGA_ID_AGFC023R25AR0, FPGA_ID_MASK_FULL, "AGFC023R25AR0"},
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{FPGA_ID_AGFC023R25A, FPGA_ID_MASK_FULL, "AGFC023R25A"},
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{FPGA_ID_AGFD019R25A, FPGA_ID_MASK_FULL, "AGFD019R25A"},
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{FPGA_ID_AGFD023R25AR0, FPGA_ID_MASK_FULL, "AGFD023R25AR0"},
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{FPGA_ID_AGFD023R25A, FPGA_ID_MASK_FULL, "AGFD023R25A"},
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{FPGA_ID_AGIB022R29A, FPGA_ID_MASK_FULL, "AGIB022R29A"},
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{FPGA_ID_AGIB022R31B, FPGA_ID_MASK_FULL, "AGIB022R31B"},
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{FPGA_ID_AGIB027R29AR0, FPGA_ID_MASK_FULL, "AGIB027R29AR0"},
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{FPGA_ID_AGIB027R29AR1, FPGA_ID_MASK_FULL, "AGIB027R29AR1"},
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{FPGA_ID_AGIB027R29AR3, FPGA_ID_MASK_FULL, "AGIB027R29AR3"},
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{FPGA_ID_AGIB027R29A, FPGA_ID_MASK_FULL, "AGIB027R29A"},
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{FPGA_ID_AGIB027R31BR0, FPGA_ID_MASK_FULL, "AGIB027R31BR0"},
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{FPGA_ID_AGIB027R31B, FPGA_ID_MASK_FULL, "AGIB027R31B"},
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// end of list
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{0, 0, ""}
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@ -232,6 +232,59 @@ either expressed or implied, of The Regents of the University of California.
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#define FPGA_ID_1SD110P_NL 0x032C20DD
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#define FPGA_ID_1SD21BP 0x632CC0DD
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#define FPGA_ID_1SD280P 0xC32450DD
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// Agilex
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#define FPGA_ID_AGFA006R16A 0x134310DD
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#define FPGA_ID_AGFA008R16A 0x034310DD
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#define FPGA_ID_AGFA012R24A 0x534120DD
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#define FPGA_ID_AGFA012R24B 0xD34120DD
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#define FPGA_ID_AGFA014R24AR0 0x034120DD
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#define FPGA_ID_AGFA014R24A 0x434120DD
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#define FPGA_ID_AGFA014R24B 0xC34120DD
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#define FPGA_ID_AGFA019R25A 0x134150DD
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#define FPGA_ID_AGFA022R24C 0x134330DD
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#define FPGA_ID_AGFA022R25A 0x134130DD
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#define FPGA_ID_AGFA022R31C 0x134330DD
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#define FPGA_ID_AGFA023R25AR0 0x034150DD
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#define FPGA_ID_AGFA023R25A 0x034150DD
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#define FPGA_ID_AGFA027R24CR0 0x034330DD
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#define FPGA_ID_AGFA027R24CR2 0x034330DD
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#define FPGA_ID_AGFA027R24C 0x034330DD
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#define FPGA_ID_AGFA027R25AR0 0x034130DD
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#define FPGA_ID_AGFA027R25A 0x034130DD
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#define FPGA_ID_AGFA027R31C 0x034330DD
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#define FPGA_ID_AGFB006R16A 0x134390DD
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#define FPGA_ID_AGFB008R16A 0x034390DD
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#define FPGA_ID_AGFB012R24A 0x5341A0DD
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#define FPGA_ID_AGFB012R24B 0xD341A0DD
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#define FPGA_ID_AGFB014R24AR0 0x0341A0DD
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#define FPGA_ID_AGFB014R24A 0x4341A0DD
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#define FPGA_ID_AGFB014R24B 0xC341A0DD
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#define FPGA_ID_AGFB019R25A 0x1341D0DD
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#define FPGA_ID_AGFB022R24C 0x1343B0DD
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#define FPGA_ID_AGFB022R25A 0x1341B0DD
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#define FPGA_ID_AGFB022R31C 0x1343B0DD
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#define FPGA_ID_AGFB023R25AR0 0x0341D0DD
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#define FPGA_ID_AGFB023R25A 0x0341D0DD
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#define FPGA_ID_AGFB027R24CR0 0x0343B0DD
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#define FPGA_ID_AGFB027R24CR2 0x0343B0DD
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#define FPGA_ID_AGFB027R24C 0x0343B0DD
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#define FPGA_ID_AGFB027R25AR0 0x0341B0DD
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#define FPGA_ID_AGFB027R25A 0x0341B0DD
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#define FPGA_ID_AGFB027R31C 0x0343B0DD
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#define FPGA_ID_AGFC019R25A 0x334150DD
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#define FPGA_ID_AGFC023R25AR0 0x234150DD
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#define FPGA_ID_AGFC023R25A 0x234150DD
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#define FPGA_ID_AGFD019R25A 0x3341D0DD
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#define FPGA_ID_AGFD023R25AR0 0x2341D0DD
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#define FPGA_ID_AGFD023R25A 0x2341D0DD
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#define FPGA_ID_AGIB022R29A 0x134BB0DD
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#define FPGA_ID_AGIB022R31B 0x1343B0DD
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#define FPGA_ID_AGIB027R29AR0 0x034BB0DD
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#define FPGA_ID_AGIB027R29AR1 0x034BB0DD
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#define FPGA_ID_AGIB027R29AR3 0x034BB0DD
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#define FPGA_ID_AGIB027R29A 0x034BB0DD
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#define FPGA_ID_AGIB027R31BR0 0x0343B0DD
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#define FPGA_ID_AGIB027R31B 0x0343B0DD
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const char *get_fpga_part(int id);
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