From ac97cffc2b45f4bc9e7fe884c2aea04cf2ca17d2 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Mon, 13 Jul 2015 23:15:09 -0700
Subject: [PATCH] Properly reset all registers

---
 rtl/axis_srl_fifo.v        | 2 ++
 rtl/axis_srl_fifo_64.v     | 2 ++
 rtl/axis_srl_register.v    | 1 +
 rtl/axis_srl_register_64.v | 1 +
 4 files changed, 6 insertions(+)

diff --git a/rtl/axis_srl_fifo.v b/rtl/axis_srl_fifo.v
index 6a15d7d4d..b5b887cd0 100644
--- a/rtl/axis_srl_fifo.v
+++ b/rtl/axis_srl_fifo.v
@@ -115,6 +115,8 @@ end
 always @(posedge clk) begin
     if (rst) begin
         ptr_reg <= 0;
+        full_reg <= 0;
+        empty_reg <= 1;
     end else begin
         if (shift) begin
             data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tdata};
diff --git a/rtl/axis_srl_fifo_64.v b/rtl/axis_srl_fifo_64.v
index fb3480e44..8411b94d1 100644
--- a/rtl/axis_srl_fifo_64.v
+++ b/rtl/axis_srl_fifo_64.v
@@ -118,6 +118,8 @@ end
 always @(posedge clk) begin
     if (rst) begin
         ptr_reg <= 0;
+        full_reg <= 0;
+        empty_reg <= 1;
     end else begin
         if (shift) begin
             data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
diff --git a/rtl/axis_srl_register.v b/rtl/axis_srl_register.v
index 52666e5c3..2e4ea4731 100644
--- a/rtl/axis_srl_register.v
+++ b/rtl/axis_srl_register.v
@@ -77,6 +77,7 @@ end
 always @(posedge clk) begin
     if (rst) begin
         ptr_reg <= 0;
+        full_reg <= 0;
     end else begin
         // transfer empty to full
         full_reg <= ~output_axis_tready & output_axis_tvalid;
diff --git a/rtl/axis_srl_register_64.v b/rtl/axis_srl_register_64.v
index 28ff084d8..3c569f596 100644
--- a/rtl/axis_srl_register_64.v
+++ b/rtl/axis_srl_register_64.v
@@ -80,6 +80,7 @@ end
 always @(posedge clk) begin
     if (rst) begin
         ptr_reg <= 0;
+        full_reg <= 0;
     end else begin
         // transfer empty to full
         full_reg <= ~output_axis_tready & output_axis_tvalid;