From 8a46e6900c0ee06b06de81319ed7deeb505dabf3 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 13 Nov 2014 10:21:54 -0800 Subject: [PATCH 1/4] Update readme --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 99a985c56..182e346da 100644 --- a/README.md +++ b/README.md @@ -103,7 +103,7 @@ width and depth. Supports power of two depths only. Basic frame-based synchronous FIFO with parametrizable data width and depth. Supports power of two depths only. -### axis_fifo_64 module +### axis_frame_fifo_64 module Basic frame-based synchronous FIFO with tkeep signal and parametrizable data width and depth. Supports power of two depths only. From 698234c2979c962b731b3a87db38af8ce5369cde Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 13 Nov 2014 10:39:27 -0800 Subject: [PATCH 2/4] Update comments --- rtl/axis_arb_mux.py | 4 ++-- rtl/axis_arb_mux_64.py | 4 ++-- rtl/axis_async_frame_fifo.v | 2 +- rtl/axis_async_frame_fifo_64.v | 2 +- rtl/axis_crosspoint_64.py | 2 +- rtl/axis_demux.py | 4 ++-- rtl/axis_demux_64.py | 4 ++-- rtl/axis_mux.py | 2 +- rtl/axis_mux_64.py | 4 ++-- 9 files changed, 14 insertions(+), 14 deletions(-) diff --git a/rtl/axis_arb_mux.py b/rtl/axis_arb_mux.py index b1223060c..9b40e7fca 100755 --- a/rtl/axis_arb_mux.py +++ b/rtl/axis_arb_mux.py @@ -1,9 +1,9 @@ #!/usr/bin/env python -"""axis_mux +"""axis_arb_mux Generates an arbitrated AXI Stream mux with the specified number of ports -Usage: axis_crosspoint [OPTION]... +Usage: axis_arb_mux [OPTION]... -?, --help display this help and exit -p, --ports specify number of ports -n, --name specify module name diff --git a/rtl/axis_arb_mux_64.py b/rtl/axis_arb_mux_64.py index 6b05df0cb..75571c11e 100755 --- a/rtl/axis_arb_mux_64.py +++ b/rtl/axis_arb_mux_64.py @@ -1,9 +1,9 @@ #!/usr/bin/env python -"""axis_mux +"""axis_arb_mux_64 Generates an arbitrated AXI Stream mux with the specified number of ports -Usage: axis_crosspoint [OPTION]... +Usage: axis_arb_mux_64 [OPTION]... -?, --help display this help and exit -p, --ports specify number of ports -n, --name specify module name diff --git a/rtl/axis_async_frame_fifo.v b/rtl/axis_async_frame_fifo.v index 16f2e17bc..be2374241 100644 --- a/rtl/axis_async_frame_fifo.v +++ b/rtl/axis_async_frame_fifo.v @@ -27,7 +27,7 @@ THE SOFTWARE. `timescale 1ns / 1ps /* - * AXI4-Stream asynchronous FIFO + * AXI4-Stream asynchronous frame FIFO */ module axis_async_frame_fifo # ( diff --git a/rtl/axis_async_frame_fifo_64.v b/rtl/axis_async_frame_fifo_64.v index 3da51f5ef..2a200f691 100644 --- a/rtl/axis_async_frame_fifo_64.v +++ b/rtl/axis_async_frame_fifo_64.v @@ -27,7 +27,7 @@ THE SOFTWARE. `timescale 1ns / 1ps /* - * AXI4-Stream asynchronous FIFO (64 bit datapath) + * AXI4-Stream asynchronous frame FIFO (64 bit datapath) */ module axis_async_frame_fifo_64 # ( diff --git a/rtl/axis_crosspoint_64.py b/rtl/axis_crosspoint_64.py index fa674ffab..c666299a4 100755 --- a/rtl/axis_crosspoint_64.py +++ b/rtl/axis_crosspoint_64.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -"""axis_crosspoint_64_64 +"""axis_crosspoint_64 Generates an AXI Stream crosspoint switch with the specified number of ports diff --git a/rtl/axis_demux.py b/rtl/axis_demux.py index 4fb494ef2..419d09f35 100755 --- a/rtl/axis_demux.py +++ b/rtl/axis_demux.py @@ -1,9 +1,9 @@ #!/usr/bin/env python -"""axis_mux +"""axis_demux Generates an AXI Stream demux with the specified number of ports -Usage: axis_crosspoint [OPTION]... +Usage: axis_demux [OPTION]... -?, --help display this help and exit -p, --ports specify number of ports -n, --name specify module name diff --git a/rtl/axis_demux_64.py b/rtl/axis_demux_64.py index e28e5d3ac..b1ad161be 100755 --- a/rtl/axis_demux_64.py +++ b/rtl/axis_demux_64.py @@ -1,9 +1,9 @@ #!/usr/bin/env python -"""axis_mux +"""axis_demux_64 Generates an AXI Stream demux with the specified number of ports -Usage: axis_crosspoint [OPTION]... +Usage: axis_demux_64 [OPTION]... -?, --help display this help and exit -p, --ports specify number of ports -n, --name specify module name diff --git a/rtl/axis_mux.py b/rtl/axis_mux.py index 6286e3c19..711e80970 100755 --- a/rtl/axis_mux.py +++ b/rtl/axis_mux.py @@ -3,7 +3,7 @@ Generates an AXI Stream mux with the specified number of ports -Usage: axis_crosspoint [OPTION]... +Usage: axis_mux [OPTION]... -?, --help display this help and exit -p, --ports specify number of ports -n, --name specify module name diff --git a/rtl/axis_mux_64.py b/rtl/axis_mux_64.py index 53acfe832..7ef021d78 100755 --- a/rtl/axis_mux_64.py +++ b/rtl/axis_mux_64.py @@ -1,9 +1,9 @@ #!/usr/bin/env python -"""axis_mux +"""axis_mux_64 Generates an AXI Stream mux with the specified number of ports -Usage: axis_crosspoint [OPTION]... +Usage: axis_mux_64 [OPTION]... -?, --help display this help and exit -p, --ports specify number of ports -n, --name specify module name From 789c7da6d65c413370da9e261dfe5eb6b9e6ff53 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 13 Nov 2014 10:39:41 -0800 Subject: [PATCH 3/4] Fix parameter --- rtl/axis_frame_join.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/axis_frame_join.py b/rtl/axis_frame_join.py index aa69ee4b6..ec866ed84 100755 --- a/rtl/axis_frame_join.py +++ b/rtl/axis_frame_join.py @@ -47,7 +47,7 @@ def main(argv=None): ports = int(a) if o in ('-n', '--name'): name = a - if o in ('-o', '--outputs'): + if o in ('-o', '--output'): out_name = a if name is None: From 7c8699939983f37ff47a56849aa8e72eac68c46c Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 13 Nov 2014 16:26:07 -0800 Subject: [PATCH 4/4] Minor reorganization --- rtl/axis_demux.py | 11 ++++++----- rtl/axis_demux_4.v | 11 ++++++----- rtl/axis_demux_64.py | 11 ++++++----- rtl/axis_demux_64_4.v | 11 ++++++----- rtl/axis_mux.py | 12 ++++++------ rtl/axis_mux_4.v | 16 ++++++++-------- rtl/axis_mux_64.py | 12 ++++++------ rtl/axis_mux_64_4.v | 16 ++++++++-------- 8 files changed, 52 insertions(+), 48 deletions(-) diff --git a/rtl/axis_demux.py b/rtl/axis_demux.py index 419d09f35..601e87d29 100755 --- a/rtl/axis_demux.py +++ b/rtl/axis_demux.py @@ -132,7 +132,12 @@ module {{name}} # input wire [{{w-1}}:0] select ); -// // internal datapath +reg [{{w-1}}:0] select_reg = 0, select_next; +reg frame_reg = 0, frame_next; + +reg input_axis_tready_reg = 0, input_axis_tready_next; + +// internal datapath reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg output_axis_tvalid_int; reg output_axis_tready_int = 0; @@ -140,10 +145,6 @@ reg output_axis_tlast_int; reg output_axis_tuser_int; wire output_axis_tready_int_early; -reg [{{w-1}}:0] select_reg = 0, select_next; -reg frame_reg = 0, frame_next; - -reg input_axis_tready_reg = 0, input_axis_tready_next; assign input_axis_tready = input_axis_tready_reg; // mux for output control signals diff --git a/rtl/axis_demux_4.v b/rtl/axis_demux_4.v index f045c1558..1209f07c0 100644 --- a/rtl/axis_demux_4.v +++ b/rtl/axis_demux_4.v @@ -79,7 +79,12 @@ module axis_demux_4 # input wire [1:0] select ); -// // internal datapath +reg [1:0] select_reg = 0, select_next; +reg frame_reg = 0, frame_next; + +reg input_axis_tready_reg = 0, input_axis_tready_next; + +// internal datapath reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg output_axis_tvalid_int; reg output_axis_tready_int = 0; @@ -87,10 +92,6 @@ reg output_axis_tlast_int; reg output_axis_tuser_int; wire output_axis_tready_int_early; -reg [1:0] select_reg = 0, select_next; -reg frame_reg = 0, frame_next; - -reg input_axis_tready_reg = 0, input_axis_tready_next; assign input_axis_tready = input_axis_tready_reg; // mux for output control signals diff --git a/rtl/axis_demux_64.py b/rtl/axis_demux_64.py index b1ad161be..7f485bb14 100755 --- a/rtl/axis_demux_64.py +++ b/rtl/axis_demux_64.py @@ -135,7 +135,12 @@ module {{name}} # input wire [{{w-1}}:0] select ); -// // internal datapath +reg [{{w-1}}:0] select_reg = 0, select_next; +reg frame_reg = 0, frame_next; + +reg input_axis_tready_reg = 0, input_axis_tready_next; + +// internal datapath reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg [KEEP_WIDTH-1:0] output_axis_tkeep_int; reg output_axis_tvalid_int; @@ -144,10 +149,6 @@ reg output_axis_tlast_int; reg output_axis_tuser_int; wire output_axis_tready_int_early; -reg [{{w-1}}:0] select_reg = 0, select_next; -reg frame_reg = 0, frame_next; - -reg input_axis_tready_reg = 0, input_axis_tready_next; assign input_axis_tready = input_axis_tready_reg; // mux for output control signals diff --git a/rtl/axis_demux_64_4.v b/rtl/axis_demux_64_4.v index 3605ff394..47940c670 100644 --- a/rtl/axis_demux_64_4.v +++ b/rtl/axis_demux_64_4.v @@ -85,7 +85,12 @@ module axis_demux_64_4 # input wire [1:0] select ); -// // internal datapath +reg [1:0] select_reg = 0, select_next; +reg frame_reg = 0, frame_next; + +reg input_axis_tready_reg = 0, input_axis_tready_next; + +// internal datapath reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg [KEEP_WIDTH-1:0] output_axis_tkeep_int; reg output_axis_tvalid_int; @@ -94,10 +99,6 @@ reg output_axis_tlast_int; reg output_axis_tuser_int; wire output_axis_tready_int_early; -reg [1:0] select_reg = 0, select_next; -reg frame_reg = 0, frame_next; - -reg input_axis_tready_reg = 0, input_axis_tready_next; assign input_axis_tready = input_axis_tready_reg; // mux for output control signals diff --git a/rtl/axis_mux.py b/rtl/axis_mux.py index 711e80970..37c2f8a3a 100755 --- a/rtl/axis_mux.py +++ b/rtl/axis_mux.py @@ -132,6 +132,12 @@ module {{name}} # input wire [{{w-1}}:0] select ); +reg [{{w-1}}:0] select_reg = 0, select_next; +reg frame_reg = 0, frame_next; +{% for p in ports %} +reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next; +{%- endfor %} + // internal datapath reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg output_axis_tvalid_int; @@ -139,12 +145,6 @@ reg output_axis_tready_int = 0; reg output_axis_tlast_int; reg output_axis_tuser_int; wire output_axis_tready_int_early; - -reg [{{w-1}}:0] select_reg = 0, select_next; -reg frame_reg = 0, frame_next; -{% for p in ports %} -reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next; -{%- endfor %} {% for p in ports %} assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg; {%- endfor %} diff --git a/rtl/axis_mux_4.v b/rtl/axis_mux_4.v index b1e04fb63..12ad752a6 100644 --- a/rtl/axis_mux_4.v +++ b/rtl/axis_mux_4.v @@ -79,14 +79,6 @@ module axis_mux_4 # input wire [1:0] select ); -// internal datapath -reg [DATA_WIDTH-1:0] output_axis_tdata_int; -reg output_axis_tvalid_int; -reg output_axis_tready_int = 0; -reg output_axis_tlast_int; -reg output_axis_tuser_int; -wire output_axis_tready_int_early; - reg [1:0] select_reg = 0, select_next; reg frame_reg = 0, frame_next; @@ -95,6 +87,14 @@ reg input_1_axis_tready_reg = 0, input_1_axis_tready_next; reg input_2_axis_tready_reg = 0, input_2_axis_tready_next; reg input_3_axis_tready_reg = 0, input_3_axis_tready_next; +// internal datapath +reg [DATA_WIDTH-1:0] output_axis_tdata_int; +reg output_axis_tvalid_int; +reg output_axis_tready_int = 0; +reg output_axis_tlast_int; +reg output_axis_tuser_int; +wire output_axis_tready_int_early; + assign input_0_axis_tready = input_0_axis_tready_reg; assign input_1_axis_tready = input_1_axis_tready_reg; assign input_2_axis_tready = input_2_axis_tready_reg; diff --git a/rtl/axis_mux_64.py b/rtl/axis_mux_64.py index 7ef021d78..9b9165612 100755 --- a/rtl/axis_mux_64.py +++ b/rtl/axis_mux_64.py @@ -135,6 +135,12 @@ module {{name}} # input wire [{{w-1}}:0] select ); +reg [{{w-1}}:0] select_reg = 0, select_next; +reg frame_reg = 0, frame_next; +{% for p in ports %} +reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next; +{%- endfor %} + // internal datapath reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg [KEEP_WIDTH-1:0] output_axis_tkeep_int; @@ -143,12 +149,6 @@ reg output_axis_tready_int = 0; reg output_axis_tlast_int; reg output_axis_tuser_int; wire output_axis_tready_int_early; - -reg [{{w-1}}:0] select_reg = 0, select_next; -reg frame_reg = 0, frame_next; -{% for p in ports %} -reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next; -{%- endfor %} {% for p in ports %} assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg; {%- endfor %} diff --git a/rtl/axis_mux_64_4.v b/rtl/axis_mux_64_4.v index 038e377f5..bbf945e09 100644 --- a/rtl/axis_mux_64_4.v +++ b/rtl/axis_mux_64_4.v @@ -85,6 +85,14 @@ module axis_mux_64_4 # input wire [1:0] select ); +reg [1:0] select_reg = 0, select_next; +reg frame_reg = 0, frame_next; + +reg input_0_axis_tready_reg = 0, input_0_axis_tready_next; +reg input_1_axis_tready_reg = 0, input_1_axis_tready_next; +reg input_2_axis_tready_reg = 0, input_2_axis_tready_next; +reg input_3_axis_tready_reg = 0, input_3_axis_tready_next; + // internal datapath reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg [KEEP_WIDTH-1:0] output_axis_tkeep_int; @@ -94,14 +102,6 @@ reg output_axis_tlast_int; reg output_axis_tuser_int; wire output_axis_tready_int_early; -reg [1:0] select_reg = 0, select_next; -reg frame_reg = 0, frame_next; - -reg input_0_axis_tready_reg = 0, input_0_axis_tready_next; -reg input_1_axis_tready_reg = 0, input_1_axis_tready_next; -reg input_2_axis_tready_reg = 0, input_2_axis_tready_next; -reg input_3_axis_tready_reg = 0, input_3_axis_tready_next; - assign input_0_axis_tready = input_0_axis_tready_reg; assign input_1_axis_tready = input_1_axis_tready_reg; assign input_2_axis_tready = input_2_axis_tready_reg;