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fpga/common: Update Stratix 10 core logic based on RX completion buffer size test results

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-06-21 16:12:58 -07:00
parent f049e9bc37
commit acfd88a043
1 changed files with 1 additions and 1 deletions
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fpga/common/rtl/mqnic_core_pcie_s10.v
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@ -196,7 +196,7 @@ module mqnic_core_pcie_s10 #
parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
parameter PCIE_DMA_READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_READ_CPLH_FC_LIMIT = 770,
parameter PCIE_DMA_READ_CPLD_FC_LIMIT = 2500,
parameter PCIE_DMA_READ_CPLD_FC_LIMIT = 2400,
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,