From acfd88a043df3cf5e45ad28f8002e4b9ed909fd1 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 21 Jun 2023 16:12:58 -0700 Subject: [PATCH] fpga/common: Update Stratix 10 core logic based on RX completion buffer size test results Signed-off-by: Alex Forencich --- fpga/common/rtl/mqnic_core_pcie_s10.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v index 39ca4d38f..f20425634 100644 --- a/fpga/common/rtl/mqnic_core_pcie_s10.v +++ b/fpga/common/rtl/mqnic_core_pcie_s10.v @@ -196,7 +196,7 @@ module mqnic_core_pcie_s10 # parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT, parameter PCIE_DMA_READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH, parameter PCIE_DMA_READ_CPLH_FC_LIMIT = 770, - parameter PCIE_DMA_READ_CPLD_FC_LIMIT = 2500, + parameter PCIE_DMA_READ_CPLD_FC_LIMIT = 2400, parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH, parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,