From ad3905ac4db5e0e1db4725a31932a0290c3cd497 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Thu, 28 Mar 2019 16:33:01 -0700
Subject: [PATCH] Account for more merged registers

---
 syn/axis_async_fifo.tcl | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/syn/axis_async_fifo.tcl b/syn/axis_async_fifo.tcl
index 6565f9b50..6b3fe44cf 100644
--- a/syn/axis_async_fifo.tcl
+++ b/syn/axis_async_fifo.tcl
@@ -35,8 +35,10 @@ foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == axis_async_fifo ||
     # reset synchronization
     set reset_ffs [get_cells -hier -regexp ".*/(s|m)_rst_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"]
 
-    set_property ASYNC_REG TRUE $reset_ffs
-    set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}]
+    if {[llength $reset_ffs]} {
+        set_property ASYNC_REG TRUE $reset_ffs
+        set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}]
+    }
 
     if {[llength [get_cells $fifo_inst/s_rst_sync2_reg_reg]]} {
         set_false_path -to [get_pins $fifo_inst/s_rst_sync2_reg_reg/D]